linux/drivers/cpufreq/pmac64-cpufreq.c
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   1/*
   2 *  Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
   3 *  and                       Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License version 2 as
   7 * published by the Free Software Foundation.
   8 *
   9 * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
  10 * that is iMac G5 and latest single CPU desktop.
  11 */
  12
  13#undef DEBUG
  14
  15#include <linux/module.h>
  16#include <linux/types.h>
  17#include <linux/errno.h>
  18#include <linux/kernel.h>
  19#include <linux/delay.h>
  20#include <linux/sched.h>
  21#include <linux/cpufreq.h>
  22#include <linux/init.h>
  23#include <linux/completion.h>
  24#include <linux/mutex.h>
  25#include <asm/prom.h>
  26#include <asm/machdep.h>
  27#include <asm/irq.h>
  28#include <asm/sections.h>
  29#include <asm/cputable.h>
  30#include <asm/time.h>
  31#include <asm/smu.h>
  32#include <asm/pmac_pfunc.h>
  33
  34#define DBG(fmt...) pr_debug(fmt)
  35
  36/* see 970FX user manual */
  37
  38#define SCOM_PCR 0x0aa001                       /* PCR scom addr */
  39
  40#define PCR_HILO_SELECT         0x80000000U     /* 1 = PCR, 0 = PCRH */
  41#define PCR_SPEED_FULL          0x00000000U     /* 1:1 speed value */
  42#define PCR_SPEED_HALF          0x00020000U     /* 1:2 speed value */
  43#define PCR_SPEED_QUARTER       0x00040000U     /* 1:4 speed value */
  44#define PCR_SPEED_MASK          0x000e0000U     /* speed mask */
  45#define PCR_SPEED_SHIFT         17
  46#define PCR_FREQ_REQ_VALID      0x00010000U     /* freq request valid */
  47#define PCR_VOLT_REQ_VALID      0x00008000U     /* volt request valid */
  48#define PCR_TARGET_TIME_MASK    0x00006000U     /* target time */
  49#define PCR_STATLAT_MASK        0x00001f00U     /* STATLAT value */
  50#define PCR_SNOOPLAT_MASK       0x000000f0U     /* SNOOPLAT value */
  51#define PCR_SNOOPACC_MASK       0x0000000fU     /* SNOOPACC value */
  52
  53#define SCOM_PSR 0x408001                       /* PSR scom addr */
  54/* warning: PSR is a 64 bits register */
  55#define PSR_CMD_RECEIVED        0x2000000000000000U   /* command received */
  56#define PSR_CMD_COMPLETED       0x1000000000000000U   /* command completed */
  57#define PSR_CUR_SPEED_MASK      0x0300000000000000U   /* current speed */
  58#define PSR_CUR_SPEED_SHIFT     (56)
  59
  60/*
  61 * The G5 only supports two frequencies (Quarter speed is not supported)
  62 */
  63#define CPUFREQ_HIGH                  0
  64#define CPUFREQ_LOW                   1
  65
  66static struct cpufreq_frequency_table g5_cpu_freqs[] = {
  67        {CPUFREQ_HIGH,          0},
  68        {CPUFREQ_LOW,           0},
  69        {0,                     CPUFREQ_TABLE_END},
  70};
  71
  72static struct freq_attr* g5_cpu_freqs_attr[] = {
  73        &cpufreq_freq_attr_scaling_available_freqs,
  74        NULL,
  75};
  76
  77/* Power mode data is an array of the 32 bits PCR values to use for
  78 * the various frequencies, retrieved from the device-tree
  79 */
  80static int g5_pmode_cur;
  81
  82static void (*g5_switch_volt)(int speed_mode);
  83static int (*g5_switch_freq)(int speed_mode);
  84static int (*g5_query_freq)(void);
  85
  86static DEFINE_MUTEX(g5_switch_mutex);
  87
  88static unsigned long transition_latency;
  89
  90#ifdef CONFIG_PMAC_SMU
  91
  92static const u32 *g5_pmode_data;
  93static int g5_pmode_max;
  94
  95static struct smu_sdbp_fvt *g5_fvt_table;       /* table of op. points */
  96static int g5_fvt_count;                        /* number of op. points */
  97static int g5_fvt_cur;                          /* current op. point */
  98
  99/*
 100 * SMU based voltage switching for Neo2 platforms
 101 */
 102
 103static void g5_smu_switch_volt(int speed_mode)
 104{
 105        struct smu_simple_cmd   cmd;
 106
 107        DECLARE_COMPLETION_ONSTACK(comp);
 108        smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete,
 109                         &comp, 'V', 'S', 'L', 'E', 'W',
 110                         0xff, g5_fvt_cur+1, speed_mode);
 111        wait_for_completion(&comp);
 112}
 113
 114/*
 115 * Platform function based voltage/vdnap switching for Neo2
 116 */
 117
 118static struct pmf_function *pfunc_set_vdnap0;
 119static struct pmf_function *pfunc_vdnap0_complete;
 120
 121static void g5_vdnap_switch_volt(int speed_mode)
 122{
 123        struct pmf_args args;
 124        u32 slew, done = 0;
 125        unsigned long timeout;
 126
 127        slew = (speed_mode == CPUFREQ_LOW) ? 1 : 0;
 128        args.count = 1;
 129        args.u[0].p = &slew;
 130
 131        pmf_call_one(pfunc_set_vdnap0, &args);
 132
 133        /* It's an irq GPIO so we should be able to just block here,
 134         * I'll do that later after I've properly tested the IRQ code for
 135         * platform functions
 136         */
 137        timeout = jiffies + HZ/10;
 138        while(!time_after(jiffies, timeout)) {
 139                args.count = 1;
 140                args.u[0].p = &done;
 141                pmf_call_one(pfunc_vdnap0_complete, &args);
 142                if (done)
 143                        break;
 144                msleep(1);
 145        }
 146        if (done == 0)
 147                printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n");
 148}
 149
 150
 151/*
 152 * SCOM based frequency switching for 970FX rev3
 153 */
 154static int g5_scom_switch_freq(int speed_mode)
 155{
 156        unsigned long flags;
 157        int to;
 158
 159        /* If frequency is going up, first ramp up the voltage */
 160        if (speed_mode < g5_pmode_cur)
 161                g5_switch_volt(speed_mode);
 162
 163        local_irq_save(flags);
 164
 165        /* Clear PCR high */
 166        scom970_write(SCOM_PCR, 0);
 167        /* Clear PCR low */
 168        scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
 169        /* Set PCR low */
 170        scom970_write(SCOM_PCR, PCR_HILO_SELECT |
 171                      g5_pmode_data[speed_mode]);
 172
 173        /* Wait for completion */
 174        for (to = 0; to < 10; to++) {
 175                unsigned long psr = scom970_read(SCOM_PSR);
 176
 177                if ((psr & PSR_CMD_RECEIVED) == 0 &&
 178                    (((psr >> PSR_CUR_SPEED_SHIFT) ^
 179                      (g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
 180                    == 0)
 181                        break;
 182                if (psr & PSR_CMD_COMPLETED)
 183                        break;
 184                udelay(100);
 185        }
 186
 187        local_irq_restore(flags);
 188
 189        /* If frequency is going down, last ramp the voltage */
 190        if (speed_mode > g5_pmode_cur)
 191                g5_switch_volt(speed_mode);
 192
 193        g5_pmode_cur = speed_mode;
 194        ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
 195
 196        return 0;
 197}
 198
 199static int g5_scom_query_freq(void)
 200{
 201        unsigned long psr = scom970_read(SCOM_PSR);
 202        int i;
 203
 204        for (i = 0; i <= g5_pmode_max; i++)
 205                if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
 206                      (g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
 207                        break;
 208        return i;
 209}
 210
 211/*
 212 * Fake voltage switching for platforms with missing support
 213 */
 214
 215static void g5_dummy_switch_volt(int speed_mode)
 216{
 217}
 218
 219#endif /* CONFIG_PMAC_SMU */
 220
 221/*
 222 * Platform function based voltage switching for PowerMac7,2 & 7,3
 223 */
 224
 225static struct pmf_function *pfunc_cpu0_volt_high;
 226static struct pmf_function *pfunc_cpu0_volt_low;
 227static struct pmf_function *pfunc_cpu1_volt_high;
 228static struct pmf_function *pfunc_cpu1_volt_low;
 229
 230static void g5_pfunc_switch_volt(int speed_mode)
 231{
 232        if (speed_mode == CPUFREQ_HIGH) {
 233                if (pfunc_cpu0_volt_high)
 234                        pmf_call_one(pfunc_cpu0_volt_high, NULL);
 235                if (pfunc_cpu1_volt_high)
 236                        pmf_call_one(pfunc_cpu1_volt_high, NULL);
 237        } else {
 238                if (pfunc_cpu0_volt_low)
 239                        pmf_call_one(pfunc_cpu0_volt_low, NULL);
 240                if (pfunc_cpu1_volt_low)
 241                        pmf_call_one(pfunc_cpu1_volt_low, NULL);
 242        }
 243        msleep(10); /* should be faster , to fix */
 244}
 245
 246/*
 247 * Platform function based frequency switching for PowerMac7,2 & 7,3
 248 */
 249
 250static struct pmf_function *pfunc_cpu_setfreq_high;
 251static struct pmf_function *pfunc_cpu_setfreq_low;
 252static struct pmf_function *pfunc_cpu_getfreq;
 253static struct pmf_function *pfunc_slewing_done;
 254
 255static int g5_pfunc_switch_freq(int speed_mode)
 256{
 257        struct pmf_args args;
 258        u32 done = 0;
 259        unsigned long timeout;
 260        int rc;
 261
 262        DBG("g5_pfunc_switch_freq(%d)\n", speed_mode);
 263
 264        /* If frequency is going up, first ramp up the voltage */
 265        if (speed_mode < g5_pmode_cur)
 266                g5_switch_volt(speed_mode);
 267
 268        /* Do it */
 269        if (speed_mode == CPUFREQ_HIGH)
 270                rc = pmf_call_one(pfunc_cpu_setfreq_high, NULL);
 271        else
 272                rc = pmf_call_one(pfunc_cpu_setfreq_low, NULL);
 273
 274        if (rc)
 275                printk(KERN_WARNING "cpufreq: pfunc switch error %d\n", rc);
 276
 277        /* It's an irq GPIO so we should be able to just block here,
 278         * I'll do that later after I've properly tested the IRQ code for
 279         * platform functions
 280         */
 281        timeout = jiffies + HZ/10;
 282        while(!time_after(jiffies, timeout)) {
 283                args.count = 1;
 284                args.u[0].p = &done;
 285                pmf_call_one(pfunc_slewing_done, &args);
 286                if (done)
 287                        break;
 288                msleep(1);
 289        }
 290        if (done == 0)
 291                printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n");
 292
 293        /* If frequency is going down, last ramp the voltage */
 294        if (speed_mode > g5_pmode_cur)
 295                g5_switch_volt(speed_mode);
 296
 297        g5_pmode_cur = speed_mode;
 298        ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
 299
 300        return 0;
 301}
 302
 303static int g5_pfunc_query_freq(void)
 304{
 305        struct pmf_args args;
 306        u32 val = 0;
 307
 308        args.count = 1;
 309        args.u[0].p = &val;
 310        pmf_call_one(pfunc_cpu_getfreq, &args);
 311        return val ? CPUFREQ_HIGH : CPUFREQ_LOW;
 312}
 313
 314
 315/*
 316 * Common interface to the cpufreq core
 317 */
 318
 319static int g5_cpufreq_verify(struct cpufreq_policy *policy)
 320{
 321        return cpufreq_frequency_table_verify(policy, g5_cpu_freqs);
 322}
 323
 324static int g5_cpufreq_target(struct cpufreq_policy *policy,
 325        unsigned int target_freq, unsigned int relation)
 326{
 327        unsigned int newstate = 0;
 328        struct cpufreq_freqs freqs;
 329        int rc;
 330
 331        if (cpufreq_frequency_table_target(policy, g5_cpu_freqs,
 332                        target_freq, relation, &newstate))
 333                return -EINVAL;
 334
 335        if (g5_pmode_cur == newstate)
 336                return 0;
 337
 338        mutex_lock(&g5_switch_mutex);
 339
 340        freqs.old = g5_cpu_freqs[g5_pmode_cur].frequency;
 341        freqs.new = g5_cpu_freqs[newstate].frequency;
 342
 343        cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
 344        rc = g5_switch_freq(newstate);
 345        cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
 346
 347        mutex_unlock(&g5_switch_mutex);
 348
 349        return rc;
 350}
 351
 352static unsigned int g5_cpufreq_get_speed(unsigned int cpu)
 353{
 354        return g5_cpu_freqs[g5_pmode_cur].frequency;
 355}
 356
 357static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy)
 358{
 359        policy->cpuinfo.transition_latency = transition_latency;
 360        policy->cur = g5_cpu_freqs[g5_query_freq()].frequency;
 361        /* secondary CPUs are tied to the primary one by the
 362         * cpufreq core if in the secondary policy we tell it that
 363         * it actually must be one policy together with all others. */
 364        cpumask_copy(policy->cpus, cpu_online_mask);
 365        cpufreq_frequency_table_get_attr(g5_cpu_freqs, policy->cpu);
 366
 367        return cpufreq_frequency_table_cpuinfo(policy,
 368                g5_cpu_freqs);
 369}
 370
 371
 372static struct cpufreq_driver g5_cpufreq_driver = {
 373        .name           = "powermac",
 374        .owner          = THIS_MODULE,
 375        .flags          = CPUFREQ_CONST_LOOPS,
 376        .init           = g5_cpufreq_cpu_init,
 377        .verify         = g5_cpufreq_verify,
 378        .target         = g5_cpufreq_target,
 379        .get            = g5_cpufreq_get_speed,
 380        .attr           = g5_cpu_freqs_attr,
 381};
 382
 383
 384#ifdef CONFIG_PMAC_SMU
 385
 386static int __init g5_neo2_cpufreq_init(struct device_node *cpus)
 387{
 388        struct device_node *cpunode;
 389        unsigned int psize, ssize;
 390        unsigned long max_freq;
 391        char *freq_method, *volt_method;
 392        const u32 *valp;
 393        u32 pvr_hi;
 394        int use_volts_vdnap = 0;
 395        int use_volts_smu = 0;
 396        int rc = -ENODEV;
 397
 398        /* Check supported platforms */
 399        if (of_machine_is_compatible("PowerMac8,1") ||
 400            of_machine_is_compatible("PowerMac8,2") ||
 401            of_machine_is_compatible("PowerMac9,1"))
 402                use_volts_smu = 1;
 403        else if (of_machine_is_compatible("PowerMac11,2"))
 404                use_volts_vdnap = 1;
 405        else
 406                return -ENODEV;
 407
 408        /* Get first CPU node */
 409        for (cpunode = NULL;
 410             (cpunode = of_get_next_child(cpus, cpunode)) != NULL;) {
 411                const u32 *reg = of_get_property(cpunode, "reg", NULL);
 412                if (reg == NULL || (*reg) != 0)
 413                        continue;
 414                if (!strcmp(cpunode->type, "cpu"))
 415                        break;
 416        }
 417        if (cpunode == NULL) {
 418                printk(KERN_ERR "cpufreq: Can't find any CPU 0 node\n");
 419                return -ENODEV;
 420        }
 421
 422        /* Check 970FX for now */
 423        valp = of_get_property(cpunode, "cpu-version", NULL);
 424        if (!valp) {
 425                DBG("No cpu-version property !\n");
 426                goto bail_noprops;
 427        }
 428        pvr_hi = (*valp) >> 16;
 429        if (pvr_hi != 0x3c && pvr_hi != 0x44) {
 430                printk(KERN_ERR "cpufreq: Unsupported CPU version\n");
 431                goto bail_noprops;
 432        }
 433
 434        /* Look for the powertune data in the device-tree */
 435        g5_pmode_data = of_get_property(cpunode, "power-mode-data",&psize);
 436        if (!g5_pmode_data) {
 437                DBG("No power-mode-data !\n");
 438                goto bail_noprops;
 439        }
 440        g5_pmode_max = psize / sizeof(u32) - 1;
 441
 442        if (use_volts_smu) {
 443                const struct smu_sdbp_header *shdr;
 444
 445                /* Look for the FVT table */
 446                shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL);
 447                if (!shdr)
 448                        goto bail_noprops;
 449                g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1];
 450                ssize = (shdr->len * sizeof(u32)) -
 451                        sizeof(struct smu_sdbp_header);
 452                g5_fvt_count = ssize / sizeof(struct smu_sdbp_fvt);
 453                g5_fvt_cur = 0;
 454
 455                /* Sanity checking */
 456                if (g5_fvt_count < 1 || g5_pmode_max < 1)
 457                        goto bail_noprops;
 458
 459                g5_switch_volt = g5_smu_switch_volt;
 460                volt_method = "SMU";
 461        } else if (use_volts_vdnap) {
 462                struct device_node *root;
 463
 464                root = of_find_node_by_path("/");
 465                if (root == NULL) {
 466                        printk(KERN_ERR "cpufreq: Can't find root of "
 467                               "device tree\n");
 468                        goto bail_noprops;
 469                }
 470                pfunc_set_vdnap0 = pmf_find_function(root, "set-vdnap0");
 471                pfunc_vdnap0_complete =
 472                        pmf_find_function(root, "slewing-done");
 473                if (pfunc_set_vdnap0 == NULL ||
 474                    pfunc_vdnap0_complete == NULL) {
 475                        printk(KERN_ERR "cpufreq: Can't find required "
 476                               "platform function\n");
 477                        goto bail_noprops;
 478                }
 479
 480                g5_switch_volt = g5_vdnap_switch_volt;
 481                volt_method = "GPIO";
 482        } else {
 483                g5_switch_volt = g5_dummy_switch_volt;
 484                volt_method = "none";
 485        }
 486
 487        /*
 488         * From what I see, clock-frequency is always the maximal frequency.
 489         * The current driver can not slew sysclk yet, so we really only deal
 490         * with powertune steps for now. We also only implement full freq and
 491         * half freq in this version. So far, I haven't yet seen a machine
 492         * supporting anything else.
 493         */
 494        valp = of_get_property(cpunode, "clock-frequency", NULL);
 495        if (!valp)
 496                return -ENODEV;
 497        max_freq = (*valp)/1000;
 498        g5_cpu_freqs[0].frequency = max_freq;
 499        g5_cpu_freqs[1].frequency = max_freq/2;
 500
 501        /* Set callbacks */
 502        transition_latency = 12000;
 503        g5_switch_freq = g5_scom_switch_freq;
 504        g5_query_freq = g5_scom_query_freq;
 505        freq_method = "SCOM";
 506
 507        /* Force apply current frequency to make sure everything is in
 508         * sync (voltage is right for example). Firmware may leave us with
 509         * a strange setting ...
 510         */
 511        g5_switch_volt(CPUFREQ_HIGH);
 512        msleep(10);
 513        g5_pmode_cur = -1;
 514        g5_switch_freq(g5_query_freq());
 515
 516        printk(KERN_INFO "Registering G5 CPU frequency driver\n");
 517        printk(KERN_INFO "Frequency method: %s, Voltage method: %s\n",
 518               freq_method, volt_method);
 519        printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
 520                g5_cpu_freqs[1].frequency/1000,
 521                g5_cpu_freqs[0].frequency/1000,
 522                g5_cpu_freqs[g5_pmode_cur].frequency/1000);
 523
 524        rc = cpufreq_register_driver(&g5_cpufreq_driver);
 525
 526        /* We keep the CPU node on hold... hopefully, Apple G5 don't have
 527         * hotplug CPU with a dynamic device-tree ...
 528         */
 529        return rc;
 530
 531 bail_noprops:
 532        of_node_put(cpunode);
 533
 534        return rc;
 535}
 536
 537#endif /* CONFIG_PMAC_SMU */
 538
 539
 540static int __init g5_pm72_cpufreq_init(struct device_node *cpus)
 541{
 542        struct device_node *cpuid = NULL, *hwclock = NULL, *cpunode = NULL;
 543        const u8 *eeprom = NULL;
 544        const u32 *valp;
 545        u64 max_freq, min_freq, ih, il;
 546        int has_volt = 1, rc = 0;
 547
 548        DBG("cpufreq: Initializing for PowerMac7,2, PowerMac7,3 and"
 549            " RackMac3,1...\n");
 550
 551        /* Get first CPU node */
 552        for (cpunode = NULL;
 553             (cpunode = of_get_next_child(cpus, cpunode)) != NULL;) {
 554                if (!strcmp(cpunode->type, "cpu"))
 555                        break;
 556        }
 557        if (cpunode == NULL) {
 558                printk(KERN_ERR "cpufreq: Can't find any CPU node\n");
 559                return -ENODEV;
 560        }
 561
 562        /* Lookup the cpuid eeprom node */
 563        cpuid = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/cpuid@a0");
 564        if (cpuid != NULL)
 565                eeprom = of_get_property(cpuid, "cpuid", NULL);
 566        if (eeprom == NULL) {
 567                printk(KERN_ERR "cpufreq: Can't find cpuid EEPROM !\n");
 568                rc = -ENODEV;
 569                goto bail;
 570        }
 571
 572        /* Lookup the i2c hwclock */
 573        for (hwclock = NULL;
 574             (hwclock = of_find_node_by_name(hwclock, "i2c-hwclock")) != NULL;){
 575                const char *loc = of_get_property(hwclock,
 576                                "hwctrl-location", NULL);
 577                if (loc == NULL)
 578                        continue;
 579                if (strcmp(loc, "CPU CLOCK"))
 580                        continue;
 581                if (!of_get_property(hwclock, "platform-get-frequency", NULL))
 582                        continue;
 583                break;
 584        }
 585        if (hwclock == NULL) {
 586                printk(KERN_ERR "cpufreq: Can't find i2c clock chip !\n");
 587                rc = -ENODEV;
 588                goto bail;
 589        }
 590
 591        DBG("cpufreq: i2c clock chip found: %s\n", hwclock->full_name);
 592
 593        /* Now get all the platform functions */
 594        pfunc_cpu_getfreq =
 595                pmf_find_function(hwclock, "get-frequency");
 596        pfunc_cpu_setfreq_high =
 597                pmf_find_function(hwclock, "set-frequency-high");
 598        pfunc_cpu_setfreq_low =
 599                pmf_find_function(hwclock, "set-frequency-low");
 600        pfunc_slewing_done =
 601                pmf_find_function(hwclock, "slewing-done");
 602        pfunc_cpu0_volt_high =
 603                pmf_find_function(hwclock, "set-voltage-high-0");
 604        pfunc_cpu0_volt_low =
 605                pmf_find_function(hwclock, "set-voltage-low-0");
 606        pfunc_cpu1_volt_high =
 607                pmf_find_function(hwclock, "set-voltage-high-1");
 608        pfunc_cpu1_volt_low =
 609                pmf_find_function(hwclock, "set-voltage-low-1");
 610
 611        /* Check we have minimum requirements */
 612        if (pfunc_cpu_getfreq == NULL || pfunc_cpu_setfreq_high == NULL ||
 613            pfunc_cpu_setfreq_low == NULL || pfunc_slewing_done == NULL) {
 614                printk(KERN_ERR "cpufreq: Can't find platform functions !\n");
 615                rc = -ENODEV;
 616                goto bail;
 617        }
 618
 619        /* Check that we have complete sets */
 620        if (pfunc_cpu0_volt_high == NULL || pfunc_cpu0_volt_low == NULL) {
 621                pmf_put_function(pfunc_cpu0_volt_high);
 622                pmf_put_function(pfunc_cpu0_volt_low);
 623                pfunc_cpu0_volt_high = pfunc_cpu0_volt_low = NULL;
 624                has_volt = 0;
 625        }
 626        if (!has_volt ||
 627            pfunc_cpu1_volt_high == NULL || pfunc_cpu1_volt_low == NULL) {
 628                pmf_put_function(pfunc_cpu1_volt_high);
 629                pmf_put_function(pfunc_cpu1_volt_low);
 630                pfunc_cpu1_volt_high = pfunc_cpu1_volt_low = NULL;
 631        }
 632
 633        /* Note: The device tree also contains a "platform-set-values"
 634         * function for which I haven't quite figured out the usage. It
 635         * might have to be called on init and/or wakeup, I'm not too sure
 636         * but things seem to work fine without it so far ...
 637         */
 638
 639        /* Get max frequency from device-tree */
 640        valp = of_get_property(cpunode, "clock-frequency", NULL);
 641        if (!valp) {
 642                printk(KERN_ERR "cpufreq: Can't find CPU frequency !\n");
 643                rc = -ENODEV;
 644                goto bail;
 645        }
 646
 647        max_freq = (*valp)/1000;
 648
 649        /* Now calculate reduced frequency by using the cpuid input freq
 650         * ratio. This requires 64 bits math unless we are willing to lose
 651         * some precision
 652         */
 653        ih = *((u32 *)(eeprom + 0x10));
 654        il = *((u32 *)(eeprom + 0x20));
 655
 656        /* Check for machines with no useful settings */
 657        if (il == ih) {
 658                printk(KERN_WARNING "cpufreq: No low frequency mode available"
 659                       " on this model !\n");
 660                rc = -ENODEV;
 661                goto bail;
 662        }
 663
 664        min_freq = 0;
 665        if (ih != 0 && il != 0)
 666                min_freq = (max_freq * il) / ih;
 667
 668        /* Sanity check */
 669        if (min_freq >= max_freq || min_freq < 1000) {
 670                printk(KERN_ERR "cpufreq: Can't calculate low frequency !\n");
 671                rc = -ENXIO;
 672                goto bail;
 673        }
 674        g5_cpu_freqs[0].frequency = max_freq;
 675        g5_cpu_freqs[1].frequency = min_freq;
 676
 677        /* Set callbacks */
 678        transition_latency = CPUFREQ_ETERNAL;
 679        g5_switch_volt = g5_pfunc_switch_volt;
 680        g5_switch_freq = g5_pfunc_switch_freq;
 681        g5_query_freq = g5_pfunc_query_freq;
 682
 683        /* Force apply current frequency to make sure everything is in
 684         * sync (voltage is right for example). Firmware may leave us with
 685         * a strange setting ...
 686         */
 687        g5_switch_volt(CPUFREQ_HIGH);
 688        msleep(10);
 689        g5_pmode_cur = -1;
 690        g5_switch_freq(g5_query_freq());
 691
 692        printk(KERN_INFO "Registering G5 CPU frequency driver\n");
 693        printk(KERN_INFO "Frequency method: i2c/pfunc, "
 694               "Voltage method: %s\n", has_volt ? "i2c/pfunc" : "none");
 695        printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
 696                g5_cpu_freqs[1].frequency/1000,
 697                g5_cpu_freqs[0].frequency/1000,
 698                g5_cpu_freqs[g5_pmode_cur].frequency/1000);
 699
 700        rc = cpufreq_register_driver(&g5_cpufreq_driver);
 701 bail:
 702        if (rc != 0) {
 703                pmf_put_function(pfunc_cpu_getfreq);
 704                pmf_put_function(pfunc_cpu_setfreq_high);
 705                pmf_put_function(pfunc_cpu_setfreq_low);
 706                pmf_put_function(pfunc_slewing_done);
 707                pmf_put_function(pfunc_cpu0_volt_high);
 708                pmf_put_function(pfunc_cpu0_volt_low);
 709                pmf_put_function(pfunc_cpu1_volt_high);
 710                pmf_put_function(pfunc_cpu1_volt_low);
 711        }
 712        of_node_put(hwclock);
 713        of_node_put(cpuid);
 714        of_node_put(cpunode);
 715
 716        return rc;
 717}
 718
 719static int __init g5_cpufreq_init(void)
 720{
 721        struct device_node *cpus;
 722        int rc = 0;
 723
 724        cpus = of_find_node_by_path("/cpus");
 725        if (cpus == NULL) {
 726                DBG("No /cpus node !\n");
 727                return -ENODEV;
 728        }
 729
 730        if (of_machine_is_compatible("PowerMac7,2") ||
 731            of_machine_is_compatible("PowerMac7,3") ||
 732            of_machine_is_compatible("RackMac3,1"))
 733                rc = g5_pm72_cpufreq_init(cpus);
 734#ifdef CONFIG_PMAC_SMU
 735        else
 736                rc = g5_neo2_cpufreq_init(cpus);
 737#endif /* CONFIG_PMAC_SMU */
 738
 739        of_node_put(cpus);
 740        return rc;
 741}
 742
 743module_init(g5_cpufreq_init);
 744
 745
 746MODULE_LICENSE("GPL");
 747
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