linux/drivers/cpufreq/imx6q-cpufreq.c
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   1/*
   2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License version 2 as
   6 * published by the Free Software Foundation.
   7 */
   8
   9#include <linux/clk.h>
  10#include <linux/cpufreq.h>
  11#include <linux/delay.h>
  12#include <linux/err.h>
  13#include <linux/module.h>
  14#include <linux/of.h>
  15#include <linux/opp.h>
  16#include <linux/platform_device.h>
  17#include <linux/regulator/consumer.h>
  18
  19#define PU_SOC_VOLTAGE_NORMAL   1250000
  20#define PU_SOC_VOLTAGE_HIGH     1275000
  21#define FREQ_1P2_GHZ            1200000000
  22
  23static struct regulator *arm_reg;
  24static struct regulator *pu_reg;
  25static struct regulator *soc_reg;
  26
  27static struct clk *arm_clk;
  28static struct clk *pll1_sys_clk;
  29static struct clk *pll1_sw_clk;
  30static struct clk *step_clk;
  31static struct clk *pll2_pfd2_396m_clk;
  32
  33static struct device *cpu_dev;
  34static struct cpufreq_frequency_table *freq_table;
  35static unsigned int transition_latency;
  36
  37static int imx6q_verify_speed(struct cpufreq_policy *policy)
  38{
  39        return cpufreq_frequency_table_verify(policy, freq_table);
  40}
  41
  42static unsigned int imx6q_get_speed(unsigned int cpu)
  43{
  44        return clk_get_rate(arm_clk) / 1000;
  45}
  46
  47static int imx6q_set_target(struct cpufreq_policy *policy,
  48                            unsigned int target_freq, unsigned int relation)
  49{
  50        struct cpufreq_freqs freqs;
  51        struct opp *opp;
  52        unsigned long freq_hz, volt, volt_old;
  53        unsigned int index;
  54        int ret;
  55
  56        ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
  57                                             relation, &index);
  58        if (ret) {
  59                dev_err(cpu_dev, "failed to match target frequency %d: %d\n",
  60                        target_freq, ret);
  61                return ret;
  62        }
  63
  64        freqs.new = freq_table[index].frequency;
  65        freq_hz = freqs.new * 1000;
  66        freqs.old = clk_get_rate(arm_clk) / 1000;
  67
  68        if (freqs.old == freqs.new)
  69                return 0;
  70
  71        rcu_read_lock();
  72        opp = opp_find_freq_ceil(cpu_dev, &freq_hz);
  73        if (IS_ERR(opp)) {
  74                rcu_read_unlock();
  75                dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
  76                return PTR_ERR(opp);
  77        }
  78
  79        volt = opp_get_voltage(opp);
  80        rcu_read_unlock();
  81        volt_old = regulator_get_voltage(arm_reg);
  82
  83        dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
  84                freqs.old / 1000, volt_old / 1000,
  85                freqs.new / 1000, volt / 1000);
  86
  87        cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
  88
  89        /* scaling up?  scale voltage before frequency */
  90        if (freqs.new > freqs.old) {
  91                ret = regulator_set_voltage_tol(arm_reg, volt, 0);
  92                if (ret) {
  93                        dev_err(cpu_dev,
  94                                "failed to scale vddarm up: %d\n", ret);
  95                        freqs.new = freqs.old;
  96                        goto post_notify;
  97                }
  98
  99                /*
 100                 * Need to increase vddpu and vddsoc for safety
 101                 * if we are about to run at 1.2 GHz.
 102                 */
 103                if (freqs.new == FREQ_1P2_GHZ / 1000) {
 104                        regulator_set_voltage_tol(pu_reg,
 105                                        PU_SOC_VOLTAGE_HIGH, 0);
 106                        regulator_set_voltage_tol(soc_reg,
 107                                        PU_SOC_VOLTAGE_HIGH, 0);
 108                }
 109        }
 110
 111        /*
 112         * The setpoints are selected per PLL/PDF frequencies, so we need to
 113         * reprogram PLL for frequency scaling.  The procedure of reprogramming
 114         * PLL1 is as below.
 115         *
 116         *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
 117         *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
 118         *  - Disable pll2_pfd2_396m_clk
 119         */
 120        clk_prepare_enable(pll2_pfd2_396m_clk);
 121        clk_set_parent(step_clk, pll2_pfd2_396m_clk);
 122        clk_set_parent(pll1_sw_clk, step_clk);
 123        if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
 124                clk_set_rate(pll1_sys_clk, freqs.new * 1000);
 125                /*
 126                 * If we are leaving 396 MHz set-point, we need to enable
 127                 * pll1_sys_clk and disable pll2_pfd2_396m_clk to keep
 128                 * their use count correct.
 129                 */
 130                if (freqs.old * 1000 <= clk_get_rate(pll2_pfd2_396m_clk)) {
 131                        clk_prepare_enable(pll1_sys_clk);
 132                        clk_disable_unprepare(pll2_pfd2_396m_clk);
 133                }
 134                clk_set_parent(pll1_sw_clk, pll1_sys_clk);
 135                clk_disable_unprepare(pll2_pfd2_396m_clk);
 136        } else {
 137                /*
 138                 * Disable pll1_sys_clk if pll2_pfd2_396m_clk is sufficient
 139                 * to provide the frequency.
 140                 */
 141                clk_disable_unprepare(pll1_sys_clk);
 142        }
 143
 144        /* Ensure the arm clock divider is what we expect */
 145        ret = clk_set_rate(arm_clk, freqs.new * 1000);
 146        if (ret) {
 147                dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
 148                regulator_set_voltage_tol(arm_reg, volt_old, 0);
 149                freqs.new = freqs.old;
 150                goto post_notify;
 151        }
 152
 153        /* scaling down?  scale voltage after frequency */
 154        if (freqs.new < freqs.old) {
 155                ret = regulator_set_voltage_tol(arm_reg, volt, 0);
 156                if (ret) {
 157                        dev_warn(cpu_dev,
 158                                 "failed to scale vddarm down: %d\n", ret);
 159                        ret = 0;
 160                }
 161
 162                if (freqs.old == FREQ_1P2_GHZ / 1000) {
 163                        regulator_set_voltage_tol(pu_reg,
 164                                        PU_SOC_VOLTAGE_NORMAL, 0);
 165                        regulator_set_voltage_tol(soc_reg,
 166                                        PU_SOC_VOLTAGE_NORMAL, 0);
 167                }
 168        }
 169
 170post_notify:
 171        cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
 172
 173        return ret;
 174}
 175
 176static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
 177{
 178        int ret;
 179
 180        ret = cpufreq_frequency_table_cpuinfo(policy, freq_table);
 181        if (ret) {
 182                dev_err(cpu_dev, "invalid frequency table: %d\n", ret);
 183                return ret;
 184        }
 185
 186        policy->cpuinfo.transition_latency = transition_latency;
 187        policy->cur = clk_get_rate(arm_clk) / 1000;
 188        cpumask_setall(policy->cpus);
 189        cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
 190
 191        return 0;
 192}
 193
 194static int imx6q_cpufreq_exit(struct cpufreq_policy *policy)
 195{
 196        cpufreq_frequency_table_put_attr(policy->cpu);
 197        return 0;
 198}
 199
 200static struct freq_attr *imx6q_cpufreq_attr[] = {
 201        &cpufreq_freq_attr_scaling_available_freqs,
 202        NULL,
 203};
 204
 205static struct cpufreq_driver imx6q_cpufreq_driver = {
 206        .verify = imx6q_verify_speed,
 207        .target = imx6q_set_target,
 208        .get = imx6q_get_speed,
 209        .init = imx6q_cpufreq_init,
 210        .exit = imx6q_cpufreq_exit,
 211        .name = "imx6q-cpufreq",
 212        .attr = imx6q_cpufreq_attr,
 213};
 214
 215static int imx6q_cpufreq_probe(struct platform_device *pdev)
 216{
 217        struct device_node *np;
 218        struct opp *opp;
 219        unsigned long min_volt, max_volt;
 220        int num, ret;
 221
 222        cpu_dev = &pdev->dev;
 223
 224        np = of_find_node_by_path("/cpus/cpu@0");
 225        if (!np) {
 226                dev_err(cpu_dev, "failed to find cpu0 node\n");
 227                return -ENOENT;
 228        }
 229
 230        cpu_dev->of_node = np;
 231
 232        arm_clk = devm_clk_get(cpu_dev, "arm");
 233        pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys");
 234        pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw");
 235        step_clk = devm_clk_get(cpu_dev, "step");
 236        pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m");
 237        if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
 238            IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
 239                dev_err(cpu_dev, "failed to get clocks\n");
 240                ret = -ENOENT;
 241                goto put_node;
 242        }
 243
 244        arm_reg = devm_regulator_get(cpu_dev, "arm");
 245        pu_reg = devm_regulator_get(cpu_dev, "pu");
 246        soc_reg = devm_regulator_get(cpu_dev, "soc");
 247        if (IS_ERR(arm_reg) || IS_ERR(pu_reg) || IS_ERR(soc_reg)) {
 248                dev_err(cpu_dev, "failed to get regulators\n");
 249                ret = -ENOENT;
 250                goto put_node;
 251        }
 252
 253        /* We expect an OPP table supplied by platform */
 254        num = opp_get_opp_count(cpu_dev);
 255        if (num < 0) {
 256                ret = num;
 257                dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
 258                goto put_node;
 259        }
 260
 261        ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
 262        if (ret) {
 263                dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
 264                goto put_node;
 265        }
 266
 267        if (of_property_read_u32(np, "clock-latency", &transition_latency))
 268                transition_latency = CPUFREQ_ETERNAL;
 269
 270        /*
 271         * OPP is maintained in order of increasing frequency, and
 272         * freq_table initialised from OPP is therefore sorted in the
 273         * same order.
 274         */
 275        rcu_read_lock();
 276        opp = opp_find_freq_exact(cpu_dev,
 277                                  freq_table[0].frequency * 1000, true);
 278        min_volt = opp_get_voltage(opp);
 279        opp = opp_find_freq_exact(cpu_dev,
 280                                  freq_table[--num].frequency * 1000, true);
 281        max_volt = opp_get_voltage(opp);
 282        rcu_read_unlock();
 283        ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
 284        if (ret > 0)
 285                transition_latency += ret * 1000;
 286
 287        /* Count vddpu and vddsoc latency in for 1.2 GHz support */
 288        if (freq_table[num].frequency == FREQ_1P2_GHZ / 1000) {
 289                ret = regulator_set_voltage_time(pu_reg, PU_SOC_VOLTAGE_NORMAL,
 290                                                 PU_SOC_VOLTAGE_HIGH);
 291                if (ret > 0)
 292                        transition_latency += ret * 1000;
 293                ret = regulator_set_voltage_time(soc_reg, PU_SOC_VOLTAGE_NORMAL,
 294                                                 PU_SOC_VOLTAGE_HIGH);
 295                if (ret > 0)
 296                        transition_latency += ret * 1000;
 297        }
 298
 299        ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
 300        if (ret) {
 301                dev_err(cpu_dev, "failed register driver: %d\n", ret);
 302                goto free_freq_table;
 303        }
 304
 305        of_node_put(np);
 306        return 0;
 307
 308free_freq_table:
 309        opp_free_cpufreq_table(cpu_dev, &freq_table);
 310put_node:
 311        of_node_put(np);
 312        return ret;
 313}
 314
 315static int imx6q_cpufreq_remove(struct platform_device *pdev)
 316{
 317        cpufreq_unregister_driver(&imx6q_cpufreq_driver);
 318        opp_free_cpufreq_table(cpu_dev, &freq_table);
 319
 320        return 0;
 321}
 322
 323static struct platform_driver imx6q_cpufreq_platdrv = {
 324        .driver = {
 325                .name   = "imx6q-cpufreq",
 326                .owner  = THIS_MODULE,
 327        },
 328        .probe          = imx6q_cpufreq_probe,
 329        .remove         = imx6q_cpufreq_remove,
 330};
 331module_platform_driver(imx6q_cpufreq_platdrv);
 332
 333MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
 334MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
 335MODULE_LICENSE("GPL");
 336
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