linux/Documentation/scsi/hptiop.txt
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   1HIGHPOINT ROCKETRAID 3xxx/4xxx ADAPTER DRIVER (hptiop)
   2
   3Controller Register Map
   4-------------------------
   5
   6For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2:
   7
   8     BAR0 offset    Register
   9            0x11C5C Link Interface IRQ Set
  10            0x11C60 Link Interface IRQ Clear
  11
  12     BAR2 offset    Register
  13            0x10    Inbound Message Register 0
  14            0x14    Inbound Message Register 1
  15            0x18    Outbound Message Register 0
  16            0x1C    Outbound Message Register 1
  17            0x20    Inbound Doorbell Register
  18            0x24    Inbound Interrupt Status Register
  19            0x28    Inbound Interrupt Mask Register
  20            0x30    Outbound Interrupt Status Register
  21            0x34    Outbound Interrupt Mask Register
  22            0x40    Inbound Queue Port
  23            0x44    Outbound Queue Port
  24
  25For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0:
  26
  27     BAR0 offset    Register
  28            0x10    Inbound Message Register 0
  29            0x14    Inbound Message Register 1
  30            0x18    Outbound Message Register 0
  31            0x1C    Outbound Message Register 1
  32            0x20    Inbound Doorbell Register
  33            0x24    Inbound Interrupt Status Register
  34            0x28    Inbound Interrupt Mask Register
  35            0x30    Outbound Interrupt Status Register
  36            0x34    Outbound Interrupt Mask Register
  37            0x40    Inbound Queue Port
  38            0x44    Outbound Queue Port
  39
  40For Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
  41
  42     BAR0 offset    Register
  43         0x20400    Inbound Doorbell Register
  44         0x20404    Inbound Interrupt Mask Register
  45         0x20408    Outbound Doorbell Register
  46         0x2040C    Outbound Interrupt Mask Register
  47
  48     BAR1 offset    Register
  49             0x0    Inbound Queue Head Pointer
  50             0x4    Inbound Queue Tail Pointer
  51             0x8    Outbound Queue Head Pointer
  52             0xC    Outbound Queue Tail Pointer
  53            0x10    Inbound Message Register
  54            0x14    Outbound Message Register
  55     0x40-0x1040    Inbound Queue
  56   0x1040-0x2040    Outbound Queue
  57
  58For Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
  59
  60     BAR0 offset    Register
  61             0x0    IOP configuration information.
  62
  63     BAR1 offset    Register
  64          0x4000    Inbound List Base Address Low
  65          0x4004    Inbound List Base Address High
  66          0x4018    Inbound List Write Pointer
  67          0x402C    Inbound List Configuration and Control
  68          0x4050    Outbound List Base Address Low
  69          0x4054    Outbound List Base Address High
  70          0x4058    Outbound List Copy Pointer Shadow Base Address Low
  71          0x405C    Outbound List Copy Pointer Shadow Base Address High
  72          0x4088    Outbound List Interrupt Cause
  73          0x408C    Outbound List Interrupt Enable
  74         0x1020C    PCIe Function 0 Interrupt Enable
  75         0x10400    PCIe Function 0 to CPU Message A
  76         0x10420    CPU to PCIe Function 0 Message A
  77         0x10480    CPU to PCIe Function 0 Doorbell
  78         0x10484    CPU to PCIe Function 0 Doorbell Enable
  79
  80
  81I/O Request Workflow of Not Marvell Frey
  82------------------------------------------
  83
  84All queued requests are handled via inbound/outbound queue port.
  85A request packet can be allocated in either IOP or host memory.
  86
  87To send a request to the controller:
  88
  89    - Get a free request packet by reading the inbound queue port or
  90      allocate a free request in host DMA coherent memory.
  91
  92      The value returned from the inbound queue port is an offset
  93      relative to the IOP BAR0.
  94
  95      Requests allocated in host memory must be aligned on 32-bytes boundary.
  96
  97    - Fill the packet.
  98
  99    - Post the packet to IOP by writing it to inbound queue. For requests
 100      allocated in IOP memory, write the offset to inbound queue port. For
 101      requests allocated in host memory, write (0x80000000|(bus_addr>>5))
 102      to the inbound queue port.
 103
 104    - The IOP process the request. When the request is completed, it
 105      will be put into outbound queue. An outbound interrupt will be
 106      generated.
 107
 108      For requests allocated in IOP memory, the request offset is posted to
 109      outbound queue.
 110
 111      For requests allocated in host memory, (0x80000000|(bus_addr>>5))
 112      is posted to the outbound queue. If IOP_REQUEST_FLAG_OUTPUT_CONTEXT
 113      flag is set in the request, the low 32-bit context value will be
 114      posted instead.
 115
 116    - The host read the outbound queue and complete the request.
 117
 118      For requests allocated in IOP memory, the host driver free the request
 119      by writing it to the outbound queue.
 120
 121Non-queued requests (reset/flush etc) can be sent via inbound message
 122register 0. An outbound message with the same value indicates the completion
 123of an inbound message.
 124
 125
 126I/O Request Workflow of Marvell Frey
 127--------------------------------------
 128
 129All queued requests are handled via inbound/outbound list.
 130
 131To send a request to the controller:
 132
 133    - Allocate a free request in host DMA coherent memory.
 134
 135      Requests allocated in host memory must be aligned on 32-bytes boundary.
 136
 137    - Fill the request with index of the request in the flag.
 138
 139      Fill a free inbound list unit with the physical address and the size of
 140      the request.
 141
 142      Set up the inbound list write pointer with the index of previous unit,
 143      round to 0 if the index reaches the supported count of requests.
 144
 145    - Post the inbound list writer pointer to IOP.
 146
 147    - The IOP process the request. When the request is completed, the flag of
 148      the request with or-ed IOPMU_QUEUE_MASK_HOST_BITS will be put into a
 149      free outbound list unit and the index of the outbound list unit will be
 150      put into the copy pointer shadow register. An outbound interrupt will be
 151      generated.
 152
 153    - The host read the outbound list copy pointer shadow register and compare
 154      with previous saved read ponter N. If they are different, the host will
 155      read the (N+1)th outbound list unit.
 156
 157      The host get the index of the request from the (N+1)th outbound list
 158      unit and complete the request.
 159
 160Non-queued requests (reset communication/reset/flush etc) can be sent via PCIe
 161Function 0 to CPU Message A register. The CPU to PCIe Function 0 Message register
 162with the same value indicates the completion of message.
 163
 164
 165User-level Interface
 166---------------------
 167
 168The driver exposes following sysfs attributes:
 169
 170     NAME                 R/W    Description
 171     driver-version        R     driver version string
 172     firmware-version      R     firmware version string
 173
 174
 175-----------------------------------------------------------------------------
 176Copyright (C) 2006-2012 HighPoint Technologies, Inc. All Rights Reserved.
 177
 178  This file is distributed in the hope that it will be useful,
 179  but WITHOUT ANY WARRANTY; without even the implied warranty of
 180  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 181  GNU General Public License for more details.
 182
 183  linux@highpoint-tech.com
 184  http://www.highpoint-tech.com
 185
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