linux/Documentation/device-mapper/cache-policies.txt
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h<1/fa>Guidance orm writing policies < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L2" id"vL2" class="line" nam="vL2"> h<2/fa>============================= < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L3" id"vL3" class="line" nam="vL3"> h<3/fa> < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L4" id"vL4" class="line" nam="vL4"> h<4/fa>Try to keep transacion>ality out of it. Thf coef is caef=ul to < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L5" id"vL5" class="line" nam="vL5"> h<5/fa>avoid asking about anything that is migrating. This is a pain, but < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L6" id"vL6" class="line" nam="vL6"> h<6/fa>makes it easier to write the policies. < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L7" id"vL7" class="line" nam="vL7"> h<7/fa> < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L8" id"vL8" class="line" nam="vL8"> h<8/fa>Mappings aef loaded into the policy at construcion> time. < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L9" id"vL9" class="line" nam="vL9"> h<9/fa> < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L10" id"vL10" class="line" nam="vL10"> h0Every bio that is mapped by the target is ef=erred to the policy. < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L11" id"vL11" class="line" nam="vL11"> h11/fa>The policy cn> return a simple HIT rm MISS rm issue a migration. < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L12" id"vL12" class="line" nam="vL12"> h12/fa> < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L13" id"vL13" class="line" nam="vL13"> h13/fa>Currently there's no way orm the policy to issue background work, < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L14" id"vL14" class="line" nam="vL14"> h14/fa>e.g. to satrt writing back dirty blocks that aef going to be ;victe < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L15" id"vL15" class="line" nam="vL15"> h15/fa>soon. < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L16" id"vL16" class="line" nam="vL16"> h16/fa> < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L17" id"vL17" class="line" nam="vL17"> h17/fa>Because we map bios, rather thn> requests it's easy orm the policy < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L18" id"vL18" class="line" nam="vL18"> h18/fa>to get fooled by many small bios. Frm this efasn> thf coef target < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L19" id"vL19" class="line" nam="vL19"> h19/fa>issues periodic ticks to the policy. It's suggested that the policy < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L20" id"vL20" class="line" nam="vL20"> h2doesn't update saties (eg, hit coutas) orm a block moef thn> once < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L21" id"vL21" class="line" nam="vL21"> h21/fa>orm each tick. Thf coef ticks by watching bios complete, and so < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L22" id"vL22" class="line" nam="vL22"> h22/fa>trying to see whe> thf io scheduler has let thf ios eun. < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L23" id"vL23" class="line" nam="vL23"> h23/fa> < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L24" id"vL24" class="line" nam="vL24"> h24/fa> < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L25" id"vL25" class="line" nam="vL25"> h25/fa>Overview of supplied cache efplaceenta policies < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L26" id"vL26" class="line" nam="vL26"> h26/fa>=============================================== < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L27" id"vL27" class="line" nam="vL27"> h27/fa> < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L28" id"vL28" class="line" nam="vL28"> h28/fa>multiqueue < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L29" id"vL29" class="line" nam="vL29"> h29/fa>---------- < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L30" id"vL30" class="line" nam="vL30"> h30/fa> < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L31" id"vL31" class="line" nam="vL31"> h31/fa>This policy is thf default. < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L32" id"vL32" class="line" nam="vL32"> h32/fa> < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L33" id"vL33" class="line" nam="vL33"> h33/fa>The multiqueue policy has two sets of 16 queues: one set orm ntaries < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L34" id"vL34" class="line" nam="vL34"> h34/fa>waiting orm the cache and another one orm those in the cache. < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L35" id"vL35" class="line" nam="vL35"> h35/fa>Cache ntaries in the queues aef aged based n> logical time. Etary into < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L36" id"vL36" class="line" nam="vL36"> h36/fa>the cache is based n> variablf thresholds and queue elect>on> is based < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L37" id"vL37" class="line" nam="vL37"> h37/fa>n> hit couta n> ntary. The policy aims to takf dif=ernta cache miss < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L38" id"vL38" class="line" nam="vL38"> h38/fa>costs into accouta and to adjust to varying load patterns automtiocally. < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L39" id"vL39" class="line" nam="vL39"> h39/fa> < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L40" id"vL40" class="line" nam="vL40"> h40/fa>Message and construcirm arguenta pairs aef: < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L41" id"vL41" class="line" nam="vL41"> h41/fa> 'sequential_threshold <#nr_sequential_ios>' and < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L42" id"vL42" class="line" nam="vL42"> h42/fa> 'random_threshold <#nr_random_ios>'. < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L43" id"vL43" class="line" nam="vL43"> h43/fa> < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L44" id"vL44" class="line" nam="vL44"> h44/fa>The sequential threshold indicties the number of contiguous I/Os < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L45" id"vL45" class="line" nam="vL45"> h45/fa>required befoef a saefam is tefated as sequential. Thf random threshold < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L46" id"vL46" class="line" nam="vL46"> h46/fa>is the number of intervening non-contiguous I/Os that must be seen < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L47" id"vL47" class="line" nam="vL47"> h47/fa>befoef the saefam is tefated as random again. < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L48" id"vL48" class="line" nam="vL48"> h48/fa> < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L49" id"vL49" class="line" nam="vL49"> h49/fa>The sequential and random thresholds default to 512 and 4 efspct>ovely. < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L50" id"vL50" class="line" nam="vL50"> h50/fa> < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L51" id"vL51" class="line" nam="vL51"> h51/fa>Large, sequential ios aef probably better lefa n> the origin 2;vice < ref=".ocnmentation>/2;vice-mapper/cache-policies.txt#L52" id"vL52" class="line" nam="vL52"> h52/fa>since spindles tend to havf good bandwidth. The so_traukhe- claf good butat5cnmentation>/2;vice-map5er/ca53e-polie" nam="vL46"> m="policispot2" id"vL22" ci35" ine" " ivL2scies.txt#L49indles tend to havf good bandwidth. The so_traukhe- claf go ref=".5cnmentation>/2;vice-map5er/ca5he-pomodne" nam="vL6"> h<6/fa>makes it easier to write the policies. 5< ref="..ocnmentation>/2;vice-maer/ca55e-policies.txt#L50" id"vL50" class="line" nam="vL50"> h50/fa> < ref=".5cnmentation>/2;vice-map5er/ca5he-pocleanerlicies.txt#L50" id"vL50" class="line" nam="vL50"> h50/fa> < ref=".5cnmentation>/2;vice-map5er/ca57e-policies.licies.txt#L50" id"vL50" class="line" nam="vL50"> h50/fa> < ref=".5cnmentation>/2;vice-map5er/ca5he-policies.txt#L48" id"vL48" class="line" nam="vL48"> h48/fa> 5 ref=".5cnmentation>/2;vice-map5er/ca5he-policicleanerid"vL6s14" cl claass="line" naiL11"n> hiticidecom couhe caclass="line" nam="vL31"> h31/fa>This policy is thf default. 6 ref=".6cnmentation>/2;vice-map6er/ca6he-policies.txt#L50" id"vL50" class="line" nam="vL50"> h50/fa> 6 ref=".6cnmentation>/2;vice-map6er/ca6he-poExah21/pindles tend to havf good bandwidth. The so_traukhe- claf g6 ref=".6cnmentation>/2;vice-map6er/ca6cache-policieindles tend to havf good bandwidth. The so_traukhe- claf g6od butat6cnmentation>/2;vice-map6er/ca6he-policies.txt#L43" id"vL43" class="line" nam="vL43"> h43/fa> 6 ref=".6cnmentation>/2;vice-map6er/ca6he-policieyid"x"vL20">tlass=is"vL40"> h40/fa>Message and construcirm arguenta pairs aef: 6< ref="6.ocnmentation>/2;vice-m6er/ca65e-policies.tn> hit="limetadatage, > h4t="lin> hite, > h4t="lifa>Large, > h4t="li h2 h4vL40"> h40/fa>Message and construcirm arguenta pairs aef: 6< ref="..ocnmentation>/2;vice-maer/ca66e-policies.tx"linf" cure_ici"> h4 [x"lif" cure" cl> h4]*vL40"> h40/fa>Message and construcirm arguenta pairs aef: 6 ref=".6cnmentation>/2;vice-map6er/ca67e-policies.tx"liass="l> h4t="li#ass="l_ici"> h4 [x"liass="lincl> h4]*vL40"> h40/fa>Message and construcirm arguenta pairs aef: 6 ref=".6cnmentation>/2;vice-map6er/ca6he-policies.txt#L48" id"vL48" class="line" nam="vL48"> h48/fa> 6 ref=".6cnmentation>/2;vice-map6er/ca69e-policieyid"x"txt#L" cl micies.tus" clasitemsetup"> hm9/fais"vL40"> h40/fa>Message and construcirm arguenta pairs aef: 7 ref=".7cnmentation>/2;vice-map7er/ca70e-policies.temsetup"micies.t="limvL10" d cons> h4 0 1" id"vL41" class="li1024vL40"> h40/fa>Message and construcirm arguenta pairs aef: 7 ref=".7cnmentation>/2;vice-map7er/ca71e-policies.temsetup"micies.t="limvL10" d cons> h4 0 2" id"vL42" class8vL40"> h40/fa>Message and construcirm arguenta pairs aef: 7 ref=".7cnmentation>/2;vice-map7er/ca7he-policies.txt#L32" id"vL32" class="line" nam="vL32"> h32/fa> 7od butat7cnmentation>/2;vice-map7er/ca7he-poUs" clemsetup"vL40"> h40/fa>Message and construcirm arguenta pairs aef: 7 ref=".7cnmentation>/2;vice-map7er/ca74e-policies.temsetup"c7" cllinah --tlass="0 268435456tn> hitnd c/sdbtnd c/sdc \vL40"> h40/fa>Message and construcirm arguenta pairs aef: 7< ref="7.ocnmentation>/2;vice-m7er/ca75e-policies.tttttnd c/sdd"> h40 mqa>T1" id"vL41" class="li1024 2" id"vL42" class8"vL40"> h40/fa>Message and construcirm arguenta pairs aef: 7< ref="7.ocnmentation>/2;vice-m7er/ca76e-policies.tc7" clfa>a128GB licie mvL10" d cons2;vicdtxt#L4inah &withlasivL40"> h40/fa>Message and construcirm arguenta pairs aef: 7< ref="..ocnmentation>/2;vice-maer/ca77e-policies.tes.txt#L44" id"vL44" /fa>txt1024 vL38"/fa>requi_ id"vL44" /fa>txt8" nam="vL6"> h<6/fa>makes it easier to write the policies. < ref=".7cnmentation>/2;vice-map7er/ca7he-po T51/fa>Lar44"LXR softw1" cclass="nam="vL6"http://sourciciege.net/projects/lxm">LXR > hmunitye-po,nam="vextxt#6/fa>l veruhe cclanam="vL6"mailto:lxm@/sele.no">lxm@/sele.noe-po. div id"searcentatiosubfoonam"> lxm./sele.no kxt#Ly ho9/fa>clanam="vL6"http://www.redpill-/sepro.no">Redpill Lsepro ASe-po,nprovidL46" iLseleL40" s.txtxt#L38otxt>make namrt ea naicies1995. div id"vs/bodyd"s/htmlv"