linux/drivers/video/mxsfb.c
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   1/*
   2 * Copyright (C) 2010 Juergen Beisert, Pengutronix
   3 *
   4 * This code is based on:
   5 * Author: Vitaly Wool <vital@embeddedalley.com>
   6 *
   7 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
   8 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   9 *
  10 * This program is free software; you can redistribute it and/or
  11 * modify it under the terms of the GNU General Public License
  12 * as published by the Free Software Foundation; either version 2
  13 * of the License, or (at your option) any later version.
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 */
  19
  20#define DRIVER_NAME "mxsfb"
  21
  22/**
  23 * @file
  24 * @brief LCDIF driver for i.MX23 and i.MX28
  25 *
  26 * The LCDIF support four modes of operation
  27 * - MPU interface (to drive smart displays) -> not supported yet
  28 * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet
  29 * - Dotclock interface (to drive LC displays with RGB data and sync signals)
  30 * - DVI (to drive ITU-R BT656)  -> not supported yet
  31 *
  32 * This driver depends on a correct setup of the pins used for this purpose
  33 * (platform specific).
  34 *
  35 * For the developer: Don't forget to set the data bus width to the display
  36 * in the imx_fb_videomode structure. You will else end up with ugly colours.
  37 * If you fight against jitter you can vary the clock delay. This is a feature
  38 * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give
  39 * the required value in the imx_fb_videomode structure.
  40 */
  41
  42#include <linux/module.h>
  43#include <linux/kernel.h>
  44#include <linux/of_device.h>
  45#include <linux/platform_device.h>
  46#include <linux/clk.h>
  47#include <linux/dma-mapping.h>
  48#include <linux/io.h>
  49#include <linux/pinctrl/consumer.h>
  50#include <linux/fb.h>
  51#include <linux/regulator/consumer.h>
  52#include <video/of_display_timing.h>
  53#include <video/videomode.h>
  54
  55#define REG_SET 4
  56#define REG_CLR 8
  57
  58#define LCDC_CTRL                       0x00
  59#define LCDC_CTRL1                      0x10
  60#define LCDC_V4_CTRL2                   0x20
  61#define LCDC_V3_TRANSFER_COUNT          0x20
  62#define LCDC_V4_TRANSFER_COUNT          0x30
  63#define LCDC_V4_CUR_BUF                 0x40
  64#define LCDC_V4_NEXT_BUF                0x50
  65#define LCDC_V3_CUR_BUF                 0x30
  66#define LCDC_V3_NEXT_BUF                0x40
  67#define LCDC_TIMING                     0x60
  68#define LCDC_VDCTRL0                    0x70
  69#define LCDC_VDCTRL1                    0x80
  70#define LCDC_VDCTRL2                    0x90
  71#define LCDC_VDCTRL3                    0xa0
  72#define LCDC_VDCTRL4                    0xb0
  73#define LCDC_DVICTRL0                   0xc0
  74#define LCDC_DVICTRL1                   0xd0
  75#define LCDC_DVICTRL2                   0xe0
  76#define LCDC_DVICTRL3                   0xf0
  77#define LCDC_DVICTRL4                   0x100
  78#define LCDC_V4_DATA                    0x180
  79#define LCDC_V3_DATA                    0x1b0
  80#define LCDC_V4_DEBUG0                  0x1d0
  81#define LCDC_V3_DEBUG0                  0x1f0
  82
  83#define CTRL_SFTRST                     (1 << 31)
  84#define CTRL_CLKGATE                    (1 << 30)
  85#define CTRL_BYPASS_COUNT               (1 << 19)
  86#define CTRL_VSYNC_MODE                 (1 << 18)
  87#define CTRL_DOTCLK_MODE                (1 << 17)
  88#define CTRL_DATA_SELECT                (1 << 16)
  89#define CTRL_SET_BUS_WIDTH(x)           (((x) & 0x3) << 10)
  90#define CTRL_GET_BUS_WIDTH(x)           (((x) >> 10) & 0x3)
  91#define CTRL_SET_WORD_LENGTH(x)         (((x) & 0x3) << 8)
  92#define CTRL_GET_WORD_LENGTH(x)         (((x) >> 8) & 0x3)
  93#define CTRL_MASTER                     (1 << 5)
  94#define CTRL_DF16                       (1 << 3)
  95#define CTRL_DF18                       (1 << 2)
  96#define CTRL_DF24                       (1 << 1)
  97#define CTRL_RUN                        (1 << 0)
  98
  99#define CTRL1_FIFO_CLEAR                (1 << 21)
 100#define CTRL1_SET_BYTE_PACKAGING(x)     (((x) & 0xf) << 16)
 101#define CTRL1_GET_BYTE_PACKAGING(x)     (((x) >> 16) & 0xf)
 102
 103#define TRANSFER_COUNT_SET_VCOUNT(x)    (((x) & 0xffff) << 16)
 104#define TRANSFER_COUNT_GET_VCOUNT(x)    (((x) >> 16) & 0xffff)
 105#define TRANSFER_COUNT_SET_HCOUNT(x)    ((x) & 0xffff)
 106#define TRANSFER_COUNT_GET_HCOUNT(x)    ((x) & 0xffff)
 107
 108
 109#define VDCTRL0_ENABLE_PRESENT          (1 << 28)
 110#define VDCTRL0_VSYNC_ACT_HIGH          (1 << 27)
 111#define VDCTRL0_HSYNC_ACT_HIGH          (1 << 26)
 112#define VDCTRL0_DOTCLK_ACT_FALLING      (1 << 25)
 113#define VDCTRL0_ENABLE_ACT_HIGH         (1 << 24)
 114#define VDCTRL0_VSYNC_PERIOD_UNIT       (1 << 21)
 115#define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT  (1 << 20)
 116#define VDCTRL0_HALF_LINE               (1 << 19)
 117#define VDCTRL0_HALF_LINE_MODE          (1 << 18)
 118#define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
 119#define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
 120
 121#define VDCTRL2_SET_HSYNC_PERIOD(x)     ((x) & 0x3ffff)
 122#define VDCTRL2_GET_HSYNC_PERIOD(x)     ((x) & 0x3ffff)
 123
 124#define VDCTRL3_MUX_SYNC_SIGNALS        (1 << 29)
 125#define VDCTRL3_VSYNC_ONLY              (1 << 28)
 126#define SET_HOR_WAIT_CNT(x)             (((x) & 0xfff) << 16)
 127#define GET_HOR_WAIT_CNT(x)             (((x) >> 16) & 0xfff)
 128#define SET_VERT_WAIT_CNT(x)            ((x) & 0xffff)
 129#define GET_VERT_WAIT_CNT(x)            ((x) & 0xffff)
 130
 131#define VDCTRL4_SET_DOTCLK_DLY(x)       (((x) & 0x7) << 29) /* v4 only */
 132#define VDCTRL4_GET_DOTCLK_DLY(x)       (((x) >> 29) & 0x7) /* v4 only */
 133#define VDCTRL4_SYNC_SIGNALS_ON         (1 << 18)
 134#define SET_DOTCLK_H_VALID_DATA_CNT(x)  ((x) & 0x3ffff)
 135
 136#define DEBUG0_HSYNC                    (1 < 26)
 137#define DEBUG0_VSYNC                    (1 < 25)
 138
 139#define MIN_XRES                        120
 140#define MIN_YRES                        120
 141
 142#define RED 0
 143#define GREEN 1
 144#define BLUE 2
 145#define TRANSP 3
 146
 147#define STMLCDIF_8BIT  1 /** pixel data bus to the display is of 8 bit width */
 148#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */
 149#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */
 150#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */
 151
 152#define MXSFB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6)
 153#define MXSFB_SYNC_DOTCLK_FALLING_ACT   (1 << 7) /* negtive edge sampling */
 154
 155enum mxsfb_devtype {
 156        MXSFB_V3,
 157        MXSFB_V4,
 158};
 159
 160/* CPU dependent register offsets */
 161struct mxsfb_devdata {
 162        unsigned transfer_count;
 163        unsigned cur_buf;
 164        unsigned next_buf;
 165        unsigned debug0;
 166        unsigned hs_wdth_mask;
 167        unsigned hs_wdth_shift;
 168        unsigned ipversion;
 169};
 170
 171struct mxsfb_info {
 172        struct fb_info fb_info;
 173        struct platform_device *pdev;
 174        struct clk *clk;
 175        void __iomem *base;     /* registers */
 176        unsigned allocated_size;
 177        int enabled;
 178        unsigned ld_intf_width;
 179        unsigned dotclk_delay;
 180        const struct mxsfb_devdata *devdata;
 181        u32 sync;
 182        struct regulator *reg_lcd;
 183};
 184
 185#define mxsfb_is_v3(host) (host->devdata->ipversion == 3)
 186#define mxsfb_is_v4(host) (host->devdata->ipversion == 4)
 187
 188static const struct mxsfb_devdata mxsfb_devdata[] = {
 189        [MXSFB_V3] = {
 190                .transfer_count = LCDC_V3_TRANSFER_COUNT,
 191                .cur_buf = LCDC_V3_CUR_BUF,
 192                .next_buf = LCDC_V3_NEXT_BUF,
 193                .debug0 = LCDC_V3_DEBUG0,
 194                .hs_wdth_mask = 0xff,
 195                .hs_wdth_shift = 24,
 196                .ipversion = 3,
 197        },
 198        [MXSFB_V4] = {
 199                .transfer_count = LCDC_V4_TRANSFER_COUNT,
 200                .cur_buf = LCDC_V4_CUR_BUF,
 201                .next_buf = LCDC_V4_NEXT_BUF,
 202                .debug0 = LCDC_V4_DEBUG0,
 203                .hs_wdth_mask = 0x3fff,
 204                .hs_wdth_shift = 18,
 205                .ipversion = 4,
 206        },
 207};
 208
 209#define to_imxfb_host(x) (container_of(x, struct mxsfb_info, fb_info))
 210
 211/* mask and shift depends on architecture */
 212static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
 213{
 214        return (val & host->devdata->hs_wdth_mask) <<
 215                host->devdata->hs_wdth_shift;
 216}
 217
 218static inline u32 get_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
 219{
 220        return (val >> host->devdata->hs_wdth_shift) &
 221                host->devdata->hs_wdth_mask;
 222}
 223
 224static const struct fb_bitfield def_rgb565[] = {
 225        [RED] = {
 226                .offset = 11,
 227                .length = 5,
 228        },
 229        [GREEN] = {
 230                .offset = 5,
 231                .length = 6,
 232        },
 233        [BLUE] = {
 234                .offset = 0,
 235                .length = 5,
 236        },
 237        [TRANSP] = {    /* no support for transparency */
 238                .length = 0,
 239        }
 240};
 241
 242static const struct fb_bitfield def_rgb666[] = {
 243        [RED] = {
 244                .offset = 16,
 245                .length = 6,
 246        },
 247        [GREEN] = {
 248                .offset = 8,
 249                .length = 6,
 250        },
 251        [BLUE] = {
 252                .offset = 0,
 253                .length = 6,
 254        },
 255        [TRANSP] = {    /* no support for transparency */
 256                .length = 0,
 257        }
 258};
 259
 260static const struct fb_bitfield def_rgb888[] = {
 261        [RED] = {
 262                .offset = 16,
 263                .length = 8,
 264        },
 265        [GREEN] = {
 266                .offset = 8,
 267                .length = 8,
 268        },
 269        [BLUE] = {
 270                .offset = 0,
 271                .length = 8,
 272        },
 273        [TRANSP] = {    /* no support for transparency */
 274                .length = 0,
 275        }
 276};
 277
 278static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf)
 279{
 280        chan &= 0xffff;
 281        chan >>= 16 - bf->length;
 282        return chan << bf->offset;
 283}
 284
 285static int mxsfb_check_var(struct fb_var_screeninfo *var,
 286                struct fb_info *fb_info)
 287{
 288        struct mxsfb_info *host = to_imxfb_host(fb_info);
 289        const struct fb_bitfield *rgb = NULL;
 290
 291        if (var->xres < MIN_XRES)
 292                var->xres = MIN_XRES;
 293        if (var->yres < MIN_YRES)
 294                var->yres = MIN_YRES;
 295
 296        var->xres_virtual = var->xres;
 297
 298        var->yres_virtual = var->yres;
 299
 300        switch (var->bits_per_pixel) {
 301        case 16:
 302                /* always expect RGB 565 */
 303                rgb = def_rgb565;
 304                break;
 305        case 32:
 306                switch (host->ld_intf_width) {
 307                case STMLCDIF_8BIT:
 308                        pr_debug("Unsupported LCD bus width mapping\n");
 309                        break;
 310                case STMLCDIF_16BIT:
 311                case STMLCDIF_18BIT:
 312                        /* 24 bit to 18 bit mapping */
 313                        rgb = def_rgb666;
 314                        break;
 315                case STMLCDIF_24BIT:
 316                        /* real 24 bit */
 317                        rgb = def_rgb888;
 318                        break;
 319                }
 320                break;
 321        default:
 322                pr_debug("Unsupported colour depth: %u\n", var->bits_per_pixel);
 323                return -EINVAL;
 324        }
 325
 326        /*
 327         * Copy the RGB parameters for this display
 328         * from the machine specific parameters.
 329         */
 330        var->red    = rgb[RED];
 331        var->green  = rgb[GREEN];
 332        var->blue   = rgb[BLUE];
 333        var->transp = rgb[TRANSP];
 334
 335        return 0;
 336}
 337
 338static void mxsfb_enable_controller(struct fb_info *fb_info)
 339{
 340        struct mxsfb_info *host = to_imxfb_host(fb_info);
 341        u32 reg;
 342        int ret;
 343
 344        dev_dbg(&host->pdev->dev, "%s\n", __func__);
 345
 346        if (host->reg_lcd) {
 347                ret = regulator_enable(host->reg_lcd);
 348                if (ret) {
 349                        dev_err(&host->pdev->dev,
 350                                "lcd regulator enable failed:   %d\n", ret);
 351                        return;
 352                }
 353        }
 354
 355        clk_prepare_enable(host->clk);
 356        clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U);
 357
 358        /* if it was disabled, re-enable the mode again */
 359        writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET);
 360
 361        /* enable the SYNC signals first, then the DMA engine */
 362        reg = readl(host->base + LCDC_VDCTRL4);
 363        reg |= VDCTRL4_SYNC_SIGNALS_ON;
 364        writel(reg, host->base + LCDC_VDCTRL4);
 365
 366        writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET);
 367
 368        host->enabled = 1;
 369}
 370
 371static void mxsfb_disable_controller(struct fb_info *fb_info)
 372{
 373        struct mxsfb_info *host = to_imxfb_host(fb_info);
 374        unsigned loop;
 375        u32 reg;
 376        int ret;
 377
 378        dev_dbg(&host->pdev->dev, "%s\n", __func__);
 379
 380        /*
 381         * Even if we disable the controller here, it will still continue
 382         * until its FIFOs are running out of data
 383         */
 384        writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_CLR);
 385
 386        loop = 1000;
 387        while (loop) {
 388                reg = readl(host->base + LCDC_CTRL);
 389                if (!(reg & CTRL_RUN))
 390                        break;
 391                loop--;
 392        }
 393
 394        reg = readl(host->base + LCDC_VDCTRL4);
 395        writel(reg & ~VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4);
 396
 397        clk_disable_unprepare(host->clk);
 398
 399        host->enabled = 0;
 400
 401        if (host->reg_lcd) {
 402                ret = regulator_disable(host->reg_lcd);
 403                if (ret)
 404                        dev_err(&host->pdev->dev,
 405                                "lcd regulator disable failed: %d\n", ret);
 406        }
 407}
 408
 409static int mxsfb_set_par(struct fb_info *fb_info)
 410{
 411        struct mxsfb_info *host = to_imxfb_host(fb_info);
 412        u32 ctrl, vdctrl0, vdctrl4;
 413        int line_size, fb_size;
 414        int reenable = 0;
 415
 416        line_size =  fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3);
 417        fb_size = fb_info->var.yres_virtual * line_size;
 418
 419        if (fb_size > fb_info->fix.smem_len)
 420                return -ENOMEM;
 421
 422        fb_info->fix.line_length = line_size;
 423
 424        /*
 425         * It seems, you can't re-program the controller if it is still running.
 426         * This may lead into shifted pictures (FIFO issue?).
 427         * So, first stop the controller and drain its FIFOs
 428         */
 429        if (host->enabled) {
 430                reenable = 1;
 431                mxsfb_disable_controller(fb_info);
 432        }
 433
 434        /* clear the FIFOs */
 435        writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET);
 436
 437        ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER |
 438                CTRL_SET_BUS_WIDTH(host->ld_intf_width);
 439
 440        switch (fb_info->var.bits_per_pixel) {
 441        case 16:
 442                dev_dbg(&host->pdev->dev, "Setting up RGB565 mode\n");
 443                ctrl |= CTRL_SET_WORD_LENGTH(0);
 444                writel(CTRL1_SET_BYTE_PACKAGING(0xf), host->base + LCDC_CTRL1);
 445                break;
 446        case 32:
 447                dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n");
 448                ctrl |= CTRL_SET_WORD_LENGTH(3);
 449                switch (host->ld_intf_width) {
 450                case STMLCDIF_8BIT:
 451                        dev_dbg(&host->pdev->dev,
 452                                        "Unsupported LCD bus width mapping\n");
 453                        return -EINVAL;
 454                case STMLCDIF_16BIT:
 455                case STMLCDIF_18BIT:
 456                        /* 24 bit to 18 bit mapping */
 457                        ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
 458                                            *  each colour component
 459                                            */
 460                        break;
 461                case STMLCDIF_24BIT:
 462                        /* real 24 bit */
 463                        break;
 464                }
 465                /* do not use packed pixels = one pixel per word instead */
 466                writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1);
 467                break;
 468        default:
 469                dev_dbg(&host->pdev->dev, "Unhandled color depth of %u\n",
 470                                fb_info->var.bits_per_pixel);
 471                return -EINVAL;
 472        }
 473
 474        writel(ctrl, host->base + LCDC_CTRL);
 475
 476        writel(TRANSFER_COUNT_SET_VCOUNT(fb_info->var.yres) |
 477                        TRANSFER_COUNT_SET_HCOUNT(fb_info->var.xres),
 478                        host->base + host->devdata->transfer_count);
 479
 480        vdctrl0 = VDCTRL0_ENABLE_PRESENT |      /* always in DOTCLOCK mode */
 481                VDCTRL0_VSYNC_PERIOD_UNIT |
 482                VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
 483                VDCTRL0_SET_VSYNC_PULSE_WIDTH(fb_info->var.vsync_len);
 484        if (fb_info->var.sync & FB_SYNC_HOR_HIGH_ACT)
 485                vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH;
 486        if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT)
 487                vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH;
 488        if (host->sync & MXSFB_SYNC_DATA_ENABLE_HIGH_ACT)
 489                vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH;
 490        if (host->sync & MXSFB_SYNC_DOTCLK_FALLING_ACT)
 491                vdctrl0 |= VDCTRL0_DOTCLK_ACT_FALLING;
 492
 493        writel(vdctrl0, host->base + LCDC_VDCTRL0);
 494
 495        /* frame length in lines */
 496        writel(fb_info->var.upper_margin + fb_info->var.vsync_len +
 497                fb_info->var.lower_margin + fb_info->var.yres,
 498                host->base + LCDC_VDCTRL1);
 499
 500        /* line length in units of clocks or pixels */
 501        writel(set_hsync_pulse_width(host, fb_info->var.hsync_len) |
 502                VDCTRL2_SET_HSYNC_PERIOD(fb_info->var.left_margin +
 503                fb_info->var.hsync_len + fb_info->var.right_margin +
 504                fb_info->var.xres),
 505                host->base + LCDC_VDCTRL2);
 506
 507        writel(SET_HOR_WAIT_CNT(fb_info->var.left_margin +
 508                fb_info->var.hsync_len) |
 509                SET_VERT_WAIT_CNT(fb_info->var.upper_margin +
 510                        fb_info->var.vsync_len),
 511                host->base + LCDC_VDCTRL3);
 512
 513        vdctrl4 = SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres);
 514        if (mxsfb_is_v4(host))
 515                vdctrl4 |= VDCTRL4_SET_DOTCLK_DLY(host->dotclk_delay);
 516        writel(vdctrl4, host->base + LCDC_VDCTRL4);
 517
 518        writel(fb_info->fix.smem_start +
 519                        fb_info->fix.line_length * fb_info->var.yoffset,
 520                        host->base + host->devdata->next_buf);
 521
 522        if (reenable)
 523                mxsfb_enable_controller(fb_info);
 524
 525        return 0;
 526}
 527
 528static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 529                u_int transp, struct fb_info *fb_info)
 530{
 531        unsigned int val;
 532        int ret = -EINVAL;
 533
 534        /*
 535         * If greyscale is true, then we convert the RGB value
 536         * to greyscale no matter what visual we are using.
 537         */
 538        if (fb_info->var.grayscale)
 539                red = green = blue = (19595 * red + 38470 * green +
 540                                        7471 * blue) >> 16;
 541
 542        switch (fb_info->fix.visual) {
 543        case FB_VISUAL_TRUECOLOR:
 544                /*
 545                 * 12 or 16-bit True Colour.  We encode the RGB value
 546                 * according to the RGB bitfield information.
 547                 */
 548                if (regno < 16) {
 549                        u32 *pal = fb_info->pseudo_palette;
 550
 551                        val  = chan_to_field(red, &fb_info->var.red);
 552                        val |= chan_to_field(green, &fb_info->var.green);
 553                        val |= chan_to_field(blue, &fb_info->var.blue);
 554
 555                        pal[regno] = val;
 556                        ret = 0;
 557                }
 558                break;
 559
 560        case FB_VISUAL_STATIC_PSEUDOCOLOR:
 561        case FB_VISUAL_PSEUDOCOLOR:
 562                break;
 563        }
 564
 565        return ret;
 566}
 567
 568static int mxsfb_blank(int blank, struct fb_info *fb_info)
 569{
 570        struct mxsfb_info *host = to_imxfb_host(fb_info);
 571
 572        switch (blank) {
 573        case FB_BLANK_POWERDOWN:
 574        case FB_BLANK_VSYNC_SUSPEND:
 575        case FB_BLANK_HSYNC_SUSPEND:
 576        case FB_BLANK_NORMAL:
 577                if (host->enabled)
 578                        mxsfb_disable_controller(fb_info);
 579                break;
 580
 581        case FB_BLANK_UNBLANK:
 582                if (!host->enabled)
 583                        mxsfb_enable_controller(fb_info);
 584                break;
 585        }
 586        return 0;
 587}
 588
 589static int mxsfb_pan_display(struct fb_var_screeninfo *var,
 590                struct fb_info *fb_info)
 591{
 592        struct mxsfb_info *host = to_imxfb_host(fb_info);
 593        unsigned offset;
 594
 595        if (var->xoffset != 0)
 596                return -EINVAL;
 597
 598        offset = fb_info->fix.line_length * var->yoffset;
 599
 600        /* update on next VSYNC */
 601        writel(fb_info->fix.smem_start + offset,
 602                        host->base + host->devdata->next_buf);
 603
 604        return 0;
 605}
 606
 607static struct fb_ops mxsfb_ops = {
 608        .owner = THIS_MODULE,
 609        .fb_check_var = mxsfb_check_var,
 610        .fb_set_par = mxsfb_set_par,
 611        .fb_setcolreg = mxsfb_setcolreg,
 612        .fb_blank = mxsfb_blank,
 613        .fb_pan_display = mxsfb_pan_display,
 614        .fb_fillrect = cfb_fillrect,
 615        .fb_copyarea = cfb_copyarea,
 616        .fb_imageblit = cfb_imageblit,
 617};
 618
 619static int mxsfb_restore_mode(struct mxsfb_info *host)
 620{
 621        struct fb_info *fb_info = &host->fb_info;
 622        unsigned line_count;
 623        unsigned period;
 624        unsigned long pa, fbsize;
 625        int bits_per_pixel, ofs;
 626        u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl;
 627        struct fb_videomode vmode;
 628
 629        /* Only restore the mode when the controller is running */
 630        ctrl = readl(host->base + LCDC_CTRL);
 631        if (!(ctrl & CTRL_RUN))
 632                return -EINVAL;
 633
 634        vdctrl0 = readl(host->base + LCDC_VDCTRL0);
 635        vdctrl2 = readl(host->base + LCDC_VDCTRL2);
 636        vdctrl3 = readl(host->base + LCDC_VDCTRL3);
 637        vdctrl4 = readl(host->base + LCDC_VDCTRL4);
 638
 639        transfer_count = readl(host->base + host->devdata->transfer_count);
 640
 641        vmode.xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count);
 642        vmode.yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count);
 643
 644        switch (CTRL_GET_WORD_LENGTH(ctrl)) {
 645        case 0:
 646                bits_per_pixel = 16;
 647                break;
 648        case 3:
 649                bits_per_pixel = 32;
 650        case 1:
 651        default:
 652                return -EINVAL;
 653        }
 654
 655        fb_info->var.bits_per_pixel = bits_per_pixel;
 656
 657        vmode.pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U);
 658        vmode.hsync_len = get_hsync_pulse_width(host, vdctrl2);
 659        vmode.left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode.hsync_len;
 660        vmode.right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) - vmode.hsync_len -
 661                vmode.left_margin - vmode.xres;
 662        vmode.vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0);
 663        period = readl(host->base + LCDC_VDCTRL1);
 664        vmode.upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode.vsync_len;
 665        vmode.lower_margin = period - vmode.vsync_len - vmode.upper_margin - vmode.yres;
 666
 667        vmode.vmode = FB_VMODE_NONINTERLACED;
 668
 669        vmode.sync = 0;
 670        if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH)
 671                vmode.sync |= FB_SYNC_HOR_HIGH_ACT;
 672        if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH)
 673                vmode.sync |= FB_SYNC_VERT_HIGH_ACT;
 674
 675        pr_debug("Reconstructed video mode:\n");
 676        pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n",
 677                        vmode.xres, vmode.yres,
 678                        vmode.hsync_len, vmode.left_margin, vmode.right_margin,
 679                        vmode.vsync_len, vmode.upper_margin, vmode.lower_margin);
 680        pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode.pixclock));
 681
 682        fb_add_videomode(&vmode, &fb_info->modelist);
 683
 684        host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl);
 685        host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4);
 686
 687        fb_info->fix.line_length = vmode.xres * (bits_per_pixel >> 3);
 688
 689        pa = readl(host->base + host->devdata->cur_buf);
 690        fbsize = fb_info->fix.line_length * vmode.yres;
 691        if (pa < fb_info->fix.smem_start)
 692                return -EINVAL;
 693        if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len)
 694                return -EINVAL;
 695        ofs = pa - fb_info->fix.smem_start;
 696        if (ofs) {
 697                memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize);
 698                writel(fb_info->fix.smem_start, host->base + host->devdata->next_buf);
 699        }
 700
 701        line_count = fb_info->fix.smem_len / fb_info->fix.line_length;
 702        fb_info->fix.ypanstep = 1;
 703
 704        clk_prepare_enable(host->clk);
 705        host->enabled = 1;
 706
 707        return 0;
 708}
 709
 710static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host)
 711{
 712        struct fb_info *fb_info = &host->fb_info;
 713        struct fb_var_screeninfo *var = &fb_info->var;
 714        struct device *dev = &host->pdev->dev;
 715        struct device_node *np = host->pdev->dev.of_node;
 716        struct device_node *display_np;
 717        struct device_node *timings_np;
 718        struct display_timings *timings;
 719        u32 width;
 720        int i;
 721        int ret = 0;
 722
 723        display_np = of_parse_phandle(np, "display", 0);
 724        if (!display_np) {
 725                dev_err(dev, "failed to find display phandle\n");
 726                return -ENOENT;
 727        }
 728
 729        ret = of_property_read_u32(display_np, "bus-width", &width);
 730        if (ret < 0) {
 731                dev_err(dev, "failed to get property bus-width\n");
 732                goto put_display_node;
 733        }
 734
 735        switch (width) {
 736        case 8:
 737                host->ld_intf_width = STMLCDIF_8BIT;
 738                break;
 739        case 16:
 740                host->ld_intf_width = STMLCDIF_16BIT;
 741                break;
 742        case 18:
 743                host->ld_intf_width = STMLCDIF_18BIT;
 744                break;
 745        case 24:
 746                host->ld_intf_width = STMLCDIF_24BIT;
 747                break;
 748        default:
 749                dev_err(dev, "invalid bus-width value\n");
 750                ret = -EINVAL;
 751                goto put_display_node;
 752        }
 753
 754        ret = of_property_read_u32(display_np, "bits-per-pixel",
 755                                   &var->bits_per_pixel);
 756        if (ret < 0) {
 757                dev_err(dev, "failed to get property bits-per-pixel\n");
 758                goto put_display_node;
 759        }
 760
 761        timings = of_get_display_timings(display_np);
 762        if (!timings) {
 763                dev_err(dev, "failed to get display timings\n");
 764                ret = -ENOENT;
 765                goto put_display_node;
 766        }
 767
 768        timings_np = of_find_node_by_name(display_np,
 769                                          "display-timings");
 770        if (!timings_np) {
 771                dev_err(dev, "failed to find display-timings node\n");
 772                ret = -ENOENT;
 773                goto put_display_node;
 774        }
 775
 776        for (i = 0; i < of_get_child_count(timings_np); i++) {
 777                struct videomode vm;
 778                struct fb_videomode fb_vm;
 779
 780                ret = videomode_from_timings(timings, &vm, i);
 781                if (ret < 0)
 782                        goto put_timings_node;
 783                ret = fb_videomode_from_videomode(&vm, &fb_vm);
 784                if (ret < 0)
 785                        goto put_timings_node;
 786
 787                if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
 788                        host->sync |= MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
 789                if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
 790                        host->sync |= MXSFB_SYNC_DOTCLK_FALLING_ACT;
 791                fb_add_videomode(&fb_vm, &fb_info->modelist);
 792        }
 793
 794put_timings_node:
 795        of_node_put(timings_np);
 796put_display_node:
 797        of_node_put(display_np);
 798        return ret;
 799}
 800
 801static int mxsfb_init_fbinfo(struct mxsfb_info *host)
 802{
 803        struct fb_info *fb_info = &host->fb_info;
 804        struct fb_var_screeninfo *var = &fb_info->var;
 805        dma_addr_t fb_phys;
 806        void *fb_virt;
 807        unsigned fb_size;
 808        int ret;
 809
 810        fb_info->fbops = &mxsfb_ops;
 811        fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST;
 812        strlcpy(fb_info->fix.id, "mxs", sizeof(fb_info->fix.id));
 813        fb_info->fix.type = FB_TYPE_PACKED_PIXELS;
 814        fb_info->fix.ypanstep = 1;
 815        fb_info->fix.visual = FB_VISUAL_TRUECOLOR,
 816        fb_info->fix.accel = FB_ACCEL_NONE;
 817
 818        ret = mxsfb_init_fbinfo_dt(host);
 819        if (ret)
 820                return ret;
 821
 822        var->nonstd = 0;
 823        var->activate = FB_ACTIVATE_NOW;
 824        var->accel_flags = 0;
 825        var->vmode = FB_VMODE_NONINTERLACED;
 826
 827        /* Memory allocation for framebuffer */
 828        fb_size = SZ_2M;
 829        fb_virt = alloc_pages_exact(fb_size, GFP_DMA);
 830        if (!fb_virt)
 831                return -ENOMEM;
 832
 833        fb_phys = virt_to_phys(fb_virt);
 834
 835        fb_info->fix.smem_start = fb_phys;
 836        fb_info->screen_base = fb_virt;
 837        fb_info->screen_size = fb_info->fix.smem_len = fb_size;
 838
 839        if (mxsfb_restore_mode(host))
 840                memset(fb_virt, 0, fb_size);
 841
 842        return 0;
 843}
 844
 845static void mxsfb_free_videomem(struct mxsfb_info *host)
 846{
 847        struct fb_info *fb_info = &host->fb_info;
 848
 849        free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len);
 850}
 851
 852static struct platform_device_id mxsfb_devtype[] = {
 853        {
 854                .name = "imx23-fb",
 855                .driver_data = MXSFB_V3,
 856        }, {
 857                .name = "imx28-fb",
 858                .driver_data = MXSFB_V4,
 859        }, {
 860                /* sentinel */
 861        }
 862};
 863MODULE_DEVICE_TABLE(platform, mxsfb_devtype);
 864
 865static const struct of_device_id mxsfb_dt_ids[] = {
 866        { .compatible = "fsl,imx23-lcdif", .data = &mxsfb_devtype[0], },
 867        { .compatible = "fsl,imx28-lcdif", .data = &mxsfb_devtype[1], },
 868        { /* sentinel */ }
 869};
 870MODULE_DEVICE_TABLE(of, mxsfb_dt_ids);
 871
 872static int mxsfb_probe(struct platform_device *pdev)
 873{
 874        const struct of_device_id *of_id =
 875                        of_match_device(mxsfb_dt_ids, &pdev->dev);
 876        struct resource *res;
 877        struct mxsfb_info *host;
 878        struct fb_info *fb_info;
 879        struct fb_modelist *modelist;
 880        struct pinctrl *pinctrl;
 881        int ret;
 882
 883        if (of_id)
 884                pdev->id_entry = of_id->data;
 885
 886        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 887        if (!res) {
 888                dev_err(&pdev->dev, "Cannot get memory IO resource\n");
 889                return -ENODEV;
 890        }
 891
 892        fb_info = framebuffer_alloc(sizeof(struct mxsfb_info), &pdev->dev);
 893        if (!fb_info) {
 894                dev_err(&pdev->dev, "Failed to allocate fbdev\n");
 895                return -ENOMEM;
 896        }
 897
 898        host = to_imxfb_host(fb_info);
 899
 900        host->base = devm_ioremap_resource(&pdev->dev, res);
 901        if (IS_ERR(host->base)) {
 902                dev_err(&pdev->dev, "ioremap failed\n");
 903                ret = PTR_ERR(host->base);
 904                goto fb_release;
 905        }
 906
 907        host->pdev = pdev;
 908        platform_set_drvdata(pdev, host);
 909
 910        host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data];
 911
 912        pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
 913        if (IS_ERR(pinctrl)) {
 914                ret = PTR_ERR(pinctrl);
 915                goto fb_release;
 916        }
 917
 918        host->clk = devm_clk_get(&host->pdev->dev, NULL);
 919        if (IS_ERR(host->clk)) {
 920                ret = PTR_ERR(host->clk);
 921                goto fb_release;
 922        }
 923
 924        host->reg_lcd = devm_regulator_get(&pdev->dev, "lcd");
 925        if (IS_ERR(host->reg_lcd))
 926                host->reg_lcd = NULL;
 927
 928        fb_info->pseudo_palette = devm_kzalloc(&pdev->dev, sizeof(u32) * 16,
 929                                               GFP_KERNEL);
 930        if (!fb_info->pseudo_palette) {
 931                ret = -ENOMEM;
 932                goto fb_release;
 933        }
 934
 935        INIT_LIST_HEAD(&fb_info->modelist);
 936
 937        ret = mxsfb_init_fbinfo(host);
 938        if (ret != 0)
 939                goto fb_release;
 940
 941        modelist = list_first_entry(&fb_info->modelist,
 942                        struct fb_modelist, list);
 943        fb_videomode_to_var(&fb_info->var, &modelist->mode);
 944
 945        /* init the color fields */
 946        mxsfb_check_var(&fb_info->var, fb_info);
 947
 948        platform_set_drvdata(pdev, fb_info);
 949
 950        ret = register_framebuffer(fb_info);
 951        if (ret != 0) {
 952                dev_err(&pdev->dev,"Failed to register framebuffer\n");
 953                goto fb_destroy;
 954        }
 955
 956        if (!host->enabled) {
 957                writel(0, host->base + LCDC_CTRL);
 958                mxsfb_set_par(fb_info);
 959                mxsfb_enable_controller(fb_info);
 960        }
 961
 962        dev_info(&pdev->dev, "initialized\n");
 963
 964        return 0;
 965
 966fb_destroy:
 967        if (host->enabled)
 968                clk_disable_unprepare(host->clk);
 969        fb_destroy_modelist(&fb_info->modelist);
 970fb_release:
 971        framebuffer_release(fb_info);
 972
 973        return ret;
 974}
 975
 976static int mxsfb_remove(struct platform_device *pdev)
 977{
 978        struct fb_info *fb_info = platform_get_drvdata(pdev);
 979        struct mxsfb_info *host = to_imxfb_host(fb_info);
 980
 981        if (host->enabled)
 982                mxsfb_disable_controller(fb_info);
 983
 984        unregister_framebuffer(fb_info);
 985        mxsfb_free_videomem(host);
 986
 987        framebuffer_release(fb_info);
 988
 989        platform_set_drvdata(pdev, NULL);
 990
 991        return 0;
 992}
 993
 994static void mxsfb_shutdown(struct platform_device *pdev)
 995{
 996        struct fb_info *fb_info = platform_get_drvdata(pdev);
 997        struct mxsfb_info *host = to_imxfb_host(fb_info);
 998
 999        /*
1000         * Force stop the LCD controller as keeping it running during reboot
1001         * might interfere with the BootROM's boot mode pads sampling.
1002         */
1003        writel(CTRL_RUN, host->base + LCDC_CTRL + REG_CLR);
1004}
1005
1006static struct platform_driver mxsfb_driver = {
1007        .probe = mxsfb_probe,
1008        .remove = mxsfb_remove,
1009        .shutdown = mxsfb_shutdown,
1010        .id_table = mxsfb_devtype,
1011        .driver = {
1012                   .name = DRIVER_NAME,
1013                   .of_match_table = mxsfb_dt_ids,
1014        },
1015};
1016
1017module_platform_driver(mxsfb_driver);
1018
1019MODULE_DESCRIPTION("Freescale mxs framebuffer driver");
1020MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1021MODULE_LICENSE("GPL");
1022
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