linux/drivers/video/au1100fb.h
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   1/*
   2 * BRIEF MODULE DESCRIPTION
   3 *      Hardware definitions for the Au1100 LCD controller
   4 *
   5 * Copyright 2002 MontaVista Software
   6 * Copyright 2002 Alchemy Semiconductor
   7 * Author:      Alchemy Semiconductor, MontaVista Software
   8 *
   9 *  This program is free software; you can redistribute  it and/or modify it
  10 *  under  the terms of  the GNU General  Public License as published by the
  11 *  Free Software Foundation;  either version 2 of the  License, or (at your
  12 *  option) any later version.
  13 *
  14 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  15 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  16 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  17 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  18 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  20 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  21 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  22 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24 *
  25 *  You should have received a copy of the  GNU General Public License along
  26 *  with this program; if not, write  to the Free Software Foundation, Inc.,
  27 *  675 Mass Ave, Cambridge, MA 02139, USA.
  28 */
  29
  30#ifndef _AU1100LCD_H
  31#define _AU1100LCD_H
  32
  33#include <asm/mach-au1x00/au1000.h>
  34
  35#define print_err(f, arg...) printk(KERN_ERR DRIVER_NAME ": " f "\n", ## arg)
  36#define print_warn(f, arg...) printk(KERN_WARNING DRIVER_NAME ": " f "\n", ## arg)
  37#define print_info(f, arg...) printk(KERN_INFO DRIVER_NAME ": " f "\n", ## arg)
  38
  39#if DEBUG
  40#define print_dbg(f, arg...) printk(__FILE__ ": " f "\n", ## arg)
  41#else
  42#define print_dbg(f, arg...) do {} while (0)
  43#endif
  44
  45#if defined(__BIG_ENDIAN)
  46#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
  47#else
  48#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
  49#endif
  50#define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
  51
  52/********************************************************************/
  53
  54/* LCD controller restrictions */
  55#define AU1100_LCD_MAX_XRES     800
  56#define AU1100_LCD_MAX_YRES     600
  57#define AU1100_LCD_MAX_BPP      16
  58#define AU1100_LCD_MAX_CLK      48000000
  59#define AU1100_LCD_NBR_PALETTE_ENTRIES 256
  60
  61/* Default number of visible screen buffer to allocate */
  62#define AU1100FB_NBR_VIDEO_BUFFERS 4
  63
  64/********************************************************************/
  65
  66struct au1100fb_panel
  67{
  68        const char name[25];            /* Full name <vendor>_<model> */
  69
  70        u32     control_base;           /* Mode-independent control values */
  71        u32     clkcontrol_base;        /* Panel pixclock preferences */
  72
  73        u32     horztiming;
  74        u32     verttiming;
  75
  76        u32     xres;           /* Maximum horizontal resolution */
  77        u32     yres;           /* Maximum vertical resolution */
  78        u32     bpp;            /* Maximum depth supported */
  79};
  80
  81struct au1100fb_regs
  82{
  83        u32  lcd_control;
  84        u32  lcd_intstatus;
  85        u32  lcd_intenable;
  86        u32  lcd_horztiming;
  87        u32  lcd_verttiming;
  88        u32  lcd_clkcontrol;
  89        u32  lcd_dmaaddr0;
  90        u32  lcd_dmaaddr1;
  91        u32  lcd_words;
  92        u32  lcd_pwmdiv;
  93        u32  lcd_pwmhi;
  94        u32  reserved[(0x0400-0x002C)/4];
  95        u32  lcd_pallettebase[256];
  96};
  97
  98struct au1100fb_device {
  99
 100        struct fb_info info;                    /* FB driver info record */
 101
 102        struct au1100fb_panel   *panel;         /* Panel connected to this device */
 103
 104        struct au1100fb_regs*   regs;           /* Registers memory map */
 105        size_t                  regs_len;
 106        unsigned int            regs_phys;
 107
 108        unsigned char*          fb_mem;         /* FrameBuffer memory map */
 109        size_t                  fb_len;
 110        dma_addr_t              fb_phys;
 111        int                     panel_idx;
 112};
 113
 114/********************************************************************/
 115
 116#define LCD_CONTROL                (AU1100_LCD_BASE + 0x0)
 117  #define LCD_CONTROL_SBB_BIT      21
 118  #define LCD_CONTROL_SBB_MASK     (0x3 << LCD_CONTROL_SBB_BIT)
 119    #define LCD_CONTROL_SBB_1        (0 << LCD_CONTROL_SBB_BIT)
 120    #define LCD_CONTROL_SBB_2        (1 << LCD_CONTROL_SBB_BIT)
 121    #define LCD_CONTROL_SBB_3        (2 << LCD_CONTROL_SBB_BIT)
 122    #define LCD_CONTROL_SBB_4        (3 << LCD_CONTROL_SBB_BIT)
 123  #define LCD_CONTROL_SBPPF_BIT    18
 124  #define LCD_CONTROL_SBPPF_MASK   (0x7 << LCD_CONTROL_SBPPF_BIT)
 125    #define LCD_CONTROL_SBPPF_655    (0 << LCD_CONTROL_SBPPF_BIT)
 126    #define LCD_CONTROL_SBPPF_565    (1 << LCD_CONTROL_SBPPF_BIT)
 127    #define LCD_CONTROL_SBPPF_556    (2 << LCD_CONTROL_SBPPF_BIT)
 128    #define LCD_CONTROL_SBPPF_1555   (3 << LCD_CONTROL_SBPPF_BIT)
 129    #define LCD_CONTROL_SBPPF_5551   (4 << LCD_CONTROL_SBPPF_BIT)
 130  #define LCD_CONTROL_WP           (1<<17)
 131  #define LCD_CONTROL_WD           (1<<16)
 132  #define LCD_CONTROL_C            (1<<15)
 133  #define LCD_CONTROL_SM_BIT       13
 134  #define LCD_CONTROL_SM_MASK      (0x3 << LCD_CONTROL_SM_BIT)
 135    #define LCD_CONTROL_SM_0         (0 << LCD_CONTROL_SM_BIT)
 136    #define LCD_CONTROL_SM_90        (1 << LCD_CONTROL_SM_BIT)
 137    #define LCD_CONTROL_SM_180       (2 << LCD_CONTROL_SM_BIT)
 138    #define LCD_CONTROL_SM_270       (3 << LCD_CONTROL_SM_BIT)
 139  #define LCD_CONTROL_DB           (1<<12)
 140  #define LCD_CONTROL_CCO          (1<<11)
 141  #define LCD_CONTROL_DP           (1<<10)
 142  #define LCD_CONTROL_PO_BIT       8
 143  #define LCD_CONTROL_PO_MASK      (0x3 << LCD_CONTROL_PO_BIT)
 144    #define LCD_CONTROL_PO_00        (0 << LCD_CONTROL_PO_BIT)
 145    #define LCD_CONTROL_PO_01        (1 << LCD_CONTROL_PO_BIT)
 146    #define LCD_CONTROL_PO_10        (2 << LCD_CONTROL_PO_BIT)
 147    #define LCD_CONTROL_PO_11        (3 << LCD_CONTROL_PO_BIT)
 148  #define LCD_CONTROL_MPI          (1<<7)
 149  #define LCD_CONTROL_PT           (1<<6)
 150  #define LCD_CONTROL_PC           (1<<5)
 151  #define LCD_CONTROL_BPP_BIT      1
 152  #define LCD_CONTROL_BPP_MASK     (0x7 << LCD_CONTROL_BPP_BIT)
 153    #define LCD_CONTROL_BPP_1        (0 << LCD_CONTROL_BPP_BIT)
 154    #define LCD_CONTROL_BPP_2        (1 << LCD_CONTROL_BPP_BIT)
 155    #define LCD_CONTROL_BPP_4        (2 << LCD_CONTROL_BPP_BIT)
 156    #define LCD_CONTROL_BPP_8        (3 << LCD_CONTROL_BPP_BIT)
 157    #define LCD_CONTROL_BPP_12       (4 << LCD_CONTROL_BPP_BIT)
 158    #define LCD_CONTROL_BPP_16       (5 << LCD_CONTROL_BPP_BIT)
 159  #define LCD_CONTROL_GO           (1<<0)
 160
 161#define LCD_INTSTATUS              (AU1100_LCD_BASE + 0x4)
 162#define LCD_INTENABLE              (AU1100_LCD_BASE + 0x8)
 163  #define LCD_INT_SD               (1<<7)
 164  #define LCD_INT_OF               (1<<6)
 165  #define LCD_INT_UF               (1<<5)
 166  #define LCD_INT_SA               (1<<3)
 167  #define LCD_INT_SS               (1<<2)
 168  #define LCD_INT_S1               (1<<1)
 169  #define LCD_INT_S0               (1<<0)
 170
 171#define LCD_HORZTIMING             (AU1100_LCD_BASE + 0xC)
 172  #define LCD_HORZTIMING_HN2_BIT   24
 173  #define LCD_HORZTIMING_HN2_MASK  (0xFF << LCD_HORZTIMING_HN2_BIT)
 174  #define LCD_HORZTIMING_HN2_N(N)  ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK)
 175  #define LCD_HORZTIMING_HN1_BIT   16
 176  #define LCD_HORZTIMING_HN1_MASK  (0xFF << LCD_HORZTIMING_HN1_BIT)
 177  #define LCD_HORZTIMING_HN1_N(N)  ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK)
 178  #define LCD_HORZTIMING_HPW_BIT   10
 179  #define LCD_HORZTIMING_HPW_MASK  (0x3F << LCD_HORZTIMING_HPW_BIT)
 180  #define LCD_HORZTIMING_HPW_N(N)  ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK)
 181  #define LCD_HORZTIMING_PPL_BIT   0
 182  #define LCD_HORZTIMING_PPL_MASK  (0x3FF << LCD_HORZTIMING_PPL_BIT)
 183  #define LCD_HORZTIMING_PPL_N(N)  ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK)
 184
 185#define LCD_VERTTIMING             (AU1100_LCD_BASE + 0x10)
 186  #define LCD_VERTTIMING_VN2_BIT   24
 187  #define LCD_VERTTIMING_VN2_MASK  (0xFF << LCD_VERTTIMING_VN2_BIT)
 188  #define LCD_VERTTIMING_VN2_N(N)  ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK)
 189  #define LCD_VERTTIMING_VN1_BIT   16
 190  #define LCD_VERTTIMING_VN1_MASK  (0xFF << LCD_VERTTIMING_VN1_BIT)
 191  #define LCD_VERTTIMING_VN1_N(N)  ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK)
 192  #define LCD_VERTTIMING_VPW_BIT   10
 193  #define LCD_VERTTIMING_VPW_MASK  (0x3F << LCD_VERTTIMING_VPW_BIT)
 194  #define LCD_VERTTIMING_VPW_N(N)  ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK)
 195  #define LCD_VERTTIMING_LPP_BIT   0
 196  #define LCD_VERTTIMING_LPP_MASK  (0x3FF << LCD_VERTTIMING_LPP_BIT)
 197  #define LCD_VERTTIMING_LPP_N(N)  ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK)
 198
 199#define LCD_CLKCONTROL             (AU1100_LCD_BASE + 0x14)
 200  #define LCD_CLKCONTROL_IB        (1<<18)
 201  #define LCD_CLKCONTROL_IC        (1<<17)
 202  #define LCD_CLKCONTROL_IH        (1<<16)
 203  #define LCD_CLKCONTROL_IV        (1<<15)
 204  #define LCD_CLKCONTROL_BF_BIT    10
 205  #define LCD_CLKCONTROL_BF_MASK   (0x1F << LCD_CLKCONTROL_BF_BIT)
 206  #define LCD_CLKCONTROL_BF_N(N)   ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK)
 207  #define LCD_CLKCONTROL_PCD_BIT   0
 208  #define LCD_CLKCONTROL_PCD_MASK  (0x3FF << LCD_CLKCONTROL_PCD_BIT)
 209  #define LCD_CLKCONTROL_PCD_N(N)  (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK)
 210
 211#define LCD_DMAADDR0               (AU1100_LCD_BASE + 0x18)
 212#define LCD_DMAADDR1               (AU1100_LCD_BASE + 0x1C)
 213  #define LCD_DMA_SA_BIT           5
 214  #define LCD_DMA_SA_MASK          (0x7FFFFFF << LCD_DMA_SA_BIT)
 215  #define LCD_DMA_SA_N(N)          ((N) & LCD_DMA_SA_MASK)
 216
 217#define LCD_WORDS                  (AU1100_LCD_BASE + 0x20)
 218  #define LCD_WRD_WRDS_BIT         0
 219  #define LCD_WRD_WRDS_MASK        (0xFFFFFFFF << LCD_WRD_WRDS_BIT)
 220  #define LCD_WRD_WRDS_N(N)        ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK)
 221
 222#define LCD_PWMDIV                 (AU1100_LCD_BASE + 0x24)
 223  #define LCD_PWMDIV_EN            (1<<12)
 224  #define LCD_PWMDIV_PWMDIV_BIT    0
 225  #define LCD_PWMDIV_PWMDIV_MASK   (0xFFF << LCD_PWMDIV_PWMDIV_BIT)
 226  #define LCD_PWMDIV_PWMDIV_N(N)   ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK)
 227
 228#define LCD_PWMHI                  (AU1100_LCD_BASE + 0x28)
 229  #define LCD_PWMHI_PWMHI1_BIT     12
 230  #define LCD_PWMHI_PWMHI1_MASK    (0xFFF << LCD_PWMHI_PWMHI1_BIT)
 231  #define LCD_PWMHI_PWMHI1_N(N)    (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK)
 232  #define LCD_PWMHI_PWMHI0_BIT     0
 233  #define LCD_PWMHI_PWMHI0_MASK    (0xFFF << LCD_PWMHI_PWMHI0_BIT)
 234  #define LCD_PWMHI_PWMHI0_N(N)    (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK)
 235
 236#define LCD_PALLETTEBASE                (AU1100_LCD_BASE + 0x400)
 237  #define LCD_PALLETTE_MONO_MI_BIT      0
 238  #define LCD_PALLETTE_MONO_MI_MASK     (0xF << LCD_PALLETTE_MONO_MI_BIT)
 239  #define LCD_PALLETTE_MONO_MI_N(N)     (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK)
 240
 241  #define LCD_PALLETTE_COLOR_RI_BIT     8
 242  #define LCD_PALLETTE_COLOR_RI_MASK    (0xF << LCD_PALLETTE_COLOR_RI_BIT)
 243  #define LCD_PALLETTE_COLOR_RI_N(N)    (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK)
 244  #define LCD_PALLETTE_COLOR_GI_BIT     4
 245  #define LCD_PALLETTE_COLOR_GI_MASK    (0xF << LCD_PALLETTE_COLOR_GI_BIT)
 246  #define LCD_PALLETTE_COLOR_GI_N(N)    (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK)
 247  #define LCD_PALLETTE_COLOR_BI_BIT     0
 248  #define LCD_PALLETTE_COLOR_BI_MASK    (0xF << LCD_PALLETTE_COLOR_BI_BIT)
 249  #define LCD_PALLETTE_COLOR_BI_N(N)    (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK)
 250
 251  #define LCD_PALLETTE_TFT_DC_BIT       0
 252  #define LCD_PALLETTE_TFT_DC_MASK      (0xFFFF << LCD_PALLETTE_TFT_DC_BIT)
 253  #define LCD_PALLETTE_TFT_DC_N(N)      (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK)
 254
 255/********************************************************************/
 256
 257/* List of panels known to work with the AU1100 LCD controller.
 258 * To add a new panel, enter the same specifications as the
 259 * Generic_TFT one, and MAKE SURE that it doesn't conflicts
 260 * with the controller restrictions. Restrictions are:
 261 *
 262 * STN color panels: max_bpp <= 12
 263 * STN mono panels: max_bpp <= 4
 264 * TFT panels: max_bpp <= 16
 265 * max_xres <= 800
 266 * max_yres <= 600
 267 */
 268static struct au1100fb_panel known_lcd_panels[] =
 269{
 270        /* 800x600x16bpp CRT */
 271        [0] = {
 272                .name = "CRT_800x600_16",
 273                .xres = 800,
 274                .yres = 600,
 275                .bpp = 16,
 276                .control_base = 0x0004886A |
 277                        LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF |
 278                        LCD_CONTROL_BPP_16 | LCD_CONTROL_SBB_4,
 279                .clkcontrol_base = 0x00020000,
 280                .horztiming = 0x005aff1f,
 281                .verttiming = 0x16000e57,
 282        },
 283        /* just the standard LCD */
 284        [1] = {
 285                .name = "WWPC LCD",
 286                .xres = 240,
 287                .yres = 320,
 288                .bpp = 16,
 289                .control_base = 0x0006806A,
 290                .horztiming = 0x0A1010EF,
 291                .verttiming = 0x0301013F,
 292                .clkcontrol_base = 0x00018001,
 293        },
 294        /* Sharp 320x240 TFT panel */
 295        [2] = {
 296                .name = "Sharp_LQ038Q5DR01",
 297                .xres = 320,
 298                .yres = 240,
 299                .bpp = 16,
 300                .control_base =
 301                ( LCD_CONTROL_SBPPF_565
 302                | LCD_CONTROL_C
 303                | LCD_CONTROL_SM_0
 304                        | LCD_CONTROL_DEFAULT_PO
 305                | LCD_CONTROL_PT
 306                | LCD_CONTROL_PC
 307                | LCD_CONTROL_BPP_16 ),
 308                .horztiming =
 309                ( LCD_HORZTIMING_HN2_N(8)
 310                | LCD_HORZTIMING_HN1_N(60)
 311                | LCD_HORZTIMING_HPW_N(12)
 312                | LCD_HORZTIMING_PPL_N(320) ),
 313                .verttiming =
 314                ( LCD_VERTTIMING_VN2_N(5)
 315                | LCD_VERTTIMING_VN1_N(17)
 316                | LCD_VERTTIMING_VPW_N(1)
 317                | LCD_VERTTIMING_LPP_N(240) ),
 318                .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
 319        },
 320
 321        /* Hitachi SP14Q005 and possibly others */
 322        [3] = {
 323                .name = "Hitachi_SP14Qxxx",
 324                .xres = 320,
 325                .yres = 240,
 326                .bpp = 4,
 327                .control_base =
 328                        ( LCD_CONTROL_C
 329                        | LCD_CONTROL_BPP_4 ),
 330                .horztiming =
 331                        ( LCD_HORZTIMING_HN2_N(1)
 332                        | LCD_HORZTIMING_HN1_N(1)
 333                        | LCD_HORZTIMING_HPW_N(1)
 334                        | LCD_HORZTIMING_PPL_N(320) ),
 335                .verttiming =
 336                        ( LCD_VERTTIMING_VN2_N(1)
 337                        | LCD_VERTTIMING_VN1_N(1)
 338                        | LCD_VERTTIMING_VPW_N(1)
 339                        | LCD_VERTTIMING_LPP_N(240) ),
 340                .clkcontrol_base = LCD_CLKCONTROL_PCD_N(4),
 341        },
 342
 343        /* Generic 640x480 TFT panel */
 344        [4] = {
 345                .name = "TFT_640x480_16",
 346                .xres = 640,
 347                .yres = 480,
 348                .bpp = 16,
 349                .control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO,
 350                .horztiming = 0x3434d67f,
 351                .verttiming = 0x0e0e39df,
 352                .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
 353        },
 354
 355         /* Pb1100 LCDB 640x480 PrimeView TFT panel */
 356        [5] = {
 357                .name = "PrimeView_640x480_16",
 358                .xres = 640,
 359                .yres = 480,
 360                .bpp = 16,
 361                .control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO,
 362                .horztiming = 0x0e4bfe7f,
 363                .verttiming = 0x210805df,
 364                .clkcontrol_base = 0x00038001,
 365        },
 366};
 367
 368/********************************************************************/
 369
 370/* Inline helpers */
 371
 372#define panel_is_dual(panel)  (panel->control_base & LCD_CONTROL_DP)
 373#define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT)
 374#define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC)
 375#define panel_swap_rgb(panel) (panel->control_base & LCD_CONTROL_CCO)
 376
 377#endif /* _AU1100LCD_H */
 378
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