linux/drivers/spi/spi-tegra20-slink.c
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   1/*
   2 * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller.
   3 *
   4 * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public License,
   8 * version 2, as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope it will be useful, but WITHOUT
  11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13 * more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17 */
  18
  19#include <linux/clk.h>
  20#include <linux/completion.h>
  21#include <linux/delay.h>
  22#include <linux/dmaengine.h>
  23#include <linux/dma-mapping.h>
  24#include <linux/dmapool.h>
  25#include <linux/err.h>
  26#include <linux/init.h>
  27#include <linux/interrupt.h>
  28#include <linux/io.h>
  29#include <linux/kernel.h>
  30#include <linux/kthread.h>
  31#include <linux/module.h>
  32#include <linux/platform_device.h>
  33#include <linux/pm_runtime.h>
  34#include <linux/of.h>
  35#include <linux/of_device.h>
  36#include <linux/spi/spi.h>
  37#include <linux/clk/tegra.h>
  38
  39#define SLINK_COMMAND                   0x000
  40#define SLINK_BIT_LENGTH(x)             (((x) & 0x1f) << 0)
  41#define SLINK_WORD_SIZE(x)              (((x) & 0x1f) << 5)
  42#define SLINK_BOTH_EN                   (1 << 10)
  43#define SLINK_CS_SW                     (1 << 11)
  44#define SLINK_CS_VALUE                  (1 << 12)
  45#define SLINK_CS_POLARITY               (1 << 13)
  46#define SLINK_IDLE_SDA_DRIVE_LOW        (0 << 16)
  47#define SLINK_IDLE_SDA_DRIVE_HIGH       (1 << 16)
  48#define SLINK_IDLE_SDA_PULL_LOW         (2 << 16)
  49#define SLINK_IDLE_SDA_PULL_HIGH        (3 << 16)
  50#define SLINK_IDLE_SDA_MASK             (3 << 16)
  51#define SLINK_CS_POLARITY1              (1 << 20)
  52#define SLINK_CK_SDA                    (1 << 21)
  53#define SLINK_CS_POLARITY2              (1 << 22)
  54#define SLINK_CS_POLARITY3              (1 << 23)
  55#define SLINK_IDLE_SCLK_DRIVE_LOW       (0 << 24)
  56#define SLINK_IDLE_SCLK_DRIVE_HIGH      (1 << 24)
  57#define SLINK_IDLE_SCLK_PULL_LOW        (2 << 24)
  58#define SLINK_IDLE_SCLK_PULL_HIGH       (3 << 24)
  59#define SLINK_IDLE_SCLK_MASK            (3 << 24)
  60#define SLINK_M_S                       (1 << 28)
  61#define SLINK_WAIT                      (1 << 29)
  62#define SLINK_GO                        (1 << 30)
  63#define SLINK_ENB                       (1 << 31)
  64
  65#define SLINK_MODES                     (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA)
  66
  67#define SLINK_COMMAND2                  0x004
  68#define SLINK_LSBFE                     (1 << 0)
  69#define SLINK_SSOE                      (1 << 1)
  70#define SLINK_SPIE                      (1 << 4)
  71#define SLINK_BIDIROE                   (1 << 6)
  72#define SLINK_MODFEN                    (1 << 7)
  73#define SLINK_INT_SIZE(x)               (((x) & 0x1f) << 8)
  74#define SLINK_CS_ACTIVE_BETWEEN         (1 << 17)
  75#define SLINK_SS_EN_CS(x)               (((x) & 0x3) << 18)
  76#define SLINK_SS_SETUP(x)               (((x) & 0x3) << 20)
  77#define SLINK_FIFO_REFILLS_0            (0 << 22)
  78#define SLINK_FIFO_REFILLS_1            (1 << 22)
  79#define SLINK_FIFO_REFILLS_2            (2 << 22)
  80#define SLINK_FIFO_REFILLS_3            (3 << 22)
  81#define SLINK_FIFO_REFILLS_MASK         (3 << 22)
  82#define SLINK_WAIT_PACK_INT(x)          (((x) & 0x7) << 26)
  83#define SLINK_SPC0                      (1 << 29)
  84#define SLINK_TXEN                      (1 << 30)
  85#define SLINK_RXEN                      (1 << 31)
  86
  87#define SLINK_STATUS                    0x008
  88#define SLINK_COUNT(val)                (((val) >> 0) & 0x1f)
  89#define SLINK_WORD(val)                 (((val) >> 5) & 0x1f)
  90#define SLINK_BLK_CNT(val)              (((val) >> 0) & 0xffff)
  91#define SLINK_MODF                      (1 << 16)
  92#define SLINK_RX_UNF                    (1 << 18)
  93#define SLINK_TX_OVF                    (1 << 19)
  94#define SLINK_TX_FULL                   (1 << 20)
  95#define SLINK_TX_EMPTY                  (1 << 21)
  96#define SLINK_RX_FULL                   (1 << 22)
  97#define SLINK_RX_EMPTY                  (1 << 23)
  98#define SLINK_TX_UNF                    (1 << 24)
  99#define SLINK_RX_OVF                    (1 << 25)
 100#define SLINK_TX_FLUSH                  (1 << 26)
 101#define SLINK_RX_FLUSH                  (1 << 27)
 102#define SLINK_SCLK                      (1 << 28)
 103#define SLINK_ERR                       (1 << 29)
 104#define SLINK_RDY                       (1 << 30)
 105#define SLINK_BSY                       (1 << 31)
 106#define SLINK_FIFO_ERROR                (SLINK_TX_OVF | SLINK_RX_UNF |  \
 107                                        SLINK_TX_UNF | SLINK_RX_OVF)
 108
 109#define SLINK_FIFO_EMPTY                (SLINK_TX_EMPTY | SLINK_RX_EMPTY)
 110
 111#define SLINK_MAS_DATA                  0x010
 112#define SLINK_SLAVE_DATA                0x014
 113
 114#define SLINK_DMA_CTL                   0x018
 115#define SLINK_DMA_BLOCK_SIZE(x)         (((x) & 0xffff) << 0)
 116#define SLINK_TX_TRIG_1                 (0 << 16)
 117#define SLINK_TX_TRIG_4                 (1 << 16)
 118#define SLINK_TX_TRIG_8                 (2 << 16)
 119#define SLINK_TX_TRIG_16                (3 << 16)
 120#define SLINK_TX_TRIG_MASK              (3 << 16)
 121#define SLINK_RX_TRIG_1                 (0 << 18)
 122#define SLINK_RX_TRIG_4                 (1 << 18)
 123#define SLINK_RX_TRIG_8                 (2 << 18)
 124#define SLINK_RX_TRIG_16                (3 << 18)
 125#define SLINK_RX_TRIG_MASK              (3 << 18)
 126#define SLINK_PACKED                    (1 << 20)
 127#define SLINK_PACK_SIZE_4               (0 << 21)
 128#define SLINK_PACK_SIZE_8               (1 << 21)
 129#define SLINK_PACK_SIZE_16              (2 << 21)
 130#define SLINK_PACK_SIZE_32              (3 << 21)
 131#define SLINK_PACK_SIZE_MASK            (3 << 21)
 132#define SLINK_IE_TXC                    (1 << 26)
 133#define SLINK_IE_RXC                    (1 << 27)
 134#define SLINK_DMA_EN                    (1 << 31)
 135
 136#define SLINK_STATUS2                   0x01c
 137#define SLINK_TX_FIFO_EMPTY_COUNT(val)  (((val) & 0x3f) >> 0)
 138#define SLINK_RX_FIFO_FULL_COUNT(val)   (((val) & 0x3f0000) >> 16)
 139#define SLINK_SS_HOLD_TIME(val)         (((val) & 0xF) << 6)
 140
 141#define SLINK_TX_FIFO                   0x100
 142#define SLINK_RX_FIFO                   0x180
 143
 144#define DATA_DIR_TX                     (1 << 0)
 145#define DATA_DIR_RX                     (1 << 1)
 146
 147#define SLINK_DMA_TIMEOUT               (msecs_to_jiffies(1000))
 148
 149#define DEFAULT_SPI_DMA_BUF_LEN         (16*1024)
 150#define TX_FIFO_EMPTY_COUNT_MAX         SLINK_TX_FIFO_EMPTY_COUNT(0x20)
 151#define RX_FIFO_FULL_COUNT_ZERO         SLINK_RX_FIFO_FULL_COUNT(0)
 152
 153#define SLINK_STATUS2_RESET \
 154        (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16)
 155
 156#define MAX_CHIP_SELECT                 4
 157#define SLINK_FIFO_DEPTH                32
 158
 159struct tegra_slink_chip_data {
 160        bool cs_hold_time;
 161};
 162
 163struct tegra_slink_data {
 164        struct device                           *dev;
 165        struct spi_master                       *master;
 166        const struct tegra_slink_chip_data      *chip_data;
 167        spinlock_t                              lock;
 168
 169        struct clk                              *clk;
 170        void __iomem                            *base;
 171        phys_addr_t                             phys;
 172        unsigned                                irq;
 173        int                                     dma_req_sel;
 174        u32                                     spi_max_frequency;
 175        u32                                     cur_speed;
 176
 177        struct spi_device                       *cur_spi;
 178        unsigned                                cur_pos;
 179        unsigned                                cur_len;
 180        unsigned                                words_per_32bit;
 181        unsigned                                bytes_per_word;
 182        unsigned                                curr_dma_words;
 183        unsigned                                cur_direction;
 184
 185        unsigned                                cur_rx_pos;
 186        unsigned                                cur_tx_pos;
 187
 188        unsigned                                dma_buf_size;
 189        unsigned                                max_buf_size;
 190        bool                                    is_curr_dma_xfer;
 191
 192        struct completion                       rx_dma_complete;
 193        struct completion                       tx_dma_complete;
 194
 195        u32                                     tx_status;
 196        u32                                     rx_status;
 197        u32                                     status_reg;
 198        bool                                    is_packed;
 199        unsigned long                           packed_size;
 200
 201        u32                                     command_reg;
 202        u32                                     command2_reg;
 203        u32                                     dma_control_reg;
 204        u32                                     def_command_reg;
 205        u32                                     def_command2_reg;
 206
 207        struct completion                       xfer_completion;
 208        struct spi_transfer                     *curr_xfer;
 209        struct dma_chan                         *rx_dma_chan;
 210        u32                                     *rx_dma_buf;
 211        dma_addr_t                              rx_dma_phys;
 212        struct dma_async_tx_descriptor          *rx_dma_desc;
 213
 214        struct dma_chan                         *tx_dma_chan;
 215        u32                                     *tx_dma_buf;
 216        dma_addr_t                              tx_dma_phys;
 217        struct dma_async_tx_descriptor          *tx_dma_desc;
 218};
 219
 220static int tegra_slink_runtime_suspend(struct device *dev);
 221static int tegra_slink_runtime_resume(struct device *dev);
 222
 223static inline unsigned long tegra_slink_readl(struct tegra_slink_data *tspi,
 224                unsigned long reg)
 225{
 226        return readl(tspi->base + reg);
 227}
 228
 229static inline void tegra_slink_writel(struct tegra_slink_data *tspi,
 230                unsigned long val, unsigned long reg)
 231{
 232        writel(val, tspi->base + reg);
 233
 234        /* Read back register to make sure that register writes completed */
 235        if (reg != SLINK_TX_FIFO)
 236                readl(tspi->base + SLINK_MAS_DATA);
 237}
 238
 239static void tegra_slink_clear_status(struct tegra_slink_data *tspi)
 240{
 241        unsigned long val;
 242        unsigned long val_write = 0;
 243
 244        val = tegra_slink_readl(tspi, SLINK_STATUS);
 245
 246        /* Write 1 to clear status register */
 247        val_write = SLINK_RDY | SLINK_FIFO_ERROR;
 248        tegra_slink_writel(tspi, val_write, SLINK_STATUS);
 249}
 250
 251static unsigned long tegra_slink_get_packed_size(struct tegra_slink_data *tspi,
 252                                  struct spi_transfer *t)
 253{
 254        unsigned long val;
 255
 256        switch (tspi->bytes_per_word) {
 257        case 0:
 258                val = SLINK_PACK_SIZE_4;
 259                break;
 260        case 1:
 261                val = SLINK_PACK_SIZE_8;
 262                break;
 263        case 2:
 264                val = SLINK_PACK_SIZE_16;
 265                break;
 266        case 4:
 267                val = SLINK_PACK_SIZE_32;
 268                break;
 269        default:
 270                val = 0;
 271        }
 272        return val;
 273}
 274
 275static unsigned tegra_slink_calculate_curr_xfer_param(
 276        struct spi_device *spi, struct tegra_slink_data *tspi,
 277        struct spi_transfer *t)
 278{
 279        unsigned remain_len = t->len - tspi->cur_pos;
 280        unsigned max_word;
 281        unsigned bits_per_word ;
 282        unsigned max_len;
 283        unsigned total_fifo_words;
 284
 285        bits_per_word = t->bits_per_word;
 286        tspi->bytes_per_word = (bits_per_word - 1) / 8 + 1;
 287
 288        if (bits_per_word == 8 || bits_per_word == 16) {
 289                tspi->is_packed = 1;
 290                tspi->words_per_32bit = 32/bits_per_word;
 291        } else {
 292                tspi->is_packed = 0;
 293                tspi->words_per_32bit = 1;
 294        }
 295        tspi->packed_size = tegra_slink_get_packed_size(tspi, t);
 296
 297        if (tspi->is_packed) {
 298                max_len = min(remain_len, tspi->max_buf_size);
 299                tspi->curr_dma_words = max_len/tspi->bytes_per_word;
 300                total_fifo_words = max_len/4;
 301        } else {
 302                max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
 303                max_word = min(max_word, tspi->max_buf_size/4);
 304                tspi->curr_dma_words = max_word;
 305                total_fifo_words = max_word;
 306        }
 307        return total_fifo_words;
 308}
 309
 310static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
 311        struct tegra_slink_data *tspi, struct spi_transfer *t)
 312{
 313        unsigned nbytes;
 314        unsigned tx_empty_count;
 315        unsigned long fifo_status;
 316        unsigned max_n_32bit;
 317        unsigned i, count;
 318        unsigned long x;
 319        unsigned int written_words;
 320        unsigned fifo_words_left;
 321        u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
 322
 323        fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
 324        tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status);
 325
 326        if (tspi->is_packed) {
 327                fifo_words_left = tx_empty_count * tspi->words_per_32bit;
 328                written_words = min(fifo_words_left, tspi->curr_dma_words);
 329                nbytes = written_words * tspi->bytes_per_word;
 330                max_n_32bit = DIV_ROUND_UP(nbytes, 4);
 331                for (count = 0; count < max_n_32bit; count++) {
 332                        x = 0;
 333                        for (i = 0; (i < 4) && nbytes; i++, nbytes--)
 334                                x |= (*tx_buf++) << (i*8);
 335                        tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
 336                }
 337        } else {
 338                max_n_32bit = min(tspi->curr_dma_words,  tx_empty_count);
 339                written_words = max_n_32bit;
 340                nbytes = written_words * tspi->bytes_per_word;
 341                for (count = 0; count < max_n_32bit; count++) {
 342                        x = 0;
 343                        for (i = 0; nbytes && (i < tspi->bytes_per_word);
 344                                                        i++, nbytes--)
 345                                x |= ((*tx_buf++) << i*8);
 346                        tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
 347                }
 348        }
 349        tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
 350        return written_words;
 351}
 352
 353static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
 354                struct tegra_slink_data *tspi, struct spi_transfer *t)
 355{
 356        unsigned rx_full_count;
 357        unsigned long fifo_status;
 358        unsigned i, count;
 359        unsigned long x;
 360        unsigned int read_words = 0;
 361        unsigned len;
 362        u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
 363
 364        fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
 365        rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status);
 366        if (tspi->is_packed) {
 367                len = tspi->curr_dma_words * tspi->bytes_per_word;
 368                for (count = 0; count < rx_full_count; count++) {
 369                        x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
 370                        for (i = 0; len && (i < 4); i++, len--)
 371                                *rx_buf++ = (x >> i*8) & 0xFF;
 372                }
 373                tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 374                read_words += tspi->curr_dma_words;
 375        } else {
 376                for (count = 0; count < rx_full_count; count++) {
 377                        x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
 378                        for (i = 0; (i < tspi->bytes_per_word); i++)
 379                                *rx_buf++ = (x >> (i*8)) & 0xFF;
 380                }
 381                tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
 382                read_words += rx_full_count;
 383        }
 384        return read_words;
 385}
 386
 387static void tegra_slink_copy_client_txbuf_to_spi_txbuf(
 388                struct tegra_slink_data *tspi, struct spi_transfer *t)
 389{
 390        unsigned len;
 391
 392        /* Make the dma buffer to read by cpu */
 393        dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
 394                                tspi->dma_buf_size, DMA_TO_DEVICE);
 395
 396        if (tspi->is_packed) {
 397                len = tspi->curr_dma_words * tspi->bytes_per_word;
 398                memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
 399        } else {
 400                unsigned int i;
 401                unsigned int count;
 402                u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
 403                unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
 404                unsigned int x;
 405
 406                for (count = 0; count < tspi->curr_dma_words; count++) {
 407                        x = 0;
 408                        for (i = 0; consume && (i < tspi->bytes_per_word);
 409                                                        i++, consume--)
 410                                x |= ((*tx_buf++) << i * 8);
 411                        tspi->tx_dma_buf[count] = x;
 412                }
 413        }
 414        tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 415
 416        /* Make the dma buffer to read by dma */
 417        dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
 418                                tspi->dma_buf_size, DMA_TO_DEVICE);
 419}
 420
 421static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf(
 422                struct tegra_slink_data *tspi, struct spi_transfer *t)
 423{
 424        unsigned len;
 425
 426        /* Make the dma buffer to read by cpu */
 427        dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
 428                tspi->dma_buf_size, DMA_FROM_DEVICE);
 429
 430        if (tspi->is_packed) {
 431                len = tspi->curr_dma_words * tspi->bytes_per_word;
 432                memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
 433        } else {
 434                unsigned int i;
 435                unsigned int count;
 436                unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
 437                unsigned int x;
 438                unsigned int rx_mask, bits_per_word;
 439
 440                bits_per_word = t->bits_per_word;
 441                rx_mask = (1 << bits_per_word) - 1;
 442                for (count = 0; count < tspi->curr_dma_words; count++) {
 443                        x = tspi->rx_dma_buf[count];
 444                        x &= rx_mask;
 445                        for (i = 0; (i < tspi->bytes_per_word); i++)
 446                                *rx_buf++ = (x >> (i*8)) & 0xFF;
 447                }
 448        }
 449        tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 450
 451        /* Make the dma buffer to read by dma */
 452        dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
 453                tspi->dma_buf_size, DMA_FROM_DEVICE);
 454}
 455
 456static void tegra_slink_dma_complete(void *args)
 457{
 458        struct completion *dma_complete = args;
 459
 460        complete(dma_complete);
 461}
 462
 463static int tegra_slink_start_tx_dma(struct tegra_slink_data *tspi, int len)
 464{
 465        INIT_COMPLETION(tspi->tx_dma_complete);
 466        tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
 467                                tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
 468                                DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
 469        if (!tspi->tx_dma_desc) {
 470                dev_err(tspi->dev, "Not able to get desc for Tx\n");
 471                return -EIO;
 472        }
 473
 474        tspi->tx_dma_desc->callback = tegra_slink_dma_complete;
 475        tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
 476
 477        dmaengine_submit(tspi->tx_dma_desc);
 478        dma_async_issue_pending(tspi->tx_dma_chan);
 479        return 0;
 480}
 481
 482static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len)
 483{
 484        INIT_COMPLETION(tspi->rx_dma_complete);
 485        tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
 486                                tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
 487                                DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
 488        if (!tspi->rx_dma_desc) {
 489                dev_err(tspi->dev, "Not able to get desc for Rx\n");
 490                return -EIO;
 491        }
 492
 493        tspi->rx_dma_desc->callback = tegra_slink_dma_complete;
 494        tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
 495
 496        dmaengine_submit(tspi->rx_dma_desc);
 497        dma_async_issue_pending(tspi->rx_dma_chan);
 498        return 0;
 499}
 500
 501static int tegra_slink_start_dma_based_transfer(
 502                struct tegra_slink_data *tspi, struct spi_transfer *t)
 503{
 504        unsigned long val;
 505        unsigned long test_val;
 506        unsigned int len;
 507        int ret = 0;
 508        unsigned long status;
 509
 510        /* Make sure that Rx and Tx fifo are empty */
 511        status = tegra_slink_readl(tspi, SLINK_STATUS);
 512        if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) {
 513                dev_err(tspi->dev,
 514                        "Rx/Tx fifo are not empty status 0x%08lx\n", status);
 515                return -EIO;
 516        }
 517
 518        val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1);
 519        val |= tspi->packed_size;
 520        if (tspi->is_packed)
 521                len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
 522                                        4) * 4;
 523        else
 524                len = tspi->curr_dma_words * 4;
 525
 526        /* Set attention level based on length of transfer */
 527        if (len & 0xF)
 528                val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1;
 529        else if (((len) >> 4) & 0x1)
 530                val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4;
 531        else
 532                val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8;
 533
 534        if (tspi->cur_direction & DATA_DIR_TX)
 535                val |= SLINK_IE_TXC;
 536
 537        if (tspi->cur_direction & DATA_DIR_RX)
 538                val |= SLINK_IE_RXC;
 539
 540        tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
 541        tspi->dma_control_reg = val;
 542
 543        if (tspi->cur_direction & DATA_DIR_TX) {
 544                tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi, t);
 545                wmb();
 546                ret = tegra_slink_start_tx_dma(tspi, len);
 547                if (ret < 0) {
 548                        dev_err(tspi->dev,
 549                                "Starting tx dma failed, err %d\n", ret);
 550                        return ret;
 551                }
 552
 553                /* Wait for tx fifo to be fill before starting slink */
 554                test_val = tegra_slink_readl(tspi, SLINK_STATUS);
 555                while (!(test_val & SLINK_TX_FULL))
 556                        test_val = tegra_slink_readl(tspi, SLINK_STATUS);
 557        }
 558
 559        if (tspi->cur_direction & DATA_DIR_RX) {
 560                /* Make the dma buffer to read by dma */
 561                dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
 562                                tspi->dma_buf_size, DMA_FROM_DEVICE);
 563
 564                ret = tegra_slink_start_rx_dma(tspi, len);
 565                if (ret < 0) {
 566                        dev_err(tspi->dev,
 567                                "Starting rx dma failed, err %d\n", ret);
 568                        if (tspi->cur_direction & DATA_DIR_TX)
 569                                dmaengine_terminate_all(tspi->tx_dma_chan);
 570                        return ret;
 571                }
 572        }
 573        tspi->is_curr_dma_xfer = true;
 574        if (tspi->is_packed) {
 575                val |= SLINK_PACKED;
 576                tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
 577                /* HW need small delay after settign Packed mode */
 578                udelay(1);
 579        }
 580        tspi->dma_control_reg = val;
 581
 582        val |= SLINK_DMA_EN;
 583        tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
 584        return ret;
 585}
 586
 587static int tegra_slink_start_cpu_based_transfer(
 588                struct tegra_slink_data *tspi, struct spi_transfer *t)
 589{
 590        unsigned long val;
 591        unsigned cur_words;
 592
 593        val = tspi->packed_size;
 594        if (tspi->cur_direction & DATA_DIR_TX)
 595                val |= SLINK_IE_TXC;
 596
 597        if (tspi->cur_direction & DATA_DIR_RX)
 598                val |= SLINK_IE_RXC;
 599
 600        tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
 601        tspi->dma_control_reg = val;
 602
 603        if (tspi->cur_direction & DATA_DIR_TX)
 604                cur_words = tegra_slink_fill_tx_fifo_from_client_txbuf(tspi, t);
 605        else
 606                cur_words = tspi->curr_dma_words;
 607        val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1);
 608        tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
 609        tspi->dma_control_reg = val;
 610
 611        tspi->is_curr_dma_xfer = false;
 612        if (tspi->is_packed) {
 613                val |= SLINK_PACKED;
 614                tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
 615                udelay(1);
 616                wmb();
 617        }
 618        tspi->dma_control_reg = val;
 619        val |= SLINK_DMA_EN;
 620        tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
 621        return 0;
 622}
 623
 624static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi,
 625                        bool dma_to_memory)
 626{
 627        struct dma_chan *dma_chan;
 628        u32 *dma_buf;
 629        dma_addr_t dma_phys;
 630        int ret;
 631        struct dma_slave_config dma_sconfig;
 632        dma_cap_mask_t mask;
 633
 634        dma_cap_zero(mask);
 635        dma_cap_set(DMA_SLAVE, mask);
 636        dma_chan = dma_request_channel(mask, NULL, NULL);
 637        if (!dma_chan) {
 638                dev_err(tspi->dev,
 639                        "Dma channel is not available, will try later\n");
 640                return -EPROBE_DEFER;
 641        }
 642
 643        dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
 644                                &dma_phys, GFP_KERNEL);
 645        if (!dma_buf) {
 646                dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
 647                dma_release_channel(dma_chan);
 648                return -ENOMEM;
 649        }
 650
 651        dma_sconfig.slave_id = tspi->dma_req_sel;
 652        if (dma_to_memory) {
 653                dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
 654                dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 655                dma_sconfig.src_maxburst = 0;
 656        } else {
 657                dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO;
 658                dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 659                dma_sconfig.dst_maxburst = 0;
 660        }
 661
 662        ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
 663        if (ret)
 664                goto scrub;
 665        if (dma_to_memory) {
 666                tspi->rx_dma_chan = dma_chan;
 667                tspi->rx_dma_buf = dma_buf;
 668                tspi->rx_dma_phys = dma_phys;
 669        } else {
 670                tspi->tx_dma_chan = dma_chan;
 671                tspi->tx_dma_buf = dma_buf;
 672                tspi->tx_dma_phys = dma_phys;
 673        }
 674        return 0;
 675
 676scrub:
 677        dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
 678        dma_release_channel(dma_chan);
 679        return ret;
 680}
 681
 682static void tegra_slink_deinit_dma_param(struct tegra_slink_data *tspi,
 683        bool dma_to_memory)
 684{
 685        u32 *dma_buf;
 686        dma_addr_t dma_phys;
 687        struct dma_chan *dma_chan;
 688
 689        if (dma_to_memory) {
 690                dma_buf = tspi->rx_dma_buf;
 691                dma_chan = tspi->rx_dma_chan;
 692                dma_phys = tspi->rx_dma_phys;
 693                tspi->rx_dma_chan = NULL;
 694                tspi->rx_dma_buf = NULL;
 695        } else {
 696                dma_buf = tspi->tx_dma_buf;
 697                dma_chan = tspi->tx_dma_chan;
 698                dma_phys = tspi->tx_dma_phys;
 699                tspi->tx_dma_buf = NULL;
 700                tspi->tx_dma_chan = NULL;
 701        }
 702        if (!dma_chan)
 703                return;
 704
 705        dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
 706        dma_release_channel(dma_chan);
 707}
 708
 709static int tegra_slink_start_transfer_one(struct spi_device *spi,
 710                struct spi_transfer *t, bool is_first_of_msg,
 711                bool is_single_xfer)
 712{
 713        struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
 714        u32 speed;
 715        u8 bits_per_word;
 716        unsigned total_fifo_words;
 717        int ret;
 718        unsigned long command;
 719        unsigned long command2;
 720
 721        bits_per_word = t->bits_per_word;
 722        speed = t->speed_hz;
 723        if (speed != tspi->cur_speed) {
 724                clk_set_rate(tspi->clk, speed * 4);
 725                tspi->cur_speed = speed;
 726        }
 727
 728        tspi->cur_spi = spi;
 729        tspi->cur_pos = 0;
 730        tspi->cur_rx_pos = 0;
 731        tspi->cur_tx_pos = 0;
 732        tspi->curr_xfer = t;
 733        total_fifo_words = tegra_slink_calculate_curr_xfer_param(spi, tspi, t);
 734
 735        if (is_first_of_msg) {
 736                tegra_slink_clear_status(tspi);
 737
 738                command = tspi->def_command_reg;
 739                command |= SLINK_BIT_LENGTH(bits_per_word - 1);
 740                command |= SLINK_CS_SW | SLINK_CS_VALUE;
 741
 742                command2 = tspi->def_command2_reg;
 743                command2 |= SLINK_SS_EN_CS(spi->chip_select);
 744
 745                command &= ~SLINK_MODES;
 746                if (spi->mode & SPI_CPHA)
 747                        command |= SLINK_CK_SDA;
 748
 749                if (spi->mode & SPI_CPOL)
 750                        command |= SLINK_IDLE_SCLK_DRIVE_HIGH;
 751                else
 752                        command |= SLINK_IDLE_SCLK_DRIVE_LOW;
 753        } else {
 754                command = tspi->command_reg;
 755                command &= ~SLINK_BIT_LENGTH(~0);
 756                command |= SLINK_BIT_LENGTH(bits_per_word - 1);
 757
 758                command2 = tspi->command2_reg;
 759                command2 &= ~(SLINK_RXEN | SLINK_TXEN);
 760        }
 761
 762        tegra_slink_writel(tspi, command, SLINK_COMMAND);
 763        tspi->command_reg = command;
 764
 765        tspi->cur_direction = 0;
 766        if (t->rx_buf) {
 767                command2 |= SLINK_RXEN;
 768                tspi->cur_direction |= DATA_DIR_RX;
 769        }
 770        if (t->tx_buf) {
 771                command2 |= SLINK_TXEN;
 772                tspi->cur_direction |= DATA_DIR_TX;
 773        }
 774        tegra_slink_writel(tspi, command2, SLINK_COMMAND2);
 775        tspi->command2_reg = command2;
 776
 777        if (total_fifo_words > SLINK_FIFO_DEPTH)
 778                ret = tegra_slink_start_dma_based_transfer(tspi, t);
 779        else
 780                ret = tegra_slink_start_cpu_based_transfer(tspi, t);
 781        return ret;
 782}
 783
 784static int tegra_slink_setup(struct spi_device *spi)
 785{
 786        struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
 787        unsigned long val;
 788        unsigned long flags;
 789        int ret;
 790        unsigned int cs_pol_bit[MAX_CHIP_SELECT] = {
 791                        SLINK_CS_POLARITY,
 792                        SLINK_CS_POLARITY1,
 793                        SLINK_CS_POLARITY2,
 794                        SLINK_CS_POLARITY3,
 795        };
 796
 797        dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
 798                spi->bits_per_word,
 799                spi->mode & SPI_CPOL ? "" : "~",
 800                spi->mode & SPI_CPHA ? "" : "~",
 801                spi->max_speed_hz);
 802
 803        BUG_ON(spi->chip_select >= MAX_CHIP_SELECT);
 804
 805        /* Set speed to the spi max fequency if spi device has not set */
 806        spi->max_speed_hz = spi->max_speed_hz ? : tspi->spi_max_frequency;
 807        ret = pm_runtime_get_sync(tspi->dev);
 808        if (ret < 0) {
 809                dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
 810                return ret;
 811        }
 812
 813        spin_lock_irqsave(&tspi->lock, flags);
 814        val = tspi->def_command_reg;
 815        if (spi->mode & SPI_CS_HIGH)
 816                val |= cs_pol_bit[spi->chip_select];
 817        else
 818                val &= ~cs_pol_bit[spi->chip_select];
 819        tspi->def_command_reg = val;
 820        tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
 821        spin_unlock_irqrestore(&tspi->lock, flags);
 822
 823        pm_runtime_put(tspi->dev);
 824        return 0;
 825}
 826
 827static int tegra_slink_transfer_one_message(struct spi_master *master,
 828                        struct spi_message *msg)
 829{
 830        bool is_first_msg = true;
 831        int single_xfer;
 832        struct tegra_slink_data *tspi = spi_master_get_devdata(master);
 833        struct spi_transfer *xfer;
 834        struct spi_device *spi = msg->spi;
 835        int ret;
 836
 837        msg->status = 0;
 838        msg->actual_length = 0;
 839        ret = pm_runtime_get_sync(tspi->dev);
 840        if (ret < 0) {
 841                dev_err(tspi->dev, "runtime get failed: %d\n", ret);
 842                goto done;
 843        }
 844
 845        single_xfer = list_is_singular(&msg->transfers);
 846        list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 847                INIT_COMPLETION(tspi->xfer_completion);
 848                ret = tegra_slink_start_transfer_one(spi, xfer,
 849                                        is_first_msg, single_xfer);
 850                if (ret < 0) {
 851                        dev_err(tspi->dev,
 852                                "spi can not start transfer, err %d\n", ret);
 853                        goto exit;
 854                }
 855                is_first_msg = false;
 856                ret = wait_for_completion_timeout(&tspi->xfer_completion,
 857                                                SLINK_DMA_TIMEOUT);
 858                if (WARN_ON(ret == 0)) {
 859                        dev_err(tspi->dev,
 860                                "spi trasfer timeout, err %d\n", ret);
 861                        ret = -EIO;
 862                        goto exit;
 863                }
 864
 865                if (tspi->tx_status ||  tspi->rx_status) {
 866                        dev_err(tspi->dev, "Error in Transfer\n");
 867                        ret = -EIO;
 868                        goto exit;
 869                }
 870                msg->actual_length += xfer->len;
 871                if (xfer->cs_change && xfer->delay_usecs) {
 872                        tegra_slink_writel(tspi, tspi->def_command_reg,
 873                                        SLINK_COMMAND);
 874                        udelay(xfer->delay_usecs);
 875                }
 876        }
 877        ret = 0;
 878exit:
 879        tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
 880        tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
 881        pm_runtime_put(tspi->dev);
 882done:
 883        msg->status = ret;
 884        spi_finalize_current_message(master);
 885        return ret;
 886}
 887
 888static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi)
 889{
 890        struct spi_transfer *t = tspi->curr_xfer;
 891        unsigned long flags;
 892
 893        spin_lock_irqsave(&tspi->lock, flags);
 894        if (tspi->tx_status ||  tspi->rx_status ||
 895                                (tspi->status_reg & SLINK_BSY)) {
 896                dev_err(tspi->dev,
 897                        "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg);
 898                dev_err(tspi->dev,
 899                        "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
 900                                tspi->command2_reg, tspi->dma_control_reg);
 901                tegra_periph_reset_assert(tspi->clk);
 902                udelay(2);
 903                tegra_periph_reset_deassert(tspi->clk);
 904                complete(&tspi->xfer_completion);
 905                goto exit;
 906        }
 907
 908        if (tspi->cur_direction & DATA_DIR_RX)
 909                tegra_slink_read_rx_fifo_to_client_rxbuf(tspi, t);
 910
 911        if (tspi->cur_direction & DATA_DIR_TX)
 912                tspi->cur_pos = tspi->cur_tx_pos;
 913        else
 914                tspi->cur_pos = tspi->cur_rx_pos;
 915
 916        if (tspi->cur_pos == t->len) {
 917                complete(&tspi->xfer_completion);
 918                goto exit;
 919        }
 920
 921        tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
 922        tegra_slink_start_cpu_based_transfer(tspi, t);
 923exit:
 924        spin_unlock_irqrestore(&tspi->lock, flags);
 925        return IRQ_HANDLED;
 926}
 927
 928static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi)
 929{
 930        struct spi_transfer *t = tspi->curr_xfer;
 931        long wait_status;
 932        int err = 0;
 933        unsigned total_fifo_words;
 934        unsigned long flags;
 935
 936        /* Abort dmas if any error */
 937        if (tspi->cur_direction & DATA_DIR_TX) {
 938                if (tspi->tx_status) {
 939                        dmaengine_terminate_all(tspi->tx_dma_chan);
 940                        err += 1;
 941                } else {
 942                        wait_status = wait_for_completion_interruptible_timeout(
 943                                &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT);
 944                        if (wait_status <= 0) {
 945                                dmaengine_terminate_all(tspi->tx_dma_chan);
 946                                dev_err(tspi->dev, "TxDma Xfer failed\n");
 947                                err += 1;
 948                        }
 949                }
 950        }
 951
 952        if (tspi->cur_direction & DATA_DIR_RX) {
 953                if (tspi->rx_status) {
 954                        dmaengine_terminate_all(tspi->rx_dma_chan);
 955                        err += 2;
 956                } else {
 957                        wait_status = wait_for_completion_interruptible_timeout(
 958                                &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT);
 959                        if (wait_status <= 0) {
 960                                dmaengine_terminate_all(tspi->rx_dma_chan);
 961                                dev_err(tspi->dev, "RxDma Xfer failed\n");
 962                                err += 2;
 963                        }
 964                }
 965        }
 966
 967        spin_lock_irqsave(&tspi->lock, flags);
 968        if (err) {
 969                dev_err(tspi->dev,
 970                        "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg);
 971                dev_err(tspi->dev,
 972                        "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
 973                                tspi->command2_reg, tspi->dma_control_reg);
 974                tegra_periph_reset_assert(tspi->clk);
 975                udelay(2);
 976                tegra_periph_reset_deassert(tspi->clk);
 977                complete(&tspi->xfer_completion);
 978                spin_unlock_irqrestore(&tspi->lock, flags);
 979                return IRQ_HANDLED;
 980        }
 981
 982        if (tspi->cur_direction & DATA_DIR_RX)
 983                tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
 984
 985        if (tspi->cur_direction & DATA_DIR_TX)
 986                tspi->cur_pos = tspi->cur_tx_pos;
 987        else
 988                tspi->cur_pos = tspi->cur_rx_pos;
 989
 990        if (tspi->cur_pos == t->len) {
 991                complete(&tspi->xfer_completion);
 992                goto exit;
 993        }
 994
 995        /* Continue transfer in current message */
 996        total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi,
 997                                                        tspi, t);
 998        if (total_fifo_words > SLINK_FIFO_DEPTH)
 999                err = tegra_slink_start_dma_based_transfer(tspi, t);
1000        else
1001                err = tegra_slink_start_cpu_based_transfer(tspi, t);
1002
1003exit:
1004        spin_unlock_irqrestore(&tspi->lock, flags);
1005        return IRQ_HANDLED;
1006}
1007
1008static irqreturn_t tegra_slink_isr_thread(int irq, void *context_data)
1009{
1010        struct tegra_slink_data *tspi = context_data;
1011
1012        if (!tspi->is_curr_dma_xfer)
1013                return handle_cpu_based_xfer(tspi);
1014        return handle_dma_based_xfer(tspi);
1015}
1016
1017static irqreturn_t tegra_slink_isr(int irq, void *context_data)
1018{
1019        struct tegra_slink_data *tspi = context_data;
1020
1021        tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS);
1022        if (tspi->cur_direction & DATA_DIR_TX)
1023                tspi->tx_status = tspi->status_reg &
1024                                        (SLINK_TX_OVF | SLINK_TX_UNF);
1025
1026        if (tspi->cur_direction & DATA_DIR_RX)
1027                tspi->rx_status = tspi->status_reg &
1028                                        (SLINK_RX_OVF | SLINK_RX_UNF);
1029        tegra_slink_clear_status(tspi);
1030
1031        return IRQ_WAKE_THREAD;
1032}
1033
1034static void tegra_slink_parse_dt(struct tegra_slink_data *tspi)
1035{
1036        struct device_node *np = tspi->dev->of_node;
1037        u32 of_dma[2];
1038
1039        if (of_property_read_u32_array(np, "nvidia,dma-request-selector",
1040                                of_dma, 2) >= 0)
1041                tspi->dma_req_sel = of_dma[1];
1042
1043        if (of_property_read_u32(np, "spi-max-frequency",
1044                                        &tspi->spi_max_frequency))
1045                tspi->spi_max_frequency = 25000000; /* 25MHz */
1046}
1047
1048static const struct tegra_slink_chip_data tegra30_spi_cdata = {
1049        .cs_hold_time = true,
1050};
1051
1052static const struct tegra_slink_chip_data tegra20_spi_cdata = {
1053        .cs_hold_time = false,
1054};
1055
1056static struct of_device_id tegra_slink_of_match[] = {
1057        { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, },
1058        { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, },
1059        {}
1060};
1061MODULE_DEVICE_TABLE(of, tegra_slink_of_match);
1062
1063static int tegra_slink_probe(struct platform_device *pdev)
1064{
1065        struct spi_master       *master;
1066        struct tegra_slink_data *tspi;
1067        struct resource         *r;
1068        int ret, spi_irq;
1069        const struct tegra_slink_chip_data *cdata = NULL;
1070        const struct of_device_id *match;
1071
1072        match = of_match_device(tegra_slink_of_match, &pdev->dev);
1073        if (!match) {
1074                dev_err(&pdev->dev, "Error: No device match found\n");
1075                return -ENODEV;
1076        }
1077        cdata = match->data;
1078
1079        master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1080        if (!master) {
1081                dev_err(&pdev->dev, "master allocation failed\n");
1082                return -ENOMEM;
1083        }
1084
1085        /* the spi->mode bits understood by this driver: */
1086        master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1087        master->setup = tegra_slink_setup;
1088        master->transfer_one_message = tegra_slink_transfer_one_message;
1089        master->num_chipselect = MAX_CHIP_SELECT;
1090        master->bus_num = -1;
1091
1092        dev_set_drvdata(&pdev->dev, master);
1093        tspi = spi_master_get_devdata(master);
1094        tspi->master = master;
1095        tspi->dev = &pdev->dev;
1096        tspi->chip_data = cdata;
1097        spin_lock_init(&tspi->lock);
1098
1099        tegra_slink_parse_dt(tspi);
1100
1101        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1102        if (!r) {
1103                dev_err(&pdev->dev, "No IO memory resource\n");
1104                ret = -ENODEV;
1105                goto exit_free_master;
1106        }
1107        tspi->phys = r->start;
1108        tspi->base = devm_ioremap_resource(&pdev->dev, r);
1109        if (IS_ERR(tspi->base)) {
1110                ret = PTR_ERR(tspi->base);
1111                goto exit_free_master;
1112        }
1113
1114        spi_irq = platform_get_irq(pdev, 0);
1115        tspi->irq = spi_irq;
1116        ret = request_threaded_irq(tspi->irq, tegra_slink_isr,
1117                        tegra_slink_isr_thread, IRQF_ONESHOT,
1118                        dev_name(&pdev->dev), tspi);
1119        if (ret < 0) {
1120                dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1121                                        tspi->irq);
1122                goto exit_free_master;
1123        }
1124
1125        tspi->clk = devm_clk_get(&pdev->dev, NULL);
1126        if (IS_ERR(tspi->clk)) {
1127                dev_err(&pdev->dev, "can not get clock\n");
1128                ret = PTR_ERR(tspi->clk);
1129                goto exit_free_irq;
1130        }
1131
1132        tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
1133        tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1134
1135        if (tspi->dma_req_sel) {
1136                ret = tegra_slink_init_dma_param(tspi, true);
1137                if (ret < 0) {
1138                        dev_err(&pdev->dev, "RxDma Init failed, err %d\n", ret);
1139                        goto exit_free_irq;
1140                }
1141
1142                ret = tegra_slink_init_dma_param(tspi, false);
1143                if (ret < 0) {
1144                        dev_err(&pdev->dev, "TxDma Init failed, err %d\n", ret);
1145                        goto exit_rx_dma_free;
1146                }
1147                tspi->max_buf_size = tspi->dma_buf_size;
1148                init_completion(&tspi->tx_dma_complete);
1149                init_completion(&tspi->rx_dma_complete);
1150        }
1151
1152        init_completion(&tspi->xfer_completion);
1153
1154        pm_runtime_enable(&pdev->dev);
1155        if (!pm_runtime_enabled(&pdev->dev)) {
1156                ret = tegra_slink_runtime_resume(&pdev->dev);
1157                if (ret)
1158                        goto exit_pm_disable;
1159        }
1160
1161        ret = pm_runtime_get_sync(&pdev->dev);
1162        if (ret < 0) {
1163                dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1164                goto exit_pm_disable;
1165        }
1166        tspi->def_command_reg  = SLINK_M_S;
1167        tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN;
1168        tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
1169        tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
1170        pm_runtime_put(&pdev->dev);
1171
1172        master->dev.of_node = pdev->dev.of_node;
1173        ret = spi_register_master(master);
1174        if (ret < 0) {
1175                dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1176                goto exit_pm_disable;
1177        }
1178        return ret;
1179
1180exit_pm_disable:
1181        pm_runtime_disable(&pdev->dev);
1182        if (!pm_runtime_status_suspended(&pdev->dev))
1183                tegra_slink_runtime_suspend(&pdev->dev);
1184        tegra_slink_deinit_dma_param(tspi, false);
1185exit_rx_dma_free:
1186        tegra_slink_deinit_dma_param(tspi, true);
1187exit_free_irq:
1188        free_irq(spi_irq, tspi);
1189exit_free_master:
1190        spi_master_put(master);
1191        return ret;
1192}
1193
1194static int tegra_slink_remove(struct platform_device *pdev)
1195{
1196        struct spi_master *master = dev_get_drvdata(&pdev->dev);
1197        struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1198
1199        free_irq(tspi->irq, tspi);
1200        spi_unregister_master(master);
1201
1202        if (tspi->tx_dma_chan)
1203                tegra_slink_deinit_dma_param(tspi, false);
1204
1205        if (tspi->rx_dma_chan)
1206                tegra_slink_deinit_dma_param(tspi, true);
1207
1208        pm_runtime_disable(&pdev->dev);
1209        if (!pm_runtime_status_suspended(&pdev->dev))
1210                tegra_slink_runtime_suspend(&pdev->dev);
1211
1212        return 0;
1213}
1214
1215#ifdef CONFIG_PM_SLEEP
1216static int tegra_slink_suspend(struct device *dev)
1217{
1218        struct spi_master *master = dev_get_drvdata(dev);
1219
1220        return spi_master_suspend(master);
1221}
1222
1223static int tegra_slink_resume(struct device *dev)
1224{
1225        struct spi_master *master = dev_get_drvdata(dev);
1226        struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1227        int ret;
1228
1229        ret = pm_runtime_get_sync(dev);
1230        if (ret < 0) {
1231                dev_err(dev, "pm runtime failed, e = %d\n", ret);
1232                return ret;
1233        }
1234        tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND);
1235        tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2);
1236        pm_runtime_put(dev);
1237
1238        return spi_master_resume(master);
1239}
1240#endif
1241
1242static int tegra_slink_runtime_suspend(struct device *dev)
1243{
1244        struct spi_master *master = dev_get_drvdata(dev);
1245        struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1246
1247        /* Flush all write which are in PPSB queue by reading back */
1248        tegra_slink_readl(tspi, SLINK_MAS_DATA);
1249
1250        clk_disable_unprepare(tspi->clk);
1251        return 0;
1252}
1253
1254static int tegra_slink_runtime_resume(struct device *dev)
1255{
1256        struct spi_master *master = dev_get_drvdata(dev);
1257        struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1258        int ret;
1259
1260        ret = clk_prepare_enable(tspi->clk);
1261        if (ret < 0) {
1262                dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1263                return ret;
1264        }
1265        return 0;
1266}
1267
1268static const struct dev_pm_ops slink_pm_ops = {
1269        SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend,
1270                tegra_slink_runtime_resume, NULL)
1271        SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend, tegra_slink_resume)
1272};
1273static struct platform_driver tegra_slink_driver = {
1274        .driver = {
1275                .name           = "spi-tegra-slink",
1276                .owner          = THIS_MODULE,
1277                .pm             = &slink_pm_ops,
1278                .of_match_table = tegra_slink_of_match,
1279        },
1280        .probe =        tegra_slink_probe,
1281        .remove =       tegra_slink_remove,
1282};
1283module_platform_driver(tegra_slink_driver);
1284
1285MODULE_ALIAS("platform:spi-tegra-slink");
1286MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver");
1287MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1288MODULE_LICENSE("GPL v2");
1289
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