linux/drivers/spi/spi-omap2-mcspi.c
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   1/*
   2 * OMAP2 McSPI controller driver
   3 *
   4 * Copyright (C) 2005, 2006 Nokia Corporation
   5 * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
   6 *              Juha Yrj�l� <juha.yrjola@nokia.com>
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License as published by
  10 * the Free Software Foundation; either version 2 of the License, or
  11 * (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21 *
  22 */
  23
  24#include <linux/kernel.h>
  25#include <linux/init.h>
  26#include <linux/interrupt.h>
  27#include <linux/module.h>
  28#include <linux/device.h>
  29#include <linux/delay.h>
  30#include <linux/dma-mapping.h>
  31#include <linux/dmaengine.h>
  32#include <linux/omap-dma.h>
  33#include <linux/platform_device.h>
  34#include <linux/err.h>
  35#include <linux/clk.h>
  36#include <linux/io.h>
  37#include <linux/slab.h>
  38#include <linux/pm_runtime.h>
  39#include <linux/of.h>
  40#include <linux/of_device.h>
  41#include <linux/pinctrl/consumer.h>
  42
  43#include <linux/spi/spi.h>
  44
  45#include <linux/platform_data/spi-omap2-mcspi.h>
  46
  47#define OMAP2_MCSPI_MAX_FREQ            48000000
  48#define SPI_AUTOSUSPEND_TIMEOUT         2000
  49
  50#define OMAP2_MCSPI_REVISION            0x00
  51#define OMAP2_MCSPI_SYSSTATUS           0x14
  52#define OMAP2_MCSPI_IRQSTATUS           0x18
  53#define OMAP2_MCSPI_IRQENABLE           0x1c
  54#define OMAP2_MCSPI_WAKEUPENABLE        0x20
  55#define OMAP2_MCSPI_SYST                0x24
  56#define OMAP2_MCSPI_MODULCTRL           0x28
  57
  58/* per-channel banks, 0x14 bytes each, first is: */
  59#define OMAP2_MCSPI_CHCONF0             0x2c
  60#define OMAP2_MCSPI_CHSTAT0             0x30
  61#define OMAP2_MCSPI_CHCTRL0             0x34
  62#define OMAP2_MCSPI_TX0                 0x38
  63#define OMAP2_MCSPI_RX0                 0x3c
  64
  65/* per-register bitmasks: */
  66
  67#define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
  68#define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
  69#define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
  70
  71#define OMAP2_MCSPI_CHCONF_PHA          BIT(0)
  72#define OMAP2_MCSPI_CHCONF_POL          BIT(1)
  73#define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
  74#define OMAP2_MCSPI_CHCONF_EPOL         BIT(6)
  75#define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
  76#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
  77#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
  78#define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
  79#define OMAP2_MCSPI_CHCONF_DMAW         BIT(14)
  80#define OMAP2_MCSPI_CHCONF_DMAR         BIT(15)
  81#define OMAP2_MCSPI_CHCONF_DPE0         BIT(16)
  82#define OMAP2_MCSPI_CHCONF_DPE1         BIT(17)
  83#define OMAP2_MCSPI_CHCONF_IS           BIT(18)
  84#define OMAP2_MCSPI_CHCONF_TURBO        BIT(19)
  85#define OMAP2_MCSPI_CHCONF_FORCE        BIT(20)
  86
  87#define OMAP2_MCSPI_CHSTAT_RXS          BIT(0)
  88#define OMAP2_MCSPI_CHSTAT_TXS          BIT(1)
  89#define OMAP2_MCSPI_CHSTAT_EOT          BIT(2)
  90
  91#define OMAP2_MCSPI_CHCTRL_EN           BIT(0)
  92
  93#define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
  94
  95/* We have 2 DMA channels per CS, one for RX and one for TX */
  96struct omap2_mcspi_dma {
  97        struct dma_chan *dma_tx;
  98        struct dma_chan *dma_rx;
  99
 100        int dma_tx_sync_dev;
 101        int dma_rx_sync_dev;
 102
 103        struct completion dma_tx_completion;
 104        struct completion dma_rx_completion;
 105};
 106
 107/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 108 * cache operations; better heuristics consider wordsize and bitrate.
 109 */
 110#define DMA_MIN_BYTES                   160
 111
 112
 113/*
 114 * Used for context save and restore, structure members to be updated whenever
 115 * corresponding registers are modified.
 116 */
 117struct omap2_mcspi_regs {
 118        u32 modulctrl;
 119        u32 wakeupenable;
 120        struct list_head cs;
 121};
 122
 123struct omap2_mcspi {
 124        struct spi_master       *master;
 125        /* Virtual base address of the controller */
 126        void __iomem            *base;
 127        unsigned long           phys;
 128        /* SPI1 has 4 channels, while SPI2 has 2 */
 129        struct omap2_mcspi_dma  *dma_channels;
 130        struct device           *dev;
 131        struct omap2_mcspi_regs ctx;
 132        unsigned int            pin_dir:1;
 133};
 134
 135struct omap2_mcspi_cs {
 136        void __iomem            *base;
 137        unsigned long           phys;
 138        int                     word_len;
 139        struct list_head        node;
 140        /* Context save and restore shadow register */
 141        u32                     chconf0;
 142};
 143
 144static inline void mcspi_write_reg(struct spi_master *master,
 145                int idx, u32 val)
 146{
 147        struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 148
 149        __raw_writel(val, mcspi->base + idx);
 150}
 151
 152static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
 153{
 154        struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 155
 156        return __raw_readl(mcspi->base + idx);
 157}
 158
 159static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 160                int idx, u32 val)
 161{
 162        struct omap2_mcspi_cs   *cs = spi->controller_state;
 163
 164        __raw_writel(val, cs->base +  idx);
 165}
 166
 167static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
 168{
 169        struct omap2_mcspi_cs   *cs = spi->controller_state;
 170
 171        return __raw_readl(cs->base + idx);
 172}
 173
 174static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
 175{
 176        struct omap2_mcspi_cs *cs = spi->controller_state;
 177
 178        return cs->chconf0;
 179}
 180
 181static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
 182{
 183        struct omap2_mcspi_cs *cs = spi->controller_state;
 184
 185        cs->chconf0 = val;
 186        mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
 187        mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 188}
 189
 190static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
 191                int is_read, int enable)
 192{
 193        u32 l, rw;
 194
 195        l = mcspi_cached_chconf0(spi);
 196
 197        if (is_read) /* 1 is read, 0 write */
 198                rw = OMAP2_MCSPI_CHCONF_DMAR;
 199        else
 200                rw = OMAP2_MCSPI_CHCONF_DMAW;
 201
 202        if (enable)
 203                l |= rw;
 204        else
 205                l &= ~rw;
 206
 207        mcspi_write_chconf0(spi, l);
 208}
 209
 210static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 211{
 212        u32 l;
 213
 214        l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
 215        mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
 216        /* Flash post-writes */
 217        mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
 218}
 219
 220static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
 221{
 222        u32 l;
 223
 224        l = mcspi_cached_chconf0(spi);
 225        if (cs_active)
 226                l |= OMAP2_MCSPI_CHCONF_FORCE;
 227        else
 228                l &= ~OMAP2_MCSPI_CHCONF_FORCE;
 229
 230        mcspi_write_chconf0(spi, l);
 231}
 232
 233static void omap2_mcspi_set_master_mode(struct spi_master *master)
 234{
 235        struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
 236        struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 237        u32 l;
 238
 239        /*
 240         * Setup when switching from (reset default) slave mode
 241         * to single-channel master mode
 242         */
 243        l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
 244        l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
 245        l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
 246        mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
 247
 248        ctx->modulctrl = l;
 249}
 250
 251static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
 252{
 253        struct spi_master       *spi_cntrl = mcspi->master;
 254        struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 255        struct omap2_mcspi_cs   *cs;
 256
 257        /* McSPI: context restore */
 258        mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
 259        mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
 260
 261        list_for_each_entry(cs, &ctx->cs, node)
 262                __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
 263}
 264
 265static int omap2_prepare_transfer(struct spi_master *master)
 266{
 267        struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 268
 269        pm_runtime_get_sync(mcspi->dev);
 270        return 0;
 271}
 272
 273static int omap2_unprepare_transfer(struct spi_master *master)
 274{
 275        struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 276
 277        pm_runtime_mark_last_busy(mcspi->dev);
 278        pm_runtime_put_autosuspend(mcspi->dev);
 279        return 0;
 280}
 281
 282static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
 283{
 284        unsigned long timeout;
 285
 286        timeout = jiffies + msecs_to_jiffies(1000);
 287        while (!(__raw_readl(reg) & bit)) {
 288                if (time_after(jiffies, timeout)) {
 289                        if (!(__raw_readl(reg) & bit))
 290                                return -ETIMEDOUT;
 291                        else
 292                                return 0;
 293                }
 294                cpu_relax();
 295        }
 296        return 0;
 297}
 298
 299static void omap2_mcspi_rx_callback(void *data)
 300{
 301        struct spi_device *spi = data;
 302        struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 303        struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 304
 305        /* We must disable the DMA RX request */
 306        omap2_mcspi_set_dma_req(spi, 1, 0);
 307
 308        complete(&mcspi_dma->dma_rx_completion);
 309}
 310
 311static void omap2_mcspi_tx_callback(void *data)
 312{
 313        struct spi_device *spi = data;
 314        struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 315        struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 316
 317        /* We must disable the DMA TX request */
 318        omap2_mcspi_set_dma_req(spi, 0, 0);
 319
 320        complete(&mcspi_dma->dma_tx_completion);
 321}
 322
 323static void omap2_mcspi_tx_dma(struct spi_device *spi,
 324                                struct spi_transfer *xfer,
 325                                struct dma_slave_config cfg)
 326{
 327        struct omap2_mcspi      *mcspi;
 328        struct omap2_mcspi_dma  *mcspi_dma;
 329        unsigned int            count;
 330
 331        mcspi = spi_master_get_devdata(spi->master);
 332        mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 333        count = xfer->len;
 334
 335        if (mcspi_dma->dma_tx) {
 336                struct dma_async_tx_descriptor *tx;
 337                struct scatterlist sg;
 338
 339                dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
 340
 341                sg_init_table(&sg, 1);
 342                sg_dma_address(&sg) = xfer->tx_dma;
 343                sg_dma_len(&sg) = xfer->len;
 344
 345                tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
 346                DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 347                if (tx) {
 348                        tx->callback = omap2_mcspi_tx_callback;
 349                        tx->callback_param = spi;
 350                        dmaengine_submit(tx);
 351                } else {
 352                        /* FIXME: fall back to PIO? */
 353                }
 354        }
 355        dma_async_issue_pending(mcspi_dma->dma_tx);
 356        omap2_mcspi_set_dma_req(spi, 0, 1);
 357
 358}
 359
 360static unsigned
 361omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
 362                                struct dma_slave_config cfg,
 363                                unsigned es)
 364{
 365        struct omap2_mcspi      *mcspi;
 366        struct omap2_mcspi_dma  *mcspi_dma;
 367        unsigned int            count;
 368        u32                     l;
 369        int                     elements = 0;
 370        int                     word_len, element_count;
 371        struct omap2_mcspi_cs   *cs = spi->controller_state;
 372        mcspi = spi_master_get_devdata(spi->master);
 373        mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 374        count = xfer->len;
 375        word_len = cs->word_len;
 376        l = mcspi_cached_chconf0(spi);
 377
 378        if (word_len <= 8)
 379                element_count = count;
 380        else if (word_len <= 16)
 381                element_count = count >> 1;
 382        else /* word_len <= 32 */
 383                element_count = count >> 2;
 384
 385        if (mcspi_dma->dma_rx) {
 386                struct dma_async_tx_descriptor *tx;
 387                struct scatterlist sg;
 388                size_t len = xfer->len - es;
 389
 390                dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
 391
 392                if (l & OMAP2_MCSPI_CHCONF_TURBO)
 393                        len -= es;
 394
 395                sg_init_table(&sg, 1);
 396                sg_dma_address(&sg) = xfer->rx_dma;
 397                sg_dma_len(&sg) = len;
 398
 399                tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
 400                                DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
 401                                DMA_CTRL_ACK);
 402                if (tx) {
 403                        tx->callback = omap2_mcspi_rx_callback;
 404                        tx->callback_param = spi;
 405                        dmaengine_submit(tx);
 406                } else {
 407                                /* FIXME: fall back to PIO? */
 408                }
 409        }
 410
 411        dma_async_issue_pending(mcspi_dma->dma_rx);
 412        omap2_mcspi_set_dma_req(spi, 1, 1);
 413
 414        wait_for_completion(&mcspi_dma->dma_rx_completion);
 415        dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
 416                         DMA_FROM_DEVICE);
 417        omap2_mcspi_set_enable(spi, 0);
 418
 419        elements = element_count - 1;
 420
 421        if (l & OMAP2_MCSPI_CHCONF_TURBO) {
 422                elements--;
 423
 424                if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 425                                   & OMAP2_MCSPI_CHSTAT_RXS)) {
 426                        u32 w;
 427
 428                        w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 429                        if (word_len <= 8)
 430                                ((u8 *)xfer->rx_buf)[elements++] = w;
 431                        else if (word_len <= 16)
 432                                ((u16 *)xfer->rx_buf)[elements++] = w;
 433                        else /* word_len <= 32 */
 434                                ((u32 *)xfer->rx_buf)[elements++] = w;
 435                } else {
 436                        dev_err(&spi->dev, "DMA RX penultimate word empty");
 437                        count -= (word_len <= 8)  ? 2 :
 438                                (word_len <= 16) ? 4 :
 439                                /* word_len <= 32 */ 8;
 440                        omap2_mcspi_set_enable(spi, 1);
 441                        return count;
 442                }
 443        }
 444        if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 445                                & OMAP2_MCSPI_CHSTAT_RXS)) {
 446                u32 w;
 447
 448                w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 449                if (word_len <= 8)
 450                        ((u8 *)xfer->rx_buf)[elements] = w;
 451                else if (word_len <= 16)
 452                        ((u16 *)xfer->rx_buf)[elements] = w;
 453                else /* word_len <= 32 */
 454                        ((u32 *)xfer->rx_buf)[elements] = w;
 455        } else {
 456                dev_err(&spi->dev, "DMA RX last word empty");
 457                count -= (word_len <= 8)  ? 1 :
 458                         (word_len <= 16) ? 2 :
 459                       /* word_len <= 32 */ 4;
 460        }
 461        omap2_mcspi_set_enable(spi, 1);
 462        return count;
 463}
 464
 465static unsigned
 466omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 467{
 468        struct omap2_mcspi      *mcspi;
 469        struct omap2_mcspi_cs   *cs = spi->controller_state;
 470        struct omap2_mcspi_dma  *mcspi_dma;
 471        unsigned int            count;
 472        u32                     l;
 473        u8                      *rx;
 474        const u8                *tx;
 475        struct dma_slave_config cfg;
 476        enum dma_slave_buswidth width;
 477        unsigned es;
 478        void __iomem            *chstat_reg;
 479
 480        mcspi = spi_master_get_devdata(spi->master);
 481        mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 482        l = mcspi_cached_chconf0(spi);
 483
 484
 485        if (cs->word_len <= 8) {
 486                width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 487                es = 1;
 488        } else if (cs->word_len <= 16) {
 489                width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 490                es = 2;
 491        } else {
 492                width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 493                es = 4;
 494        }
 495
 496        memset(&cfg, 0, sizeof(cfg));
 497        cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
 498        cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
 499        cfg.src_addr_width = width;
 500        cfg.dst_addr_width = width;
 501        cfg.src_maxburst = 1;
 502        cfg.dst_maxburst = 1;
 503
 504        rx = xfer->rx_buf;
 505        tx = xfer->tx_buf;
 506
 507        count = xfer->len;
 508
 509        if (tx != NULL)
 510                omap2_mcspi_tx_dma(spi, xfer, cfg);
 511
 512        if (rx != NULL)
 513                count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
 514
 515        if (tx != NULL) {
 516                chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
 517                wait_for_completion(&mcspi_dma->dma_tx_completion);
 518                dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
 519                                 DMA_TO_DEVICE);
 520
 521                /* for TX_ONLY mode, be sure all words have shifted out */
 522                if (rx == NULL) {
 523                        if (mcspi_wait_for_reg_bit(chstat_reg,
 524                                                OMAP2_MCSPI_CHSTAT_TXS) < 0)
 525                                dev_err(&spi->dev, "TXS timed out\n");
 526                        else if (mcspi_wait_for_reg_bit(chstat_reg,
 527                                                OMAP2_MCSPI_CHSTAT_EOT) < 0)
 528                                dev_err(&spi->dev, "EOT timed out\n");
 529                }
 530        }
 531        return count;
 532}
 533
 534static unsigned
 535omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 536{
 537        struct omap2_mcspi      *mcspi;
 538        struct omap2_mcspi_cs   *cs = spi->controller_state;
 539        unsigned int            count, c;
 540        u32                     l;
 541        void __iomem            *base = cs->base;
 542        void __iomem            *tx_reg;
 543        void __iomem            *rx_reg;
 544        void __iomem            *chstat_reg;
 545        int                     word_len;
 546
 547        mcspi = spi_master_get_devdata(spi->master);
 548        count = xfer->len;
 549        c = count;
 550        word_len = cs->word_len;
 551
 552        l = mcspi_cached_chconf0(spi);
 553
 554        /* We store the pre-calculated register addresses on stack to speed
 555         * up the transfer loop. */
 556        tx_reg          = base + OMAP2_MCSPI_TX0;
 557        rx_reg          = base + OMAP2_MCSPI_RX0;
 558        chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
 559
 560        if (c < (word_len>>3))
 561                return 0;
 562
 563        if (word_len <= 8) {
 564                u8              *rx;
 565                const u8        *tx;
 566
 567                rx = xfer->rx_buf;
 568                tx = xfer->tx_buf;
 569
 570                do {
 571                        c -= 1;
 572                        if (tx != NULL) {
 573                                if (mcspi_wait_for_reg_bit(chstat_reg,
 574                                                OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 575                                        dev_err(&spi->dev, "TXS timed out\n");
 576                                        goto out;
 577                                }
 578                                dev_vdbg(&spi->dev, "write-%d %02x\n",
 579                                                word_len, *tx);
 580                                __raw_writel(*tx++, tx_reg);
 581                        }
 582                        if (rx != NULL) {
 583                                if (mcspi_wait_for_reg_bit(chstat_reg,
 584                                                OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 585                                        dev_err(&spi->dev, "RXS timed out\n");
 586                                        goto out;
 587                                }
 588
 589                                if (c == 1 && tx == NULL &&
 590                                    (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 591                                        omap2_mcspi_set_enable(spi, 0);
 592                                        *rx++ = __raw_readl(rx_reg);
 593                                        dev_vdbg(&spi->dev, "read-%d %02x\n",
 594                                                    word_len, *(rx - 1));
 595                                        if (mcspi_wait_for_reg_bit(chstat_reg,
 596                                                OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 597                                                dev_err(&spi->dev,
 598                                                        "RXS timed out\n");
 599                                                goto out;
 600                                        }
 601                                        c = 0;
 602                                } else if (c == 0 && tx == NULL) {
 603                                        omap2_mcspi_set_enable(spi, 0);
 604                                }
 605
 606                                *rx++ = __raw_readl(rx_reg);
 607                                dev_vdbg(&spi->dev, "read-%d %02x\n",
 608                                                word_len, *(rx - 1));
 609                        }
 610                } while (c);
 611        } else if (word_len <= 16) {
 612                u16             *rx;
 613                const u16       *tx;
 614
 615                rx = xfer->rx_buf;
 616                tx = xfer->tx_buf;
 617                do {
 618                        c -= 2;
 619                        if (tx != NULL) {
 620                                if (mcspi_wait_for_reg_bit(chstat_reg,
 621                                                OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 622                                        dev_err(&spi->dev, "TXS timed out\n");
 623                                        goto out;
 624                                }
 625                                dev_vdbg(&spi->dev, "write-%d %04x\n",
 626                                                word_len, *tx);
 627                                __raw_writel(*tx++, tx_reg);
 628                        }
 629                        if (rx != NULL) {
 630                                if (mcspi_wait_for_reg_bit(chstat_reg,
 631                                                OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 632                                        dev_err(&spi->dev, "RXS timed out\n");
 633                                        goto out;
 634                                }
 635
 636                                if (c == 2 && tx == NULL &&
 637                                    (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 638                                        omap2_mcspi_set_enable(spi, 0);
 639                                        *rx++ = __raw_readl(rx_reg);
 640                                        dev_vdbg(&spi->dev, "read-%d %04x\n",
 641                                                    word_len, *(rx - 1));
 642                                        if (mcspi_wait_for_reg_bit(chstat_reg,
 643                                                OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 644                                                dev_err(&spi->dev,
 645                                                        "RXS timed out\n");
 646                                                goto out;
 647                                        }
 648                                        c = 0;
 649                                } else if (c == 0 && tx == NULL) {
 650                                        omap2_mcspi_set_enable(spi, 0);
 651                                }
 652
 653                                *rx++ = __raw_readl(rx_reg);
 654                                dev_vdbg(&spi->dev, "read-%d %04x\n",
 655                                                word_len, *(rx - 1));
 656                        }
 657                } while (c >= 2);
 658        } else if (word_len <= 32) {
 659                u32             *rx;
 660                const u32       *tx;
 661
 662                rx = xfer->rx_buf;
 663                tx = xfer->tx_buf;
 664                do {
 665                        c -= 4;
 666                        if (tx != NULL) {
 667                                if (mcspi_wait_for_reg_bit(chstat_reg,
 668                                                OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 669                                        dev_err(&spi->dev, "TXS timed out\n");
 670                                        goto out;
 671                                }
 672                                dev_vdbg(&spi->dev, "write-%d %08x\n",
 673                                                word_len, *tx);
 674                                __raw_writel(*tx++, tx_reg);
 675                        }
 676                        if (rx != NULL) {
 677                                if (mcspi_wait_for_reg_bit(chstat_reg,
 678                                                OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 679                                        dev_err(&spi->dev, "RXS timed out\n");
 680                                        goto out;
 681                                }
 682
 683                                if (c == 4 && tx == NULL &&
 684                                    (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 685                                        omap2_mcspi_set_enable(spi, 0);
 686                                        *rx++ = __raw_readl(rx_reg);
 687                                        dev_vdbg(&spi->dev, "read-%d %08x\n",
 688                                                    word_len, *(rx - 1));
 689                                        if (mcspi_wait_for_reg_bit(chstat_reg,
 690                                                OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 691                                                dev_err(&spi->dev,
 692                                                        "RXS timed out\n");
 693                                                goto out;
 694                                        }
 695                                        c = 0;
 696                                } else if (c == 0 && tx == NULL) {
 697                                        omap2_mcspi_set_enable(spi, 0);
 698                                }
 699
 700                                *rx++ = __raw_readl(rx_reg);
 701                                dev_vdbg(&spi->dev, "read-%d %08x\n",
 702                                                word_len, *(rx - 1));
 703                        }
 704                } while (c >= 4);
 705        }
 706
 707        /* for TX_ONLY mode, be sure all words have shifted out */
 708        if (xfer->rx_buf == NULL) {
 709                if (mcspi_wait_for_reg_bit(chstat_reg,
 710                                OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 711                        dev_err(&spi->dev, "TXS timed out\n");
 712                } else if (mcspi_wait_for_reg_bit(chstat_reg,
 713                                OMAP2_MCSPI_CHSTAT_EOT) < 0)
 714                        dev_err(&spi->dev, "EOT timed out\n");
 715
 716                /* disable chan to purge rx datas received in TX_ONLY transfer,
 717                 * otherwise these rx datas will affect the direct following
 718                 * RX_ONLY transfer.
 719                 */
 720                omap2_mcspi_set_enable(spi, 0);
 721        }
 722out:
 723        omap2_mcspi_set_enable(spi, 1);
 724        return count - c;
 725}
 726
 727static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
 728{
 729        u32 div;
 730
 731        for (div = 0; div < 15; div++)
 732                if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
 733                        return div;
 734
 735        return 15;
 736}
 737
 738/* called only when no transfer is active to this device */
 739static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 740                struct spi_transfer *t)
 741{
 742        struct omap2_mcspi_cs *cs = spi->controller_state;
 743        struct omap2_mcspi *mcspi;
 744        struct spi_master *spi_cntrl;
 745        u32 l = 0, div = 0;
 746        u8 word_len = spi->bits_per_word;
 747        u32 speed_hz = spi->max_speed_hz;
 748
 749        mcspi = spi_master_get_devdata(spi->master);
 750        spi_cntrl = mcspi->master;
 751
 752        if (t != NULL && t->bits_per_word)
 753                word_len = t->bits_per_word;
 754
 755        cs->word_len = word_len;
 756
 757        if (t && t->speed_hz)
 758                speed_hz = t->speed_hz;
 759
 760        speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
 761        div = omap2_mcspi_calc_divisor(speed_hz);
 762
 763        l = mcspi_cached_chconf0(spi);
 764
 765        /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
 766         * REVISIT: this controller could support SPI_3WIRE mode.
 767         */
 768        if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
 769                l &= ~OMAP2_MCSPI_CHCONF_IS;
 770                l &= ~OMAP2_MCSPI_CHCONF_DPE1;
 771                l |= OMAP2_MCSPI_CHCONF_DPE0;
 772        } else {
 773                l |= OMAP2_MCSPI_CHCONF_IS;
 774                l |= OMAP2_MCSPI_CHCONF_DPE1;
 775                l &= ~OMAP2_MCSPI_CHCONF_DPE0;
 776        }
 777
 778        /* wordlength */
 779        l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
 780        l |= (word_len - 1) << 7;
 781
 782        /* set chipselect polarity; manage with FORCE */
 783        if (!(spi->mode & SPI_CS_HIGH))
 784                l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
 785        else
 786                l &= ~OMAP2_MCSPI_CHCONF_EPOL;
 787
 788        /* set clock divisor */
 789        l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
 790        l |= div << 2;
 791
 792        /* set SPI mode 0..3 */
 793        if (spi->mode & SPI_CPOL)
 794                l |= OMAP2_MCSPI_CHCONF_POL;
 795        else
 796                l &= ~OMAP2_MCSPI_CHCONF_POL;
 797        if (spi->mode & SPI_CPHA)
 798                l |= OMAP2_MCSPI_CHCONF_PHA;
 799        else
 800                l &= ~OMAP2_MCSPI_CHCONF_PHA;
 801
 802        mcspi_write_chconf0(spi, l);
 803
 804        dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
 805                        OMAP2_MCSPI_MAX_FREQ >> div,
 806                        (spi->mode & SPI_CPHA) ? "trailing" : "leading",
 807                        (spi->mode & SPI_CPOL) ? "inverted" : "normal");
 808
 809        return 0;
 810}
 811
 812/*
 813 * Note that we currently allow DMA only if we get a channel
 814 * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
 815 */
 816static int omap2_mcspi_request_dma(struct spi_device *spi)
 817{
 818        struct spi_master       *master = spi->master;
 819        struct omap2_mcspi      *mcspi;
 820        struct omap2_mcspi_dma  *mcspi_dma;
 821        dma_cap_mask_t mask;
 822        unsigned sig;
 823
 824        mcspi = spi_master_get_devdata(master);
 825        mcspi_dma = mcspi->dma_channels + spi->chip_select;
 826
 827        init_completion(&mcspi_dma->dma_rx_completion);
 828        init_completion(&mcspi_dma->dma_tx_completion);
 829
 830        dma_cap_zero(mask);
 831        dma_cap_set(DMA_SLAVE, mask);
 832        sig = mcspi_dma->dma_rx_sync_dev;
 833        mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
 834        if (!mcspi_dma->dma_rx)
 835                goto no_dma;
 836
 837        sig = mcspi_dma->dma_tx_sync_dev;
 838        mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
 839        if (!mcspi_dma->dma_tx) {
 840                dma_release_channel(mcspi_dma->dma_rx);
 841                mcspi_dma->dma_rx = NULL;
 842                goto no_dma;
 843        }
 844
 845        return 0;
 846
 847no_dma:
 848        dev_warn(&spi->dev, "not using DMA for McSPI\n");
 849        return -EAGAIN;
 850}
 851
 852static int omap2_mcspi_setup(struct spi_device *spi)
 853{
 854        int                     ret;
 855        struct omap2_mcspi      *mcspi = spi_master_get_devdata(spi->master);
 856        struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 857        struct omap2_mcspi_dma  *mcspi_dma;
 858        struct omap2_mcspi_cs   *cs = spi->controller_state;
 859
 860        if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
 861                dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
 862                        spi->bits_per_word);
 863                return -EINVAL;
 864        }
 865
 866        mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 867
 868        if (!cs) {
 869                cs = kzalloc(sizeof *cs, GFP_KERNEL);
 870                if (!cs)
 871                        return -ENOMEM;
 872                cs->base = mcspi->base + spi->chip_select * 0x14;
 873                cs->phys = mcspi->phys + spi->chip_select * 0x14;
 874                cs->chconf0 = 0;
 875                spi->controller_state = cs;
 876                /* Link this to context save list */
 877                list_add_tail(&cs->node, &ctx->cs);
 878        }
 879
 880        if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
 881                ret = omap2_mcspi_request_dma(spi);
 882                if (ret < 0 && ret != -EAGAIN)
 883                        return ret;
 884        }
 885
 886        ret = pm_runtime_get_sync(mcspi->dev);
 887        if (ret < 0)
 888                return ret;
 889
 890        ret = omap2_mcspi_setup_transfer(spi, NULL);
 891        pm_runtime_mark_last_busy(mcspi->dev);
 892        pm_runtime_put_autosuspend(mcspi->dev);
 893
 894        return ret;
 895}
 896
 897static void omap2_mcspi_cleanup(struct spi_device *spi)
 898{
 899        struct omap2_mcspi      *mcspi;
 900        struct omap2_mcspi_dma  *mcspi_dma;
 901        struct omap2_mcspi_cs   *cs;
 902
 903        mcspi = spi_master_get_devdata(spi->master);
 904
 905        if (spi->controller_state) {
 906                /* Unlink controller state from context save list */
 907                cs = spi->controller_state;
 908                list_del(&cs->node);
 909
 910                kfree(cs);
 911        }
 912
 913        if (spi->chip_select < spi->master->num_chipselect) {
 914                mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 915
 916                if (mcspi_dma->dma_rx) {
 917                        dma_release_channel(mcspi_dma->dma_rx);
 918                        mcspi_dma->dma_rx = NULL;
 919                }
 920                if (mcspi_dma->dma_tx) {
 921                        dma_release_channel(mcspi_dma->dma_tx);
 922                        mcspi_dma->dma_tx = NULL;
 923                }
 924        }
 925}
 926
 927static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
 928{
 929
 930        /* We only enable one channel at a time -- the one whose message is
 931         * -- although this controller would gladly
 932         * arbitrate among multiple channels.  This corresponds to "single
 933         * channel" master mode.  As a side effect, we need to manage the
 934         * chipselect with the FORCE bit ... CS != channel enable.
 935         */
 936
 937        struct spi_device               *spi;
 938        struct spi_transfer             *t = NULL;
 939        struct spi_master               *master;
 940        struct omap2_mcspi_dma          *mcspi_dma;
 941        int                             cs_active = 0;
 942        struct omap2_mcspi_cs           *cs;
 943        struct omap2_mcspi_device_config *cd;
 944        int                             par_override = 0;
 945        int                             status = 0;
 946        u32                             chconf;
 947
 948        spi = m->spi;
 949        master = spi->master;
 950        mcspi_dma = mcspi->dma_channels + spi->chip_select;
 951        cs = spi->controller_state;
 952        cd = spi->controller_data;
 953
 954        omap2_mcspi_set_enable(spi, 1);
 955        list_for_each_entry(t, &m->transfers, transfer_list) {
 956                if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 957                        status = -EINVAL;
 958                        break;
 959                }
 960                if (par_override || t->speed_hz || t->bits_per_word) {
 961                        par_override = 1;
 962                        status = omap2_mcspi_setup_transfer(spi, t);
 963                        if (status < 0)
 964                                break;
 965                        if (!t->speed_hz && !t->bits_per_word)
 966                                par_override = 0;
 967                }
 968                if (cd && cd->cs_per_word) {
 969                        chconf = mcspi->ctx.modulctrl;
 970                        chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
 971                        mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
 972                        mcspi->ctx.modulctrl =
 973                                mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
 974                }
 975
 976
 977                if (!cs_active) {
 978                        omap2_mcspi_force_cs(spi, 1);
 979                        cs_active = 1;
 980                }
 981
 982                chconf = mcspi_cached_chconf0(spi);
 983                chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
 984                chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
 985
 986                if (t->tx_buf == NULL)
 987                        chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
 988                else if (t->rx_buf == NULL)
 989                        chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
 990
 991                if (cd && cd->turbo_mode && t->tx_buf == NULL) {
 992                        /* Turbo mode is for more than one word */
 993                        if (t->len > ((cs->word_len + 7) >> 3))
 994                                chconf |= OMAP2_MCSPI_CHCONF_TURBO;
 995                }
 996
 997                mcspi_write_chconf0(spi, chconf);
 998
 999                if (t->len) {
1000                        unsigned        count;
1001
1002                        /* RX_ONLY mode needs dummy data in TX reg */
1003                        if (t->tx_buf == NULL)
1004                                __raw_writel(0, cs->base
1005                                                + OMAP2_MCSPI_TX0);
1006
1007                        if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1008                            (m->is_dma_mapped || t->len >= DMA_MIN_BYTES))
1009                                count = omap2_mcspi_txrx_dma(spi, t);
1010                        else
1011                                count = omap2_mcspi_txrx_pio(spi, t);
1012                        m->actual_length += count;
1013
1014                        if (count != t->len) {
1015                                status = -EIO;
1016                                break;
1017                        }
1018                }
1019
1020                if (t->delay_usecs)
1021                        udelay(t->delay_usecs);
1022
1023                /* ignore the "leave it on after last xfer" hint */
1024                if (t->cs_change) {
1025                        omap2_mcspi_force_cs(spi, 0);
1026                        cs_active = 0;
1027                }
1028        }
1029        /* Restore defaults if they were overriden */
1030        if (par_override) {
1031                par_override = 0;
1032                status = omap2_mcspi_setup_transfer(spi, NULL);
1033        }
1034
1035        if (cs_active)
1036                omap2_mcspi_force_cs(spi, 0);
1037
1038        if (cd && cd->cs_per_word) {
1039                chconf = mcspi->ctx.modulctrl;
1040                chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1041                mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1042                mcspi->ctx.modulctrl =
1043                        mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1044        }
1045
1046        omap2_mcspi_set_enable(spi, 0);
1047
1048        m->status = status;
1049
1050}
1051
1052static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1053                struct spi_message *m)
1054{
1055        struct spi_device       *spi;
1056        struct omap2_mcspi      *mcspi;
1057        struct omap2_mcspi_dma  *mcspi_dma;
1058        struct spi_transfer     *t;
1059
1060        spi = m->spi;
1061        mcspi = spi_master_get_devdata(master);
1062        mcspi_dma = mcspi->dma_channels + spi->chip_select;
1063        m->actual_length = 0;
1064        m->status = 0;
1065
1066        /* reject invalid messages and transfers */
1067        if (list_empty(&m->transfers))
1068                return -EINVAL;
1069        list_for_each_entry(t, &m->transfers, transfer_list) {
1070                const void      *tx_buf = t->tx_buf;
1071                void            *rx_buf = t->rx_buf;
1072                unsigned        len = t->len;
1073
1074                if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
1075                                || (len && !(rx_buf || tx_buf))
1076                                || (t->bits_per_word &&
1077                                        (  t->bits_per_word < 4
1078                                           || t->bits_per_word > 32))) {
1079                        dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1080                                        t->speed_hz,
1081                                        len,
1082                                        tx_buf ? "tx" : "",
1083                                        rx_buf ? "rx" : "",
1084                                        t->bits_per_word);
1085                        return -EINVAL;
1086                }
1087                if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
1088                        dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
1089                                        t->speed_hz,
1090                                        OMAP2_MCSPI_MAX_FREQ >> 15);
1091                        return -EINVAL;
1092                }
1093
1094                if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1095                        continue;
1096
1097                if (mcspi_dma->dma_tx && tx_buf != NULL) {
1098                        t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
1099                                        len, DMA_TO_DEVICE);
1100                        if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1101                                dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1102                                                'T', len);
1103                                return -EINVAL;
1104                        }
1105                }
1106                if (mcspi_dma->dma_rx && rx_buf != NULL) {
1107                        t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
1108                                        DMA_FROM_DEVICE);
1109                        if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1110                                dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1111                                                'R', len);
1112                                if (tx_buf != NULL)
1113                                        dma_unmap_single(mcspi->dev, t->tx_dma,
1114                                                        len, DMA_TO_DEVICE);
1115                                return -EINVAL;
1116                        }
1117                }
1118        }
1119
1120        omap2_mcspi_work(mcspi, m);
1121        spi_finalize_current_message(master);
1122        return 0;
1123}
1124
1125static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1126{
1127        struct spi_master       *master = mcspi->master;
1128        struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1129        int                     ret = 0;
1130
1131        ret = pm_runtime_get_sync(mcspi->dev);
1132        if (ret < 0)
1133                return ret;
1134
1135        mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1136                        OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1137        ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1138
1139        omap2_mcspi_set_master_mode(master);
1140        pm_runtime_mark_last_busy(mcspi->dev);
1141        pm_runtime_put_autosuspend(mcspi->dev);
1142        return 0;
1143}
1144
1145static int omap_mcspi_runtime_resume(struct device *dev)
1146{
1147        struct omap2_mcspi      *mcspi;
1148        struct spi_master       *master;
1149
1150        master = dev_get_drvdata(dev);
1151        mcspi = spi_master_get_devdata(master);
1152        omap2_mcspi_restore_ctx(mcspi);
1153
1154        return 0;
1155}
1156
1157static struct omap2_mcspi_platform_config omap2_pdata = {
1158        .regs_offset = 0,
1159};
1160
1161static struct omap2_mcspi_platform_config omap4_pdata = {
1162        .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1163};
1164
1165static const struct of_device_id omap_mcspi_of_match[] = {
1166        {
1167                .compatible = "ti,omap2-mcspi",
1168                .data = &omap2_pdata,
1169        },
1170        {
1171                .compatible = "ti,omap4-mcspi",
1172                .data = &omap4_pdata,
1173        },
1174        { },
1175};
1176MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1177
1178static int omap2_mcspi_probe(struct platform_device *pdev)
1179{
1180        struct spi_master       *master;
1181        const struct omap2_mcspi_platform_config *pdata;
1182        struct omap2_mcspi      *mcspi;
1183        struct resource         *r;
1184        int                     status = 0, i;
1185        u32                     regs_offset = 0;
1186        static int              bus_num = 1;
1187        struct device_node      *node = pdev->dev.of_node;
1188        const struct of_device_id *match;
1189        struct pinctrl *pinctrl;
1190
1191        master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1192        if (master == NULL) {
1193                dev_dbg(&pdev->dev, "master allocation failed\n");
1194                return -ENOMEM;
1195        }
1196
1197        /* the spi->mode bits understood by this driver: */
1198        master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1199
1200        master->setup = omap2_mcspi_setup;
1201        master->prepare_transfer_hardware = omap2_prepare_transfer;
1202        master->unprepare_transfer_hardware = omap2_unprepare_transfer;
1203        master->transfer_one_message = omap2_mcspi_transfer_one_message;
1204        master->cleanup = omap2_mcspi_cleanup;
1205        master->dev.of_node = node;
1206
1207        dev_set_drvdata(&pdev->dev, master);
1208
1209        mcspi = spi_master_get_devdata(master);
1210        mcspi->master = master;
1211
1212        match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1213        if (match) {
1214                u32 num_cs = 1; /* default number of chipselect */
1215                pdata = match->data;
1216
1217                of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1218                master->num_chipselect = num_cs;
1219                master->bus_num = bus_num++;
1220                if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1221                        mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1222        } else {
1223                pdata = pdev->dev.platform_data;
1224                master->num_chipselect = pdata->num_cs;
1225                if (pdev->id != -1)
1226                        master->bus_num = pdev->id;
1227                mcspi->pin_dir = pdata->pin_dir;
1228        }
1229        regs_offset = pdata->regs_offset;
1230
1231        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1232        if (r == NULL) {
1233                status = -ENODEV;
1234                goto free_master;
1235        }
1236
1237        r->start += regs_offset;
1238        r->end += regs_offset;
1239        mcspi->phys = r->start;
1240
1241        mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1242        if (IS_ERR(mcspi->base)) {
1243                status = PTR_ERR(mcspi->base);
1244                goto free_master;
1245        }
1246
1247        mcspi->dev = &pdev->dev;
1248
1249        INIT_LIST_HEAD(&mcspi->ctx.cs);
1250
1251        mcspi->dma_channels = kcalloc(master->num_chipselect,
1252                        sizeof(struct omap2_mcspi_dma),
1253                        GFP_KERNEL);
1254
1255        if (mcspi->dma_channels == NULL)
1256                goto free_master;
1257
1258        for (i = 0; i < master->num_chipselect; i++) {
1259                char dma_ch_name[14];
1260                struct resource *dma_res;
1261
1262                sprintf(dma_ch_name, "rx%d", i);
1263                dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1264                                dma_ch_name);
1265                if (!dma_res) {
1266                        dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1267                        status = -ENODEV;
1268                        break;
1269                }
1270
1271                mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1272                sprintf(dma_ch_name, "tx%d", i);
1273                dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1274                                dma_ch_name);
1275                if (!dma_res) {
1276                        dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1277                        status = -ENODEV;
1278                        break;
1279                }
1280
1281                mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
1282        }
1283
1284        if (status < 0)
1285                goto dma_chnl_free;
1286
1287        pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1288        if (IS_ERR(pinctrl))
1289                dev_warn(&pdev->dev,
1290                                "pins are not configured from the driver\n");
1291
1292        pm_runtime_use_autosuspend(&pdev->dev);
1293        pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1294        pm_runtime_enable(&pdev->dev);
1295
1296        status = omap2_mcspi_master_setup(mcspi);
1297        if (status < 0)
1298                goto disable_pm;
1299
1300        status = spi_register_master(master);
1301        if (status < 0)
1302                goto disable_pm;
1303
1304        return status;
1305
1306disable_pm:
1307        pm_runtime_disable(&pdev->dev);
1308dma_chnl_free:
1309        kfree(mcspi->dma_channels);
1310free_master:
1311        spi_master_put(master);
1312        return status;
1313}
1314
1315static int omap2_mcspi_remove(struct platform_device *pdev)
1316{
1317        struct spi_master       *master;
1318        struct omap2_mcspi      *mcspi;
1319        struct omap2_mcspi_dma  *dma_channels;
1320
1321        master = dev_get_drvdata(&pdev->dev);
1322        mcspi = spi_master_get_devdata(master);
1323        dma_channels = mcspi->dma_channels;
1324
1325        pm_runtime_put_sync(mcspi->dev);
1326        pm_runtime_disable(&pdev->dev);
1327
1328        spi_unregister_master(master);
1329        kfree(dma_channels);
1330
1331        return 0;
1332}
1333
1334/* work with hotplug and coldplug */
1335MODULE_ALIAS("platform:omap2_mcspi");
1336
1337#ifdef  CONFIG_SUSPEND
1338/*
1339 * When SPI wake up from off-mode, CS is in activate state. If it was in
1340 * unactive state when driver was suspend, then force it to unactive state at
1341 * wake up.
1342 */
1343static int omap2_mcspi_resume(struct device *dev)
1344{
1345        struct spi_master       *master = dev_get_drvdata(dev);
1346        struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1347        struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1348        struct omap2_mcspi_cs   *cs;
1349
1350        pm_runtime_get_sync(mcspi->dev);
1351        list_for_each_entry(cs, &ctx->cs, node) {
1352                if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1353                        /*
1354                         * We need to toggle CS state for OMAP take this
1355                         * change in account.
1356                         */
1357                        cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1358                        __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1359                        cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1360                        __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1361                }
1362        }
1363        pm_runtime_mark_last_busy(mcspi->dev);
1364        pm_runtime_put_autosuspend(mcspi->dev);
1365        return 0;
1366}
1367#else
1368#define omap2_mcspi_resume      NULL
1369#endif
1370
1371static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1372        .resume = omap2_mcspi_resume,
1373        .runtime_resume = omap_mcspi_runtime_resume,
1374};
1375
1376static struct platform_driver omap2_mcspi_driver = {
1377        .driver = {
1378                .name =         "omap2_mcspi",
1379                .owner =        THIS_MODULE,
1380                .pm =           &omap2_mcspi_pm_ops,
1381                .of_match_table = omap_mcspi_of_match,
1382        },
1383        .probe =        omap2_mcspi_probe,
1384        .remove =       omap2_mcspi_remove,
1385};
1386
1387module_platform_driver(omap2_mcspi_driver);
1388MODULE_LICENSE("GPL");
1389
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