linux/drivers/spi/spi-bcm63xx.c
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   1/*
   2 * Broadcom BCM63xx SPI controller support
   3 *
   4 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
   5 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License
   9 * as published by the Free Software Foundation; either version 2
  10 * of the License, or (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the
  19 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  20 */
  21
  22#include <linux/kernel.h>
  23#include <linux/init.h>
  24#include <linux/clk.h>
  25#include <linux/io.h>
  26#include <linux/module.h>
  27#include <linux/platform_device.h>
  28#include <linux/delay.h>
  29#include <linux/interrupt.h>
  30#include <linux/spi/spi.h>
  31#include <linux/completion.h>
  32#include <linux/err.h>
  33#include <linux/workqueue.h>
  34#include <linux/pm_runtime.h>
  35
  36#include <bcm63xx_dev_spi.h>
  37
  38#define PFX             KBUILD_MODNAME
  39
  40#define BCM63XX_SPI_MAX_PREPEND         15
  41
  42struct bcm63xx_spi {
  43        struct completion       done;
  44
  45        void __iomem            *regs;
  46        int                     irq;
  47
  48        /* Platform data */
  49        unsigned                fifo_size;
  50        unsigned int            msg_type_shift;
  51        unsigned int            msg_ctl_width;
  52
  53        /* data iomem */
  54        u8 __iomem              *tx_io;
  55        const u8 __iomem        *rx_io;
  56
  57        struct clk              *clk;
  58        struct platform_device  *pdev;
  59};
  60
  61static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
  62                                unsigned int offset)
  63{
  64        return bcm_readb(bs->regs + bcm63xx_spireg(offset));
  65}
  66
  67static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
  68                                unsigned int offset)
  69{
  70        return bcm_readw(bs->regs + bcm63xx_spireg(offset));
  71}
  72
  73static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
  74                                  u8 value, unsigned int offset)
  75{
  76        bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
  77}
  78
  79static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
  80                                  u16 value, unsigned int offset)
  81{
  82        bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
  83}
  84
  85static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
  86        { 20000000, SPI_CLK_20MHZ },
  87        { 12500000, SPI_CLK_12_50MHZ },
  88        {  6250000, SPI_CLK_6_250MHZ },
  89        {  3125000, SPI_CLK_3_125MHZ },
  90        {  1563000, SPI_CLK_1_563MHZ },
  91        {   781000, SPI_CLK_0_781MHZ },
  92        {   391000, SPI_CLK_0_391MHZ }
  93};
  94
  95static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
  96                                      struct spi_transfer *t)
  97{
  98        struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
  99        u8 clk_cfg, reg;
 100        int i;
 101
 102        /* Find the closest clock configuration */
 103        for (i = 0; i < SPI_CLK_MASK; i++) {
 104                if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
 105                        clk_cfg = bcm63xx_spi_freq_table[i][1];
 106                        break;
 107                }
 108        }
 109
 110        /* No matching configuration found, default to lowest */
 111        if (i == SPI_CLK_MASK)
 112                clk_cfg = SPI_CLK_0_391MHZ;
 113
 114        /* clear existing clock configuration bits of the register */
 115        reg = bcm_spi_readb(bs, SPI_CLK_CFG);
 116        reg &= ~SPI_CLK_MASK;
 117        reg |= clk_cfg;
 118
 119        bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
 120        dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
 121                clk_cfg, t->speed_hz);
 122}
 123
 124/* the spi->mode bits understood by this driver: */
 125#define MODEBITS (SPI_CPOL | SPI_CPHA)
 126
 127static int bcm63xx_spi_setup(struct spi_device *spi)
 128{
 129        if (spi->bits_per_word != 8) {
 130                dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
 131                        __func__, spi->bits_per_word);
 132                return -EINVAL;
 133        }
 134
 135        return 0;
 136}
 137
 138static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
 139                                unsigned int num_transfers)
 140{
 141        struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 142        u16 msg_ctl;
 143        u16 cmd;
 144        u8 rx_tail;
 145        unsigned int i, timeout = 0, prepend_len = 0, len = 0;
 146        struct spi_transfer *t = first;
 147        bool do_rx = false;
 148        bool do_tx = false;
 149
 150        /* Disable the CMD_DONE interrupt */
 151        bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 152
 153        dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
 154                t->tx_buf, t->rx_buf, t->len);
 155
 156        if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
 157                prepend_len = t->len;
 158
 159        /* prepare the buffer */
 160        for (i = 0; i < num_transfers; i++) {
 161                if (t->tx_buf) {
 162                        do_tx = true;
 163                        memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
 164
 165                        /* don't prepend more than one tx */
 166                        if (t != first)
 167                                prepend_len = 0;
 168                }
 169
 170                if (t->rx_buf) {
 171                        do_rx = true;
 172                        /* prepend is half-duplex write only */
 173                        if (t == first)
 174                                prepend_len = 0;
 175                }
 176
 177                len += t->len;
 178
 179                t = list_entry(t->transfer_list.next, struct spi_transfer,
 180                               transfer_list);
 181        }
 182
 183        len -= prepend_len;
 184
 185        init_completion(&bs->done);
 186
 187        /* Fill in the Message control register */
 188        msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
 189
 190        if (do_rx && do_tx && prepend_len == 0)
 191                msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
 192        else if (do_rx)
 193                msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
 194        else if (do_tx)
 195                msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
 196
 197        switch (bs->msg_ctl_width) {
 198        case 8:
 199                bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
 200                break;
 201        case 16:
 202                bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
 203                break;
 204        }
 205
 206        /* Issue the transfer */
 207        cmd = SPI_CMD_START_IMMEDIATE;
 208        cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 209        cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
 210        bcm_spi_writew(bs, cmd, SPI_CMD);
 211
 212        /* Enable the CMD_DONE interrupt */
 213        bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
 214
 215        timeout = wait_for_completion_timeout(&bs->done, HZ);
 216        if (!timeout)
 217                return -ETIMEDOUT;
 218
 219        /* read out all data */
 220        rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
 221
 222        if (do_rx && rx_tail != len)
 223                return -EIO;
 224
 225        if (!rx_tail)
 226                return 0;
 227
 228        len = 0;
 229        t = first;
 230        /* Read out all the data */
 231        for (i = 0; i < num_transfers; i++) {
 232                if (t->rx_buf)
 233                        memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
 234
 235                if (t != first || prepend_len == 0)
 236                        len += t->len;
 237
 238                t = list_entry(t->transfer_list.next, struct spi_transfer,
 239                               transfer_list);
 240        }
 241
 242        return 0;
 243}
 244
 245static int bcm63xx_spi_prepare_transfer(struct spi_master *master)
 246{
 247        struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 248
 249        pm_runtime_get_sync(&bs->pdev->dev);
 250
 251        return 0;
 252}
 253
 254static int bcm63xx_spi_unprepare_transfer(struct spi_master *master)
 255{
 256        struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 257
 258        pm_runtime_put(&bs->pdev->dev);
 259
 260        return 0;
 261}
 262
 263static int bcm63xx_spi_transfer_one(struct spi_master *master,
 264                                        struct spi_message *m)
 265{
 266        struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 267        struct spi_transfer *t, *first = NULL;
 268        struct spi_device *spi = m->spi;
 269        int status = 0;
 270        unsigned int n_transfers = 0, total_len = 0;
 271        bool can_use_prepend = false;
 272
 273        /*
 274         * This SPI controller does not support keeping CS active after a
 275         * transfer.
 276         * Work around this by merging as many transfers we can into one big
 277         * full-duplex transfers.
 278         */
 279        list_for_each_entry(t, &m->transfers, transfer_list) {
 280                if (t->bits_per_word != 8) {
 281                        dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
 282                                __func__, t->bits_per_word);
 283                        status = -EINVAL;
 284                        goto exit;
 285                }
 286
 287                if (!first)
 288                        first = t;
 289
 290                n_transfers++;
 291                total_len += t->len;
 292
 293                if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
 294                    first->len <= BCM63XX_SPI_MAX_PREPEND)
 295                        can_use_prepend = true;
 296                else if (can_use_prepend && t->tx_buf)
 297                        can_use_prepend = false;
 298
 299                /* we can only transfer one fifo worth of data */
 300                if ((can_use_prepend &&
 301                     total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
 302                    (!can_use_prepend && total_len > bs->fifo_size)) {
 303                        dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
 304                                total_len, bs->fifo_size);
 305                        status = -EINVAL;
 306                        goto exit;
 307                }
 308
 309                /* all combined transfers have to have the same speed */
 310                if (t->speed_hz != first->speed_hz) {
 311                        dev_err(&spi->dev, "unable to change speed between transfers\n");
 312                        status = -EINVAL;
 313                        goto exit;
 314                }
 315
 316                /* CS will be deasserted directly after transfer */
 317                if (t->delay_usecs) {
 318                        dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
 319                        status = -EINVAL;
 320                        goto exit;
 321                }
 322
 323                if (t->cs_change ||
 324                    list_is_last(&t->transfer_list, &m->transfers)) {
 325                        /* configure adapter for a new transfer */
 326                        bcm63xx_spi_setup_transfer(spi, first);
 327
 328                        /* send the data */
 329                        status = bcm63xx_txrx_bufs(spi, first, n_transfers);
 330                        if (status)
 331                                goto exit;
 332
 333                        m->actual_length += total_len;
 334
 335                        first = NULL;
 336                        n_transfers = 0;
 337                        total_len = 0;
 338                        can_use_prepend = false;
 339                }
 340        }
 341exit:
 342        m->status = status;
 343        spi_finalize_current_message(master);
 344
 345        return 0;
 346}
 347
 348/* This driver supports single master mode only. Hence
 349 * CMD_DONE is the only interrupt we care about
 350 */
 351static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
 352{
 353        struct spi_master *master = (struct spi_master *)dev_id;
 354        struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 355        u8 intr;
 356
 357        /* Read interupts and clear them immediately */
 358        intr = bcm_spi_readb(bs, SPI_INT_STATUS);
 359        bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 360        bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 361
 362        /* A transfer completed */
 363        if (intr & SPI_INTR_CMD_DONE)
 364                complete(&bs->done);
 365
 366        return IRQ_HANDLED;
 367}
 368
 369
 370static int bcm63xx_spi_probe(struct platform_device *pdev)
 371{
 372        struct resource *r;
 373        struct device *dev = &pdev->dev;
 374        struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
 375        int irq;
 376        struct spi_master *master;
 377        struct clk *clk;
 378        struct bcm63xx_spi *bs;
 379        int ret;
 380
 381        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 382        if (!r) {
 383                dev_err(dev, "no iomem\n");
 384                ret = -ENXIO;
 385                goto out;
 386        }
 387
 388        irq = platform_get_irq(pdev, 0);
 389        if (irq < 0) {
 390                dev_err(dev, "no irq\n");
 391                ret = -ENXIO;
 392                goto out;
 393        }
 394
 395        clk = clk_get(dev, "spi");
 396        if (IS_ERR(clk)) {
 397                dev_err(dev, "no clock for device\n");
 398                ret = PTR_ERR(clk);
 399                goto out;
 400        }
 401
 402        master = spi_alloc_master(dev, sizeof(*bs));
 403        if (!master) {
 404                dev_err(dev, "out of memory\n");
 405                ret = -ENOMEM;
 406                goto out_clk;
 407        }
 408
 409        bs = spi_master_get_devdata(master);
 410
 411        platform_set_drvdata(pdev, master);
 412        bs->pdev = pdev;
 413
 414        bs->regs = devm_ioremap_resource(&pdev->dev, r);
 415        if (IS_ERR(bs->regs)) {
 416                ret = PTR_ERR(bs->regs);
 417                goto out_err;
 418        }
 419
 420        bs->irq = irq;
 421        bs->clk = clk;
 422        bs->fifo_size = pdata->fifo_size;
 423
 424        ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
 425                                                        pdev->name, master);
 426        if (ret) {
 427                dev_err(dev, "unable to request irq\n");
 428                goto out_err;
 429        }
 430
 431        master->bus_num = pdata->bus_num;
 432        master->num_chipselect = pdata->num_chipselect;
 433        master->setup = bcm63xx_spi_setup;
 434        master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer;
 435        master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer;
 436        master->transfer_one_message = bcm63xx_spi_transfer_one;
 437        master->mode_bits = MODEBITS;
 438        bs->msg_type_shift = pdata->msg_type_shift;
 439        bs->msg_ctl_width = pdata->msg_ctl_width;
 440        bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
 441        bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
 442
 443        switch (bs->msg_ctl_width) {
 444        case 8:
 445        case 16:
 446                break;
 447        default:
 448                dev_err(dev, "unsupported MSG_CTL width: %d\n",
 449                         bs->msg_ctl_width);
 450                goto out_err;
 451        }
 452
 453        /* Initialize hardware */
 454        clk_prepare_enable(bs->clk);
 455        bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 456
 457        /* register and we are done */
 458        ret = spi_register_master(master);
 459        if (ret) {
 460                dev_err(dev, "spi register failed\n");
 461                goto out_clk_disable;
 462        }
 463
 464        dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n",
 465                 r->start, irq, bs->fifo_size);
 466
 467        return 0;
 468
 469out_clk_disable:
 470        clk_disable_unprepare(clk);
 471out_err:
 472        platform_set_drvdata(pdev, NULL);
 473        spi_master_put(master);
 474out_clk:
 475        clk_put(clk);
 476out:
 477        return ret;
 478}
 479
 480static int bcm63xx_spi_remove(struct platform_device *pdev)
 481{
 482        struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
 483        struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 484
 485        spi_unregister_master(master);
 486
 487        /* reset spi block */
 488        bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 489
 490        /* HW shutdown */
 491        clk_disable_unprepare(bs->clk);
 492        clk_put(bs->clk);
 493
 494        platform_set_drvdata(pdev, 0);
 495
 496        spi_master_put(master);
 497
 498        return 0;
 499}
 500
 501#ifdef CONFIG_PM
 502static int bcm63xx_spi_suspend(struct device *dev)
 503{
 504        struct spi_master *master =
 505                        platform_get_drvdata(to_platform_device(dev));
 506        struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 507
 508        spi_master_suspend(master);
 509
 510        clk_disable_unprepare(bs->clk);
 511
 512        return 0;
 513}
 514
 515static int bcm63xx_spi_resume(struct device *dev)
 516{
 517        struct spi_master *master =
 518                        platform_get_drvdata(to_platform_device(dev));
 519        struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 520
 521        clk_prepare_enable(bs->clk);
 522
 523        spi_master_resume(master);
 524
 525        return 0;
 526}
 527
 528static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
 529        .suspend        = bcm63xx_spi_suspend,
 530        .resume         = bcm63xx_spi_resume,
 531};
 532
 533#define BCM63XX_SPI_PM_OPS      (&bcm63xx_spi_pm_ops)
 534#else
 535#define BCM63XX_SPI_PM_OPS      NULL
 536#endif
 537
 538static struct platform_driver bcm63xx_spi_driver = {
 539        .driver = {
 540                .name   = "bcm63xx-spi",
 541                .owner  = THIS_MODULE,
 542                .pm     = BCM63XX_SPI_PM_OPS,
 543        },
 544        .probe          = bcm63xx_spi_probe,
 545        .remove         = bcm63xx_spi_remove,
 546};
 547
 548module_platform_driver(bcm63xx_spi_driver);
 549
 550MODULE_ALIAS("platform:bcm63xx_spi");
 551MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
 552MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
 553MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
 554MODULE_LICENSE("GPL");
 555
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