linux/drivers/spi/spi-atmel.c
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   1/*
   2 * Driver for Atmel AT32 and AT91 SPI Controllers
   3 *
   4 * Copyright (C) 2006 Atmel Corporation
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 */
  10
  11#include <linux/kernel.h>
  12#include <linux/init.h>
  13#include <linux/clk.h>
  14#include <linux/module.h>
  15#include <linux/platform_device.h>
  16#include <linux/delay.h>
  17#include <linux/dma-mapping.h>
  18#include <linux/dmaengine.h>
  19#include <linux/err.h>
  20#include <linux/interrupt.h>
  21#include <linux/spi/spi.h>
  22#include <linux/slab.h>
  23#include <linux/platform_data/atmel.h>
  24#include <linux/platform_data/dma-atmel.h>
  25#include <linux/of.h>
  26
  27#include <linux/io.h>
  28#include <linux/gpio.h>
  29
  30/* SPI register offsets */
  31#define SPI_CR                                  0x0000
  32#define SPI_MR                                  0x0004
  33#define SPI_RDR                                 0x0008
  34#define SPI_TDR                                 0x000c
  35#define SPI_SR                                  0x0010
  36#define SPI_IER                                 0x0014
  37#define SPI_IDR                                 0x0018
  38#define SPI_IMR                                 0x001c
  39#define SPI_CSR0                                0x0030
  40#define SPI_CSR1                                0x0034
  41#define SPI_CSR2                                0x0038
  42#define SPI_CSR3                                0x003c
  43#define SPI_VERSION                             0x00fc
  44#define SPI_RPR                                 0x0100
  45#define SPI_RCR                                 0x0104
  46#define SPI_TPR                                 0x0108
  47#define SPI_TCR                                 0x010c
  48#define SPI_RNPR                                0x0110
  49#define SPI_RNCR                                0x0114
  50#define SPI_TNPR                                0x0118
  51#define SPI_TNCR                                0x011c
  52#define SPI_PTCR                                0x0120
  53#define SPI_PTSR                                0x0124
  54
  55/* Bitfields in CR */
  56#define SPI_SPIEN_OFFSET                        0
  57#define SPI_SPIEN_SIZE                          1
  58#define SPI_SPIDIS_OFFSET                       1
  59#define SPI_SPIDIS_SIZE                         1
  60#define SPI_SWRST_OFFSET                        7
  61#define SPI_SWRST_SIZE                          1
  62#define SPI_LASTXFER_OFFSET                     24
  63#define SPI_LASTXFER_SIZE                       1
  64
  65/* Bitfields in MR */
  66#define SPI_MSTR_OFFSET                         0
  67#define SPI_MSTR_SIZE                           1
  68#define SPI_PS_OFFSET                           1
  69#define SPI_PS_SIZE                             1
  70#define SPI_PCSDEC_OFFSET                       2
  71#define SPI_PCSDEC_SIZE                         1
  72#define SPI_FDIV_OFFSET                         3
  73#define SPI_FDIV_SIZE                           1
  74#define SPI_MODFDIS_OFFSET                      4
  75#define SPI_MODFDIS_SIZE                        1
  76#define SPI_WDRBT_OFFSET                        5
  77#define SPI_WDRBT_SIZE                          1
  78#define SPI_LLB_OFFSET                          7
  79#define SPI_LLB_SIZE                            1
  80#define SPI_PCS_OFFSET                          16
  81#define SPI_PCS_SIZE                            4
  82#define SPI_DLYBCS_OFFSET                       24
  83#define SPI_DLYBCS_SIZE                         8
  84
  85/* Bitfields in RDR */
  86#define SPI_RD_OFFSET                           0
  87#define SPI_RD_SIZE                             16
  88
  89/* Bitfields in TDR */
  90#define SPI_TD_OFFSET                           0
  91#define SPI_TD_SIZE                             16
  92
  93/* Bitfields in SR */
  94#define SPI_RDRF_OFFSET                         0
  95#define SPI_RDRF_SIZE                           1
  96#define SPI_TDRE_OFFSET                         1
  97#define SPI_TDRE_SIZE                           1
  98#define SPI_MODF_OFFSET                         2
  99#define SPI_MODF_SIZE                           1
 100#define SPI_OVRES_OFFSET                        3
 101#define SPI_OVRES_SIZE                          1
 102#define SPI_ENDRX_OFFSET                        4
 103#define SPI_ENDRX_SIZE                          1
 104#define SPI_ENDTX_OFFSET                        5
 105#define SPI_ENDTX_SIZE                          1
 106#define SPI_RXBUFF_OFFSET                       6
 107#define SPI_RXBUFF_SIZE                         1
 108#define SPI_TXBUFE_OFFSET                       7
 109#define SPI_TXBUFE_SIZE                         1
 110#define SPI_NSSR_OFFSET                         8
 111#define SPI_NSSR_SIZE                           1
 112#define SPI_TXEMPTY_OFFSET                      9
 113#define SPI_TXEMPTY_SIZE                        1
 114#define SPI_SPIENS_OFFSET                       16
 115#define SPI_SPIENS_SIZE                         1
 116
 117/* Bitfields in CSR0 */
 118#define SPI_CPOL_OFFSET                         0
 119#define SPI_CPOL_SIZE                           1
 120#define SPI_NCPHA_OFFSET                        1
 121#define SPI_NCPHA_SIZE                          1
 122#define SPI_CSAAT_OFFSET                        3
 123#define SPI_CSAAT_SIZE                          1
 124#define SPI_BITS_OFFSET                         4
 125#define SPI_BITS_SIZE                           4
 126#define SPI_SCBR_OFFSET                         8
 127#define SPI_SCBR_SIZE                           8
 128#define SPI_DLYBS_OFFSET                        16
 129#define SPI_DLYBS_SIZE                          8
 130#define SPI_DLYBCT_OFFSET                       24
 131#define SPI_DLYBCT_SIZE                         8
 132
 133/* Bitfields in RCR */
 134#define SPI_RXCTR_OFFSET                        0
 135#define SPI_RXCTR_SIZE                          16
 136
 137/* Bitfields in TCR */
 138#define SPI_TXCTR_OFFSET                        0
 139#define SPI_TXCTR_SIZE                          16
 140
 141/* Bitfields in RNCR */
 142#define SPI_RXNCR_OFFSET                        0
 143#define SPI_RXNCR_SIZE                          16
 144
 145/* Bitfields in TNCR */
 146#define SPI_TXNCR_OFFSET                        0
 147#define SPI_TXNCR_SIZE                          16
 148
 149/* Bitfields in PTCR */
 150#define SPI_RXTEN_OFFSET                        0
 151#define SPI_RXTEN_SIZE                          1
 152#define SPI_RXTDIS_OFFSET                       1
 153#define SPI_RXTDIS_SIZE                         1
 154#define SPI_TXTEN_OFFSET                        8
 155#define SPI_TXTEN_SIZE                          1
 156#define SPI_TXTDIS_OFFSET                       9
 157#define SPI_TXTDIS_SIZE                         1
 158
 159/* Constants for BITS */
 160#define SPI_BITS_8_BPT                          0
 161#define SPI_BITS_9_BPT                          1
 162#define SPI_BITS_10_BPT                         2
 163#define SPI_BITS_11_BPT                         3
 164#define SPI_BITS_12_BPT                         4
 165#define SPI_BITS_13_BPT                         5
 166#define SPI_BITS_14_BPT                         6
 167#define SPI_BITS_15_BPT                         7
 168#define SPI_BITS_16_BPT                         8
 169
 170/* Bit manipulation macros */
 171#define SPI_BIT(name) \
 172        (1 << SPI_##name##_OFFSET)
 173#define SPI_BF(name,value) \
 174        (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
 175#define SPI_BFEXT(name,value) \
 176        (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
 177#define SPI_BFINS(name,value,old) \
 178        ( ((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
 179          | SPI_BF(name,value))
 180
 181/* Register access macros */
 182#define spi_readl(port,reg) \
 183        __raw_readl((port)->regs + SPI_##reg)
 184#define spi_writel(port,reg,value) \
 185        __raw_writel((value), (port)->regs + SPI_##reg)
 186
 187/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 188 * cache operations; better heuristics consider wordsize and bitrate.
 189 */
 190#define DMA_MIN_BYTES   16
 191
 192struct atmel_spi_dma {
 193        struct dma_chan                 *chan_rx;
 194        struct dma_chan                 *chan_tx;
 195        struct scatterlist              sgrx;
 196        struct scatterlist              sgtx;
 197        struct dma_async_tx_descriptor  *data_desc_rx;
 198        struct dma_async_tx_descriptor  *data_desc_tx;
 199
 200        struct at_dma_slave     dma_slave;
 201};
 202
 203struct atmel_spi_caps {
 204        bool    is_spi2;
 205        bool    has_wdrbt;
 206        bool    has_dma_support;
 207};
 208
 209/*
 210 * The core SPI transfer engine just talks to a register bank to set up
 211 * DMA transfers; transfer queue progress is driven by IRQs.  The clock
 212 * framework provides the base clock, subdivided for each spi_device.
 213 */
 214struct atmel_spi {
 215        spinlock_t              lock;
 216        unsigned long           flags;
 217
 218        phys_addr_t             phybase;
 219        void __iomem            *regs;
 220        int                     irq;
 221        struct clk              *clk;
 222        struct platform_device  *pdev;
 223        struct spi_device       *stay;
 224
 225        u8                      stopping;
 226        struct list_head        queue;
 227        struct tasklet_struct   tasklet;
 228        struct spi_transfer     *current_transfer;
 229        unsigned long           current_remaining_bytes;
 230        struct spi_transfer     *next_transfer;
 231        unsigned long           next_remaining_bytes;
 232        int                     done_status;
 233
 234        /* scratch buffer */
 235        void                    *buffer;
 236        dma_addr_t              buffer_dma;
 237
 238        struct atmel_spi_caps   caps;
 239
 240        bool                    use_dma;
 241        bool                    use_pdc;
 242        /* dmaengine data */
 243        struct atmel_spi_dma    dma;
 244};
 245
 246/* Controller-specific per-slave state */
 247struct atmel_spi_device {
 248        unsigned int            npcs_pin;
 249        u32                     csr;
 250};
 251
 252#define BUFFER_SIZE             PAGE_SIZE
 253#define INVALID_DMA_ADDRESS     0xffffffff
 254
 255/*
 256 * Version 2 of the SPI controller has
 257 *  - CR.LASTXFER
 258 *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
 259 *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
 260 *  - SPI_CSRx.CSAAT
 261 *  - SPI_CSRx.SBCR allows faster clocking
 262 */
 263static bool atmel_spi_is_v2(struct atmel_spi *as)
 264{
 265        return as->caps.is_spi2;
 266}
 267
 268/*
 269 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
 270 * they assume that spi slave device state will not change on deselect, so
 271 * that automagic deselection is OK.  ("NPCSx rises if no data is to be
 272 * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
 273 * controllers have CSAAT and friends.
 274 *
 275 * Since the CSAAT functionality is a bit weird on newer controllers as
 276 * well, we use GPIO to control nCSx pins on all controllers, updating
 277 * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
 278 * support active-high chipselects despite the controller's belief that
 279 * only active-low devices/systems exists.
 280 *
 281 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
 282 * right when driven with GPIO.  ("Mode Fault does not allow more than one
 283 * Master on Chip Select 0.")  No workaround exists for that ... so for
 284 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
 285 * and (c) will trigger that first erratum in some cases.
 286 */
 287
 288static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
 289{
 290        struct atmel_spi_device *asd = spi->controller_state;
 291        unsigned active = spi->mode & SPI_CS_HIGH;
 292        u32 mr;
 293
 294        if (atmel_spi_is_v2(as)) {
 295                spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
 296                /* For the low SPI version, there is a issue that PDC transfer
 297                 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
 298                 */
 299                spi_writel(as, CSR0, asd->csr);
 300                if (as->caps.has_wdrbt) {
 301                        spi_writel(as, MR,
 302                                        SPI_BF(PCS, ~(0x01 << spi->chip_select))
 303                                        | SPI_BIT(WDRBT)
 304                                        | SPI_BIT(MODFDIS)
 305                                        | SPI_BIT(MSTR));
 306                } else {
 307                        spi_writel(as, MR,
 308                                        SPI_BF(PCS, ~(0x01 << spi->chip_select))
 309                                        | SPI_BIT(MODFDIS)
 310                                        | SPI_BIT(MSTR));
 311                }
 312
 313                mr = spi_readl(as, MR);
 314                gpio_set_value(asd->npcs_pin, active);
 315        } else {
 316                u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
 317                int i;
 318                u32 csr;
 319
 320                /* Make sure clock polarity is correct */
 321                for (i = 0; i < spi->master->num_chipselect; i++) {
 322                        csr = spi_readl(as, CSR0 + 4 * i);
 323                        if ((csr ^ cpol) & SPI_BIT(CPOL))
 324                                spi_writel(as, CSR0 + 4 * i,
 325                                                csr ^ SPI_BIT(CPOL));
 326                }
 327
 328                mr = spi_readl(as, MR);
 329                mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
 330                if (spi->chip_select != 0)
 331                        gpio_set_value(asd->npcs_pin, active);
 332                spi_writel(as, MR, mr);
 333        }
 334
 335        dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
 336                        asd->npcs_pin, active ? " (high)" : "",
 337                        mr);
 338}
 339
 340static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
 341{
 342        struct atmel_spi_device *asd = spi->controller_state;
 343        unsigned active = spi->mode & SPI_CS_HIGH;
 344        u32 mr;
 345
 346        /* only deactivate *this* device; sometimes transfers to
 347         * another device may be active when this routine is called.
 348         */
 349        mr = spi_readl(as, MR);
 350        if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
 351                mr = SPI_BFINS(PCS, 0xf, mr);
 352                spi_writel(as, MR, mr);
 353        }
 354
 355        dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
 356                        asd->npcs_pin, active ? " (low)" : "",
 357                        mr);
 358
 359        if (atmel_spi_is_v2(as) || spi->chip_select != 0)
 360                gpio_set_value(asd->npcs_pin, !active);
 361}
 362
 363static void atmel_spi_lock(struct atmel_spi *as)
 364{
 365        spin_lock_irqsave(&as->lock, as->flags);
 366}
 367
 368static void atmel_spi_unlock(struct atmel_spi *as)
 369{
 370        spin_unlock_irqrestore(&as->lock, as->flags);
 371}
 372
 373static inline bool atmel_spi_use_dma(struct atmel_spi *as,
 374                                struct spi_transfer *xfer)
 375{
 376        return as->use_dma && xfer->len >= DMA_MIN_BYTES;
 377}
 378
 379static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
 380                                        struct spi_transfer *xfer)
 381{
 382        return msg->transfers.prev == &xfer->transfer_list;
 383}
 384
 385static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
 386{
 387        return xfer->delay_usecs == 0 && !xfer->cs_change;
 388}
 389
 390static int atmel_spi_dma_slave_config(struct atmel_spi *as,
 391                                struct dma_slave_config *slave_config,
 392                                u8 bits_per_word)
 393{
 394        int err = 0;
 395
 396        if (bits_per_word > 8) {
 397                slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 398                slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 399        } else {
 400                slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 401                slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 402        }
 403
 404        slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
 405        slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
 406        slave_config->src_maxburst = 1;
 407        slave_config->dst_maxburst = 1;
 408        slave_config->device_fc = false;
 409
 410        slave_config->direction = DMA_MEM_TO_DEV;
 411        if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) {
 412                dev_err(&as->pdev->dev,
 413                        "failed to configure tx dma channel\n");
 414                err = -EINVAL;
 415        }
 416
 417        slave_config->direction = DMA_DEV_TO_MEM;
 418        if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) {
 419                dev_err(&as->pdev->dev,
 420                        "failed to configure rx dma channel\n");
 421                err = -EINVAL;
 422        }
 423
 424        return err;
 425}
 426
 427static bool filter(struct dma_chan *chan, void *slave)
 428{
 429        struct  at_dma_slave *sl = slave;
 430
 431        if (sl->dma_dev == chan->device->dev) {
 432                chan->private = sl;
 433                return true;
 434        } else {
 435                return false;
 436        }
 437}
 438
 439static int atmel_spi_configure_dma(struct atmel_spi *as)
 440{
 441        struct at_dma_slave *sdata = &as->dma.dma_slave;
 442        struct dma_slave_config slave_config;
 443        int err;
 444
 445        if (sdata && sdata->dma_dev) {
 446                dma_cap_mask_t mask;
 447
 448                /* Try to grab two DMA channels */
 449                dma_cap_zero(mask);
 450                dma_cap_set(DMA_SLAVE, mask);
 451                as->dma.chan_tx = dma_request_channel(mask, filter, sdata);
 452                if (as->dma.chan_tx)
 453                        as->dma.chan_rx =
 454                                dma_request_channel(mask, filter, sdata);
 455        }
 456        if (!as->dma.chan_rx || !as->dma.chan_tx) {
 457                dev_err(&as->pdev->dev,
 458                        "DMA channel not available, SPI unable to use DMA\n");
 459                err = -EBUSY;
 460                goto error;
 461        }
 462
 463        err = atmel_spi_dma_slave_config(as, &slave_config, 8);
 464        if (err)
 465                goto error;
 466
 467        dev_info(&as->pdev->dev,
 468                        "Using %s (tx) and %s (rx) for DMA transfers\n",
 469                        dma_chan_name(as->dma.chan_tx),
 470                        dma_chan_name(as->dma.chan_rx));
 471        return 0;
 472error:
 473        if (as->dma.chan_rx)
 474                dma_release_channel(as->dma.chan_rx);
 475        if (as->dma.chan_tx)
 476                dma_release_channel(as->dma.chan_tx);
 477        return err;
 478}
 479
 480static void atmel_spi_stop_dma(struct atmel_spi *as)
 481{
 482        if (as->dma.chan_rx)
 483                as->dma.chan_rx->device->device_control(as->dma.chan_rx,
 484                                                        DMA_TERMINATE_ALL, 0);
 485        if (as->dma.chan_tx)
 486                as->dma.chan_tx->device->device_control(as->dma.chan_tx,
 487                                                        DMA_TERMINATE_ALL, 0);
 488}
 489
 490static void atmel_spi_release_dma(struct atmel_spi *as)
 491{
 492        if (as->dma.chan_rx)
 493                dma_release_channel(as->dma.chan_rx);
 494        if (as->dma.chan_tx)
 495                dma_release_channel(as->dma.chan_tx);
 496}
 497
 498/* This function is called by the DMA driver from tasklet context */
 499static void dma_callback(void *data)
 500{
 501        struct spi_master       *master = data;
 502        struct atmel_spi        *as = spi_master_get_devdata(master);
 503
 504        /* trigger SPI tasklet */
 505        tasklet_schedule(&as->tasklet);
 506}
 507
 508/*
 509 * Next transfer using PIO.
 510 * lock is held, spi tasklet is blocked
 511 */
 512static void atmel_spi_next_xfer_pio(struct spi_master *master,
 513                                struct spi_transfer *xfer)
 514{
 515        struct atmel_spi        *as = spi_master_get_devdata(master);
 516
 517        dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
 518
 519        as->current_remaining_bytes = xfer->len;
 520
 521        /* Make sure data is not remaining in RDR */
 522        spi_readl(as, RDR);
 523        while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
 524                spi_readl(as, RDR);
 525                cpu_relax();
 526        }
 527
 528        if (xfer->tx_buf)
 529                if (xfer->bits_per_word > 8)
 530                        spi_writel(as, TDR, *(u16 *)(xfer->tx_buf));
 531                else
 532                        spi_writel(as, TDR, *(u8 *)(xfer->tx_buf));
 533        else
 534                spi_writel(as, TDR, 0);
 535
 536        dev_dbg(master->dev.parent,
 537                "  start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
 538                xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
 539                xfer->bits_per_word);
 540
 541        /* Enable relevant interrupts */
 542        spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
 543}
 544
 545/*
 546 * Submit next transfer for DMA.
 547 * lock is held, spi tasklet is blocked
 548 */
 549static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
 550                                struct spi_transfer *xfer,
 551                                u32 *plen)
 552{
 553        struct atmel_spi        *as = spi_master_get_devdata(master);
 554        struct dma_chan         *rxchan = as->dma.chan_rx;
 555        struct dma_chan         *txchan = as->dma.chan_tx;
 556        struct dma_async_tx_descriptor *rxdesc;
 557        struct dma_async_tx_descriptor *txdesc;
 558        struct dma_slave_config slave_config;
 559        dma_cookie_t            cookie;
 560        u32     len = *plen;
 561
 562        dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
 563
 564        /* Check that the channels are available */
 565        if (!rxchan || !txchan)
 566                return -ENODEV;
 567
 568        /* release lock for DMA operations */
 569        atmel_spi_unlock(as);
 570
 571        /* prepare the RX dma transfer */
 572        sg_init_table(&as->dma.sgrx, 1);
 573        if (xfer->rx_buf) {
 574                as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen;
 575        } else {
 576                as->dma.sgrx.dma_address = as->buffer_dma;
 577                if (len > BUFFER_SIZE)
 578                        len = BUFFER_SIZE;
 579        }
 580
 581        /* prepare the TX dma transfer */
 582        sg_init_table(&as->dma.sgtx, 1);
 583        if (xfer->tx_buf) {
 584                as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen;
 585        } else {
 586                as->dma.sgtx.dma_address = as->buffer_dma;
 587                if (len > BUFFER_SIZE)
 588                        len = BUFFER_SIZE;
 589                memset(as->buffer, 0, len);
 590        }
 591
 592        sg_dma_len(&as->dma.sgtx) = len;
 593        sg_dma_len(&as->dma.sgrx) = len;
 594
 595        *plen = len;
 596
 597        if (atmel_spi_dma_slave_config(as, &slave_config, 8))
 598                goto err_exit;
 599
 600        /* Send both scatterlists */
 601        rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
 602                                        &as->dma.sgrx,
 603                                        1,
 604                                        DMA_FROM_DEVICE,
 605                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
 606                                        NULL);
 607        if (!rxdesc)
 608                goto err_dma;
 609
 610        txdesc = txchan->device->device_prep_slave_sg(txchan,
 611                                        &as->dma.sgtx,
 612                                        1,
 613                                        DMA_TO_DEVICE,
 614                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
 615                                        NULL);
 616        if (!txdesc)
 617                goto err_dma;
 618
 619        dev_dbg(master->dev.parent,
 620                "  start dma xfer %p: len %u tx %p/%08x rx %p/%08x\n",
 621                xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
 622                xfer->rx_buf, xfer->rx_dma);
 623
 624        /* Enable relevant interrupts */
 625        spi_writel(as, IER, SPI_BIT(OVRES));
 626
 627        /* Put the callback on the RX transfer only, that should finish last */
 628        rxdesc->callback = dma_callback;
 629        rxdesc->callback_param = master;
 630
 631        /* Submit and fire RX and TX with TX last so we're ready to read! */
 632        cookie = rxdesc->tx_submit(rxdesc);
 633        if (dma_submit_error(cookie))
 634                goto err_dma;
 635        cookie = txdesc->tx_submit(txdesc);
 636        if (dma_submit_error(cookie))
 637                goto err_dma;
 638        rxchan->device->device_issue_pending(rxchan);
 639        txchan->device->device_issue_pending(txchan);
 640
 641        /* take back lock */
 642        atmel_spi_lock(as);
 643        return 0;
 644
 645err_dma:
 646        spi_writel(as, IDR, SPI_BIT(OVRES));
 647        atmel_spi_stop_dma(as);
 648err_exit:
 649        atmel_spi_lock(as);
 650        return -ENOMEM;
 651}
 652
 653static void atmel_spi_next_xfer_data(struct spi_master *master,
 654                                struct spi_transfer *xfer,
 655                                dma_addr_t *tx_dma,
 656                                dma_addr_t *rx_dma,
 657                                u32 *plen)
 658{
 659        struct atmel_spi        *as = spi_master_get_devdata(master);
 660        u32                     len = *plen;
 661
 662        /* use scratch buffer only when rx or tx data is unspecified */
 663        if (xfer->rx_buf)
 664                *rx_dma = xfer->rx_dma + xfer->len - *plen;
 665        else {
 666                *rx_dma = as->buffer_dma;
 667                if (len > BUFFER_SIZE)
 668                        len = BUFFER_SIZE;
 669        }
 670
 671        if (xfer->tx_buf)
 672                *tx_dma = xfer->tx_dma + xfer->len - *plen;
 673        else {
 674                *tx_dma = as->buffer_dma;
 675                if (len > BUFFER_SIZE)
 676                        len = BUFFER_SIZE;
 677                memset(as->buffer, 0, len);
 678                dma_sync_single_for_device(&as->pdev->dev,
 679                                as->buffer_dma, len, DMA_TO_DEVICE);
 680        }
 681
 682        *plen = len;
 683}
 684
 685/*
 686 * Submit next transfer for PDC.
 687 * lock is held, spi irq is blocked
 688 */
 689static void atmel_spi_pdc_next_xfer(struct spi_master *master,
 690                                struct spi_message *msg)
 691{
 692        struct atmel_spi        *as = spi_master_get_devdata(master);
 693        struct spi_transfer     *xfer;
 694        u32                     len, remaining;
 695        u32                     ieval;
 696        dma_addr_t              tx_dma, rx_dma;
 697
 698        if (!as->current_transfer)
 699                xfer = list_entry(msg->transfers.next,
 700                                struct spi_transfer, transfer_list);
 701        else if (!as->next_transfer)
 702                xfer = list_entry(as->current_transfer->transfer_list.next,
 703                                struct spi_transfer, transfer_list);
 704        else
 705                xfer = NULL;
 706
 707        if (xfer) {
 708                spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 709
 710                len = xfer->len;
 711                atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 712                remaining = xfer->len - len;
 713
 714                spi_writel(as, RPR, rx_dma);
 715                spi_writel(as, TPR, tx_dma);
 716
 717                if (msg->spi->bits_per_word > 8)
 718                        len >>= 1;
 719                spi_writel(as, RCR, len);
 720                spi_writel(as, TCR, len);
 721
 722                dev_dbg(&msg->spi->dev,
 723                        "  start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
 724                        xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
 725                        xfer->rx_buf, xfer->rx_dma);
 726        } else {
 727                xfer = as->next_transfer;
 728                remaining = as->next_remaining_bytes;
 729        }
 730
 731        as->current_transfer = xfer;
 732        as->current_remaining_bytes = remaining;
 733
 734        if (remaining > 0)
 735                len = remaining;
 736        else if (!atmel_spi_xfer_is_last(msg, xfer)
 737                        && atmel_spi_xfer_can_be_chained(xfer)) {
 738                xfer = list_entry(xfer->transfer_list.next,
 739                                struct spi_transfer, transfer_list);
 740                len = xfer->len;
 741        } else
 742                xfer = NULL;
 743
 744        as->next_transfer = xfer;
 745
 746        if (xfer) {
 747                u32     total;
 748
 749                total = len;
 750                atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 751                as->next_remaining_bytes = total - len;
 752
 753                spi_writel(as, RNPR, rx_dma);
 754                spi_writel(as, TNPR, tx_dma);
 755
 756                if (msg->spi->bits_per_word > 8)
 757                        len >>= 1;
 758                spi_writel(as, RNCR, len);
 759                spi_writel(as, TNCR, len);
 760
 761                dev_dbg(&msg->spi->dev,
 762                        "  next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
 763                        xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
 764                        xfer->rx_buf, xfer->rx_dma);
 765                ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES);
 766        } else {
 767                spi_writel(as, RNCR, 0);
 768                spi_writel(as, TNCR, 0);
 769                ieval = SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) | SPI_BIT(OVRES);
 770        }
 771
 772        /* REVISIT: We're waiting for ENDRX before we start the next
 773         * transfer because we need to handle some difficult timing
 774         * issues otherwise. If we wait for ENDTX in one transfer and
 775         * then starts waiting for ENDRX in the next, it's difficult
 776         * to tell the difference between the ENDRX interrupt we're
 777         * actually waiting for and the ENDRX interrupt of the
 778         * previous transfer.
 779         *
 780         * It should be doable, though. Just not now...
 781         */
 782        spi_writel(as, IER, ieval);
 783        spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
 784}
 785
 786/*
 787 * Choose way to submit next transfer and start it.
 788 * lock is held, spi tasklet is blocked
 789 */
 790static void atmel_spi_dma_next_xfer(struct spi_master *master,
 791                                struct spi_message *msg)
 792{
 793        struct atmel_spi        *as = spi_master_get_devdata(master);
 794        struct spi_transfer     *xfer;
 795        u32     remaining, len;
 796
 797        remaining = as->current_remaining_bytes;
 798        if (remaining) {
 799                xfer = as->current_transfer;
 800                len = remaining;
 801        } else {
 802                if (!as->current_transfer)
 803                        xfer = list_entry(msg->transfers.next,
 804                                struct spi_transfer, transfer_list);
 805                else
 806                        xfer = list_entry(
 807                                as->current_transfer->transfer_list.next,
 808                                        struct spi_transfer, transfer_list);
 809
 810                as->current_transfer = xfer;
 811                len = xfer->len;
 812        }
 813
 814        if (atmel_spi_use_dma(as, xfer)) {
 815                u32 total = len;
 816                if (!atmel_spi_next_xfer_dma_submit(master, xfer, &len)) {
 817                        as->current_remaining_bytes = total - len;
 818                        return;
 819                } else {
 820                        dev_err(&msg->spi->dev, "unable to use DMA, fallback to PIO\n");
 821                }
 822        }
 823
 824        /* use PIO if error appened using DMA */
 825        atmel_spi_next_xfer_pio(master, xfer);
 826}
 827
 828static void atmel_spi_next_message(struct spi_master *master)
 829{
 830        struct atmel_spi        *as = spi_master_get_devdata(master);
 831        struct spi_message      *msg;
 832        struct spi_device       *spi;
 833
 834        BUG_ON(as->current_transfer);
 835
 836        msg = list_entry(as->queue.next, struct spi_message, queue);
 837        spi = msg->spi;
 838
 839        dev_dbg(master->dev.parent, "start message %p for %s\n",
 840                        msg, dev_name(&spi->dev));
 841
 842        /* select chip if it's not still active */
 843        if (as->stay) {
 844                if (as->stay != spi) {
 845                        cs_deactivate(as, as->stay);
 846                        cs_activate(as, spi);
 847                }
 848                as->stay = NULL;
 849        } else
 850                cs_activate(as, spi);
 851
 852        if (as->use_pdc)
 853                atmel_spi_pdc_next_xfer(master, msg);
 854        else
 855                atmel_spi_dma_next_xfer(master, msg);
 856}
 857
 858/*
 859 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
 860 *  - The buffer is either valid for CPU access, else NULL
 861 *  - If the buffer is valid, so is its DMA address
 862 *
 863 * This driver manages the dma address unless message->is_dma_mapped.
 864 */
 865static int
 866atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
 867{
 868        struct device   *dev = &as->pdev->dev;
 869
 870        xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
 871        if (xfer->tx_buf) {
 872                /* tx_buf is a const void* where we need a void * for the dma
 873                 * mapping */
 874                void *nonconst_tx = (void *)xfer->tx_buf;
 875
 876                xfer->tx_dma = dma_map_single(dev,
 877                                nonconst_tx, xfer->len,
 878                                DMA_TO_DEVICE);
 879                if (dma_mapping_error(dev, xfer->tx_dma))
 880                        return -ENOMEM;
 881        }
 882        if (xfer->rx_buf) {
 883                xfer->rx_dma = dma_map_single(dev,
 884                                xfer->rx_buf, xfer->len,
 885                                DMA_FROM_DEVICE);
 886                if (dma_mapping_error(dev, xfer->rx_dma)) {
 887                        if (xfer->tx_buf)
 888                                dma_unmap_single(dev,
 889                                                xfer->tx_dma, xfer->len,
 890                                                DMA_TO_DEVICE);
 891                        return -ENOMEM;
 892                }
 893        }
 894        return 0;
 895}
 896
 897static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
 898                                     struct spi_transfer *xfer)
 899{
 900        if (xfer->tx_dma != INVALID_DMA_ADDRESS)
 901                dma_unmap_single(master->dev.parent, xfer->tx_dma,
 902                                 xfer->len, DMA_TO_DEVICE);
 903        if (xfer->rx_dma != INVALID_DMA_ADDRESS)
 904                dma_unmap_single(master->dev.parent, xfer->rx_dma,
 905                                 xfer->len, DMA_FROM_DEVICE);
 906}
 907
 908static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
 909{
 910        spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 911}
 912
 913static void
 914atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
 915                struct spi_message *msg, int stay)
 916{
 917        if (!stay || as->done_status < 0)
 918                cs_deactivate(as, msg->spi);
 919        else
 920                as->stay = msg->spi;
 921
 922        list_del(&msg->queue);
 923        msg->status = as->done_status;
 924
 925        dev_dbg(master->dev.parent,
 926                "xfer complete: %u bytes transferred\n",
 927                msg->actual_length);
 928
 929        atmel_spi_unlock(as);
 930        msg->complete(msg->context);
 931        atmel_spi_lock(as);
 932
 933        as->current_transfer = NULL;
 934        as->next_transfer = NULL;
 935        as->done_status = 0;
 936
 937        /* continue if needed */
 938        if (list_empty(&as->queue) || as->stopping) {
 939                if (as->use_pdc)
 940                        atmel_spi_disable_pdc_transfer(as);
 941        } else {
 942                atmel_spi_next_message(master);
 943        }
 944}
 945
 946/* Called from IRQ
 947 * lock is held
 948 *
 949 * Must update "current_remaining_bytes" to keep track of data
 950 * to transfer.
 951 */
 952static void
 953atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
 954{
 955        u8              *txp;
 956        u8              *rxp;
 957        u16             *txp16;
 958        u16             *rxp16;
 959        unsigned long   xfer_pos = xfer->len - as->current_remaining_bytes;
 960
 961        if (xfer->rx_buf) {
 962                if (xfer->bits_per_word > 8) {
 963                        rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
 964                        *rxp16 = spi_readl(as, RDR);
 965                } else {
 966                        rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
 967                        *rxp = spi_readl(as, RDR);
 968                }
 969        } else {
 970                spi_readl(as, RDR);
 971        }
 972        if (xfer->bits_per_word > 8) {
 973                as->current_remaining_bytes -= 2;
 974                if (as->current_remaining_bytes < 0)
 975                        as->current_remaining_bytes = 0;
 976        } else {
 977                as->current_remaining_bytes--;
 978        }
 979
 980        if (as->current_remaining_bytes) {
 981                if (xfer->tx_buf) {
 982                        if (xfer->bits_per_word > 8) {
 983                                txp16 = (u16 *)(((u8 *)xfer->tx_buf)
 984                                                        + xfer_pos + 2);
 985                                spi_writel(as, TDR, *txp16);
 986                        } else {
 987                                txp = ((u8 *)xfer->tx_buf) + xfer_pos + 1;
 988                                spi_writel(as, TDR, *txp);
 989                        }
 990                } else {
 991                        spi_writel(as, TDR, 0);
 992                }
 993        }
 994}
 995
 996/* Tasklet
 997 * Called from DMA callback + pio transfer and overrun IRQ.
 998 */
 999static void atmel_spi_tasklet_func(unsigned long data)
1000{
1001        struct spi_master       *master = (struct spi_master *)data;
1002        struct atmel_spi        *as = spi_master_get_devdata(master);
1003        struct spi_message      *msg;
1004        struct spi_transfer     *xfer;
1005
1006        dev_vdbg(master->dev.parent, "atmel_spi_tasklet_func\n");
1007
1008        atmel_spi_lock(as);
1009
1010        xfer = as->current_transfer;
1011
1012        if (xfer == NULL)
1013                /* already been there */
1014                goto tasklet_out;
1015
1016        msg = list_entry(as->queue.next, struct spi_message, queue);
1017
1018        if (as->current_remaining_bytes == 0) {
1019                if (as->done_status < 0) {
1020                        /* error happened (overrun) */
1021                        if (atmel_spi_use_dma(as, xfer))
1022                                atmel_spi_stop_dma(as);
1023                } else {
1024                        /* only update length if no error */
1025                        msg->actual_length += xfer->len;
1026                }
1027
1028                if (atmel_spi_use_dma(as, xfer))
1029                        if (!msg->is_dma_mapped)
1030                                atmel_spi_dma_unmap_xfer(master, xfer);
1031
1032                if (xfer->delay_usecs)
1033                        udelay(xfer->delay_usecs);
1034
1035                if (atmel_spi_xfer_is_last(msg, xfer) || as->done_status < 0) {
1036                        /* report completed (or erroneous) message */
1037                        atmel_spi_msg_done(master, as, msg, xfer->cs_change);
1038                } else {
1039                        if (xfer->cs_change) {
1040                                cs_deactivate(as, msg->spi);
1041                                udelay(1);
1042                                cs_activate(as, msg->spi);
1043                        }
1044
1045                        /*
1046                         * Not done yet. Submit the next transfer.
1047                         *
1048                         * FIXME handle protocol options for xfer
1049                         */
1050                        atmel_spi_dma_next_xfer(master, msg);
1051                }
1052        } else {
1053                /*
1054                 * Keep going, we still have data to send in
1055                 * the current transfer.
1056                 */
1057                atmel_spi_dma_next_xfer(master, msg);
1058        }
1059
1060tasklet_out:
1061        atmel_spi_unlock(as);
1062}
1063
1064/* Interrupt
1065 *
1066 * No need for locking in this Interrupt handler: done_status is the
1067 * only information modified. What we need is the update of this field
1068 * before tasklet runs. This is ensured by using barrier.
1069 */
1070static irqreturn_t
1071atmel_spi_pio_interrupt(int irq, void *dev_id)
1072{
1073        struct spi_master       *master = dev_id;
1074        struct atmel_spi        *as = spi_master_get_devdata(master);
1075        u32                     status, pending, imr;
1076        struct spi_transfer     *xfer;
1077        int                     ret = IRQ_NONE;
1078
1079        imr = spi_readl(as, IMR);
1080        status = spi_readl(as, SR);
1081        pending = status & imr;
1082
1083        if (pending & SPI_BIT(OVRES)) {
1084                ret = IRQ_HANDLED;
1085                spi_writel(as, IDR, SPI_BIT(OVRES));
1086                dev_warn(master->dev.parent, "overrun\n");
1087
1088                /*
1089                 * When we get an overrun, we disregard the current
1090                 * transfer. Data will not be copied back from any
1091                 * bounce buffer and msg->actual_len will not be
1092                 * updated with the last xfer.
1093                 *
1094                 * We will also not process any remaning transfers in
1095                 * the message.
1096                 *
1097                 * All actions are done in tasklet with done_status indication
1098                 */
1099                as->done_status = -EIO;
1100                smp_wmb();
1101
1102                /* Clear any overrun happening while cleaning up */
1103                spi_readl(as, SR);
1104
1105                tasklet_schedule(&as->tasklet);
1106
1107        } else if (pending & SPI_BIT(RDRF)) {
1108                atmel_spi_lock(as);
1109
1110                if (as->current_remaining_bytes) {
1111                        ret = IRQ_HANDLED;
1112                        xfer = as->current_transfer;
1113                        atmel_spi_pump_pio_data(as, xfer);
1114                        if (!as->current_remaining_bytes) {
1115                                /* no more data to xfer, kick tasklet */
1116                                spi_writel(as, IDR, pending);
1117                                tasklet_schedule(&as->tasklet);
1118                        }
1119                }
1120
1121                atmel_spi_unlock(as);
1122        } else {
1123                WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
1124                ret = IRQ_HANDLED;
1125                spi_writel(as, IDR, pending);
1126        }
1127
1128        return ret;
1129}
1130
1131static irqreturn_t
1132atmel_spi_pdc_interrupt(int irq, void *dev_id)
1133{
1134        struct spi_master       *master = dev_id;
1135        struct atmel_spi        *as = spi_master_get_devdata(master);
1136        struct spi_message      *msg;
1137        struct spi_transfer     *xfer;
1138        u32                     status, pending, imr;
1139        int                     ret = IRQ_NONE;
1140
1141        atmel_spi_lock(as);
1142
1143        xfer = as->current_transfer;
1144        msg = list_entry(as->queue.next, struct spi_message, queue);
1145
1146        imr = spi_readl(as, IMR);
1147        status = spi_readl(as, SR);
1148        pending = status & imr;
1149
1150        if (pending & SPI_BIT(OVRES)) {
1151                int timeout;
1152
1153                ret = IRQ_HANDLED;
1154
1155                spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
1156                                     | SPI_BIT(OVRES)));
1157
1158                /*
1159                 * When we get an overrun, we disregard the current
1160                 * transfer. Data will not be copied back from any
1161                 * bounce buffer and msg->actual_len will not be
1162                 * updated with the last xfer.
1163                 *
1164                 * We will also not process any remaning transfers in
1165                 * the message.
1166                 *
1167                 * First, stop the transfer and unmap the DMA buffers.
1168                 */
1169                spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1170                if (!msg->is_dma_mapped)
1171                        atmel_spi_dma_unmap_xfer(master, xfer);
1172
1173                /* REVISIT: udelay in irq is unfriendly */
1174                if (xfer->delay_usecs)
1175                        udelay(xfer->delay_usecs);
1176
1177                dev_warn(master->dev.parent, "overrun (%u/%u remaining)\n",
1178                         spi_readl(as, TCR), spi_readl(as, RCR));
1179
1180                /*
1181                 * Clean up DMA registers and make sure the data
1182                 * registers are empty.
1183                 */
1184                spi_writel(as, RNCR, 0);
1185                spi_writel(as, TNCR, 0);
1186                spi_writel(as, RCR, 0);
1187                spi_writel(as, TCR, 0);
1188                for (timeout = 1000; timeout; timeout--)
1189                        if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1190                                break;
1191                if (!timeout)
1192                        dev_warn(master->dev.parent,
1193                                 "timeout waiting for TXEMPTY");
1194                while (spi_readl(as, SR) & SPI_BIT(RDRF))
1195                        spi_readl(as, RDR);
1196
1197                /* Clear any overrun happening while cleaning up */
1198                spi_readl(as, SR);
1199
1200                as->done_status = -EIO;
1201                atmel_spi_msg_done(master, as, msg, 0);
1202        } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
1203                ret = IRQ_HANDLED;
1204
1205                spi_writel(as, IDR, pending);
1206
1207                if (as->current_remaining_bytes == 0) {
1208                        msg->actual_length += xfer->len;
1209
1210                        if (!msg->is_dma_mapped)
1211                                atmel_spi_dma_unmap_xfer(master, xfer);
1212
1213                        /* REVISIT: udelay in irq is unfriendly */
1214                        if (xfer->delay_usecs)
1215                                udelay(xfer->delay_usecs);
1216
1217                        if (atmel_spi_xfer_is_last(msg, xfer)) {
1218                                /* report completed message */
1219                                atmel_spi_msg_done(master, as, msg,
1220                                                xfer->cs_change);
1221                        } else {
1222                                if (xfer->cs_change) {
1223                                        cs_deactivate(as, msg->spi);
1224                                        udelay(1);
1225                                        cs_activate(as, msg->spi);
1226                                }
1227
1228                                /*
1229                                 * Not done yet. Submit the next transfer.
1230                                 *
1231                                 * FIXME handle protocol options for xfer
1232                                 */
1233                                atmel_spi_pdc_next_xfer(master, msg);
1234                        }
1235                } else {
1236                        /*
1237                         * Keep going, we still have data to send in
1238                         * the current transfer.
1239                         */
1240                        atmel_spi_pdc_next_xfer(master, msg);
1241                }
1242        }
1243
1244        atmel_spi_unlock(as);
1245
1246        return ret;
1247}
1248
1249static int atmel_spi_setup(struct spi_device *spi)
1250{
1251        struct atmel_spi        *as;
1252        struct atmel_spi_device *asd;
1253        u32                     scbr, csr;
1254        unsigned int            bits = spi->bits_per_word;
1255        unsigned long           bus_hz;
1256        unsigned int            npcs_pin;
1257        int                     ret;
1258
1259        as = spi_master_get_devdata(spi->master);
1260
1261        if (as->stopping)
1262                return -ESHUTDOWN;
1263
1264        if (spi->chip_select > spi->master->num_chipselect) {
1265                dev_dbg(&spi->dev,
1266                                "setup: invalid chipselect %u (%u defined)\n",
1267                                spi->chip_select, spi->master->num_chipselect);
1268                return -EINVAL;
1269        }
1270
1271        if (bits < 8 || bits > 16) {
1272                dev_dbg(&spi->dev,
1273                                "setup: invalid bits_per_word %u (8 to 16)\n",
1274                                bits);
1275                return -EINVAL;
1276        }
1277
1278        /* see notes above re chipselect */
1279        if (!atmel_spi_is_v2(as)
1280                        && spi->chip_select == 0
1281                        && (spi->mode & SPI_CS_HIGH)) {
1282                dev_dbg(&spi->dev, "setup: can't be active-high\n");
1283                return -EINVAL;
1284        }
1285
1286        /* v1 chips start out at half the peripheral bus speed. */
1287        bus_hz = clk_get_rate(as->clk);
1288        if (!atmel_spi_is_v2(as))
1289                bus_hz /= 2;
1290
1291        if (spi->max_speed_hz) {
1292                /*
1293                 * Calculate the lowest divider that satisfies the
1294                 * constraint, assuming div32/fdiv/mbz == 0.
1295                 */
1296                scbr = DIV_ROUND_UP(bus_hz, spi->max_speed_hz);
1297
1298                /*
1299                 * If the resulting divider doesn't fit into the
1300                 * register bitfield, we can't satisfy the constraint.
1301                 */
1302                if (scbr >= (1 << SPI_SCBR_SIZE)) {
1303                        dev_dbg(&spi->dev,
1304                                "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
1305                                spi->max_speed_hz, scbr, bus_hz/255);
1306                        return -EINVAL;
1307                }
1308        } else
1309                /* speed zero means "as slow as possible" */
1310                scbr = 0xff;
1311
1312        csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
1313        if (spi->mode & SPI_CPOL)
1314                csr |= SPI_BIT(CPOL);
1315        if (!(spi->mode & SPI_CPHA))
1316                csr |= SPI_BIT(NCPHA);
1317
1318        /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1319         *
1320         * DLYBCT would add delays between words, slowing down transfers.
1321         * It could potentially be useful to cope with DMA bottlenecks, but
1322         * in those cases it's probably best to just use a lower bitrate.
1323         */
1324        csr |= SPI_BF(DLYBS, 0);
1325        csr |= SPI_BF(DLYBCT, 0);
1326
1327        /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1328        npcs_pin = (unsigned int)spi->controller_data;
1329
1330        if (gpio_is_valid(spi->cs_gpio))
1331                npcs_pin = spi->cs_gpio;
1332
1333        asd = spi->controller_state;
1334        if (!asd) {
1335                asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1336                if (!asd)
1337                        return -ENOMEM;
1338
1339                ret = gpio_request(npcs_pin, dev_name(&spi->dev));
1340                if (ret) {
1341                        kfree(asd);
1342                        return ret;
1343                }
1344
1345                asd->npcs_pin = npcs_pin;
1346                spi->controller_state = asd;
1347                gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
1348        } else {
1349                atmel_spi_lock(as);
1350                if (as->stay == spi)
1351                        as->stay = NULL;
1352                cs_deactivate(as, spi);
1353                atmel_spi_unlock(as);
1354        }
1355
1356        asd->csr = csr;
1357
1358        dev_dbg(&spi->dev,
1359                "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
1360                bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
1361
1362        if (!atmel_spi_is_v2(as))
1363                spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
1364
1365        return 0;
1366}
1367
1368static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
1369{
1370        struct atmel_spi        *as;
1371        struct spi_transfer     *xfer;
1372        struct device           *controller = spi->master->dev.parent;
1373        u8                      bits;
1374        struct atmel_spi_device *asd;
1375
1376        as = spi_master_get_devdata(spi->master);
1377
1378        dev_dbg(controller, "new message %p submitted for %s\n",
1379                        msg, dev_name(&spi->dev));
1380
1381        if (unlikely(list_empty(&msg->transfers)))
1382                return -EINVAL;
1383
1384        if (as->stopping)
1385                return -ESHUTDOWN;
1386
1387        list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1388                if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1389                        dev_dbg(&spi->dev, "missing rx or tx buf\n");
1390                        return -EINVAL;
1391                }
1392
1393                if (xfer->bits_per_word) {
1394                        asd = spi->controller_state;
1395                        bits = (asd->csr >> 4) & 0xf;
1396                        if (bits != xfer->bits_per_word - 8) {
1397                                dev_dbg(&spi->dev, "you can't yet change "
1398                                         "bits_per_word in transfers\n");
1399                                return -ENOPROTOOPT;
1400                        }
1401                }
1402
1403                if (xfer->bits_per_word > 8) {
1404                        if (xfer->len % 2) {
1405                                dev_dbg(&spi->dev, "buffer len should be 16 bits aligned\n");
1406                                return -EINVAL;
1407                        }
1408                }
1409
1410                /* FIXME implement these protocol options!! */
1411                if (xfer->speed_hz < spi->max_speed_hz) {
1412                        dev_dbg(&spi->dev, "can't change speed in transfer\n");
1413                        return -ENOPROTOOPT;
1414                }
1415
1416                /*
1417                 * DMA map early, for performance (empties dcache ASAP) and
1418                 * better fault reporting.
1419                 */
1420                if ((!msg->is_dma_mapped) && (atmel_spi_use_dma(as, xfer)
1421                        || as->use_pdc)) {
1422                        if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1423                                return -ENOMEM;
1424                }
1425        }
1426
1427#ifdef VERBOSE
1428        list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1429                dev_dbg(controller,
1430                        "  xfer %p: len %u tx %p/%08x rx %p/%08x\n",
1431                        xfer, xfer->len,
1432                        xfer->tx_buf, xfer->tx_dma,
1433                        xfer->rx_buf, xfer->rx_dma);
1434        }
1435#endif
1436
1437        msg->status = -EINPROGRESS;
1438        msg->actual_length = 0;
1439
1440        atmel_spi_lock(as);
1441        list_add_tail(&msg->queue, &as->queue);
1442        if (!as->current_transfer)
1443                atmel_spi_next_message(spi->master);
1444        atmel_spi_unlock(as);
1445
1446        return 0;
1447}
1448
1449static void atmel_spi_cleanup(struct spi_device *spi)
1450{
1451        struct atmel_spi        *as = spi_master_get_devdata(spi->master);
1452        struct atmel_spi_device *asd = spi->controller_state;
1453        unsigned                gpio = (unsigned) spi->controller_data;
1454
1455        if (!asd)
1456                return;
1457
1458        atmel_spi_lock(as);
1459        if (as->stay == spi) {
1460                as->stay = NULL;
1461                cs_deactivate(as, spi);
1462        }
1463        atmel_spi_unlock(as);
1464
1465        spi->controller_state = NULL;
1466        gpio_free(gpio);
1467        kfree(asd);
1468}
1469
1470static inline unsigned int atmel_get_version(struct atmel_spi *as)
1471{
1472        return spi_readl(as, VERSION) & 0x00000fff;
1473}
1474
1475static void atmel_get_caps(struct atmel_spi *as)
1476{
1477        unsigned int version;
1478
1479        version = atmel_get_version(as);
1480        dev_info(&as->pdev->dev, "version: 0x%x\n", version);
1481
1482        as->caps.is_spi2 = version > 0x121;
1483        as->caps.has_wdrbt = version >= 0x210;
1484        as->caps.has_dma_support = version >= 0x212;
1485}
1486
1487/*-------------------------------------------------------------------------*/
1488
1489static int atmel_spi_probe(struct platform_device *pdev)
1490{
1491        struct resource         *regs;
1492        int                     irq;
1493        struct clk              *clk;
1494        int                     ret;
1495        struct spi_master       *master;
1496        struct atmel_spi        *as;
1497
1498        regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1499        if (!regs)
1500                return -ENXIO;
1501
1502        irq = platform_get_irq(pdev, 0);
1503        if (irq < 0)
1504                return irq;
1505
1506        clk = clk_get(&pdev->dev, "spi_clk");
1507        if (IS_ERR(clk))
1508                return PTR_ERR(clk);
1509
1510        /* setup spi core then atmel-specific driver state */
1511        ret = -ENOMEM;
1512        master = spi_alloc_master(&pdev->dev, sizeof *as);
1513        if (!master)
1514                goto out_free;
1515
1516        /* the spi->mode bits understood by this driver: */
1517        master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1518
1519        master->dev.of_node = pdev->dev.of_node;
1520        master->bus_num = pdev->id;
1521        master->num_chipselect = master->dev.of_node ? 0 : 4;
1522        master->setup = atmel_spi_setup;
1523        master->transfer = atmel_spi_transfer;
1524        master->cleanup = atmel_spi_cleanup;
1525        platform_set_drvdata(pdev, master);
1526
1527        as = spi_master_get_devdata(master);
1528
1529        /*
1530         * Scratch buffer is used for throwaway rx and tx data.
1531         * It's coherent to minimize dcache pollution.
1532         */
1533        as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
1534                                        &as->buffer_dma, GFP_KERNEL);
1535        if (!as->buffer)
1536                goto out_free;
1537
1538        spin_lock_init(&as->lock);
1539        INIT_LIST_HEAD(&as->queue);
1540
1541        as->pdev = pdev;
1542        as->regs = ioremap(regs->start, resource_size(regs));
1543        if (!as->regs)
1544                goto out_free_buffer;
1545        as->phybase = regs->start;
1546        as->irq = irq;
1547        as->clk = clk;
1548
1549        atmel_get_caps(as);
1550
1551        as->use_dma = false;
1552        as->use_pdc = false;
1553        if (as->caps.has_dma_support) {
1554                if (atmel_spi_configure_dma(as) == 0)
1555                        as->use_dma = true;
1556        } else {
1557                as->use_pdc = true;
1558        }
1559
1560        if (as->caps.has_dma_support && !as->use_dma)
1561                dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1562
1563        if (as->use_pdc) {
1564                ret = request_irq(irq, atmel_spi_pdc_interrupt, 0,
1565                                        dev_name(&pdev->dev), master);
1566        } else {
1567                tasklet_init(&as->tasklet, atmel_spi_tasklet_func,
1568                                        (unsigned long)master);
1569
1570                ret = request_irq(irq, atmel_spi_pio_interrupt, 0,
1571                                        dev_name(&pdev->dev), master);
1572        }
1573        if (ret)
1574                goto out_unmap_regs;
1575
1576        /* Initialize the hardware */
1577        clk_enable(clk);
1578        spi_writel(as, CR, SPI_BIT(SWRST));
1579        spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1580        if (as->caps.has_wdrbt) {
1581                spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1582                                | SPI_BIT(MSTR));
1583        } else {
1584                spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1585        }
1586
1587        if (as->use_pdc)
1588                spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1589        spi_writel(as, CR, SPI_BIT(SPIEN));
1590
1591        /* go! */
1592        dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1593                        (unsigned long)regs->start, irq);
1594
1595        ret = spi_register_master(master);
1596        if (ret)
1597                goto out_free_dma;
1598
1599        return 0;
1600
1601out_free_dma:
1602        if (as->use_dma)
1603                atmel_spi_release_dma(as);
1604
1605        spi_writel(as, CR, SPI_BIT(SWRST));
1606        spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1607        clk_disable(clk);
1608        free_irq(irq, master);
1609out_unmap_regs:
1610        iounmap(as->regs);
1611out_free_buffer:
1612        if (!as->use_pdc)
1613                tasklet_kill(&as->tasklet);
1614        dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1615                        as->buffer_dma);
1616out_free:
1617        clk_put(clk);
1618        spi_master_put(master);
1619        return ret;
1620}
1621
1622static int atmel_spi_remove(struct platform_device *pdev)
1623{
1624        struct spi_master       *master = platform_get_drvdata(pdev);
1625        struct atmel_spi        *as = spi_master_get_devdata(master);
1626        struct spi_message      *msg;
1627        struct spi_transfer     *xfer;
1628
1629        /* reset the hardware and block queue progress */
1630        spin_lock_irq(&as->lock);
1631        as->stopping = 1;
1632        if (as->use_dma) {
1633                atmel_spi_stop_dma(as);
1634                atmel_spi_release_dma(as);
1635        }
1636
1637        spi_writel(as, CR, SPI_BIT(SWRST));
1638        spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1639        spi_readl(as, SR);
1640        spin_unlock_irq(&as->lock);
1641
1642        /* Terminate remaining queued transfers */
1643        list_for_each_entry(msg, &as->queue, queue) {
1644                list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1645                        if (!msg->is_dma_mapped
1646                                && (atmel_spi_use_dma(as, xfer)
1647                                        || as->use_pdc))
1648                                atmel_spi_dma_unmap_xfer(master, xfer);
1649                }
1650                msg->status = -ESHUTDOWN;
1651                msg->complete(msg->context);
1652        }
1653
1654        if (!as->use_pdc)
1655                tasklet_kill(&as->tasklet);
1656        dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1657                        as->buffer_dma);
1658
1659        clk_disable(as->clk);
1660        clk_put(as->clk);
1661        free_irq(as->irq, master);
1662        iounmap(as->regs);
1663
1664        spi_unregister_master(master);
1665
1666        return 0;
1667}
1668
1669#ifdef  CONFIG_PM
1670
1671static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
1672{
1673        struct spi_master       *master = platform_get_drvdata(pdev);
1674        struct atmel_spi        *as = spi_master_get_devdata(master);
1675
1676        clk_disable(as->clk);
1677        return 0;
1678}
1679
1680static int atmel_spi_resume(struct platform_device *pdev)
1681{
1682        struct spi_master       *master = platform_get_drvdata(pdev);
1683        struct atmel_spi        *as = spi_master_get_devdata(master);
1684
1685        clk_enable(as->clk);
1686        return 0;
1687}
1688
1689#else
1690#define atmel_spi_suspend       NULL
1691#define atmel_spi_resume        NULL
1692#endif
1693
1694#if defined(CONFIG_OF)
1695static const struct of_device_id atmel_spi_dt_ids[] = {
1696        { .compatible = "atmel,at91rm9200-spi" },
1697        { /* sentinel */ }
1698};
1699
1700MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1701#endif
1702
1703static struct platform_driver atmel_spi_driver = {
1704        .driver         = {
1705                .name   = "atmel_spi",
1706                .owner  = THIS_MODULE,
1707                .of_match_table = of_match_ptr(atmel_spi_dt_ids),
1708        },
1709        .suspend        = atmel_spi_suspend,
1710        .resume         = atmel_spi_resume,
1711        .probe          = atmel_spi_probe,
1712        .remove         = atmel_spi_remove,
1713};
1714module_platform_driver(atmel_spi_driver);
1715
1716MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1717MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1718MODULE_LICENSE("GPL");
1719MODULE_ALIAS("platform:atmel_spi");
1720
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