linux/drivers/scsi/advansys.c
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   1#define DRV_NAME "advansys"
   2#define ASC_VERSION "3.4"       /* AdvanSys Driver Version */
   3
   4/*
   5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
   6 *
   7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
   8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
   9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
  10 * All Rights Reserved.
  11 *
  12 * This program is free software; you can redistribute it and/or modify
  13 * it under the terms of the GNU General Public License as published by
  14 * the Free Software Foundation; either version 2 of the License, or
  15 * (at your option) any later version.
  16 */
  17
  18/*
  19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
  20 * changed its name to ConnectCom Solutions, Inc.
  21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
  22 */
  23
  24#include <linux/module.h>
  25#include <linux/string.h>
  26#include <linux/kernel.h>
  27#include <linux/types.h>
  28#include <linux/ioport.h>
  29#include <linux/interrupt.h>
  30#include <linux/delay.h>
  31#include <linux/slab.h>
  32#include <linux/mm.h>
  33#include <linux/proc_fs.h>
  34#include <linux/init.h>
  35#include <linux/blkdev.h>
  36#include <linux/isa.h>
  37#include <linux/eisa.h>
  38#include <linux/pci.h>
  39#include <linux/spinlock.h>
  40#include <linux/dma-mapping.h>
  41#include <linux/firmware.h>
  42
  43#include <asm/io.h>
  44#include <asm/dma.h>
  45
  46#include <scsi/scsi_cmnd.h>
  47#include <scsi/scsi_device.h>
  48#include <scsi/scsi_tcq.h>
  49#include <scsi/scsi.h>
  50#include <scsi/scsi_host.h>
  51
  52/* FIXME:
  53 *
  54 *  1. Although all of the necessary command mapping places have the
  55 *     appropriate dma_map.. APIs, the driver still processes its internal
  56 *     queue using bus_to_virt() and virt_to_bus() which are illegal under
  57 *     the API.  The entire queue processing structure will need to be
  58 *     altered to fix this.
  59 *  2. Need to add memory mapping workaround. Test the memory mapping.
  60 *     If it doesn't work revert to I/O port access. Can a test be done
  61 *     safely?
  62 *  3. Handle an interrupt not working. Keep an interrupt counter in
  63 *     the interrupt handler. In the timeout function if the interrupt
  64 *     has not occurred then print a message and run in polled mode.
  65 *  4. Need to add support for target mode commands, cf. CAM XPT.
  66 *  5. check DMA mapping functions for failure
  67 *  6. Use scsi_transport_spi
  68 *  7. advansys_info is not safe against multiple simultaneous callers
  69 *  8. Add module_param to override ISA/VLB ioport array
  70 */
  71#warning this driver is still not properly converted to the DMA API
  72
  73/* Enable driver /proc statistics. */
  74#define ADVANSYS_STATS
  75
  76/* Enable driver tracing. */
  77#undef ADVANSYS_DEBUG
  78
  79/*
  80 * Portable Data Types
  81 *
  82 * Any instance where a 32-bit long or pointer type is assumed
  83 * for precision or HW defined structures, the following define
  84 * types must be used. In Linux the char, short, and int types
  85 * are all consistent at 8, 16, and 32 bits respectively. Pointers
  86 * and long types are 64 bits on Alpha and UltraSPARC.
  87 */
  88#define ASC_PADDR __u32         /* Physical/Bus address data type. */
  89#define ASC_VADDR __u32         /* Virtual address data type. */
  90#define ASC_DCNT  __u32         /* Unsigned Data count type. */
  91#define ASC_SDCNT __s32         /* Signed Data count type. */
  92
  93typedef unsigned char uchar;
  94
  95#ifndef TRUE
  96#define TRUE     (1)
  97#endif
  98#ifndef FALSE
  99#define FALSE    (0)
 100#endif
 101
 102#define ERR      (-1)
 103#define UW_ERR   (uint)(0xFFFF)
 104#define isodd_word(val)   ((((uint)val) & (uint)0x0001) != 0)
 105
 106#define PCI_VENDOR_ID_ASP               0x10cd
 107#define PCI_DEVICE_ID_ASP_1200A         0x1100
 108#define PCI_DEVICE_ID_ASP_ABP940        0x1200
 109#define PCI_DEVICE_ID_ASP_ABP940U       0x1300
 110#define PCI_DEVICE_ID_ASP_ABP940UW      0x2300
 111#define PCI_DEVICE_ID_38C0800_REV1      0x2500
 112#define PCI_DEVICE_ID_38C1600_REV1      0x2700
 113
 114/*
 115 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
 116 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
 117 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
 118 * SRB structure.
 119 */
 120#define CC_VERY_LONG_SG_LIST 0
 121#define ASC_SRB2SCSIQ(srb_ptr)  (srb_ptr)
 122
 123#define PortAddr                 unsigned int   /* port address size  */
 124#define inp(port)                inb(port)
 125#define outp(port, byte)         outb((byte), (port))
 126
 127#define inpw(port)               inw(port)
 128#define outpw(port, word)        outw((word), (port))
 129
 130#define ASC_MAX_SG_QUEUE    7
 131#define ASC_MAX_SG_LIST     255
 132
 133#define ASC_CS_TYPE  unsigned short
 134
 135#define ASC_IS_ISA          (0x0001)
 136#define ASC_IS_ISAPNP       (0x0081)
 137#define ASC_IS_EISA         (0x0002)
 138#define ASC_IS_PCI          (0x0004)
 139#define ASC_IS_PCI_ULTRA    (0x0104)
 140#define ASC_IS_PCMCIA       (0x0008)
 141#define ASC_IS_MCA          (0x0020)
 142#define ASC_IS_VL           (0x0040)
 143#define ASC_IS_WIDESCSI_16  (0x0100)
 144#define ASC_IS_WIDESCSI_32  (0x0200)
 145#define ASC_IS_BIG_ENDIAN   (0x8000)
 146
 147#define ASC_CHIP_MIN_VER_VL      (0x01)
 148#define ASC_CHIP_MAX_VER_VL      (0x07)
 149#define ASC_CHIP_MIN_VER_PCI     (0x09)
 150#define ASC_CHIP_MAX_VER_PCI     (0x0F)
 151#define ASC_CHIP_VER_PCI_BIT     (0x08)
 152#define ASC_CHIP_MIN_VER_ISA     (0x11)
 153#define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
 154#define ASC_CHIP_MAX_VER_ISA     (0x27)
 155#define ASC_CHIP_VER_ISA_BIT     (0x30)
 156#define ASC_CHIP_VER_ISAPNP_BIT  (0x20)
 157#define ASC_CHIP_VER_ASYN_BUG    (0x21)
 158#define ASC_CHIP_VER_PCI             0x08
 159#define ASC_CHIP_VER_PCI_ULTRA_3150  (ASC_CHIP_VER_PCI | 0x02)
 160#define ASC_CHIP_VER_PCI_ULTRA_3050  (ASC_CHIP_VER_PCI | 0x03)
 161#define ASC_CHIP_MIN_VER_EISA (0x41)
 162#define ASC_CHIP_MAX_VER_EISA (0x47)
 163#define ASC_CHIP_VER_EISA_BIT (0x40)
 164#define ASC_CHIP_LATEST_VER_EISA   ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
 165#define ASC_MAX_VL_DMA_COUNT    (0x07FFFFFFL)
 166#define ASC_MAX_PCI_DMA_COUNT   (0xFFFFFFFFL)
 167#define ASC_MAX_ISA_DMA_COUNT   (0x00FFFFFFL)
 168
 169#define ASC_SCSI_ID_BITS  3
 170#define ASC_SCSI_TIX_TYPE     uchar
 171#define ASC_ALL_DEVICE_BIT_SET  0xFF
 172#define ASC_SCSI_BIT_ID_TYPE  uchar
 173#define ASC_MAX_TID       7
 174#define ASC_MAX_LUN       7
 175#define ASC_SCSI_WIDTH_BIT_SET  0xFF
 176#define ASC_MAX_SENSE_LEN   32
 177#define ASC_MIN_SENSE_LEN   14
 178#define ASC_SCSI_RESET_HOLD_TIME_US  60
 179
 180/*
 181 * Narrow boards only support 12-byte commands, while wide boards
 182 * extend to 16-byte commands.
 183 */
 184#define ASC_MAX_CDB_LEN     12
 185#define ADV_MAX_CDB_LEN     16
 186
 187#define MS_SDTR_LEN    0x03
 188#define MS_WDTR_LEN    0x02
 189
 190#define ASC_SG_LIST_PER_Q   7
 191#define QS_FREE        0x00
 192#define QS_READY       0x01
 193#define QS_DISC1       0x02
 194#define QS_DISC2       0x04
 195#define QS_BUSY        0x08
 196#define QS_ABORTED     0x40
 197#define QS_DONE        0x80
 198#define QC_NO_CALLBACK   0x01
 199#define QC_SG_SWAP_QUEUE 0x02
 200#define QC_SG_HEAD       0x04
 201#define QC_DATA_IN       0x08
 202#define QC_DATA_OUT      0x10
 203#define QC_URGENT        0x20
 204#define QC_MSG_OUT       0x40
 205#define QC_REQ_SENSE     0x80
 206#define QCSG_SG_XFER_LIST  0x02
 207#define QCSG_SG_XFER_MORE  0x04
 208#define QCSG_SG_XFER_END   0x08
 209#define QD_IN_PROGRESS       0x00
 210#define QD_NO_ERROR          0x01
 211#define QD_ABORTED_BY_HOST   0x02
 212#define QD_WITH_ERROR        0x04
 213#define QD_INVALID_REQUEST   0x80
 214#define QD_INVALID_HOST_NUM  0x81
 215#define QD_INVALID_DEVICE    0x82
 216#define QD_ERR_INTERNAL      0xFF
 217#define QHSTA_NO_ERROR               0x00
 218#define QHSTA_M_SEL_TIMEOUT          0x11
 219#define QHSTA_M_DATA_OVER_RUN        0x12
 220#define QHSTA_M_DATA_UNDER_RUN       0x12
 221#define QHSTA_M_UNEXPECTED_BUS_FREE  0x13
 222#define QHSTA_M_BAD_BUS_PHASE_SEQ    0x14
 223#define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
 224#define QHSTA_D_ASC_DVC_ERROR_CODE_SET  0x22
 225#define QHSTA_D_HOST_ABORT_FAILED       0x23
 226#define QHSTA_D_EXE_SCSI_Q_FAILED       0x24
 227#define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
 228#define QHSTA_D_ASPI_NO_BUF_POOL        0x26
 229#define QHSTA_M_WTM_TIMEOUT         0x41
 230#define QHSTA_M_BAD_CMPL_STATUS_IN  0x42
 231#define QHSTA_M_NO_AUTO_REQ_SENSE   0x43
 232#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
 233#define QHSTA_M_TARGET_STATUS_BUSY  0x45
 234#define QHSTA_M_BAD_TAG_CODE        0x46
 235#define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY  0x47
 236#define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
 237#define QHSTA_D_LRAM_CMP_ERROR        0x81
 238#define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
 239#define ASC_FLAG_SCSIQ_REQ        0x01
 240#define ASC_FLAG_BIOS_SCSIQ_REQ   0x02
 241#define ASC_FLAG_BIOS_ASYNC_IO    0x04
 242#define ASC_FLAG_SRB_LINEAR_ADDR  0x08
 243#define ASC_FLAG_WIN16            0x10
 244#define ASC_FLAG_WIN32            0x20
 245#define ASC_FLAG_ISA_OVER_16MB    0x40
 246#define ASC_FLAG_DOS_VM_CALLBACK  0x80
 247#define ASC_TAG_FLAG_EXTRA_BYTES               0x10
 248#define ASC_TAG_FLAG_DISABLE_DISCONNECT        0x04
 249#define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX  0x08
 250#define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
 251#define ASC_SCSIQ_CPY_BEG              4
 252#define ASC_SCSIQ_SGHD_CPY_BEG         2
 253#define ASC_SCSIQ_B_FWD                0
 254#define ASC_SCSIQ_B_BWD                1
 255#define ASC_SCSIQ_B_STATUS             2
 256#define ASC_SCSIQ_B_QNO                3
 257#define ASC_SCSIQ_B_CNTL               4
 258#define ASC_SCSIQ_B_SG_QUEUE_CNT       5
 259#define ASC_SCSIQ_D_DATA_ADDR          8
 260#define ASC_SCSIQ_D_DATA_CNT          12
 261#define ASC_SCSIQ_B_SENSE_LEN         20
 262#define ASC_SCSIQ_DONE_INFO_BEG       22
 263#define ASC_SCSIQ_D_SRBPTR            22
 264#define ASC_SCSIQ_B_TARGET_IX         26
 265#define ASC_SCSIQ_B_CDB_LEN           28
 266#define ASC_SCSIQ_B_TAG_CODE          29
 267#define ASC_SCSIQ_W_VM_ID             30
 268#define ASC_SCSIQ_DONE_STATUS         32
 269#define ASC_SCSIQ_HOST_STATUS         33
 270#define ASC_SCSIQ_SCSI_STATUS         34
 271#define ASC_SCSIQ_CDB_BEG             36
 272#define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
 273#define ASC_SCSIQ_DW_REMAIN_XFER_CNT  60
 274#define ASC_SCSIQ_B_FIRST_SG_WK_QP    48
 275#define ASC_SCSIQ_B_SG_WK_QP          49
 276#define ASC_SCSIQ_B_SG_WK_IX          50
 277#define ASC_SCSIQ_W_ALT_DC1           52
 278#define ASC_SCSIQ_B_LIST_CNT          6
 279#define ASC_SCSIQ_B_CUR_LIST_CNT      7
 280#define ASC_SGQ_B_SG_CNTL             4
 281#define ASC_SGQ_B_SG_HEAD_QP          5
 282#define ASC_SGQ_B_SG_LIST_CNT         6
 283#define ASC_SGQ_B_SG_CUR_LIST_CNT     7
 284#define ASC_SGQ_LIST_BEG              8
 285#define ASC_DEF_SCSI1_QNG    4
 286#define ASC_MAX_SCSI1_QNG    4
 287#define ASC_DEF_SCSI2_QNG    16
 288#define ASC_MAX_SCSI2_QNG    32
 289#define ASC_TAG_CODE_MASK    0x23
 290#define ASC_STOP_REQ_RISC_STOP      0x01
 291#define ASC_STOP_ACK_RISC_STOP      0x03
 292#define ASC_STOP_CLEAN_UP_BUSY_Q    0x10
 293#define ASC_STOP_CLEAN_UP_DISC_Q    0x20
 294#define ASC_STOP_HOST_REQ_RISC_HALT 0x40
 295#define ASC_TIDLUN_TO_IX(tid, lun)  (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
 296#define ASC_TID_TO_TARGET_ID(tid)   (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
 297#define ASC_TIX_TO_TARGET_ID(tix)   (0x01 << ((tix) & ASC_MAX_TID))
 298#define ASC_TIX_TO_TID(tix)         ((tix) & ASC_MAX_TID)
 299#define ASC_TID_TO_TIX(tid)         ((tid) & ASC_MAX_TID)
 300#define ASC_TIX_TO_LUN(tix)         (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
 301#define ASC_QNO_TO_QADDR(q_no)      ((ASC_QADR_BEG)+((int)(q_no) << 6))
 302
 303typedef struct asc_scsiq_1 {
 304        uchar status;
 305        uchar q_no;
 306        uchar cntl;
 307        uchar sg_queue_cnt;
 308        uchar target_id;
 309        uchar target_lun;
 310        ASC_PADDR data_addr;
 311        ASC_DCNT data_cnt;
 312        ASC_PADDR sense_addr;
 313        uchar sense_len;
 314        uchar extra_bytes;
 315} ASC_SCSIQ_1;
 316
 317typedef struct asc_scsiq_2 {
 318        ASC_VADDR srb_ptr;
 319        uchar target_ix;
 320        uchar flag;
 321        uchar cdb_len;
 322        uchar tag_code;
 323        ushort vm_id;
 324} ASC_SCSIQ_2;
 325
 326typedef struct asc_scsiq_3 {
 327        uchar done_stat;
 328        uchar host_stat;
 329        uchar scsi_stat;
 330        uchar scsi_msg;
 331} ASC_SCSIQ_3;
 332
 333typedef struct asc_scsiq_4 {
 334        uchar cdb[ASC_MAX_CDB_LEN];
 335        uchar y_first_sg_list_qp;
 336        uchar y_working_sg_qp;
 337        uchar y_working_sg_ix;
 338        uchar y_res;
 339        ushort x_req_count;
 340        ushort x_reconnect_rtn;
 341        ASC_PADDR x_saved_data_addr;
 342        ASC_DCNT x_saved_data_cnt;
 343} ASC_SCSIQ_4;
 344
 345typedef struct asc_q_done_info {
 346        ASC_SCSIQ_2 d2;
 347        ASC_SCSIQ_3 d3;
 348        uchar q_status;
 349        uchar q_no;
 350        uchar cntl;
 351        uchar sense_len;
 352        uchar extra_bytes;
 353        uchar res;
 354        ASC_DCNT remain_bytes;
 355} ASC_QDONE_INFO;
 356
 357typedef struct asc_sg_list {
 358        ASC_PADDR addr;
 359        ASC_DCNT bytes;
 360} ASC_SG_LIST;
 361
 362typedef struct asc_sg_head {
 363        ushort entry_cnt;
 364        ushort queue_cnt;
 365        ushort entry_to_copy;
 366        ushort res;
 367        ASC_SG_LIST sg_list[0];
 368} ASC_SG_HEAD;
 369
 370typedef struct asc_scsi_q {
 371        ASC_SCSIQ_1 q1;
 372        ASC_SCSIQ_2 q2;
 373        uchar *cdbptr;
 374        ASC_SG_HEAD *sg_head;
 375        ushort remain_sg_entry_cnt;
 376        ushort next_sg_index;
 377} ASC_SCSI_Q;
 378
 379typedef struct asc_scsi_req_q {
 380        ASC_SCSIQ_1 r1;
 381        ASC_SCSIQ_2 r2;
 382        uchar *cdbptr;
 383        ASC_SG_HEAD *sg_head;
 384        uchar *sense_ptr;
 385        ASC_SCSIQ_3 r3;
 386        uchar cdb[ASC_MAX_CDB_LEN];
 387        uchar sense[ASC_MIN_SENSE_LEN];
 388} ASC_SCSI_REQ_Q;
 389
 390typedef struct asc_scsi_bios_req_q {
 391        ASC_SCSIQ_1 r1;
 392        ASC_SCSIQ_2 r2;
 393        uchar *cdbptr;
 394        ASC_SG_HEAD *sg_head;
 395        uchar *sense_ptr;
 396        ASC_SCSIQ_3 r3;
 397        uchar cdb[ASC_MAX_CDB_LEN];
 398        uchar sense[ASC_MIN_SENSE_LEN];
 399} ASC_SCSI_BIOS_REQ_Q;
 400
 401typedef struct asc_risc_q {
 402        uchar fwd;
 403        uchar bwd;
 404        ASC_SCSIQ_1 i1;
 405        ASC_SCSIQ_2 i2;
 406        ASC_SCSIQ_3 i3;
 407        ASC_SCSIQ_4 i4;
 408} ASC_RISC_Q;
 409
 410typedef struct asc_sg_list_q {
 411        uchar seq_no;
 412        uchar q_no;
 413        uchar cntl;
 414        uchar sg_head_qp;
 415        uchar sg_list_cnt;
 416        uchar sg_cur_list_cnt;
 417} ASC_SG_LIST_Q;
 418
 419typedef struct asc_risc_sg_list_q {
 420        uchar fwd;
 421        uchar bwd;
 422        ASC_SG_LIST_Q sg;
 423        ASC_SG_LIST sg_list[7];
 424} ASC_RISC_SG_LIST_Q;
 425
 426#define ASCQ_ERR_Q_STATUS             0x0D
 427#define ASCQ_ERR_CUR_QNG              0x17
 428#define ASCQ_ERR_SG_Q_LINKS           0x18
 429#define ASCQ_ERR_ISR_RE_ENTRY         0x1A
 430#define ASCQ_ERR_CRITICAL_RE_ENTRY    0x1B
 431#define ASCQ_ERR_ISR_ON_CRITICAL      0x1C
 432
 433/*
 434 * Warning code values are set in ASC_DVC_VAR  'warn_code'.
 435 */
 436#define ASC_WARN_NO_ERROR             0x0000
 437#define ASC_WARN_IO_PORT_ROTATE       0x0001
 438#define ASC_WARN_EEPROM_CHKSUM        0x0002
 439#define ASC_WARN_IRQ_MODIFIED         0x0004
 440#define ASC_WARN_AUTO_CONFIG          0x0008
 441#define ASC_WARN_CMD_QNG_CONFLICT     0x0010
 442#define ASC_WARN_EEPROM_RECOVER       0x0020
 443#define ASC_WARN_CFG_MSW_RECOVER      0x0040
 444
 445/*
 446 * Error code values are set in {ASC/ADV}_DVC_VAR  'err_code'.
 447 */
 448#define ASC_IERR_NO_CARRIER             0x0001  /* No more carrier memory */
 449#define ASC_IERR_MCODE_CHKSUM           0x0002  /* micro code check sum error */
 450#define ASC_IERR_SET_PC_ADDR            0x0004
 451#define ASC_IERR_START_STOP_CHIP        0x0008  /* start/stop chip failed */
 452#define ASC_IERR_ILLEGAL_CONNECTION     0x0010  /* Illegal cable connection */
 453#define ASC_IERR_SINGLE_END_DEVICE      0x0020  /* SE device on DIFF bus */
 454#define ASC_IERR_REVERSED_CABLE         0x0040  /* Narrow flat cable reversed */
 455#define ASC_IERR_SET_SCSI_ID            0x0080  /* set SCSI ID failed */
 456#define ASC_IERR_HVD_DEVICE             0x0100  /* HVD device on LVD port */
 457#define ASC_IERR_BAD_SIGNATURE          0x0200  /* signature not found */
 458#define ASC_IERR_NO_BUS_TYPE            0x0400
 459#define ASC_IERR_BIST_PRE_TEST          0x0800  /* BIST pre-test error */
 460#define ASC_IERR_BIST_RAM_TEST          0x1000  /* BIST RAM test error */
 461#define ASC_IERR_BAD_CHIPTYPE           0x2000  /* Invalid chip_type setting */
 462
 463#define ASC_DEF_MAX_TOTAL_QNG   (0xF0)
 464#define ASC_MIN_TAG_Q_PER_DVC   (0x04)
 465#define ASC_MIN_FREE_Q        (0x02)
 466#define ASC_MIN_TOTAL_QNG     ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
 467#define ASC_MAX_TOTAL_QNG 240
 468#define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
 469#define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG   8
 470#define ASC_MAX_PCI_INRAM_TOTAL_QNG  20
 471#define ASC_MAX_INRAM_TAG_QNG   16
 472#define ASC_IOADR_GAP   0x10
 473#define ASC_SYN_MAX_OFFSET         0x0F
 474#define ASC_DEF_SDTR_OFFSET        0x0F
 475#define ASC_SDTR_ULTRA_PCI_10MB_INDEX  0x02
 476#define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
 477
 478/* The narrow chip only supports a limited selection of transfer rates.
 479 * These are encoded in the range 0..7 or 0..15 depending whether the chip
 480 * is Ultra-capable or not.  These tables let us convert from one to the other.
 481 */
 482static const unsigned char asc_syn_xfer_period[8] = {
 483        25, 30, 35, 40, 50, 60, 70, 85
 484};
 485
 486static const unsigned char asc_syn_ultra_xfer_period[16] = {
 487        12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
 488};
 489
 490typedef struct ext_msg {
 491        uchar msg_type;
 492        uchar msg_len;
 493        uchar msg_req;
 494        union {
 495                struct {
 496                        uchar sdtr_xfer_period;
 497                        uchar sdtr_req_ack_offset;
 498                } sdtr;
 499                struct {
 500                        uchar wdtr_width;
 501                } wdtr;
 502                struct {
 503                        uchar mdp_b3;
 504                        uchar mdp_b2;
 505                        uchar mdp_b1;
 506                        uchar mdp_b0;
 507                } mdp;
 508        } u_ext_msg;
 509        uchar res;
 510} EXT_MSG;
 511
 512#define xfer_period     u_ext_msg.sdtr.sdtr_xfer_period
 513#define req_ack_offset  u_ext_msg.sdtr.sdtr_req_ack_offset
 514#define wdtr_width      u_ext_msg.wdtr.wdtr_width
 515#define mdp_b3          u_ext_msg.mdp_b3
 516#define mdp_b2          u_ext_msg.mdp_b2
 517#define mdp_b1          u_ext_msg.mdp_b1
 518#define mdp_b0          u_ext_msg.mdp_b0
 519
 520typedef struct asc_dvc_cfg {
 521        ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
 522        ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
 523        ASC_SCSI_BIT_ID_TYPE disc_enable;
 524        ASC_SCSI_BIT_ID_TYPE sdtr_enable;
 525        uchar chip_scsi_id;
 526        uchar isa_dma_speed;
 527        uchar isa_dma_channel;
 528        uchar chip_version;
 529        ushort mcode_date;
 530        ushort mcode_version;
 531        uchar max_tag_qng[ASC_MAX_TID + 1];
 532        uchar sdtr_period_offset[ASC_MAX_TID + 1];
 533        uchar adapter_info[6];
 534} ASC_DVC_CFG;
 535
 536#define ASC_DEF_DVC_CNTL       0xFFFF
 537#define ASC_DEF_CHIP_SCSI_ID   7
 538#define ASC_DEF_ISA_DMA_SPEED  4
 539#define ASC_INIT_STATE_BEG_GET_CFG   0x0001
 540#define ASC_INIT_STATE_END_GET_CFG   0x0002
 541#define ASC_INIT_STATE_BEG_SET_CFG   0x0004
 542#define ASC_INIT_STATE_END_SET_CFG   0x0008
 543#define ASC_INIT_STATE_BEG_LOAD_MC   0x0010
 544#define ASC_INIT_STATE_END_LOAD_MC   0x0020
 545#define ASC_INIT_STATE_BEG_INQUIRY   0x0040
 546#define ASC_INIT_STATE_END_INQUIRY   0x0080
 547#define ASC_INIT_RESET_SCSI_DONE     0x0100
 548#define ASC_INIT_STATE_WITHOUT_EEP   0x8000
 549#define ASC_BUG_FIX_IF_NOT_DWB       0x0001
 550#define ASC_BUG_FIX_ASYN_USE_SYN     0x0002
 551#define ASC_MIN_TAGGED_CMD  7
 552#define ASC_MAX_SCSI_RESET_WAIT      30
 553#define ASC_OVERRUN_BSIZE               64
 554
 555struct asc_dvc_var;             /* Forward Declaration. */
 556
 557typedef struct asc_dvc_var {
 558        PortAddr iop_base;
 559        ushort err_code;
 560        ushort dvc_cntl;
 561        ushort bug_fix_cntl;
 562        ushort bus_type;
 563        ASC_SCSI_BIT_ID_TYPE init_sdtr;
 564        ASC_SCSI_BIT_ID_TYPE sdtr_done;
 565        ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
 566        ASC_SCSI_BIT_ID_TYPE unit_not_ready;
 567        ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
 568        ASC_SCSI_BIT_ID_TYPE start_motor;
 569        uchar *overrun_buf;
 570        dma_addr_t overrun_dma;
 571        uchar scsi_reset_wait;
 572        uchar chip_no;
 573        char is_in_int;
 574        uchar max_total_qng;
 575        uchar cur_total_qng;
 576        uchar in_critical_cnt;
 577        uchar last_q_shortage;
 578        ushort init_state;
 579        uchar cur_dvc_qng[ASC_MAX_TID + 1];
 580        uchar max_dvc_qng[ASC_MAX_TID + 1];
 581        ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
 582        ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
 583        const uchar *sdtr_period_tbl;
 584        ASC_DVC_CFG *cfg;
 585        ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
 586        char redo_scam;
 587        ushort res2;
 588        uchar dos_int13_table[ASC_MAX_TID + 1];
 589        ASC_DCNT max_dma_count;
 590        ASC_SCSI_BIT_ID_TYPE no_scam;
 591        ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
 592        uchar min_sdtr_index;
 593        uchar max_sdtr_index;
 594        struct asc_board *drv_ptr;
 595        int ptr_map_count;
 596        void **ptr_map;
 597        ASC_DCNT uc_break;
 598} ASC_DVC_VAR;
 599
 600typedef struct asc_dvc_inq_info {
 601        uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
 602} ASC_DVC_INQ_INFO;
 603
 604typedef struct asc_cap_info {
 605        ASC_DCNT lba;
 606        ASC_DCNT blk_size;
 607} ASC_CAP_INFO;
 608
 609typedef struct asc_cap_info_array {
 610        ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
 611} ASC_CAP_INFO_ARRAY;
 612
 613#define ASC_MCNTL_NO_SEL_TIMEOUT  (ushort)0x0001
 614#define ASC_MCNTL_NULL_TARGET     (ushort)0x0002
 615#define ASC_CNTL_INITIATOR         (ushort)0x0001
 616#define ASC_CNTL_BIOS_GT_1GB       (ushort)0x0002
 617#define ASC_CNTL_BIOS_GT_2_DISK    (ushort)0x0004
 618#define ASC_CNTL_BIOS_REMOVABLE    (ushort)0x0008
 619#define ASC_CNTL_NO_SCAM           (ushort)0x0010
 620#define ASC_CNTL_INT_MULTI_Q       (ushort)0x0080
 621#define ASC_CNTL_NO_LUN_SUPPORT    (ushort)0x0040
 622#define ASC_CNTL_NO_VERIFY_COPY    (ushort)0x0100
 623#define ASC_CNTL_RESET_SCSI        (ushort)0x0200
 624#define ASC_CNTL_INIT_INQUIRY      (ushort)0x0400
 625#define ASC_CNTL_INIT_VERBOSE      (ushort)0x0800
 626#define ASC_CNTL_SCSI_PARITY       (ushort)0x1000
 627#define ASC_CNTL_BURST_MODE        (ushort)0x2000
 628#define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
 629#define ASC_EEP_DVC_CFG_BEG_VL    2
 630#define ASC_EEP_MAX_DVC_ADDR_VL   15
 631#define ASC_EEP_DVC_CFG_BEG      32
 632#define ASC_EEP_MAX_DVC_ADDR     45
 633#define ASC_EEP_MAX_RETRY        20
 634
 635/*
 636 * These macros keep the chip SCSI id and ISA DMA speed
 637 * bitfields in board order. C bitfields aren't portable
 638 * between big and little-endian platforms so they are
 639 * not used.
 640 */
 641
 642#define ASC_EEP_GET_CHIP_ID(cfg)    ((cfg)->id_speed & 0x0f)
 643#define ASC_EEP_GET_DMA_SPD(cfg)    (((cfg)->id_speed & 0xf0) >> 4)
 644#define ASC_EEP_SET_CHIP_ID(cfg, sid) \
 645   ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
 646#define ASC_EEP_SET_DMA_SPD(cfg, spd) \
 647   ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
 648
 649typedef struct asceep_config {
 650        ushort cfg_lsw;
 651        ushort cfg_msw;
 652        uchar init_sdtr;
 653        uchar disc_enable;
 654        uchar use_cmd_qng;
 655        uchar start_motor;
 656        uchar max_total_qng;
 657        uchar max_tag_qng;
 658        uchar bios_scan;
 659        uchar power_up_wait;
 660        uchar no_scam;
 661        uchar id_speed;         /* low order 4 bits is chip scsi id */
 662        /* high order 4 bits is isa dma speed */
 663        uchar dos_int13_table[ASC_MAX_TID + 1];
 664        uchar adapter_info[6];
 665        ushort cntl;
 666        ushort chksum;
 667} ASCEEP_CONFIG;
 668
 669#define ASC_EEP_CMD_READ          0x80
 670#define ASC_EEP_CMD_WRITE         0x40
 671#define ASC_EEP_CMD_WRITE_ABLE    0x30
 672#define ASC_EEP_CMD_WRITE_DISABLE 0x00
 673#define ASCV_MSGOUT_BEG         0x0000
 674#define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
 675#define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
 676#define ASCV_BREAK_SAVED_CODE   (ushort)0x0006
 677#define ASCV_MSGIN_BEG          (ASCV_MSGOUT_BEG+8)
 678#define ASCV_MSGIN_SDTR_PERIOD  (ASCV_MSGIN_BEG+3)
 679#define ASCV_MSGIN_SDTR_OFFSET  (ASCV_MSGIN_BEG+4)
 680#define ASCV_SDTR_DATA_BEG      (ASCV_MSGIN_BEG+8)
 681#define ASCV_SDTR_DONE_BEG      (ASCV_SDTR_DATA_BEG+8)
 682#define ASCV_MAX_DVC_QNG_BEG    (ushort)0x0020
 683#define ASCV_BREAK_ADDR           (ushort)0x0028
 684#define ASCV_BREAK_NOTIFY_COUNT   (ushort)0x002A
 685#define ASCV_BREAK_CONTROL        (ushort)0x002C
 686#define ASCV_BREAK_HIT_COUNT      (ushort)0x002E
 687
 688#define ASCV_ASCDVC_ERR_CODE_W  (ushort)0x0030
 689#define ASCV_MCODE_CHKSUM_W   (ushort)0x0032
 690#define ASCV_MCODE_SIZE_W     (ushort)0x0034
 691#define ASCV_STOP_CODE_B      (ushort)0x0036
 692#define ASCV_DVC_ERR_CODE_B   (ushort)0x0037
 693#define ASCV_OVERRUN_PADDR_D  (ushort)0x0038
 694#define ASCV_OVERRUN_BSIZE_D  (ushort)0x003C
 695#define ASCV_HALTCODE_W       (ushort)0x0040
 696#define ASCV_CHKSUM_W         (ushort)0x0042
 697#define ASCV_MC_DATE_W        (ushort)0x0044
 698#define ASCV_MC_VER_W         (ushort)0x0046
 699#define ASCV_NEXTRDY_B        (ushort)0x0048
 700#define ASCV_DONENEXT_B       (ushort)0x0049
 701#define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
 702#define ASCV_SCSIBUSY_B       (ushort)0x004B
 703#define ASCV_Q_DONE_IN_PROGRESS_B  (ushort)0x004C
 704#define ASCV_CURCDB_B         (ushort)0x004D
 705#define ASCV_RCLUN_B          (ushort)0x004E
 706#define ASCV_BUSY_QHEAD_B     (ushort)0x004F
 707#define ASCV_DISC1_QHEAD_B    (ushort)0x0050
 708#define ASCV_DISC_ENABLE_B    (ushort)0x0052
 709#define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
 710#define ASCV_HOSTSCSI_ID_B    (ushort)0x0055
 711#define ASCV_MCODE_CNTL_B     (ushort)0x0056
 712#define ASCV_NULL_TARGET_B    (ushort)0x0057
 713#define ASCV_FREE_Q_HEAD_W    (ushort)0x0058
 714#define ASCV_DONE_Q_TAIL_W    (ushort)0x005A
 715#define ASCV_FREE_Q_HEAD_B    (ushort)(ASCV_FREE_Q_HEAD_W+1)
 716#define ASCV_DONE_Q_TAIL_B    (ushort)(ASCV_DONE_Q_TAIL_W+1)
 717#define ASCV_HOST_FLAG_B      (ushort)0x005D
 718#define ASCV_TOTAL_READY_Q_B  (ushort)0x0064
 719#define ASCV_VER_SERIAL_B     (ushort)0x0065
 720#define ASCV_HALTCODE_SAVED_W (ushort)0x0066
 721#define ASCV_WTM_FLAG_B       (ushort)0x0068
 722#define ASCV_RISC_FLAG_B      (ushort)0x006A
 723#define ASCV_REQ_SG_LIST_QP   (ushort)0x006B
 724#define ASC_HOST_FLAG_IN_ISR        0x01
 725#define ASC_HOST_FLAG_ACK_INT       0x02
 726#define ASC_RISC_FLAG_GEN_INT      0x01
 727#define ASC_RISC_FLAG_REQ_SG_LIST  0x02
 728#define IOP_CTRL         (0x0F)
 729#define IOP_STATUS       (0x0E)
 730#define IOP_INT_ACK      IOP_STATUS
 731#define IOP_REG_IFC      (0x0D)
 732#define IOP_SYN_OFFSET    (0x0B)
 733#define IOP_EXTRA_CONTROL (0x0D)
 734#define IOP_REG_PC        (0x0C)
 735#define IOP_RAM_ADDR      (0x0A)
 736#define IOP_RAM_DATA      (0x08)
 737#define IOP_EEP_DATA      (0x06)
 738#define IOP_EEP_CMD       (0x07)
 739#define IOP_VERSION       (0x03)
 740#define IOP_CONFIG_HIGH   (0x04)
 741#define IOP_CONFIG_LOW    (0x02)
 742#define IOP_SIG_BYTE      (0x01)
 743#define IOP_SIG_WORD      (0x00)
 744#define IOP_REG_DC1      (0x0E)
 745#define IOP_REG_DC0      (0x0C)
 746#define IOP_REG_SB       (0x0B)
 747#define IOP_REG_DA1      (0x0A)
 748#define IOP_REG_DA0      (0x08)
 749#define IOP_REG_SC       (0x09)
 750#define IOP_DMA_SPEED    (0x07)
 751#define IOP_REG_FLAG     (0x07)
 752#define IOP_FIFO_H       (0x06)
 753#define IOP_FIFO_L       (0x04)
 754#define IOP_REG_ID       (0x05)
 755#define IOP_REG_QP       (0x03)
 756#define IOP_REG_IH       (0x02)
 757#define IOP_REG_IX       (0x01)
 758#define IOP_REG_AX       (0x00)
 759#define IFC_REG_LOCK      (0x00)
 760#define IFC_REG_UNLOCK    (0x09)
 761#define IFC_WR_EN_FILTER  (0x10)
 762#define IFC_RD_NO_EEPROM  (0x10)
 763#define IFC_SLEW_RATE     (0x20)
 764#define IFC_ACT_NEG       (0x40)
 765#define IFC_INP_FILTER    (0x80)
 766#define IFC_INIT_DEFAULT  (IFC_ACT_NEG | IFC_REG_UNLOCK)
 767#define SC_SEL   (uchar)(0x80)
 768#define SC_BSY   (uchar)(0x40)
 769#define SC_ACK   (uchar)(0x20)
 770#define SC_REQ   (uchar)(0x10)
 771#define SC_ATN   (uchar)(0x08)
 772#define SC_IO    (uchar)(0x04)
 773#define SC_CD    (uchar)(0x02)
 774#define SC_MSG   (uchar)(0x01)
 775#define SEC_SCSI_CTL         (uchar)(0x80)
 776#define SEC_ACTIVE_NEGATE    (uchar)(0x40)
 777#define SEC_SLEW_RATE        (uchar)(0x20)
 778#define SEC_ENABLE_FILTER    (uchar)(0x10)
 779#define ASC_HALT_EXTMSG_IN     (ushort)0x8000
 780#define ASC_HALT_CHK_CONDITION (ushort)0x8100
 781#define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
 782#define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX  (ushort)0x8300
 783#define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX   (ushort)0x8400
 784#define ASC_HALT_SDTR_REJECTED (ushort)0x4000
 785#define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
 786#define ASC_MAX_QNO        0xF8
 787#define ASC_DATA_SEC_BEG   (ushort)0x0080
 788#define ASC_DATA_SEC_END   (ushort)0x0080
 789#define ASC_CODE_SEC_BEG   (ushort)0x0080
 790#define ASC_CODE_SEC_END   (ushort)0x0080
 791#define ASC_QADR_BEG       (0x4000)
 792#define ASC_QADR_USED      (ushort)(ASC_MAX_QNO * 64)
 793#define ASC_QADR_END       (ushort)0x7FFF
 794#define ASC_QLAST_ADR      (ushort)0x7FC0
 795#define ASC_QBLK_SIZE      0x40
 796#define ASC_BIOS_DATA_QBEG 0xF8
 797#define ASC_MIN_ACTIVE_QNO 0x01
 798#define ASC_QLINK_END      0xFF
 799#define ASC_EEPROM_WORDS   0x10
 800#define ASC_MAX_MGS_LEN    0x10
 801#define ASC_BIOS_ADDR_DEF  0xDC00
 802#define ASC_BIOS_SIZE      0x3800
 803#define ASC_BIOS_RAM_OFF   0x3800
 804#define ASC_BIOS_RAM_SIZE  0x800
 805#define ASC_BIOS_MIN_ADDR  0xC000
 806#define ASC_BIOS_MAX_ADDR  0xEC00
 807#define ASC_BIOS_BANK_SIZE 0x0400
 808#define ASC_MCODE_START_ADDR  0x0080
 809#define ASC_CFG0_HOST_INT_ON    0x0020
 810#define ASC_CFG0_BIOS_ON        0x0040
 811#define ASC_CFG0_VERA_BURST_ON  0x0080
 812#define ASC_CFG0_SCSI_PARITY_ON 0x0800
 813#define ASC_CFG1_SCSI_TARGET_ON 0x0080
 814#define ASC_CFG1_LRAM_8BITS_ON  0x0800
 815#define ASC_CFG_MSW_CLR_MASK    0x3080
 816#define CSW_TEST1             (ASC_CS_TYPE)0x8000
 817#define CSW_AUTO_CONFIG       (ASC_CS_TYPE)0x4000
 818#define CSW_RESERVED1         (ASC_CS_TYPE)0x2000
 819#define CSW_IRQ_WRITTEN       (ASC_CS_TYPE)0x1000
 820#define CSW_33MHZ_SELECTED    (ASC_CS_TYPE)0x0800
 821#define CSW_TEST2             (ASC_CS_TYPE)0x0400
 822#define CSW_TEST3             (ASC_CS_TYPE)0x0200
 823#define CSW_RESERVED2         (ASC_CS_TYPE)0x0100
 824#define CSW_DMA_DONE          (ASC_CS_TYPE)0x0080
 825#define CSW_FIFO_RDY          (ASC_CS_TYPE)0x0040
 826#define CSW_EEP_READ_DONE     (ASC_CS_TYPE)0x0020
 827#define CSW_HALTED            (ASC_CS_TYPE)0x0010
 828#define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
 829#define CSW_PARITY_ERR        (ASC_CS_TYPE)0x0004
 830#define CSW_SCSI_RESET_LATCH  (ASC_CS_TYPE)0x0002
 831#define CSW_INT_PENDING       (ASC_CS_TYPE)0x0001
 832#define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
 833#define CIW_INT_ACK      (ASC_CS_TYPE)0x0100
 834#define CIW_TEST1        (ASC_CS_TYPE)0x0200
 835#define CIW_TEST2        (ASC_CS_TYPE)0x0400
 836#define CIW_SEL_33MHZ    (ASC_CS_TYPE)0x0800
 837#define CIW_IRQ_ACT      (ASC_CS_TYPE)0x1000
 838#define CC_CHIP_RESET   (uchar)0x80
 839#define CC_SCSI_RESET   (uchar)0x40
 840#define CC_HALT         (uchar)0x20
 841#define CC_SINGLE_STEP  (uchar)0x10
 842#define CC_DMA_ABLE     (uchar)0x08
 843#define CC_TEST         (uchar)0x04
 844#define CC_BANK_ONE     (uchar)0x02
 845#define CC_DIAG         (uchar)0x01
 846#define ASC_1000_ID0W      0x04C1
 847#define ASC_1000_ID0W_FIX  0x00C1
 848#define ASC_1000_ID1B      0x25
 849#define ASC_EISA_REV_IOP_MASK  (0x0C83)
 850#define ASC_EISA_CFG_IOP_MASK  (0x0C86)
 851#define ASC_GET_EISA_SLOT(iop)  (PortAddr)((iop) & 0xF000)
 852#define INS_HALTINT        (ushort)0x6281
 853#define INS_HALT           (ushort)0x6280
 854#define INS_SINT           (ushort)0x6200
 855#define INS_RFLAG_WTM      (ushort)0x7380
 856#define ASC_MC_SAVE_CODE_WSIZE  0x500
 857#define ASC_MC_SAVE_DATA_WSIZE  0x40
 858
 859typedef struct asc_mc_saved {
 860        ushort data[ASC_MC_SAVE_DATA_WSIZE];
 861        ushort code[ASC_MC_SAVE_CODE_WSIZE];
 862} ASC_MC_SAVED;
 863
 864#define AscGetQDoneInProgress(port)         AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
 865#define AscPutQDoneInProgress(port, val)    AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
 866#define AscGetVarFreeQHead(port)            AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
 867#define AscGetVarDoneQTail(port)            AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
 868#define AscPutVarFreeQHead(port, val)       AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
 869#define AscPutVarDoneQTail(port, val)       AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
 870#define AscGetRiscVarFreeQHead(port)        AscReadLramByte((port), ASCV_NEXTRDY_B)
 871#define AscGetRiscVarDoneQTail(port)        AscReadLramByte((port), ASCV_DONENEXT_B)
 872#define AscPutRiscVarFreeQHead(port, val)   AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
 873#define AscPutRiscVarDoneQTail(port, val)   AscWriteLramByte((port), ASCV_DONENEXT_B, val)
 874#define AscPutMCodeSDTRDoneAtID(port, id, data)  AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
 875#define AscGetMCodeSDTRDoneAtID(port, id)        AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
 876#define AscPutMCodeInitSDTRAtID(port, id, data)  AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
 877#define AscGetMCodeInitSDTRAtID(port, id)        AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
 878#define AscGetChipSignatureByte(port)     (uchar)inp((port)+IOP_SIG_BYTE)
 879#define AscGetChipSignatureWord(port)     (ushort)inpw((port)+IOP_SIG_WORD)
 880#define AscGetChipVerNo(port)             (uchar)inp((port)+IOP_VERSION)
 881#define AscGetChipCfgLsw(port)            (ushort)inpw((port)+IOP_CONFIG_LOW)
 882#define AscGetChipCfgMsw(port)            (ushort)inpw((port)+IOP_CONFIG_HIGH)
 883#define AscSetChipCfgLsw(port, data)      outpw((port)+IOP_CONFIG_LOW, data)
 884#define AscSetChipCfgMsw(port, data)      outpw((port)+IOP_CONFIG_HIGH, data)
 885#define AscGetChipEEPCmd(port)            (uchar)inp((port)+IOP_EEP_CMD)
 886#define AscSetChipEEPCmd(port, data)      outp((port)+IOP_EEP_CMD, data)
 887#define AscGetChipEEPData(port)           (ushort)inpw((port)+IOP_EEP_DATA)
 888#define AscSetChipEEPData(port, data)     outpw((port)+IOP_EEP_DATA, data)
 889#define AscGetChipLramAddr(port)          (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
 890#define AscSetChipLramAddr(port, addr)    outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
 891#define AscGetChipLramData(port)          (ushort)inpw((port)+IOP_RAM_DATA)
 892#define AscSetChipLramData(port, data)    outpw((port)+IOP_RAM_DATA, data)
 893#define AscGetChipIFC(port)               (uchar)inp((port)+IOP_REG_IFC)
 894#define AscSetChipIFC(port, data)          outp((port)+IOP_REG_IFC, data)
 895#define AscGetChipStatus(port)            (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
 896#define AscSetChipStatus(port, cs_val)    outpw((port)+IOP_STATUS, cs_val)
 897#define AscGetChipControl(port)           (uchar)inp((port)+IOP_CTRL)
 898#define AscSetChipControl(port, cc_val)   outp((port)+IOP_CTRL, cc_val)
 899#define AscGetChipSyn(port)               (uchar)inp((port)+IOP_SYN_OFFSET)
 900#define AscSetChipSyn(port, data)         outp((port)+IOP_SYN_OFFSET, data)
 901#define AscSetPCAddr(port, data)          outpw((port)+IOP_REG_PC, data)
 902#define AscGetPCAddr(port)                (ushort)inpw((port)+IOP_REG_PC)
 903#define AscIsIntPending(port)             (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
 904#define AscGetChipScsiID(port)            ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
 905#define AscGetExtraControl(port)          (uchar)inp((port)+IOP_EXTRA_CONTROL)
 906#define AscSetExtraControl(port, data)    outp((port)+IOP_EXTRA_CONTROL, data)
 907#define AscReadChipAX(port)               (ushort)inpw((port)+IOP_REG_AX)
 908#define AscWriteChipAX(port, data)        outpw((port)+IOP_REG_AX, data)
 909#define AscReadChipIX(port)               (uchar)inp((port)+IOP_REG_IX)
 910#define AscWriteChipIX(port, data)        outp((port)+IOP_REG_IX, data)
 911#define AscReadChipIH(port)               (ushort)inpw((port)+IOP_REG_IH)
 912#define AscWriteChipIH(port, data)        outpw((port)+IOP_REG_IH, data)
 913#define AscReadChipQP(port)               (uchar)inp((port)+IOP_REG_QP)
 914#define AscWriteChipQP(port, data)        outp((port)+IOP_REG_QP, data)
 915#define AscReadChipFIFO_L(port)           (ushort)inpw((port)+IOP_REG_FIFO_L)
 916#define AscWriteChipFIFO_L(port, data)    outpw((port)+IOP_REG_FIFO_L, data)
 917#define AscReadChipFIFO_H(port)           (ushort)inpw((port)+IOP_REG_FIFO_H)
 918#define AscWriteChipFIFO_H(port, data)    outpw((port)+IOP_REG_FIFO_H, data)
 919#define AscReadChipDmaSpeed(port)         (uchar)inp((port)+IOP_DMA_SPEED)
 920#define AscWriteChipDmaSpeed(port, data)  outp((port)+IOP_DMA_SPEED, data)
 921#define AscReadChipDA0(port)              (ushort)inpw((port)+IOP_REG_DA0)
 922#define AscWriteChipDA0(port)             outpw((port)+IOP_REG_DA0, data)
 923#define AscReadChipDA1(port)              (ushort)inpw((port)+IOP_REG_DA1)
 924#define AscWriteChipDA1(port)             outpw((port)+IOP_REG_DA1, data)
 925#define AscReadChipDC0(port)              (ushort)inpw((port)+IOP_REG_DC0)
 926#define AscWriteChipDC0(port)             outpw((port)+IOP_REG_DC0, data)
 927#define AscReadChipDC1(port)              (ushort)inpw((port)+IOP_REG_DC1)
 928#define AscWriteChipDC1(port)             outpw((port)+IOP_REG_DC1, data)
 929#define AscReadChipDvcID(port)            (uchar)inp((port)+IOP_REG_ID)
 930#define AscWriteChipDvcID(port, data)     outp((port)+IOP_REG_ID, data)
 931
 932/*
 933 * Portable Data Types
 934 *
 935 * Any instance where a 32-bit long or pointer type is assumed
 936 * for precision or HW defined structures, the following define
 937 * types must be used. In Linux the char, short, and int types
 938 * are all consistent at 8, 16, and 32 bits respectively. Pointers
 939 * and long types are 64 bits on Alpha and UltraSPARC.
 940 */
 941#define ADV_PADDR __u32         /* Physical address data type. */
 942#define ADV_VADDR __u32         /* Virtual address data type. */
 943#define ADV_DCNT  __u32         /* Unsigned Data count type. */
 944#define ADV_SDCNT __s32         /* Signed Data count type. */
 945
 946/*
 947 * These macros are used to convert a virtual address to a
 948 * 32-bit value. This currently can be used on Linux Alpha
 949 * which uses 64-bit virtual address but a 32-bit bus address.
 950 * This is likely to break in the future, but doing this now
 951 * will give us time to change the HW and FW to handle 64-bit
 952 * addresses.
 953 */
 954#define ADV_VADDR_TO_U32   virt_to_bus
 955#define ADV_U32_TO_VADDR   bus_to_virt
 956
 957#define AdvPortAddr  void __iomem *     /* Virtual memory address size */
 958
 959/*
 960 * Define Adv Library required memory access macros.
 961 */
 962#define ADV_MEM_READB(addr) readb(addr)
 963#define ADV_MEM_READW(addr) readw(addr)
 964#define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
 965#define ADV_MEM_WRITEW(addr, word) writew(word, addr)
 966#define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
 967
 968#define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
 969
 970/*
 971 * Define total number of simultaneous maximum element scatter-gather
 972 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
 973 * maximum number of outstanding commands per wide host adapter. Each
 974 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
 975 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
 976 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
 977 * structures or 255 scatter-gather elements.
 978 */
 979#define ADV_TOT_SG_BLOCK        ASC_DEF_MAX_HOST_QNG
 980
 981/*
 982 * Define maximum number of scatter-gather elements per request.
 983 */
 984#define ADV_MAX_SG_LIST         255
 985#define NO_OF_SG_PER_BLOCK              15
 986
 987#define ADV_EEP_DVC_CFG_BEGIN           (0x00)
 988#define ADV_EEP_DVC_CFG_END             (0x15)
 989#define ADV_EEP_DVC_CTL_BEGIN           (0x16)  /* location of OEM name */
 990#define ADV_EEP_MAX_WORD_ADDR           (0x1E)
 991
 992#define ADV_EEP_DELAY_MS                100
 993
 994#define ADV_EEPROM_BIG_ENDIAN          0x8000   /* EEPROM Bit 15 */
 995#define ADV_EEPROM_BIOS_ENABLE         0x4000   /* EEPROM Bit 14 */
 996/*
 997 * For the ASC3550 Bit 13 is Termination Polarity control bit.
 998 * For later ICs Bit 13 controls whether the CIS (Card Information
 999 * Service Section) is loaded from EEPROM.
1000 */
1001#define ADV_EEPROM_TERM_POL            0x2000   /* EEPROM Bit 13 */
1002#define ADV_EEPROM_CIS_LD              0x2000   /* EEPROM Bit 13 */
1003/*
1004 * ASC38C1600 Bit 11
1005 *
1006 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
1007 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
1008 * Function 0 will specify INT B.
1009 *
1010 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
1011 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
1012 * Function 1 will specify INT A.
1013 */
1014#define ADV_EEPROM_INTAB               0x0800   /* EEPROM Bit 11 */
1015
1016typedef struct adveep_3550_config {
1017        /* Word Offset, Description */
1018
1019        ushort cfg_lsw;         /* 00 power up initialization */
1020        /*  bit 13 set - Term Polarity Control */
1021        /*  bit 14 set - BIOS Enable */
1022        /*  bit 15 set - Big Endian Mode */
1023        ushort cfg_msw;         /* 01 unused      */
1024        ushort disc_enable;     /* 02 disconnect enable */
1025        ushort wdtr_able;       /* 03 Wide DTR able */
1026        ushort sdtr_able;       /* 04 Synchronous DTR able */
1027        ushort start_motor;     /* 05 send start up motor */
1028        ushort tagqng_able;     /* 06 tag queuing able */
1029        ushort bios_scan;       /* 07 BIOS device control */
1030        ushort scam_tolerant;   /* 08 no scam */
1031
1032        uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1033        uchar bios_boot_delay;  /*    power up wait */
1034
1035        uchar scsi_reset_delay; /* 10 reset delay */
1036        uchar bios_id_lun;      /*    first boot device scsi id & lun */
1037        /*    high nibble is lun */
1038        /*    low nibble is scsi id */
1039
1040        uchar termination;      /* 11 0 - automatic */
1041        /*    1 - low off / high off */
1042        /*    2 - low off / high on */
1043        /*    3 - low on  / high on */
1044        /*    There is no low on  / high off */
1045
1046        uchar reserved1;        /*    reserved byte (not used) */
1047
1048        ushort bios_ctrl;       /* 12 BIOS control bits */
1049        /*  bit 0  BIOS don't act as initiator. */
1050        /*  bit 1  BIOS > 1 GB support */
1051        /*  bit 2  BIOS > 2 Disk Support */
1052        /*  bit 3  BIOS don't support removables */
1053        /*  bit 4  BIOS support bootable CD */
1054        /*  bit 5  BIOS scan enabled */
1055        /*  bit 6  BIOS support multiple LUNs */
1056        /*  bit 7  BIOS display of message */
1057        /*  bit 8  SCAM disabled */
1058        /*  bit 9  Reset SCSI bus during init. */
1059        /*  bit 10 */
1060        /*  bit 11 No verbose initialization. */
1061        /*  bit 12 SCSI parity enabled */
1062        /*  bit 13 */
1063        /*  bit 14 */
1064        /*  bit 15 */
1065        ushort ultra_able;      /* 13 ULTRA speed able */
1066        ushort reserved2;       /* 14 reserved */
1067        uchar max_host_qng;     /* 15 maximum host queuing */
1068        uchar max_dvc_qng;      /*    maximum per device queuing */
1069        ushort dvc_cntl;        /* 16 control bit for driver */
1070        ushort bug_fix;         /* 17 control bit for bug fix */
1071        ushort serial_number_word1;     /* 18 Board serial number word 1 */
1072        ushort serial_number_word2;     /* 19 Board serial number word 2 */
1073        ushort serial_number_word3;     /* 20 Board serial number word 3 */
1074        ushort check_sum;       /* 21 EEP check sum */
1075        uchar oem_name[16];     /* 22 OEM name */
1076        ushort dvc_err_code;    /* 30 last device driver error code */
1077        ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1078        ushort adv_err_addr;    /* 32 last uc error address */
1079        ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1080        ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1081        ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1082        ushort num_of_err;      /* 36 number of error */
1083} ADVEEP_3550_CONFIG;
1084
1085typedef struct adveep_38C0800_config {
1086        /* Word Offset, Description */
1087
1088        ushort cfg_lsw;         /* 00 power up initialization */
1089        /*  bit 13 set - Load CIS */
1090        /*  bit 14 set - BIOS Enable */
1091        /*  bit 15 set - Big Endian Mode */
1092        ushort cfg_msw;         /* 01 unused      */
1093        ushort disc_enable;     /* 02 disconnect enable */
1094        ushort wdtr_able;       /* 03 Wide DTR able */
1095        ushort sdtr_speed1;     /* 04 SDTR Speed TID 0-3 */
1096        ushort start_motor;     /* 05 send start up motor */
1097        ushort tagqng_able;     /* 06 tag queuing able */
1098        ushort bios_scan;       /* 07 BIOS device control */
1099        ushort scam_tolerant;   /* 08 no scam */
1100
1101        uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1102        uchar bios_boot_delay;  /*    power up wait */
1103
1104        uchar scsi_reset_delay; /* 10 reset delay */
1105        uchar bios_id_lun;      /*    first boot device scsi id & lun */
1106        /*    high nibble is lun */
1107        /*    low nibble is scsi id */
1108
1109        uchar termination_se;   /* 11 0 - automatic */
1110        /*    1 - low off / high off */
1111        /*    2 - low off / high on */
1112        /*    3 - low on  / high on */
1113        /*    There is no low on  / high off */
1114
1115        uchar termination_lvd;  /* 11 0 - automatic */
1116        /*    1 - low off / high off */
1117        /*    2 - low off / high on */
1118        /*    3 - low on  / high on */
1119        /*    There is no low on  / high off */
1120
1121        ushort bios_ctrl;       /* 12 BIOS control bits */
1122        /*  bit 0  BIOS don't act as initiator. */
1123        /*  bit 1  BIOS > 1 GB support */
1124        /*  bit 2  BIOS > 2 Disk Support */
1125        /*  bit 3  BIOS don't support removables */
1126        /*  bit 4  BIOS support bootable CD */
1127        /*  bit 5  BIOS scan enabled */
1128        /*  bit 6  BIOS support multiple LUNs */
1129        /*  bit 7  BIOS display of message */
1130        /*  bit 8  SCAM disabled */
1131        /*  bit 9  Reset SCSI bus during init. */
1132        /*  bit 10 */
1133        /*  bit 11 No verbose initialization. */
1134        /*  bit 12 SCSI parity enabled */
1135        /*  bit 13 */
1136        /*  bit 14 */
1137        /*  bit 15 */
1138        ushort sdtr_speed2;     /* 13 SDTR speed TID 4-7 */
1139        ushort sdtr_speed3;     /* 14 SDTR speed TID 8-11 */
1140        uchar max_host_qng;     /* 15 maximum host queueing */
1141        uchar max_dvc_qng;      /*    maximum per device queuing */
1142        ushort dvc_cntl;        /* 16 control bit for driver */
1143        ushort sdtr_speed4;     /* 17 SDTR speed 4 TID 12-15 */
1144        ushort serial_number_word1;     /* 18 Board serial number word 1 */
1145        ushort serial_number_word2;     /* 19 Board serial number word 2 */
1146        ushort serial_number_word3;     /* 20 Board serial number word 3 */
1147        ushort check_sum;       /* 21 EEP check sum */
1148        uchar oem_name[16];     /* 22 OEM name */
1149        ushort dvc_err_code;    /* 30 last device driver error code */
1150        ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1151        ushort adv_err_addr;    /* 32 last uc error address */
1152        ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1153        ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1154        ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1155        ushort reserved36;      /* 36 reserved */
1156        ushort reserved37;      /* 37 reserved */
1157        ushort reserved38;      /* 38 reserved */
1158        ushort reserved39;      /* 39 reserved */
1159        ushort reserved40;      /* 40 reserved */
1160        ushort reserved41;      /* 41 reserved */
1161        ushort reserved42;      /* 42 reserved */
1162        ushort reserved43;      /* 43 reserved */
1163        ushort reserved44;      /* 44 reserved */
1164        ushort reserved45;      /* 45 reserved */
1165        ushort reserved46;      /* 46 reserved */
1166        ushort reserved47;      /* 47 reserved */
1167        ushort reserved48;      /* 48 reserved */
1168        ushort reserved49;      /* 49 reserved */
1169        ushort reserved50;      /* 50 reserved */
1170        ushort reserved51;      /* 51 reserved */
1171        ushort reserved52;      /* 52 reserved */
1172        ushort reserved53;      /* 53 reserved */
1173        ushort reserved54;      /* 54 reserved */
1174        ushort reserved55;      /* 55 reserved */
1175        ushort cisptr_lsw;      /* 56 CIS PTR LSW */
1176        ushort cisprt_msw;      /* 57 CIS PTR MSW */
1177        ushort subsysvid;       /* 58 SubSystem Vendor ID */
1178        ushort subsysid;        /* 59 SubSystem ID */
1179        ushort reserved60;      /* 60 reserved */
1180        ushort reserved61;      /* 61 reserved */
1181        ushort reserved62;      /* 62 reserved */
1182        ushort reserved63;      /* 63 reserved */
1183} ADVEEP_38C0800_CONFIG;
1184
1185typedef struct adveep_38C1600_config {
1186        /* Word Offset, Description */
1187
1188        ushort cfg_lsw;         /* 00 power up initialization */
1189        /*  bit 11 set - Func. 0 INTB, Func. 1 INTA */
1190        /*       clear - Func. 0 INTA, Func. 1 INTB */
1191        /*  bit 13 set - Load CIS */
1192        /*  bit 14 set - BIOS Enable */
1193        /*  bit 15 set - Big Endian Mode */
1194        ushort cfg_msw;         /* 01 unused */
1195        ushort disc_enable;     /* 02 disconnect enable */
1196        ushort wdtr_able;       /* 03 Wide DTR able */
1197        ushort sdtr_speed1;     /* 04 SDTR Speed TID 0-3 */
1198        ushort start_motor;     /* 05 send start up motor */
1199        ushort tagqng_able;     /* 06 tag queuing able */
1200        ushort bios_scan;       /* 07 BIOS device control */
1201        ushort scam_tolerant;   /* 08 no scam */
1202
1203        uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1204        uchar bios_boot_delay;  /*    power up wait */
1205
1206        uchar scsi_reset_delay; /* 10 reset delay */
1207        uchar bios_id_lun;      /*    first boot device scsi id & lun */
1208        /*    high nibble is lun */
1209        /*    low nibble is scsi id */
1210
1211        uchar termination_se;   /* 11 0 - automatic */
1212        /*    1 - low off / high off */
1213        /*    2 - low off / high on */
1214        /*    3 - low on  / high on */
1215        /*    There is no low on  / high off */
1216
1217        uchar termination_lvd;  /* 11 0 - automatic */
1218        /*    1 - low off / high off */
1219        /*    2 - low off / high on */
1220        /*    3 - low on  / high on */
1221        /*    There is no low on  / high off */
1222
1223        ushort bios_ctrl;       /* 12 BIOS control bits */
1224        /*  bit 0  BIOS don't act as initiator. */
1225        /*  bit 1  BIOS > 1 GB support */
1226        /*  bit 2  BIOS > 2 Disk Support */
1227        /*  bit 3  BIOS don't support removables */
1228        /*  bit 4  BIOS support bootable CD */
1229        /*  bit 5  BIOS scan enabled */
1230        /*  bit 6  BIOS support multiple LUNs */
1231        /*  bit 7  BIOS display of message */
1232        /*  bit 8  SCAM disabled */
1233        /*  bit 9  Reset SCSI bus during init. */
1234        /*  bit 10 Basic Integrity Checking disabled */
1235        /*  bit 11 No verbose initialization. */
1236        /*  bit 12 SCSI parity enabled */
1237        /*  bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1238        /*  bit 14 */
1239        /*  bit 15 */
1240        ushort sdtr_speed2;     /* 13 SDTR speed TID 4-7 */
1241        ushort sdtr_speed3;     /* 14 SDTR speed TID 8-11 */
1242        uchar max_host_qng;     /* 15 maximum host queueing */
1243        uchar max_dvc_qng;      /*    maximum per device queuing */
1244        ushort dvc_cntl;        /* 16 control bit for driver */
1245        ushort sdtr_speed4;     /* 17 SDTR speed 4 TID 12-15 */
1246        ushort serial_number_word1;     /* 18 Board serial number word 1 */
1247        ushort serial_number_word2;     /* 19 Board serial number word 2 */
1248        ushort serial_number_word3;     /* 20 Board serial number word 3 */
1249        ushort check_sum;       /* 21 EEP check sum */
1250        uchar oem_name[16];     /* 22 OEM name */
1251        ushort dvc_err_code;    /* 30 last device driver error code */
1252        ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1253        ushort adv_err_addr;    /* 32 last uc error address */
1254        ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1255        ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1256        ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1257        ushort reserved36;      /* 36 reserved */
1258        ushort reserved37;      /* 37 reserved */
1259        ushort reserved38;      /* 38 reserved */
1260        ushort reserved39;      /* 39 reserved */
1261        ushort reserved40;      /* 40 reserved */
1262        ushort reserved41;      /* 41 reserved */
1263        ushort reserved42;      /* 42 reserved */
1264        ushort reserved43;      /* 43 reserved */
1265        ushort reserved44;      /* 44 reserved */
1266        ushort reserved45;      /* 45 reserved */
1267        ushort reserved46;      /* 46 reserved */
1268        ushort reserved47;      /* 47 reserved */
1269        ushort reserved48;      /* 48 reserved */
1270        ushort reserved49;      /* 49 reserved */
1271        ushort reserved50;      /* 50 reserved */
1272        ushort reserved51;      /* 51 reserved */
1273        ushort reserved52;      /* 52 reserved */
1274        ushort reserved53;      /* 53 reserved */
1275        ushort reserved54;      /* 54 reserved */
1276        ushort reserved55;      /* 55 reserved */
1277        ushort cisptr_lsw;      /* 56 CIS PTR LSW */
1278        ushort cisprt_msw;      /* 57 CIS PTR MSW */
1279        ushort subsysvid;       /* 58 SubSystem Vendor ID */
1280        ushort subsysid;        /* 59 SubSystem ID */
1281        ushort reserved60;      /* 60 reserved */
1282        ushort reserved61;      /* 61 reserved */
1283        ushort reserved62;      /* 62 reserved */
1284        ushort reserved63;      /* 63 reserved */
1285} ADVEEP_38C1600_CONFIG;
1286
1287/*
1288 * EEPROM Commands
1289 */
1290#define ASC_EEP_CMD_DONE             0x0200
1291
1292/* bios_ctrl */
1293#define BIOS_CTRL_BIOS               0x0001
1294#define BIOS_CTRL_EXTENDED_XLAT      0x0002
1295#define BIOS_CTRL_GT_2_DISK          0x0004
1296#define BIOS_CTRL_BIOS_REMOVABLE     0x0008
1297#define BIOS_CTRL_BOOTABLE_CD        0x0010
1298#define BIOS_CTRL_MULTIPLE_LUN       0x0040
1299#define BIOS_CTRL_DISPLAY_MSG        0x0080
1300#define BIOS_CTRL_NO_SCAM            0x0100
1301#define BIOS_CTRL_RESET_SCSI_BUS     0x0200
1302#define BIOS_CTRL_INIT_VERBOSE       0x0800
1303#define BIOS_CTRL_SCSI_PARITY        0x1000
1304#define BIOS_CTRL_AIPP_DIS           0x2000
1305
1306#define ADV_3550_MEMSIZE   0x2000       /* 8 KB Internal Memory */
1307
1308#define ADV_38C0800_MEMSIZE  0x4000     /* 16 KB Internal Memory */
1309
1310/*
1311 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1312 * a special 16K Adv Library and Microcode version. After the issue is
1313 * resolved, should restore 32K support.
1314 *
1315 * #define ADV_38C1600_MEMSIZE  0x8000L   * 32 KB Internal Memory *
1316 */
1317#define ADV_38C1600_MEMSIZE  0x4000     /* 16 KB Internal Memory */
1318
1319/*
1320 * Byte I/O register address from base of 'iop_base'.
1321 */
1322#define IOPB_INTR_STATUS_REG    0x00
1323#define IOPB_CHIP_ID_1          0x01
1324#define IOPB_INTR_ENABLES       0x02
1325#define IOPB_CHIP_TYPE_REV      0x03
1326#define IOPB_RES_ADDR_4         0x04
1327#define IOPB_RES_ADDR_5         0x05
1328#define IOPB_RAM_DATA           0x06
1329#define IOPB_RES_ADDR_7         0x07
1330#define IOPB_FLAG_REG           0x08
1331#define IOPB_RES_ADDR_9         0x09
1332#define IOPB_RISC_CSR           0x0A
1333#define IOPB_RES_ADDR_B         0x0B
1334#define IOPB_RES_ADDR_C         0x0C
1335#define IOPB_RES_ADDR_D         0x0D
1336#define IOPB_SOFT_OVER_WR       0x0E
1337#define IOPB_RES_ADDR_F         0x0F
1338#define IOPB_MEM_CFG            0x10
1339#define IOPB_RES_ADDR_11        0x11
1340#define IOPB_GPIO_DATA          0x12
1341#define IOPB_RES_ADDR_13        0x13
1342#define IOPB_FLASH_PAGE         0x14
1343#define IOPB_RES_ADDR_15        0x15
1344#define IOPB_GPIO_CNTL          0x16
1345#define IOPB_RES_ADDR_17        0x17
1346#define IOPB_FLASH_DATA         0x18
1347#define IOPB_RES_ADDR_19        0x19
1348#define IOPB_RES_ADDR_1A        0x1A
1349#define IOPB_RES_ADDR_1B        0x1B
1350#define IOPB_RES_ADDR_1C        0x1C
1351#define IOPB_RES_ADDR_1D        0x1D
1352#define IOPB_RES_ADDR_1E        0x1E
1353#define IOPB_RES_ADDR_1F        0x1F
1354#define IOPB_DMA_CFG0           0x20
1355#define IOPB_DMA_CFG1           0x21
1356#define IOPB_TICKLE             0x22
1357#define IOPB_DMA_REG_WR         0x23
1358#define IOPB_SDMA_STATUS        0x24
1359#define IOPB_SCSI_BYTE_CNT      0x25
1360#define IOPB_HOST_BYTE_CNT      0x26
1361#define IOPB_BYTE_LEFT_TO_XFER  0x27
1362#define IOPB_BYTE_TO_XFER_0     0x28
1363#define IOPB_BYTE_TO_XFER_1     0x29
1364#define IOPB_BYTE_TO_XFER_2     0x2A
1365#define IOPB_BYTE_TO_XFER_3     0x2B
1366#define IOPB_ACC_GRP            0x2C
1367#define IOPB_RES_ADDR_2D        0x2D
1368#define IOPB_DEV_ID             0x2E
1369#define IOPB_RES_ADDR_2F        0x2F
1370#define IOPB_SCSI_DATA          0x30
1371#define IOPB_RES_ADDR_31        0x31
1372#define IOPB_RES_ADDR_32        0x32
1373#define IOPB_SCSI_DATA_HSHK     0x33
1374#define IOPB_SCSI_CTRL          0x34
1375#define IOPB_RES_ADDR_35        0x35
1376#define IOPB_RES_ADDR_36        0x36
1377#define IOPB_RES_ADDR_37        0x37
1378#define IOPB_RAM_BIST           0x38
1379#define IOPB_PLL_TEST           0x39
1380#define IOPB_PCI_INT_CFG        0x3A
1381#define IOPB_RES_ADDR_3B        0x3B
1382#define IOPB_RFIFO_CNT          0x3C
1383#define IOPB_RES_ADDR_3D        0x3D
1384#define IOPB_RES_ADDR_3E        0x3E
1385#define IOPB_RES_ADDR_3F        0x3F
1386
1387/*
1388 * Word I/O register address from base of 'iop_base'.
1389 */
1390#define IOPW_CHIP_ID_0          0x00    /* CID0  */
1391#define IOPW_CTRL_REG           0x02    /* CC    */
1392#define IOPW_RAM_ADDR           0x04    /* LA    */
1393#define IOPW_RAM_DATA           0x06    /* LD    */
1394#define IOPW_RES_ADDR_08        0x08
1395#define IOPW_RISC_CSR           0x0A    /* CSR   */
1396#define IOPW_SCSI_CFG0          0x0C    /* CFG0  */
1397#define IOPW_SCSI_CFG1          0x0E    /* CFG1  */
1398#define IOPW_RES_ADDR_10        0x10
1399#define IOPW_SEL_MASK           0x12    /* SM    */
1400#define IOPW_RES_ADDR_14        0x14
1401#define IOPW_FLASH_ADDR         0x16    /* FA    */
1402#define IOPW_RES_ADDR_18        0x18
1403#define IOPW_EE_CMD             0x1A    /* EC    */
1404#define IOPW_EE_DATA            0x1C    /* ED    */
1405#define IOPW_SFIFO_CNT          0x1E    /* SFC   */
1406#define IOPW_RES_ADDR_20        0x20
1407#define IOPW_Q_BASE             0x22    /* QB    */
1408#define IOPW_QP                 0x24    /* QP    */
1409#define IOPW_IX                 0x26    /* IX    */
1410#define IOPW_SP                 0x28    /* SP    */
1411#define IOPW_PC                 0x2A    /* PC    */
1412#define IOPW_RES_ADDR_2C        0x2C
1413#define IOPW_RES_ADDR_2E        0x2E
1414#define IOPW_SCSI_DATA          0x30    /* SD    */
1415#define IOPW_SCSI_DATA_HSHK     0x32    /* SDH   */
1416#define IOPW_SCSI_CTRL          0x34    /* SC    */
1417#define IOPW_HSHK_CFG           0x36    /* HCFG  */
1418#define IOPW_SXFR_STATUS        0x36    /* SXS   */
1419#define IOPW_SXFR_CNTL          0x38    /* SXL   */
1420#define IOPW_SXFR_CNTH          0x3A    /* SXH   */
1421#define IOPW_RES_ADDR_3C        0x3C
1422#define IOPW_RFIFO_DATA         0x3E    /* RFD   */
1423
1424/*
1425 * Doubleword I/O register address from base of 'iop_base'.
1426 */
1427#define IOPDW_RES_ADDR_0         0x00
1428#define IOPDW_RAM_DATA           0x04
1429#define IOPDW_RES_ADDR_8         0x08
1430#define IOPDW_RES_ADDR_C         0x0C
1431#define IOPDW_RES_ADDR_10        0x10
1432#define IOPDW_COMMA              0x14
1433#define IOPDW_COMMB              0x18
1434#define IOPDW_RES_ADDR_1C        0x1C
1435#define IOPDW_SDMA_ADDR0         0x20
1436#define IOPDW_SDMA_ADDR1         0x24
1437#define IOPDW_SDMA_COUNT         0x28
1438#define IOPDW_SDMA_ERROR         0x2C
1439#define IOPDW_RDMA_ADDR0         0x30
1440#define IOPDW_RDMA_ADDR1         0x34
1441#define IOPDW_RDMA_COUNT         0x38
1442#define IOPDW_RDMA_ERROR         0x3C
1443
1444#define ADV_CHIP_ID_BYTE         0x25
1445#define ADV_CHIP_ID_WORD         0x04C1
1446
1447#define ADV_INTR_ENABLE_HOST_INTR                   0x01
1448#define ADV_INTR_ENABLE_SEL_INTR                    0x02
1449#define ADV_INTR_ENABLE_DPR_INTR                    0x04
1450#define ADV_INTR_ENABLE_RTA_INTR                    0x08
1451#define ADV_INTR_ENABLE_RMA_INTR                    0x10
1452#define ADV_INTR_ENABLE_RST_INTR                    0x20
1453#define ADV_INTR_ENABLE_DPE_INTR                    0x40
1454#define ADV_INTR_ENABLE_GLOBAL_INTR                 0x80
1455
1456#define ADV_INTR_STATUS_INTRA            0x01
1457#define ADV_INTR_STATUS_INTRB            0x02
1458#define ADV_INTR_STATUS_INTRC            0x04
1459
1460#define ADV_RISC_CSR_STOP           (0x0000)
1461#define ADV_RISC_TEST_COND          (0x2000)
1462#define ADV_RISC_CSR_RUN            (0x4000)
1463#define ADV_RISC_CSR_SINGLE_STEP    (0x8000)
1464
1465#define ADV_CTRL_REG_HOST_INTR      0x0100
1466#define ADV_CTRL_REG_SEL_INTR       0x0200
1467#define ADV_CTRL_REG_DPR_INTR       0x0400
1468#define ADV_CTRL_REG_RTA_INTR       0x0800
1469#define ADV_CTRL_REG_RMA_INTR       0x1000
1470#define ADV_CTRL_REG_RES_BIT14      0x2000
1471#define ADV_CTRL_REG_DPE_INTR       0x4000
1472#define ADV_CTRL_REG_POWER_DONE     0x8000
1473#define ADV_CTRL_REG_ANY_INTR       0xFF00
1474
1475#define ADV_CTRL_REG_CMD_RESET             0x00C6
1476#define ADV_CTRL_REG_CMD_WR_IO_REG         0x00C5
1477#define ADV_CTRL_REG_CMD_RD_IO_REG         0x00C4
1478#define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE  0x00C3
1479#define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE  0x00C2
1480
1481#define ADV_TICKLE_NOP                      0x00
1482#define ADV_TICKLE_A                        0x01
1483#define ADV_TICKLE_B                        0x02
1484#define ADV_TICKLE_C                        0x03
1485
1486#define AdvIsIntPending(port) \
1487    (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1488
1489/*
1490 * SCSI_CFG0 Register bit definitions
1491 */
1492#define TIMER_MODEAB    0xC000  /* Watchdog, Second, and Select. Timer Ctrl. */
1493#define PARITY_EN       0x2000  /* Enable SCSI Parity Error detection */
1494#define EVEN_PARITY     0x1000  /* Select Even Parity */
1495#define WD_LONG         0x0800  /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1496#define QUEUE_128       0x0400  /* Queue Size, 1: 128 byte, 0: 64 byte */
1497#define PRIM_MODE       0x0100  /* Primitive SCSI mode */
1498#define SCAM_EN         0x0080  /* Enable SCAM selection */
1499#define SEL_TMO_LONG    0x0040  /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1500#define CFRM_ID         0x0020  /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1501#define OUR_ID_EN       0x0010  /* Enable OUR_ID bits */
1502#define OUR_ID          0x000F  /* SCSI ID */
1503
1504/*
1505 * SCSI_CFG1 Register bit definitions
1506 */
1507#define BIG_ENDIAN      0x8000  /* Enable Big Endian Mode MIO:15, EEP:15 */
1508#define TERM_POL        0x2000  /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1509#define SLEW_RATE       0x1000  /* SCSI output buffer slew rate */
1510#define FILTER_SEL      0x0C00  /* Filter Period Selection */
1511#define  FLTR_DISABLE    0x0000 /* Input Filtering Disabled */
1512#define  FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1513#define  FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1514#define ACTIVE_DBL      0x0200  /* Disable Active Negation */
1515#define DIFF_MODE       0x0100  /* SCSI differential Mode (Read-Only) */
1516#define DIFF_SENSE      0x0080  /* 1: No SE cables, 0: SE cable (Read-Only) */
1517#define TERM_CTL_SEL    0x0040  /* Enable TERM_CTL_H and TERM_CTL_L */
1518#define TERM_CTL        0x0030  /* External SCSI Termination Bits */
1519#define  TERM_CTL_H      0x0020 /* Enable External SCSI Upper Termination */
1520#define  TERM_CTL_L      0x0010 /* Enable External SCSI Lower Termination */
1521#define CABLE_DETECT    0x000F  /* External SCSI Cable Connection Status */
1522
1523/*
1524 * Addendum for ASC-38C0800 Chip
1525 *
1526 * The ASC-38C1600 Chip uses the same definitions except that the
1527 * bus mode override bits [12:10] have been moved to byte register
1528 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1529 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1530 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1531 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1532 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1533 */
1534#define DIS_TERM_DRV    0x4000  /* 1: Read c_det[3:0], 0: cannot read */
1535#define HVD_LVD_SE      0x1C00  /* Device Detect Bits */
1536#define  HVD             0x1000 /* HVD Device Detect */
1537#define  LVD             0x0800 /* LVD Device Detect */
1538#define  SE              0x0400 /* SE Device Detect */
1539#define TERM_LVD        0x00C0  /* LVD Termination Bits */
1540#define  TERM_LVD_HI     0x0080 /* Enable LVD Upper Termination */
1541#define  TERM_LVD_LO     0x0040 /* Enable LVD Lower Termination */
1542#define TERM_SE         0x0030  /* SE Termination Bits */
1543#define  TERM_SE_HI      0x0020 /* Enable SE Upper Termination */
1544#define  TERM_SE_LO      0x0010 /* Enable SE Lower Termination */
1545#define C_DET_LVD       0x000C  /* LVD Cable Detect Bits */
1546#define  C_DET3          0x0008 /* Cable Detect for LVD External Wide */
1547#define  C_DET2          0x0004 /* Cable Detect for LVD Internal Wide */
1548#define C_DET_SE        0x0003  /* SE Cable Detect Bits */
1549#define  C_DET1          0x0002 /* Cable Detect for SE Internal Wide */
1550#define  C_DET0          0x0001 /* Cable Detect for SE Internal Narrow */
1551
1552#define CABLE_ILLEGAL_A 0x7
1553    /* x 0 0 0  | on  on | Illegal (all 3 connectors are used) */
1554
1555#define CABLE_ILLEGAL_B 0xB
1556    /* 0 x 0 0  | on  on | Illegal (all 3 connectors are used) */
1557
1558/*
1559 * MEM_CFG Register bit definitions
1560 */
1561#define BIOS_EN         0x40    /* BIOS Enable MIO:14,EEP:14 */
1562#define FAST_EE_CLK     0x20    /* Diagnostic Bit */
1563#define RAM_SZ          0x1C    /* Specify size of RAM to RISC */
1564#define  RAM_SZ_2KB      0x00   /* 2 KB */
1565#define  RAM_SZ_4KB      0x04   /* 4 KB */
1566#define  RAM_SZ_8KB      0x08   /* 8 KB */
1567#define  RAM_SZ_16KB     0x0C   /* 16 KB */
1568#define  RAM_SZ_32KB     0x10   /* 32 KB */
1569#define  RAM_SZ_64KB     0x14   /* 64 KB */
1570
1571/*
1572 * DMA_CFG0 Register bit definitions
1573 *
1574 * This register is only accessible to the host.
1575 */
1576#define BC_THRESH_ENB   0x80    /* PCI DMA Start Conditions */
1577#define FIFO_THRESH     0x70    /* PCI DMA FIFO Threshold */
1578#define  FIFO_THRESH_16B  0x00  /* 16 bytes */
1579#define  FIFO_THRESH_32B  0x20  /* 32 bytes */
1580#define  FIFO_THRESH_48B  0x30  /* 48 bytes */
1581#define  FIFO_THRESH_64B  0x40  /* 64 bytes */
1582#define  FIFO_THRESH_80B  0x50  /* 80 bytes (default) */
1583#define  FIFO_THRESH_96B  0x60  /* 96 bytes */
1584#define  FIFO_THRESH_112B 0x70  /* 112 bytes */
1585#define START_CTL       0x0C    /* DMA start conditions */
1586#define  START_CTL_TH    0x00   /* Wait threshold level (default) */
1587#define  START_CTL_ID    0x04   /* Wait SDMA/SBUS idle */
1588#define  START_CTL_THID  0x08   /* Wait threshold and SDMA/SBUS idle */
1589#define  START_CTL_EMFU  0x0C   /* Wait SDMA FIFO empty/full */
1590#define READ_CMD        0x03    /* Memory Read Method */
1591#define  READ_CMD_MR     0x00   /* Memory Read */
1592#define  READ_CMD_MRL    0x02   /* Memory Read Long */
1593#define  READ_CMD_MRM    0x03   /* Memory Read Multiple (default) */
1594
1595/*
1596 * ASC-38C0800 RAM BIST Register bit definitions
1597 */
1598#define RAM_TEST_MODE         0x80
1599#define PRE_TEST_MODE         0x40
1600#define NORMAL_MODE           0x00
1601#define RAM_TEST_DONE         0x10
1602#define RAM_TEST_STATUS       0x0F
1603#define  RAM_TEST_HOST_ERROR   0x08
1604#define  RAM_TEST_INTRAM_ERROR 0x04
1605#define  RAM_TEST_RISC_ERROR   0x02
1606#define  RAM_TEST_SCSI_ERROR   0x01
1607#define  RAM_TEST_SUCCESS      0x00
1608#define PRE_TEST_VALUE        0x05
1609#define NORMAL_VALUE          0x00
1610
1611/*
1612 * ASC38C1600 Definitions
1613 *
1614 * IOPB_PCI_INT_CFG Bit Field Definitions
1615 */
1616
1617#define INTAB_LD        0x80    /* Value loaded from EEPROM Bit 11. */
1618
1619/*
1620 * Bit 1 can be set to change the interrupt for the Function to operate in
1621 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1622 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1623 * mode, otherwise the operating mode is undefined.
1624 */
1625#define TOTEMPOLE       0x02
1626
1627/*
1628 * Bit 0 can be used to change the Int Pin for the Function. The value is
1629 * 0 by default for both Functions with Function 0 using INT A and Function
1630 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1631 * INT A is used.
1632 *
1633 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1634 * value specified in the PCI Configuration Space.
1635 */
1636#define INTAB           0x01
1637
1638/*
1639 * Adv Library Status Definitions
1640 */
1641#define ADV_TRUE        1
1642#define ADV_FALSE       0
1643#define ADV_SUCCESS     1
1644#define ADV_BUSY        0
1645#define ADV_ERROR       (-1)
1646
1647/*
1648 * ADV_DVC_VAR 'warn_code' values
1649 */
1650#define ASC_WARN_BUSRESET_ERROR         0x0001  /* SCSI Bus Reset error */
1651#define ASC_WARN_EEPROM_CHKSUM          0x0002  /* EEP check sum error */
1652#define ASC_WARN_EEPROM_TERMINATION     0x0004  /* EEP termination bad field */
1653#define ASC_WARN_ERROR                  0xFFFF  /* ADV_ERROR return */
1654
1655#define ADV_MAX_TID                     15      /* max. target identifier */
1656#define ADV_MAX_LUN                     7       /* max. logical unit number */
1657
1658/*
1659 * Fixed locations of microcode operating variables.
1660 */
1661#define ASC_MC_CODE_BEGIN_ADDR          0x0028  /* microcode start address */
1662#define ASC_MC_CODE_END_ADDR            0x002A  /* microcode end address */
1663#define ASC_MC_CODE_CHK_SUM             0x002C  /* microcode code checksum */
1664#define ASC_MC_VERSION_DATE             0x0038  /* microcode version */
1665#define ASC_MC_VERSION_NUM              0x003A  /* microcode number */
1666#define ASC_MC_BIOSMEM                  0x0040  /* BIOS RISC Memory Start */
1667#define ASC_MC_BIOSLEN                  0x0050  /* BIOS RISC Memory Length */
1668#define ASC_MC_BIOS_SIGNATURE           0x0058  /* BIOS Signature 0x55AA */
1669#define ASC_MC_BIOS_VERSION             0x005A  /* BIOS Version (2 bytes) */
1670#define ASC_MC_SDTR_SPEED1              0x0090  /* SDTR Speed for TID 0-3 */
1671#define ASC_MC_SDTR_SPEED2              0x0092  /* SDTR Speed for TID 4-7 */
1672#define ASC_MC_SDTR_SPEED3              0x0094  /* SDTR Speed for TID 8-11 */
1673#define ASC_MC_SDTR_SPEED4              0x0096  /* SDTR Speed for TID 12-15 */
1674#define ASC_MC_CHIP_TYPE                0x009A
1675#define ASC_MC_INTRB_CODE               0x009B
1676#define ASC_MC_WDTR_ABLE                0x009C
1677#define ASC_MC_SDTR_ABLE                0x009E
1678#define ASC_MC_TAGQNG_ABLE              0x00A0
1679#define ASC_MC_DISC_ENABLE              0x00A2
1680#define ASC_MC_IDLE_CMD_STATUS          0x00A4
1681#define ASC_MC_IDLE_CMD                 0x00A6
1682#define ASC_MC_IDLE_CMD_PARAMETER       0x00A8
1683#define ASC_MC_DEFAULT_SCSI_CFG0        0x00AC
1684#define ASC_MC_DEFAULT_SCSI_CFG1        0x00AE
1685#define ASC_MC_DEFAULT_MEM_CFG          0x00B0
1686#define ASC_MC_DEFAULT_SEL_MASK         0x00B2
1687#define ASC_MC_SDTR_DONE                0x00B6
1688#define ASC_MC_NUMBER_OF_QUEUED_CMD     0x00C0
1689#define ASC_MC_NUMBER_OF_MAX_CMD        0x00D0
1690#define ASC_MC_DEVICE_HSHK_CFG_TABLE    0x0100
1691#define ASC_MC_CONTROL_FLAG             0x0122  /* Microcode control flag. */
1692#define ASC_MC_WDTR_DONE                0x0124
1693#define ASC_MC_CAM_MODE_MASK            0x015E  /* CAM mode TID bitmask. */
1694#define ASC_MC_ICQ                      0x0160
1695#define ASC_MC_IRQ                      0x0164
1696#define ASC_MC_PPR_ABLE                 0x017A
1697
1698/*
1699 * BIOS LRAM variable absolute offsets.
1700 */
1701#define BIOS_CODESEG    0x54
1702#define BIOS_CODELEN    0x56
1703#define BIOS_SIGNATURE  0x58
1704#define BIOS_VERSION    0x5A
1705
1706/*
1707 * Microcode Control Flags
1708 *
1709 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1710 * and handled by the microcode.
1711 */
1712#define CONTROL_FLAG_IGNORE_PERR        0x0001  /* Ignore DMA Parity Errors */
1713#define CONTROL_FLAG_ENABLE_AIPP        0x0002  /* Enabled AIPP checking. */
1714
1715/*
1716 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1717 */
1718#define HSHK_CFG_WIDE_XFR       0x8000
1719#define HSHK_CFG_RATE           0x0F00
1720#define HSHK_CFG_OFFSET         0x001F
1721
1722#define ASC_DEF_MAX_HOST_QNG    0xFD    /* Max. number of host commands (253) */
1723#define ASC_DEF_MIN_HOST_QNG    0x10    /* Min. number of host commands (16) */
1724#define ASC_DEF_MAX_DVC_QNG     0x3F    /* Max. number commands per device (63) */
1725#define ASC_DEF_MIN_DVC_QNG     0x04    /* Min. number commands per device (4) */
1726
1727#define ASC_QC_DATA_CHECK  0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1728#define ASC_QC_DATA_OUT    0x02 /* Data out DMA transfer. */
1729#define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1730#define ASC_QC_NO_OVERRUN  0x08 /* Don't report overrun. */
1731#define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1732
1733#define ASC_QSC_NO_DISC     0x01        /* Don't allow disconnect for request. */
1734#define ASC_QSC_NO_TAGMSG   0x02        /* Don't allow tag queuing for request. */
1735#define ASC_QSC_NO_SYNC     0x04        /* Don't use Synch. transfer on request. */
1736#define ASC_QSC_NO_WIDE     0x08        /* Don't use Wide transfer on request. */
1737#define ASC_QSC_REDO_DTR    0x10        /* Renegotiate WDTR/SDTR before request. */
1738/*
1739 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1740 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1741 */
1742#define ASC_QSC_HEAD_TAG    0x40        /* Use Head Tag Message (0x21). */
1743#define ASC_QSC_ORDERED_TAG 0x80        /* Use Ordered Tag Message (0x22). */
1744
1745/*
1746 * All fields here are accessed by the board microcode and need to be
1747 * little-endian.
1748 */
1749typedef struct adv_carr_t {
1750        ADV_VADDR carr_va;      /* Carrier Virtual Address */
1751        ADV_PADDR carr_pa;      /* Carrier Physical Address */
1752        ADV_VADDR areq_vpa;     /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1753        /*
1754         * next_vpa [31:4]            Carrier Virtual or Physical Next Pointer
1755         *
1756         * next_vpa [3:1]             Reserved Bits
1757         * next_vpa [0]               Done Flag set in Response Queue.
1758         */
1759        ADV_VADDR next_vpa;
1760} ADV_CARR_T;
1761
1762/*
1763 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1764 */
1765#define ASC_NEXT_VPA_MASK       0xFFFFFFF0
1766
1767#define ASC_RQ_DONE             0x00000001
1768#define ASC_RQ_GOOD             0x00000002
1769#define ASC_CQ_STOPPER          0x00000000
1770
1771#define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1772
1773#define ADV_CARRIER_NUM_PAGE_CROSSING \
1774    (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + (PAGE_SIZE - 1))/PAGE_SIZE)
1775
1776#define ADV_CARRIER_BUFSIZE \
1777    ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
1778
1779/*
1780 * ASC_SCSI_REQ_Q 'a_flag' definitions
1781 *
1782 * The Adv Library should limit use to the lower nibble (4 bits) of
1783 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1784 */
1785#define ADV_POLL_REQUEST                0x01    /* poll for request completion */
1786#define ADV_SCSIQ_DONE                  0x02    /* request done */
1787#define ADV_DONT_RETRY                  0x08    /* don't do retry */
1788
1789#define ADV_CHIP_ASC3550          0x01  /* Ultra-Wide IC */
1790#define ADV_CHIP_ASC38C0800       0x02  /* Ultra2-Wide/LVD IC */
1791#define ADV_CHIP_ASC38C1600       0x03  /* Ultra3-Wide/LVD2 IC */
1792
1793/*
1794 * Adapter temporary configuration structure
1795 *
1796 * This structure can be discarded after initialization. Don't add
1797 * fields here needed after initialization.
1798 *
1799 * Field naming convention:
1800 *
1801 *  *_enable indicates the field enables or disables a feature. The
1802 *  value of the field is never reset.
1803 */
1804typedef struct adv_dvc_cfg {
1805        ushort disc_enable;     /* enable disconnection */
1806        uchar chip_version;     /* chip version */
1807        uchar termination;      /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1808        ushort control_flag;    /* Microcode Control Flag */
1809        ushort mcode_date;      /* Microcode date */
1810        ushort mcode_version;   /* Microcode version */
1811        ushort serial1;         /* EEPROM serial number word 1 */
1812        ushort serial2;         /* EEPROM serial number word 2 */
1813        ushort serial3;         /* EEPROM serial number word 3 */
1814} ADV_DVC_CFG;
1815
1816struct adv_dvc_var;
1817struct adv_scsi_req_q;
1818
1819typedef struct asc_sg_block {
1820        uchar reserved1;
1821        uchar reserved2;
1822        uchar reserved3;
1823        uchar sg_cnt;           /* Valid entries in block. */
1824        ADV_PADDR sg_ptr;       /* Pointer to next sg block. */
1825        struct {
1826                ADV_PADDR sg_addr;      /* SG element address. */
1827                ADV_DCNT sg_count;      /* SG element count. */
1828        } sg_list[NO_OF_SG_PER_BLOCK];
1829} ADV_SG_BLOCK;
1830
1831/*
1832 * ADV_SCSI_REQ_Q - microcode request structure
1833 *
1834 * All fields in this structure up to byte 60 are used by the microcode.
1835 * The microcode makes assumptions about the size and ordering of fields
1836 * in this structure. Do not change the structure definition here without
1837 * coordinating the change with the microcode.
1838 *
1839 * All fields accessed by microcode must be maintained in little_endian
1840 * order.
1841 */
1842typedef struct adv_scsi_req_q {
1843        uchar cntl;             /* Ucode flags and state (ASC_MC_QC_*). */
1844        uchar target_cmd;
1845        uchar target_id;        /* Device target identifier. */
1846        uchar target_lun;       /* Device target logical unit number. */
1847        ADV_PADDR data_addr;    /* Data buffer physical address. */
1848        ADV_DCNT data_cnt;      /* Data count. Ucode sets to residual. */
1849        ADV_PADDR sense_addr;
1850        ADV_PADDR carr_pa;
1851        uchar mflag;
1852        uchar sense_len;
1853        uchar cdb_len;          /* SCSI CDB length. Must <= 16 bytes. */
1854        uchar scsi_cntl;
1855        uchar done_status;      /* Completion status. */
1856        uchar scsi_status;      /* SCSI status byte. */
1857        uchar host_status;      /* Ucode host status. */
1858        uchar sg_working_ix;
1859        uchar cdb[12];          /* SCSI CDB bytes 0-11. */
1860        ADV_PADDR sg_real_addr; /* SG list physical address. */
1861        ADV_PADDR scsiq_rptr;
1862        uchar cdb16[4];         /* SCSI CDB bytes 12-15. */
1863        ADV_VADDR scsiq_ptr;
1864        ADV_VADDR carr_va;
1865        /*
1866         * End of microcode structure - 60 bytes. The rest of the structure
1867         * is used by the Adv Library and ignored by the microcode.
1868         */
1869        ADV_VADDR srb_ptr;
1870        ADV_SG_BLOCK *sg_list_ptr;      /* SG list virtual address. */
1871        char *vdata_addr;       /* Data buffer virtual address. */
1872        uchar a_flag;
1873        uchar pad[2];           /* Pad out to a word boundary. */
1874} ADV_SCSI_REQ_Q;
1875
1876/*
1877 * The following two structures are used to process Wide Board requests.
1878 *
1879 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1880 * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
1881 * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
1882 * Mid-Level SCSI request structure.
1883 *
1884 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1885 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1886 * up to 255 scatter-gather elements may be used per request or
1887 * ADV_SCSI_REQ_Q.
1888 *
1889 * Both structures must be 32 byte aligned.
1890 */
1891typedef struct adv_sgblk {
1892        ADV_SG_BLOCK sg_block;  /* Sgblock structure. */
1893        uchar align[32];        /* Sgblock structure padding. */
1894        struct adv_sgblk *next_sgblkp;  /* Next scatter-gather structure. */
1895} adv_sgblk_t;
1896
1897typedef struct adv_req {
1898        ADV_SCSI_REQ_Q scsi_req_q;      /* Adv Library request structure. */
1899        uchar align[32];        /* Request structure padding. */
1900        struct scsi_cmnd *cmndp;        /* Mid-Level SCSI command pointer. */
1901        adv_sgblk_t *sgblkp;    /* Adv Library scatter-gather pointer. */
1902        struct adv_req *next_reqp;      /* Next Request Structure. */
1903} adv_req_t;
1904
1905/*
1906 * Adapter operation variable structure.
1907 *
1908 * One structure is required per host adapter.
1909 *
1910 * Field naming convention:
1911 *
1912 *  *_able indicates both whether a feature should be enabled or disabled
1913 *  and whether a device isi capable of the feature. At initialization
1914 *  this field may be set, but later if a device is found to be incapable
1915 *  of the feature, the field is cleared.
1916 */
1917typedef struct adv_dvc_var {
1918        AdvPortAddr iop_base;   /* I/O port address */
1919        ushort err_code;        /* fatal error code */
1920        ushort bios_ctrl;       /* BIOS control word, EEPROM word 12 */
1921        ushort wdtr_able;       /* try WDTR for a device */
1922        ushort sdtr_able;       /* try SDTR for a device */
1923        ushort ultra_able;      /* try SDTR Ultra speed for a device */
1924        ushort sdtr_speed1;     /* EEPROM SDTR Speed for TID 0-3   */
1925        ushort sdtr_speed2;     /* EEPROM SDTR Speed for TID 4-7   */
1926        ushort sdtr_speed3;     /* EEPROM SDTR Speed for TID 8-11  */
1927        ushort sdtr_speed4;     /* EEPROM SDTR Speed for TID 12-15 */
1928        ushort tagqng_able;     /* try tagged queuing with a device */
1929        ushort ppr_able;        /* PPR message capable per TID bitmask. */
1930        uchar max_dvc_qng;      /* maximum number of tagged commands per device */
1931        ushort start_motor;     /* start motor command allowed */
1932        uchar scsi_reset_wait;  /* delay in seconds after scsi bus reset */
1933        uchar chip_no;          /* should be assigned by caller */
1934        uchar max_host_qng;     /* maximum number of Q'ed command allowed */
1935        ushort no_scam;         /* scam_tolerant of EEPROM */
1936        struct asc_board *drv_ptr;      /* driver pointer to private structure */
1937        uchar chip_scsi_id;     /* chip SCSI target ID */
1938        uchar chip_type;
1939        uchar bist_err_code;
1940        ADV_CARR_T *carrier_buf;
1941        ADV_CARR_T *carr_freelist;      /* Carrier free list. */
1942        ADV_CARR_T *icq_sp;     /* Initiator command queue stopper pointer. */
1943        ADV_CARR_T *irq_sp;     /* Initiator response queue stopper pointer. */
1944        ushort carr_pending_cnt;        /* Count of pending carriers. */
1945        struct adv_req *orig_reqp;      /* adv_req_t memory block. */
1946        /*
1947         * Note: The following fields will not be used after initialization. The
1948         * driver may discard the buffer after initialization is done.
1949         */
1950        ADV_DVC_CFG *cfg;       /* temporary configuration structure  */
1951} ADV_DVC_VAR;
1952
1953/*
1954 * Microcode idle loop commands
1955 */
1956#define IDLE_CMD_COMPLETED           0
1957#define IDLE_CMD_STOP_CHIP           0x0001
1958#define IDLE_CMD_STOP_CHIP_SEND_INT  0x0002
1959#define IDLE_CMD_SEND_INT            0x0004
1960#define IDLE_CMD_ABORT               0x0008
1961#define IDLE_CMD_DEVICE_RESET        0x0010
1962#define IDLE_CMD_SCSI_RESET_START    0x0020     /* Assert SCSI Bus Reset */
1963#define IDLE_CMD_SCSI_RESET_END      0x0040     /* Deassert SCSI Bus Reset */
1964#define IDLE_CMD_SCSIREQ             0x0080
1965
1966#define IDLE_CMD_STATUS_SUCCESS      0x0001
1967#define IDLE_CMD_STATUS_FAILURE      0x0002
1968
1969/*
1970 * AdvSendIdleCmd() flag definitions.
1971 */
1972#define ADV_NOWAIT     0x01
1973
1974/*
1975 * Wait loop time out values.
1976 */
1977#define SCSI_WAIT_100_MSEC           100UL      /* 100 milliseconds */
1978#define SCSI_US_PER_MSEC             1000       /* microseconds per millisecond */
1979#define SCSI_MAX_RETRY               10 /* retry count */
1980
1981#define ADV_ASYNC_RDMA_FAILURE          0x01    /* Fatal RDMA failure. */
1982#define ADV_ASYNC_SCSI_BUS_RESET_DET    0x02    /* Detected SCSI Bus Reset. */
1983#define ADV_ASYNC_CARRIER_READY_FAILURE 0x03    /* Carrier Ready failure. */
1984#define ADV_RDMA_IN_CARR_AND_Q_INVALID  0x04    /* RDMAed-in data invalid. */
1985
1986#define ADV_HOST_SCSI_BUS_RESET      0x80       /* Host Initiated SCSI Bus Reset. */
1987
1988/* Read byte from a register. */
1989#define AdvReadByteRegister(iop_base, reg_off) \
1990     (ADV_MEM_READB((iop_base) + (reg_off)))
1991
1992/* Write byte to a register. */
1993#define AdvWriteByteRegister(iop_base, reg_off, byte) \
1994     (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1995
1996/* Read word (2 bytes) from a register. */
1997#define AdvReadWordRegister(iop_base, reg_off) \
1998     (ADV_MEM_READW((iop_base) + (reg_off)))
1999
2000/* Write word (2 bytes) to a register. */
2001#define AdvWriteWordRegister(iop_base, reg_off, word) \
2002     (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
2003
2004/* Write dword (4 bytes) to a register. */
2005#define AdvWriteDWordRegister(iop_base, reg_off, dword) \
2006     (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
2007
2008/* Read byte from LRAM. */
2009#define AdvReadByteLram(iop_base, addr, byte) \
2010do { \
2011    ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2012    (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
2013} while (0)
2014
2015/* Write byte to LRAM. */
2016#define AdvWriteByteLram(iop_base, addr, byte) \
2017    (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2018     ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2019
2020/* Read word (2 bytes) from LRAM. */
2021#define AdvReadWordLram(iop_base, addr, word) \
2022do { \
2023    ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2024    (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
2025} while (0)
2026
2027/* Write word (2 bytes) to LRAM. */
2028#define AdvWriteWordLram(iop_base, addr, word) \
2029    (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2030     ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2031
2032/* Write little-endian double word (4 bytes) to LRAM */
2033/* Because of unspecified C language ordering don't use auto-increment. */
2034#define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2035    ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2036      ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2037                     cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2038     (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2039      ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2040                     cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2041
2042/* Read word (2 bytes) from LRAM assuming that the address is already set. */
2043#define AdvReadWordAutoIncLram(iop_base) \
2044     (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2045
2046/* Write word (2 bytes) to LRAM assuming that the address is already set. */
2047#define AdvWriteWordAutoIncLram(iop_base, word) \
2048     (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2049
2050/*
2051 * Define macro to check for Condor signature.
2052 *
2053 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2054 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2055 */
2056#define AdvFindSignature(iop_base) \
2057    (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2058    ADV_CHIP_ID_BYTE) && \
2059     (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2060    ADV_CHIP_ID_WORD)) ?  ADV_TRUE : ADV_FALSE)
2061
2062/*
2063 * Define macro to Return the version number of the chip at 'iop_base'.
2064 *
2065 * The second parameter 'bus_type' is currently unused.
2066 */
2067#define AdvGetChipVersion(iop_base, bus_type) \
2068    AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2069
2070/*
2071 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
2072 * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
2073 *
2074 * If the request has not yet been sent to the device it will simply be
2075 * aborted from RISC memory. If the request is disconnected it will be
2076 * aborted on reselection by sending an Abort Message to the target ID.
2077 *
2078 * Return value:
2079 *      ADV_TRUE(1) - Queue was successfully aborted.
2080 *      ADV_FALSE(0) - Queue was not found on the active queue list.
2081 */
2082#define AdvAbortQueue(asc_dvc, scsiq) \
2083        AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2084                       (ADV_DCNT) (scsiq))
2085
2086/*
2087 * Send a Bus Device Reset Message to the specified target ID.
2088 *
2089 * All outstanding commands will be purged if sending the
2090 * Bus Device Reset Message is successful.
2091 *
2092 * Return Value:
2093 *      ADV_TRUE(1) - All requests on the target are purged.
2094 *      ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2095 *                     are not purged.
2096 */
2097#define AdvResetDevice(asc_dvc, target_id) \
2098        AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2099                    (ADV_DCNT) (target_id))
2100
2101/*
2102 * SCSI Wide Type definition.
2103 */
2104#define ADV_SCSI_BIT_ID_TYPE   ushort
2105
2106/*
2107 * AdvInitScsiTarget() 'cntl_flag' options.
2108 */
2109#define ADV_SCAN_LUN           0x01
2110#define ADV_CAPINFO_NOLUN      0x02
2111
2112/*
2113 * Convert target id to target id bit mask.
2114 */
2115#define ADV_TID_TO_TIDMASK(tid)   (0x01 << ((tid) & ADV_MAX_TID))
2116
2117/*
2118 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2119 */
2120
2121#define QD_NO_STATUS         0x00       /* Request not completed yet. */
2122#define QD_NO_ERROR          0x01
2123#define QD_ABORTED_BY_HOST   0x02
2124#define QD_WITH_ERROR        0x04
2125
2126#define QHSTA_NO_ERROR              0x00
2127#define QHSTA_M_SEL_TIMEOUT         0x11
2128#define QHSTA_M_DATA_OVER_RUN       0x12
2129#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2130#define QHSTA_M_QUEUE_ABORTED       0x15
2131#define QHSTA_M_SXFR_SDMA_ERR       0x16        /* SXFR_STATUS SCSI DMA Error */
2132#define QHSTA_M_SXFR_SXFR_PERR      0x17        /* SXFR_STATUS SCSI Bus Parity Error */
2133#define QHSTA_M_RDMA_PERR           0x18        /* RISC PCI DMA parity error */
2134#define QHSTA_M_SXFR_OFF_UFLW       0x19        /* SXFR_STATUS Offset Underflow */
2135#define QHSTA_M_SXFR_OFF_OFLW       0x20        /* SXFR_STATUS Offset Overflow */
2136#define QHSTA_M_SXFR_WD_TMO         0x21        /* SXFR_STATUS Watchdog Timeout */
2137#define QHSTA_M_SXFR_DESELECTED     0x22        /* SXFR_STATUS Deselected */
2138/* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2139#define QHSTA_M_SXFR_XFR_OFLW       0x12        /* SXFR_STATUS Transfer Overflow */
2140#define QHSTA_M_SXFR_XFR_PH_ERR     0x24        /* SXFR_STATUS Transfer Phase Error */
2141#define QHSTA_M_SXFR_UNKNOWN_ERROR  0x25        /* SXFR_STATUS Unknown Error */
2142#define QHSTA_M_SCSI_BUS_RESET      0x30        /* Request aborted from SBR */
2143#define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31       /* Request aborted from unsol. SBR */
2144#define QHSTA_M_BUS_DEVICE_RESET    0x32        /* Request aborted from BDR */
2145#define QHSTA_M_DIRECTION_ERR       0x35        /* Data Phase mismatch */
2146#define QHSTA_M_DIRECTION_ERR_HUNG  0x36        /* Data Phase mismatch and bus hang */
2147#define QHSTA_M_WTM_TIMEOUT         0x41
2148#define QHSTA_M_BAD_CMPL_STATUS_IN  0x42
2149#define QHSTA_M_NO_AUTO_REQ_SENSE   0x43
2150#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2151#define QHSTA_M_INVALID_DEVICE      0x45        /* Bad target ID */
2152#define QHSTA_M_FROZEN_TIDQ         0x46        /* TID Queue frozen. */
2153#define QHSTA_M_SGBACKUP_ERROR      0x47        /* Scatter-Gather backup error */
2154
2155/* Return the address that is aligned at the next doubleword >= to 'addr'. */
2156#define ADV_8BALIGN(addr)      (((ulong) (addr) + 0x7) & ~0x7)
2157#define ADV_16BALIGN(addr)     (((ulong) (addr) + 0xF) & ~0xF)
2158#define ADV_32BALIGN(addr)     (((ulong) (addr) + 0x1F) & ~0x1F)
2159
2160/*
2161 * Total contiguous memory needed for driver SG blocks.
2162 *
2163 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2164 * number of scatter-gather elements the driver supports in a
2165 * single request.
2166 */
2167
2168#define ADV_SG_LIST_MAX_BYTE_SIZE \
2169         (sizeof(ADV_SG_BLOCK) * \
2170          ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2171
2172/* struct asc_board flags */
2173#define ASC_IS_WIDE_BOARD       0x04    /* AdvanSys Wide Board */
2174
2175#define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2176
2177#define NO_ISA_DMA              0xff    /* No ISA DMA Channel Used */
2178
2179#define ASC_INFO_SIZE           128     /* advansys_info() line size */
2180
2181/* Asc Library return codes */
2182#define ASC_TRUE        1
2183#define ASC_FALSE       0
2184#define ASC_NOERROR     1
2185#define ASC_BUSY        0
2186#define ASC_ERROR       (-1)
2187
2188/* struct scsi_cmnd function return codes */
2189#define STATUS_BYTE(byte)   (byte)
2190#define MSG_BYTE(byte)      ((byte) << 8)
2191#define HOST_BYTE(byte)     ((byte) << 16)
2192#define DRIVER_BYTE(byte)   ((byte) << 24)
2193
2194#define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2195#ifndef ADVANSYS_STATS
2196#define ASC_STATS_ADD(shost, counter, count)
2197#else /* ADVANSYS_STATS */
2198#define ASC_STATS_ADD(shost, counter, count) \
2199        (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2200#endif /* ADVANSYS_STATS */
2201
2202/* If the result wraps when calculating tenths, return 0. */
2203#define ASC_TENTHS(num, den) \
2204    (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2205    0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2206
2207/*
2208 * Display a message to the console.
2209 */
2210#define ASC_PRINT(s) \
2211    { \
2212        printk("advansys: "); \
2213        printk(s); \
2214    }
2215
2216#define ASC_PRINT1(s, a1) \
2217    { \
2218        printk("advansys: "); \
2219        printk((s), (a1)); \
2220    }
2221
2222#define ASC_PRINT2(s, a1, a2) \
2223    { \
2224        printk("advansys: "); \
2225        printk((s), (a1), (a2)); \
2226    }
2227
2228#define ASC_PRINT3(s, a1, a2, a3) \
2229    { \
2230        printk("advansys: "); \
2231        printk((s), (a1), (a2), (a3)); \
2232    }
2233
2234#define ASC_PRINT4(s, a1, a2, a3, a4) \
2235    { \
2236        printk("advansys: "); \
2237        printk((s), (a1), (a2), (a3), (a4)); \
2238    }
2239
2240#ifndef ADVANSYS_DEBUG
2241
2242#define ASC_DBG(lvl, s...)
2243#define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2244#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2245#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2246#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2247#define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2248#define ASC_DBG_PRT_HEX(lvl, name, start, length)
2249#define ASC_DBG_PRT_CDB(lvl, cdb, len)
2250#define ASC_DBG_PRT_SENSE(lvl, sense, len)
2251#define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2252
2253#else /* ADVANSYS_DEBUG */
2254
2255/*
2256 * Debugging Message Levels:
2257 * 0: Errors Only
2258 * 1: High-Level Tracing
2259 * 2-N: Verbose Tracing
2260 */
2261
2262#define ASC_DBG(lvl, format, arg...) {                                  \
2263        if (asc_dbglvl >= (lvl))                                        \
2264                printk(KERN_DEBUG "%s: %s: " format, DRV_NAME,          \
2265                        __func__ , ## arg);                             \
2266}
2267
2268#define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2269    { \
2270        if (asc_dbglvl >= (lvl)) { \
2271            asc_prt_scsi_host(s); \
2272        } \
2273    }
2274
2275#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2276    { \
2277        if (asc_dbglvl >= (lvl)) { \
2278            asc_prt_asc_scsi_q(scsiqp); \
2279        } \
2280    }
2281
2282#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2283    { \
2284        if (asc_dbglvl >= (lvl)) { \
2285            asc_prt_asc_qdone_info(qdone); \
2286        } \
2287    }
2288
2289#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2290    { \
2291        if (asc_dbglvl >= (lvl)) { \
2292            asc_prt_adv_scsi_req_q(scsiqp); \
2293        } \
2294    }
2295
2296#define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2297    { \
2298        if (asc_dbglvl >= (lvl)) { \
2299            asc_prt_hex((name), (start), (length)); \
2300        } \
2301    }
2302
2303#define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2304        ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2305
2306#define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2307        ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2308
2309#define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2310        ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2311#endif /* ADVANSYS_DEBUG */
2312
2313#ifdef ADVANSYS_STATS
2314
2315/* Per board statistics structure */
2316struct asc_stats {
2317        /* Driver Entrypoint Statistics */
2318        ADV_DCNT queuecommand;  /* # calls to advansys_queuecommand() */
2319        ADV_DCNT reset;         /* # calls to advansys_eh_bus_reset() */
2320        ADV_DCNT biosparam;     /* # calls to advansys_biosparam() */
2321        ADV_DCNT interrupt;     /* # advansys_interrupt() calls */
2322        ADV_DCNT callback;      /* # calls to asc/adv_isr_callback() */
2323        ADV_DCNT done;          /* # calls to request's scsi_done function */
2324        ADV_DCNT build_error;   /* # asc/adv_build_req() ASC_ERROR returns. */
2325        ADV_DCNT adv_build_noreq;       /* # adv_build_req() adv_req_t alloc. fail. */
2326        ADV_DCNT adv_build_nosg;        /* # adv_build_req() adv_sgblk_t alloc. fail. */
2327        /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2328        ADV_DCNT exe_noerror;   /* # ASC_NOERROR returns. */
2329        ADV_DCNT exe_busy;      /* # ASC_BUSY returns. */
2330        ADV_DCNT exe_error;     /* # ASC_ERROR returns. */
2331        ADV_DCNT exe_unknown;   /* # unknown returns. */
2332        /* Data Transfer Statistics */
2333        ADV_DCNT xfer_cnt;      /* # I/O requests received */
2334        ADV_DCNT xfer_elem;     /* # scatter-gather elements */
2335        ADV_DCNT xfer_sect;     /* # 512-byte blocks */
2336};
2337#endif /* ADVANSYS_STATS */
2338
2339/*
2340 * Structure allocated for each board.
2341 *
2342 * This structure is allocated by scsi_host_alloc() at the end
2343 * of the 'Scsi_Host' structure starting at the 'hostdata'
2344 * field. It is guaranteed to be allocated from DMA-able memory.
2345 */
2346struct asc_board {
2347        struct device *dev;
2348        uint flags;             /* Board flags */
2349        unsigned int irq;
2350        union {
2351                ASC_DVC_VAR asc_dvc_var;        /* Narrow board */
2352                ADV_DVC_VAR adv_dvc_var;        /* Wide board */
2353        } dvc_var;
2354        union {
2355                ASC_DVC_CFG asc_dvc_cfg;        /* Narrow board */
2356                ADV_DVC_CFG adv_dvc_cfg;        /* Wide board */
2357        } dvc_cfg;
2358        ushort asc_n_io_port;   /* Number I/O ports. */
2359        ADV_SCSI_BIT_ID_TYPE init_tidmask;      /* Target init./valid mask */
2360        ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2361        ADV_SCSI_BIT_ID_TYPE queue_full;        /* Queue full mask */
2362        ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2363        union {
2364                ASCEEP_CONFIG asc_eep;  /* Narrow EEPROM config. */
2365                ADVEEP_3550_CONFIG adv_3550_eep;        /* 3550 EEPROM config. */
2366                ADVEEP_38C0800_CONFIG adv_38C0800_eep;  /* 38C0800 EEPROM config. */
2367                ADVEEP_38C1600_CONFIG adv_38C1600_eep;  /* 38C1600 EEPROM config. */
2368        } eep_config;
2369        ulong last_reset;       /* Saved last reset time */
2370        /* /proc/scsi/advansys/[0...] */
2371#ifdef ADVANSYS_STATS
2372        struct asc_stats asc_stats;     /* Board statistics */
2373#endif                          /* ADVANSYS_STATS */
2374        /*
2375         * The following fields are used only for Narrow Boards.
2376         */
2377        uchar sdtr_data[ASC_MAX_TID + 1];       /* SDTR information */
2378        /*
2379         * The following fields are used only for Wide Boards.
2380         */
2381        void __iomem *ioremap_addr;     /* I/O Memory remap address. */
2382        ushort ioport;          /* I/O Port address. */
2383        adv_req_t *adv_reqp;    /* Request structures. */
2384        adv_sgblk_t *adv_sgblkp;        /* Scatter-gather structures. */
2385        ushort bios_signature;  /* BIOS Signature. */
2386        ushort bios_version;    /* BIOS Version. */
2387        ushort bios_codeseg;    /* BIOS Code Segment. */
2388        ushort bios_codelen;    /* BIOS Code Segment Length. */
2389};
2390
2391#define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2392                                                        dvc_var.asc_dvc_var)
2393#define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2394                                                        dvc_var.adv_dvc_var)
2395#define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2396
2397#ifdef ADVANSYS_DEBUG
2398static int asc_dbglvl = 3;
2399
2400/*
2401 * asc_prt_asc_dvc_var()
2402 */
2403static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2404{
2405        printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2406
2407        printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2408               "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2409
2410        printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2411                (unsigned)h->init_sdtr);
2412
2413        printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2414               "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2415               (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2416               (unsigned)h->chip_no);
2417
2418        printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2419               "%u,\n", (unsigned)h->queue_full_or_busy,
2420               (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2421
2422        printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2423               "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2424               (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2425               (unsigned)h->in_critical_cnt);
2426
2427        printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2428               "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2429               (unsigned)h->init_state, (unsigned)h->no_scam,
2430               (unsigned)h->pci_fix_asyn_xfer);
2431
2432        printk(" cfg 0x%lx\n", (ulong)h->cfg);
2433}
2434
2435/*
2436 * asc_prt_asc_dvc_cfg()
2437 */
2438static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2439{
2440        printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2441
2442        printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2443               h->can_tagged_qng, h->cmd_qng_enabled);
2444        printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2445               h->disc_enable, h->sdtr_enable);
2446
2447        printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2448                "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2449                h->isa_dma_channel, h->chip_version);
2450
2451        printk(" mcode_date 0x%x, mcode_version %d\n",
2452                h->mcode_date, h->mcode_version);
2453}
2454
2455/*
2456 * asc_prt_adv_dvc_var()
2457 *
2458 * Display an ADV_DVC_VAR structure.
2459 */
2460static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2461{
2462        printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2463
2464        printk("  iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2465               (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2466
2467        printk("  sdtr_able 0x%x, wdtr_able 0x%x\n",
2468               (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
2469
2470        printk("  start_motor 0x%x, scsi_reset_wait 0x%x\n",
2471               (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2472
2473        printk("  max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
2474               (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2475               (ulong)h->carr_freelist);
2476
2477        printk("  icq_sp 0x%lx, irq_sp 0x%lx\n",
2478               (ulong)h->icq_sp, (ulong)h->irq_sp);
2479
2480        printk("  no_scam 0x%x, tagqng_able 0x%x\n",
2481               (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2482
2483        printk("  chip_scsi_id 0x%x, cfg 0x%lx\n",
2484               (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2485}
2486
2487/*
2488 * asc_prt_adv_dvc_cfg()
2489 *
2490 * Display an ADV_DVC_CFG structure.
2491 */
2492static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2493{
2494        printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2495
2496        printk("  disc_enable 0x%x, termination 0x%x\n",
2497               h->disc_enable, h->termination);
2498
2499        printk("  chip_version 0x%x, mcode_date 0x%x\n",
2500               h->chip_version, h->mcode_date);
2501
2502        printk("  mcode_version 0x%x, control_flag 0x%x\n",
2503               h->mcode_version, h->control_flag);
2504}
2505
2506/*
2507 * asc_prt_scsi_host()
2508 */
2509static void asc_prt_scsi_host(struct Scsi_Host *s)
2510{
2511        struct asc_board *boardp = shost_priv(s);
2512
2513        printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
2514        printk(" host_busy %u, host_no %d, last_reset %d,\n",
2515               s->host_busy, s->host_no, (unsigned)s->last_reset);
2516
2517        printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2518               (ulong)s->base, (ulong)s->io_port, boardp->irq);
2519
2520        printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2521               s->dma_channel, s->this_id, s->can_queue);
2522
2523        printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2524               s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2525
2526        if (ASC_NARROW_BOARD(boardp)) {
2527                asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2528                asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2529        } else {
2530                asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2531                asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
2532        }
2533}
2534
2535/*
2536 * asc_prt_hex()
2537 *
2538 * Print hexadecimal output in 4 byte groupings 32 bytes
2539 * or 8 double-words per line.
2540 */
2541static void asc_prt_hex(char *f, uchar *s, int l)
2542{
2543        int i;
2544        int j;
2545        int k;
2546        int m;
2547
2548        printk("%s: (%d bytes)\n", f, l);
2549
2550        for (i = 0; i < l; i += 32) {
2551
2552                /* Display a maximum of 8 double-words per line. */
2553                if ((k = (l - i) / 4) >= 8) {
2554                        k = 8;
2555                        m = 0;
2556                } else {
2557                        m = (l - i) % 4;
2558                }
2559
2560                for (j = 0; j < k; j++) {
2561                        printk(" %2.2X%2.2X%2.2X%2.2X",
2562                               (unsigned)s[i + (j * 4)],
2563                               (unsigned)s[i + (j * 4) + 1],
2564                               (unsigned)s[i + (j * 4) + 2],
2565                               (unsigned)s[i + (j * 4) + 3]);
2566                }
2567
2568                switch (m) {
2569                case 0:
2570                default:
2571                        break;
2572                case 1:
2573                        printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2574                        break;
2575                case 2:
2576                        printk(" %2.2X%2.2X",
2577                               (unsigned)s[i + (j * 4)],
2578                               (unsigned)s[i + (j * 4) + 1]);
2579                        break;
2580                case 3:
2581                        printk(" %2.2X%2.2X%2.2X",
2582                               (unsigned)s[i + (j * 4) + 1],
2583                               (unsigned)s[i + (j * 4) + 2],
2584                               (unsigned)s[i + (j * 4) + 3]);
2585                        break;
2586                }
2587
2588                printk("\n");
2589        }
2590}
2591
2592/*
2593 * asc_prt_asc_scsi_q()
2594 */
2595static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2596{
2597        ASC_SG_HEAD *sgp;
2598        int i;
2599
2600        printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2601
2602        printk
2603            (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
2604             q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr,
2605             q->q2.tag_code);
2606
2607        printk
2608            (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2609             (ulong)le32_to_cpu(q->q1.data_addr),
2610             (ulong)le32_to_cpu(q->q1.data_cnt),
2611             (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2612
2613        printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2614               (ulong)q->cdbptr, q->q2.cdb_len,
2615               (ulong)q->sg_head, q->q1.sg_queue_cnt);
2616
2617        if (q->sg_head) {
2618                sgp = q->sg_head;
2619                printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2620                printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2621                       sgp->queue_cnt);
2622                for (i = 0; i < sgp->entry_cnt; i++) {
2623                        printk(" [%u]: addr 0x%lx, bytes %lu\n",
2624                               i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2625                               (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2626                }
2627
2628        }
2629}
2630
2631/*
2632 * asc_prt_asc_qdone_info()
2633 */
2634static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2635{
2636        printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2637        printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
2638               (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
2639               q->d2.tag_code);
2640        printk
2641            (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2642             q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2643}
2644
2645/*
2646 * asc_prt_adv_sgblock()
2647 *
2648 * Display an ADV_SG_BLOCK structure.
2649 */
2650static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2651{
2652        int i;
2653
2654        printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2655               (ulong)b, sgblockno);
2656        printk("  sg_cnt %u, sg_ptr 0x%lx\n",
2657               b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2658        BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2659        if (b->sg_ptr != 0)
2660                BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2661        for (i = 0; i < b->sg_cnt; i++) {
2662                printk("  [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2663                       i, (ulong)b->sg_list[i].sg_addr,
2664                       (ulong)b->sg_list[i].sg_count);
2665        }
2666}
2667
2668/*
2669 * asc_prt_adv_scsi_req_q()
2670 *
2671 * Display an ADV_SCSI_REQ_Q structure.
2672 */
2673static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2674{
2675        int sg_blk_cnt;
2676        struct asc_sg_block *sg_ptr;
2677
2678        printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2679
2680        printk("  target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
2681               q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag);
2682
2683        printk("  cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
2684               q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr);
2685
2686        printk("  data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2687               (ulong)le32_to_cpu(q->data_cnt),
2688               (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2689
2690        printk
2691            ("  cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2692             q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2693
2694        printk("  sg_working_ix 0x%x, target_cmd %u\n",
2695               q->sg_working_ix, q->target_cmd);
2696
2697        printk("  scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2698               (ulong)le32_to_cpu(q->scsiq_rptr),
2699               (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2700
2701        /* Display the request's ADV_SG_BLOCK structures. */
2702        if (q->sg_list_ptr != NULL) {
2703                sg_blk_cnt = 0;
2704                while (1) {
2705                        /*
2706                         * 'sg_ptr' is a physical address. Convert it to a virtual
2707                         * address by indexing 'sg_blk_cnt' into the virtual address
2708                         * array 'sg_list_ptr'.
2709                         *
2710                         * XXX - Assumes all SG physical blocks are virtually contiguous.
2711                         */
2712                        sg_ptr =
2713                            &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
2714                        asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2715                        if (sg_ptr->sg_ptr == 0) {
2716                                break;
2717                        }
2718                        sg_blk_cnt++;
2719                }
2720        }
2721}
2722#endif /* ADVANSYS_DEBUG */
2723
2724/*
2725 * The advansys chip/microcode contains a 32-bit identifier for each command
2726 * known as the 'srb'.  I don't know what it stands for.  The driver used
2727 * to encode the scsi_cmnd pointer by calling virt_to_bus and retrieve it
2728 * with bus_to_virt.  Now the driver keeps a per-host map of integers to
2729 * pointers.  It auto-expands when full, unless it can't allocate memory.
2730 * Note that an srb of 0 is treated specially by the chip/firmware, hence
2731 * the return of i+1 in this routine, and the corresponding subtraction in
2732 * the inverse routine.
2733 */
2734#define BAD_SRB 0
2735static u32 advansys_ptr_to_srb(struct asc_dvc_var *asc_dvc, void *ptr)
2736{
2737        int i;
2738        void **new_ptr;
2739
2740        for (i = 0; i < asc_dvc->ptr_map_count; i++) {
2741                if (!asc_dvc->ptr_map[i])
2742                        goto out;
2743        }
2744
2745        if (asc_dvc->ptr_map_count == 0)
2746                asc_dvc->ptr_map_count = 1;
2747        else
2748                asc_dvc->ptr_map_count *= 2;
2749
2750        new_ptr = krealloc(asc_dvc->ptr_map,
2751                        asc_dvc->ptr_map_count * sizeof(void *), GFP_ATOMIC);
2752        if (!new_ptr)
2753                return BAD_SRB;
2754        asc_dvc->ptr_map = new_ptr;
2755 out:
2756        ASC_DBG(3, "Putting ptr %p into array offset %d\n", ptr, i);
2757        asc_dvc->ptr_map[i] = ptr;
2758        return i + 1;
2759}
2760
2761static void * advansys_srb_to_ptr(struct asc_dvc_var *asc_dvc, u32 srb)
2762{
2763        void *ptr;
2764
2765        srb--;
2766        if (srb >= asc_dvc->ptr_map_count) {
2767                printk("advansys: bad SRB %u, max %u\n", srb,
2768                                                        asc_dvc->ptr_map_count);
2769                return NULL;
2770        }
2771        ptr = asc_dvc->ptr_map[srb];
2772        asc_dvc->ptr_map[srb] = NULL;
2773        ASC_DBG(3, "Returning ptr %p from array offset %d\n", ptr, srb);
2774        return ptr;
2775}
2776
2777/*
2778 * advansys_info()
2779 *
2780 * Return suitable for printing on the console with the argument
2781 * adapter's configuration information.
2782 *
2783 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2784 * otherwise the static 'info' array will be overrun.
2785 */
2786static const char *advansys_info(struct Scsi_Host *shost)
2787{
2788        static char info[ASC_INFO_SIZE];
2789        struct asc_board *boardp = shost_priv(shost);
2790        ASC_DVC_VAR *asc_dvc_varp;
2791        ADV_DVC_VAR *adv_dvc_varp;
2792        char *busname;
2793        char *widename = NULL;
2794
2795        if (ASC_NARROW_BOARD(boardp)) {
2796                asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2797                ASC_DBG(1, "begin\n");
2798                if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2799                        if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2800                            ASC_IS_ISAPNP) {
2801                                busname = "ISA PnP";
2802                        } else {
2803                                busname = "ISA";
2804                        }
2805                        sprintf(info,
2806                                "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2807                                ASC_VERSION, busname,
2808                                (ulong)shost->io_port,
2809                                (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2810                                boardp->irq, shost->dma_channel);
2811                } else {
2812                        if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2813                                busname = "VL";
2814                        } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2815                                busname = "EISA";
2816                        } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2817                                if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2818                                    == ASC_IS_PCI_ULTRA) {
2819                                        busname = "PCI Ultra";
2820                                } else {
2821                                        busname = "PCI";
2822                                }
2823                        } else {
2824                                busname = "?";
2825                                shost_printk(KERN_ERR, shost, "unknown bus "
2826                                        "type %d\n", asc_dvc_varp->bus_type);
2827                        }
2828                        sprintf(info,
2829                                "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2830                                ASC_VERSION, busname, (ulong)shost->io_port,
2831                                (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2832                                boardp->irq);
2833                }
2834        } else {
2835                /*
2836                 * Wide Adapter Information
2837                 *
2838                 * Memory-mapped I/O is used instead of I/O space to access
2839                 * the adapter, but display the I/O Port range. The Memory
2840                 * I/O address is displayed through the driver /proc file.
2841                 */
2842                adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2843                if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2844                        widename = "Ultra-Wide";
2845                } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2846                        widename = "Ultra2-Wide";
2847                } else {
2848                        widename = "Ultra3-Wide";
2849                }
2850                sprintf(info,
2851                        "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2852                        ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2853                        (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2854        }
2855        BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2856        ASC_DBG(1, "end\n");
2857        return info;
2858}
2859
2860#ifdef CONFIG_PROC_FS
2861
2862/*
2863 * asc_prt_board_devices()
2864 *
2865 * Print driver information for devices attached to the board.
2866 */
2867static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
2868{
2869        struct asc_board *boardp = shost_priv(shost);
2870        int chip_scsi_id;
2871        int i;
2872
2873        seq_printf(m,
2874                   "\nDevice Information for AdvanSys SCSI Host %d:\n",
2875                   shost->host_no);
2876
2877        if (ASC_NARROW_BOARD(boardp)) {
2878                chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2879        } else {
2880                chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
2881        }
2882
2883        seq_printf(m, "Target IDs Detected:");
2884        for (i = 0; i <= ADV_MAX_TID; i++) {
2885                if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
2886                        seq_printf(m, " %X,", i);
2887        }
2888        seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
2889}
2890
2891/*
2892 * Display Wide Board BIOS Information.
2893 */
2894static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
2895{
2896        struct asc_board *boardp = shost_priv(shost);
2897        ushort major, minor, letter;
2898
2899        seq_printf(m, "\nROM BIOS Version: ");
2900
2901        /*
2902         * If the BIOS saved a valid signature, then fill in
2903         * the BIOS code segment base address.
2904         */
2905        if (boardp->bios_signature != 0x55AA) {
2906                seq_printf(m, "Disabled or Pre-3.1\n");
2907                seq_printf(m,
2908                          "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
2909                seq_printf(m,
2910                          "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2911        } else {
2912                major = (boardp->bios_version >> 12) & 0xF;
2913                minor = (boardp->bios_version >> 8) & 0xF;
2914                letter = (boardp->bios_version & 0xFF);
2915
2916                seq_printf(m, "%d.%d%c\n",
2917                                   major, minor,
2918                                   letter >= 26 ? '?' : letter + 'A');
2919                /*
2920                 * Current available ROM BIOS release is 3.1I for UW
2921                 * and 3.2I for U2W. This code doesn't differentiate
2922                 * UW and U2W boards.
2923                 */
2924                if (major < 3 || (major <= 3 && minor < 1) ||
2925                    (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
2926                        seq_printf(m,
2927                                   "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
2928                        seq_printf(m,
2929                                   "ftp://ftp.connectcom.net/pub\n");
2930                }
2931        }
2932}
2933
2934/*
2935 * Add serial number to information bar if signature AAh
2936 * is found in at bit 15-9 (7 bits) of word 1.
2937 *
2938 * Serial Number consists fo 12 alpha-numeric digits.
2939 *
2940 *       1 - Product type (A,B,C,D..)  Word0: 15-13 (3 bits)
2941 *       2 - MFG Location (A,B,C,D..)  Word0: 12-10 (3 bits)
2942 *     3-4 - Product ID (0-99)         Word0: 9-0 (10 bits)
2943 *       5 - Product revision (A-J)    Word0:  "         "
2944 *
2945 *           Signature                 Word1: 15-9 (7 bits)
2946 *       6 - Year (0-9)                Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
2947 *     7-8 - Week of the year (1-52)   Word1: 5-0 (6 bits)
2948 *
2949 *    9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
2950 *
2951 * Note 1: Only production cards will have a serial number.
2952 *
2953 * Note 2: Signature is most significant 7 bits (0xFE).
2954 *
2955 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
2956 */
2957static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
2958{
2959        ushort w, num;
2960
2961        if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
2962                return ASC_FALSE;
2963        } else {
2964                /*
2965                 * First word - 6 digits.
2966                 */
2967                w = serialnum[0];
2968
2969                /* Product type - 1st digit. */
2970                if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
2971                        /* Product type is P=Prototype */
2972                        *cp += 0x8;
2973                }
2974                cp++;
2975
2976                /* Manufacturing location - 2nd digit. */
2977                *cp++ = 'A' + ((w & 0x1C00) >> 10);
2978
2979                /* Product ID - 3rd, 4th digits. */
2980                num = w & 0x3FF;
2981                *cp++ = '0' + (num / 100);
2982                num %= 100;
2983                *cp++ = '0' + (num / 10);
2984
2985                /* Product revision - 5th digit. */
2986                *cp++ = 'A' + (num % 10);
2987
2988                /*
2989                 * Second word
2990                 */
2991                w = serialnum[1];
2992
2993                /*
2994                 * Year - 6th digit.
2995                 *
2996                 * If bit 15 of third word is set, then the
2997                 * last digit of the year is greater than 7.
2998                 */
2999                if (serialnum[2] & 0x8000) {
3000                        *cp++ = '8' + ((w & 0x1C0) >> 6);
3001                } else {
3002                        *cp++ = '0' + ((w & 0x1C0) >> 6);
3003                }
3004
3005                /* Week of year - 7th, 8th digits. */
3006                num = w & 0x003F;
3007                *cp++ = '0' + num / 10;
3008                num %= 10;
3009                *cp++ = '0' + num;
3010
3011                /*
3012                 * Third word
3013                 */
3014                w = serialnum[2] & 0x7FFF;
3015
3016                /* Serial number - 9th digit. */
3017                *cp++ = 'A' + (w / 1000);
3018
3019                /* 10th, 11th, 12th digits. */
3020                num = w % 1000;
3021                *cp++ = '0' + num / 100;
3022                num %= 100;
3023                *cp++ = '0' + num / 10;
3024                num %= 10;
3025                *cp++ = '0' + num;
3026
3027                *cp = '\0';     /* Null Terminate the string. */
3028                return ASC_TRUE;
3029        }
3030}
3031
3032/*
3033 * asc_prt_asc_board_eeprom()
3034 *
3035 * Print board EEPROM configuration.
3036 */
3037static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
3038{
3039        struct asc_board *boardp = shost_priv(shost);
3040        ASC_DVC_VAR *asc_dvc_varp;
3041        ASCEEP_CONFIG *ep;
3042        int i;
3043#ifdef CONFIG_ISA
3044        int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
3045#endif /* CONFIG_ISA */
3046        uchar serialstr[13];
3047
3048        asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
3049        ep = &boardp->eep_config.asc_eep;
3050
3051        seq_printf(m,
3052                   "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3053                   shost->host_no);
3054
3055        if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
3056            == ASC_TRUE)
3057                seq_printf(m, " Serial Number: %s\n", serialstr);
3058        else if (ep->adapter_info[5] == 0xBB)
3059                seq_printf(m,
3060                           " Default Settings Used for EEPROM-less Adapter.\n");
3061        else
3062                seq_printf(m,
3063                           " Serial Number Signature Not Present.\n");
3064
3065        seq_printf(m,
3066                   " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3067                   ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
3068                   ep->max_tag_qng);
3069
3070        seq_printf(m,
3071                   " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
3072
3073        seq_printf(m, " Target ID:           ");
3074        for (i = 0; i <= ASC_MAX_TID; i++)
3075                seq_printf(m, " %d", i);
3076        seq_printf(m, "\n");
3077
3078        seq_printf(m, " Disconnects:         ");
3079        for (i = 0; i <= ASC_MAX_TID; i++)
3080                seq_printf(m, " %c",
3081                           (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3082        seq_printf(m, "\n");
3083
3084        seq_printf(m, " Command Queuing:     ");
3085        for (i = 0; i <= ASC_MAX_TID; i++)
3086                seq_printf(m, " %c",
3087                           (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3088        seq_printf(m, "\n");
3089
3090        seq_printf(m, " Start Motor:         ");
3091        for (i = 0; i <= ASC_MAX_TID; i++)
3092                seq_printf(m, " %c",
3093                           (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3094        seq_printf(m, "\n");
3095
3096        seq_printf(m, " Synchronous Transfer:");
3097        for (i = 0; i <= ASC_MAX_TID; i++)
3098                seq_printf(m, " %c",
3099                           (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3100        seq_printf(m, "\n");
3101
3102#ifdef CONFIG_ISA
3103        if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
3104                seq_printf(m,
3105                           " Host ISA DMA speed:   %d MB/S\n",
3106                           isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
3107        }
3108#endif /* CONFIG_ISA */
3109}
3110
3111/*
3112 * asc_prt_adv_board_eeprom()
3113 *
3114 * Print board EEPROM configuration.
3115 */
3116static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
3117{
3118        struct asc_board *boardp = shost_priv(shost);
3119        ADV_DVC_VAR *adv_dvc_varp;
3120        int i;
3121        char *termstr;
3122        uchar serialstr[13];
3123        ADVEEP_3550_CONFIG *ep_3550 = NULL;
3124        ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3125        ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3126        ushort word;
3127        ushort *wordp;
3128        ushort sdtr_speed = 0;
3129
3130        adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3131        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3132                ep_3550 = &boardp->eep_config.adv_3550_eep;
3133        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3134                ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
3135        } else {
3136                ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
3137        }
3138
3139        seq_printf(m,
3140                   "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3141                   shost->host_no);
3142
3143        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3144                wordp = &ep_3550->serial_number_word1;
3145        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3146                wordp = &ep_38C0800->serial_number_word1;
3147        } else {
3148                wordp = &ep_38C1600->serial_number_word1;
3149        }
3150
3151        if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
3152                seq_printf(m, " Serial Number: %s\n", serialstr);
3153        else
3154                seq_printf(m, " Serial Number Signature Not Present.\n");
3155
3156        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3157                seq_printf(m,
3158                           " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3159                           ep_3550->adapter_scsi_id,
3160                           ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3161        else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3162                seq_printf(m,
3163                           " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3164                           ep_38C0800->adapter_scsi_id,
3165                           ep_38C0800->max_host_qng,
3166                           ep_38C0800->max_dvc_qng);
3167        else
3168                seq_printf(m,
3169                           " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3170                           ep_38C1600->adapter_scsi_id,
3171                           ep_38C1600->max_host_qng,
3172                           ep_38C1600->max_dvc_qng);
3173        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3174                word = ep_3550->termination;
3175        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3176                word = ep_38C0800->termination_lvd;
3177        } else {
3178                word = ep_38C1600->termination_lvd;
3179        }
3180        switch (word) {
3181        case 1:
3182                termstr = "Low Off/High Off";
3183                break;
3184        case 2:
3185                termstr = "Low Off/High On";
3186                break;
3187        case 3:
3188                termstr = "Low On/High On";
3189                break;
3190        default:
3191        case 0:
3192                termstr = "Automatic";
3193                break;
3194        }
3195
3196        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3197                seq_printf(m,
3198                           " termination: %u (%s), bios_ctrl: 0x%x\n",
3199                           ep_3550->termination, termstr,
3200                           ep_3550->bios_ctrl);
3201        else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3202                seq_printf(m,
3203                           " termination: %u (%s), bios_ctrl: 0x%x\n",
3204                           ep_38C0800->termination_lvd, termstr,
3205                           ep_38C0800->bios_ctrl);
3206        else
3207                seq_printf(m,
3208                           " termination: %u (%s), bios_ctrl: 0x%x\n",
3209                           ep_38C1600->termination_lvd, termstr,
3210                           ep_38C1600->bios_ctrl);
3211
3212        seq_printf(m, " Target ID:           ");
3213        for (i = 0; i <= ADV_MAX_TID; i++)
3214                seq_printf(m, " %X", i);
3215        seq_printf(m, "\n");
3216
3217        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3218                word = ep_3550->disc_enable;
3219        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3220                word = ep_38C0800->disc_enable;
3221        } else {
3222                word = ep_38C1600->disc_enable;
3223        }
3224        seq_printf(m, " Disconnects:         ");
3225        for (i = 0; i <= ADV_MAX_TID; i++)
3226                seq_printf(m, " %c",
3227                           (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3228        seq_printf(m, "\n");
3229
3230        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3231                word = ep_3550->tagqng_able;
3232        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3233                word = ep_38C0800->tagqng_able;
3234        } else {
3235                word = ep_38C1600->tagqng_able;
3236        }
3237        seq_printf(m, " Command Queuing:     ");
3238        for (i = 0; i <= ADV_MAX_TID; i++)
3239                seq_printf(m, " %c",
3240                           (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3241        seq_printf(m, "\n");
3242
3243        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3244                word = ep_3550->start_motor;
3245        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3246                word = ep_38C0800->start_motor;
3247        } else {
3248                word = ep_38C1600->start_motor;
3249        }
3250        seq_printf(m, " Start Motor:         ");
3251        for (i = 0; i <= ADV_MAX_TID; i++)
3252                seq_printf(m, " %c",
3253                           (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3254        seq_printf(m, "\n");
3255
3256        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3257                seq_printf(m, " Synchronous Transfer:");
3258                for (i = 0; i <= ADV_MAX_TID; i++)
3259                        seq_printf(m, " %c",
3260                                   (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3261                                   'Y' : 'N');
3262                seq_printf(m, "\n");
3263        }
3264
3265        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3266                seq_printf(m, " Ultra Transfer:      ");
3267                for (i = 0; i <= ADV_MAX_TID; i++)
3268                        seq_printf(m, " %c",
3269                                   (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
3270                                   ? 'Y' : 'N');
3271                seq_printf(m, "\n");
3272        }
3273
3274        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3275                word = ep_3550->wdtr_able;
3276        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3277                word = ep_38C0800->wdtr_able;
3278        } else {
3279                word = ep_38C1600->wdtr_able;
3280        }
3281        seq_printf(m, " Wide Transfer:       ");
3282        for (i = 0; i <= ADV_MAX_TID; i++)
3283                seq_printf(m, " %c",
3284                           (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3285        seq_printf(m, "\n");
3286
3287        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3288            adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3289                seq_printf(m,
3290                           " Synchronous Transfer Speed (Mhz):\n  ");
3291                for (i = 0; i <= ADV_MAX_TID; i++) {
3292                        char *speed_str;
3293
3294                        if (i == 0) {
3295                                sdtr_speed = adv_dvc_varp->sdtr_speed1;
3296                        } else if (i == 4) {
3297                                sdtr_speed = adv_dvc_varp->sdtr_speed2;
3298                        } else if (i == 8) {
3299                                sdtr_speed = adv_dvc_varp->sdtr_speed3;
3300                        } else if (i == 12) {
3301                                sdtr_speed = adv_dvc_varp->sdtr_speed4;
3302                        }
3303                        switch (sdtr_speed & ADV_MAX_TID) {
3304                        case 0:
3305                                speed_str = "Off";
3306                                break;
3307                        case 1:
3308                                speed_str = "  5";
3309                                break;
3310                        case 2:
3311                                speed_str = " 10";
3312                                break;
3313                        case 3:
3314                                speed_str = " 20";
3315                                break;
3316                        case 4:
3317                                speed_str = " 40";
3318                                break;
3319                        case 5:
3320                                speed_str = " 80";
3321                                break;
3322                        default:
3323                                speed_str = "Unk";
3324                                break;
3325                        }
3326                        seq_printf(m, "%X:%s ", i, speed_str);
3327                        if (i == 7)
3328                                seq_printf(m, "\n  ");
3329                        sdtr_speed >>= 4;
3330                }
3331                seq_printf(m, "\n");
3332        }
3333}
3334
3335/*
3336 * asc_prt_driver_conf()
3337 */
3338static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
3339{
3340        struct asc_board *boardp = shost_priv(shost);
3341        int chip_scsi_id;
3342
3343        seq_printf(m,
3344                "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3345                shost->host_no);
3346
3347        seq_printf(m,
3348                   " host_busy %u, last_reset %lu, max_id %u, max_lun %u, max_channel %u\n",
3349                   shost->host_busy, shost->last_reset, shost->max_id,
3350                   shost->max_lun, shost->max_channel);
3351
3352        seq_printf(m,
3353                   " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3354                   shost->unique_id, shost->can_queue, shost->this_id,
3355                   shost->sg_tablesize, shost->cmd_per_lun);
3356
3357        seq_printf(m,
3358                   " unchecked_isa_dma %d, use_clustering %d\n",
3359                   shost->unchecked_isa_dma, shost->use_clustering);
3360
3361        seq_printf(m,
3362                   " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
3363                   boardp->flags, boardp->last_reset, jiffies,
3364                   boardp->asc_n_io_port);
3365
3366        seq_printf(m, " io_port 0x%lx\n", shost->io_port);
3367
3368        if (ASC_NARROW_BOARD(boardp)) {
3369                chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3370        } else {
3371                chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3372        }
3373}
3374
3375/*
3376 * asc_prt_asc_board_info()
3377 *
3378 * Print dynamic board configuration information.
3379 */
3380static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
3381{
3382        struct asc_board *boardp = shost_priv(shost);
3383        int chip_scsi_id;
3384        ASC_DVC_VAR *v;
3385        ASC_DVC_CFG *c;
3386        int i;
3387        int renegotiate = 0;
3388
3389        v = &boardp->dvc_var.asc_dvc_var;
3390        c = &boardp->dvc_cfg.asc_dvc_cfg;
3391        chip_scsi_id = c->chip_scsi_id;
3392
3393        seq_printf(m,
3394                   "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3395                   shost->host_no);
3396
3397        seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3398                   "mcode_version 0x%x, err_code %u\n",
3399                   c->chip_version, c->mcode_date, c->mcode_version,
3400                   v->err_code);
3401
3402        /* Current number of commands waiting for the host. */
3403        seq_printf(m,
3404                   " Total Command Pending: %d\n", v->cur_total_qng);
3405
3406        seq_printf(m, " Command Queuing:");
3407        for (i = 0; i <= ASC_MAX_TID; i++) {
3408                if ((chip_scsi_id == i) ||
3409                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3410                        continue;
3411                }
3412                seq_printf(m, " %X:%c",
3413                           i,
3414                           (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3415        }
3416        seq_printf(m, "\n");
3417
3418        /* Current number of commands waiting for a device. */
3419        seq_printf(m, " Command Queue Pending:");
3420        for (i = 0; i <= ASC_MAX_TID; i++) {
3421                if ((chip_scsi_id == i) ||
3422                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3423                        continue;
3424                }
3425                seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
3426        }
3427        seq_printf(m, "\n");
3428
3429        /* Current limit on number of commands that can be sent to a device. */
3430        seq_printf(m, " Command Queue Limit:");
3431        for (i = 0; i <= ASC_MAX_TID; i++) {
3432                if ((chip_scsi_id == i) ||
3433                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3434                        continue;
3435                }
3436                seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
3437        }
3438        seq_printf(m, "\n");
3439
3440        /* Indicate whether the device has returned queue full status. */
3441        seq_printf(m, " Command Queue Full:");
3442        for (i = 0; i <= ASC_MAX_TID; i++) {
3443                if ((chip_scsi_id == i) ||
3444                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3445                        continue;
3446                }
3447                if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
3448                        seq_printf(m, " %X:Y-%d",
3449                                   i, boardp->queue_full_cnt[i]);
3450                else
3451                        seq_printf(m, " %X:N", i);
3452        }
3453        seq_printf(m, "\n");
3454
3455        seq_printf(m, " Synchronous Transfer:");
3456        for (i = 0; i <= ASC_MAX_TID; i++) {
3457                if ((chip_scsi_id == i) ||
3458                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3459                        continue;
3460                }
3461                seq_printf(m, " %X:%c",
3462                           i,
3463                           (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3464        }
3465        seq_printf(m, "\n");
3466
3467        for (i = 0; i <= ASC_MAX_TID; i++) {
3468                uchar syn_period_ix;
3469
3470                if ((chip_scsi_id == i) ||
3471                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3472                    ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3473                        continue;
3474                }
3475
3476                seq_printf(m, "  %X:", i);
3477
3478                if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3479                        seq_printf(m, " Asynchronous");
3480                } else {
3481                        syn_period_ix =
3482                            (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3483                                                           1);
3484
3485                        seq_printf(m,
3486                                   " Transfer Period Factor: %d (%d.%d Mhz),",
3487                                   v->sdtr_period_tbl[syn_period_ix],
3488                                   250 / v->sdtr_period_tbl[syn_period_ix],
3489                                   ASC_TENTHS(250,
3490                                              v->sdtr_period_tbl[syn_period_ix]));
3491
3492                        seq_printf(m, " REQ/ACK Offset: %d",
3493                                   boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3494                }
3495
3496                if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3497                        seq_printf(m, "*\n");
3498                        renegotiate = 1;
3499                } else {
3500                        seq_printf(m, "\n");
3501                }
3502        }
3503
3504        if (renegotiate) {
3505                seq_printf(m,
3506                           " * = Re-negotiation pending before next command.\n");
3507        }
3508}
3509
3510/*
3511 * asc_prt_adv_board_info()
3512 *
3513 * Print dynamic board configuration information.
3514 */
3515static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
3516{
3517        struct asc_board *boardp = shost_priv(shost);
3518        int i;
3519        ADV_DVC_VAR *v;
3520        ADV_DVC_CFG *c;
3521        AdvPortAddr iop_base;
3522        ushort chip_scsi_id;
3523        ushort lramword;
3524        uchar lrambyte;
3525        ushort tagqng_able;
3526        ushort sdtr_able, wdtr_able;
3527        ushort wdtr_done, sdtr_done;
3528        ushort period = 0;
3529        int renegotiate = 0;
3530
3531        v = &boardp->dvc_var.adv_dvc_var;
3532        c = &boardp->dvc_cfg.adv_dvc_cfg;
3533        iop_base = v->iop_base;
3534        chip_scsi_id = v->chip_scsi_id;
3535
3536        seq_printf(m,
3537                   "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3538                   shost->host_no);
3539
3540        seq_printf(m,
3541                   " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3542                   (unsigned long)v->iop_base,
3543                   AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
3544                   v->err_code);
3545
3546        seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3547                   "mcode_version 0x%x\n", c->chip_version,
3548                   c->mcode_date, c->mcode_version);
3549
3550        AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3551        seq_printf(m, " Queuing Enabled:");
3552        for (i = 0; i <= ADV_MAX_TID; i++) {
3553                if ((chip_scsi_id == i) ||
3554                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3555                        continue;
3556                }
3557
3558                seq_printf(m, " %X:%c",
3559                           i,
3560                           (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3561        }
3562        seq_printf(m, "\n");
3563
3564        seq_printf(m, " Queue Limit:");
3565        for (i = 0; i <= ADV_MAX_TID; i++) {
3566                if ((chip_scsi_id == i) ||
3567                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3568                        continue;
3569                }
3570
3571                AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3572                                lrambyte);
3573
3574                seq_printf(m, " %X:%d", i, lrambyte);
3575        }
3576        seq_printf(m, "\n");
3577
3578        seq_printf(m, " Command Pending:");
3579        for (i = 0; i <= ADV_MAX_TID; i++) {
3580                if ((chip_scsi_id == i) ||
3581                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3582                        continue;
3583                }
3584
3585                AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3586                                lrambyte);
3587
3588                seq_printf(m, " %X:%d", i, lrambyte);
3589        }
3590        seq_printf(m, "\n");
3591
3592        AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3593        seq_printf(m, " Wide Enabled:");
3594        for (i = 0; i <= ADV_MAX_TID; i++) {
3595                if ((chip_scsi_id == i) ||
3596                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3597                        continue;
3598                }
3599
3600                seq_printf(m, " %X:%c",
3601                           i,
3602                           (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3603        }
3604        seq_printf(m, "\n");
3605
3606        AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3607        seq_printf(m, " Transfer Bit Width:");
3608        for (i = 0; i <= ADV_MAX_TID; i++) {
3609                if ((chip_scsi_id == i) ||
3610                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3611                        continue;
3612                }
3613
3614                AdvReadWordLram(iop_base,
3615                                ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3616                                lramword);
3617
3618                seq_printf(m, " %X:%d",
3619                           i, (lramword & 0x8000) ? 16 : 8);
3620
3621                if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3622                    (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3623                        seq_printf(m, "*");
3624                        renegotiate = 1;
3625                }
3626        }
3627        seq_printf(m, "\n");
3628
3629        AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3630        seq_printf(m, " Synchronous Enabled:");
3631        for (i = 0; i <= ADV_MAX_TID; i++) {
3632                if ((chip_scsi_id == i) ||
3633                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3634                        continue;
3635                }
3636
3637                seq_printf(m, " %X:%c",
3638                           i,
3639                           (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3640        }
3641        seq_printf(m, "\n");
3642
3643        AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3644        for (i = 0; i <= ADV_MAX_TID; i++) {
3645
3646                AdvReadWordLram(iop_base,
3647                                ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3648                                lramword);
3649                lramword &= ~0x8000;
3650
3651                if ((chip_scsi_id == i) ||
3652                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3653                    ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3654                        continue;
3655                }
3656
3657                seq_printf(m, "  %X:", i);
3658
3659                if ((lramword & 0x1F) == 0) {   /* Check for REQ/ACK Offset 0. */
3660                        seq_printf(m, " Asynchronous");
3661                } else {
3662                        seq_printf(m, " Transfer Period Factor: ");
3663
3664                        if ((lramword & 0x1F00) == 0x1100) {    /* 80 Mhz */
3665                                seq_printf(m, "9 (80.0 Mhz),");
3666                        } else if ((lramword & 0x1F00) == 0x1000) {     /* 40 Mhz */
3667                                seq_printf(m, "10 (40.0 Mhz),");
3668                        } else {        /* 20 Mhz or below. */
3669
3670                                period = (((lramword >> 8) * 25) + 50) / 4;
3671
3672                                if (period == 0) {      /* Should never happen. */
3673                                        seq_printf(m, "%d (? Mhz), ", period);
3674                                } else {
3675                                        seq_printf(m,
3676                                                   "%d (%d.%d Mhz),",
3677                                                   period, 250 / period,
3678                                                   ASC_TENTHS(250, period));
3679                                }
3680                        }
3681
3682                        seq_printf(m, " REQ/ACK Offset: %d",
3683                                   lramword & 0x1F);
3684                }
3685
3686                if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3687                        seq_printf(m, "*\n");
3688                        renegotiate = 1;
3689                } else {
3690                        seq_printf(m, "\n");
3691                }
3692        }
3693
3694        if (renegotiate) {
3695                seq_printf(m,
3696                           " * = Re-negotiation pending before next command.\n");
3697        }
3698}
3699
3700#ifdef ADVANSYS_STATS
3701/*
3702 * asc_prt_board_stats()
3703 */
3704static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost)
3705{
3706        struct asc_board *boardp = shost_priv(shost);
3707        struct asc_stats *s = &boardp->asc_stats;
3708
3709        seq_printf(m,
3710                   "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
3711                   shost->host_no);
3712
3713        seq_printf(m,
3714                   " queuecommand %u, reset %u, biosparam %u, interrupt %u\n",
3715                   s->queuecommand, s->reset, s->biosparam,
3716                   s->interrupt);
3717
3718        seq_printf(m,
3719                   " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n",
3720                   s->callback, s->done, s->build_error,
3721                   s->adv_build_noreq, s->adv_build_nosg);
3722
3723        seq_printf(m,
3724                   " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n",
3725                   s->exe_noerror, s->exe_busy, s->exe_error,
3726                   s->exe_unknown);
3727
3728        /*
3729         * Display data transfer statistics.
3730         */
3731        if (s->xfer_cnt > 0) {
3732                seq_printf(m, " xfer_cnt %u, xfer_elem %u, ",
3733                           s->xfer_cnt, s->xfer_elem);
3734
3735                seq_printf(m, "xfer_bytes %u.%01u kb\n",
3736                           s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
3737
3738                /* Scatter gather transfer statistics */
3739                seq_printf(m, " avg_num_elem %u.%01u, ",
3740                           s->xfer_elem / s->xfer_cnt,
3741                           ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
3742
3743                seq_printf(m, "avg_elem_size %u.%01u kb, ",
3744                           (s->xfer_sect / 2) / s->xfer_elem,
3745                           ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
3746
3747                seq_printf(m, "avg_xfer_size %u.%01u kb\n",
3748                           (s->xfer_sect / 2) / s->xfer_cnt,
3749                           ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
3750        }
3751}
3752#endif /* ADVANSYS_STATS */
3753
3754/*
3755 * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...}
3756 *
3757 * m: seq_file to print into
3758 * shost: Scsi_Host
3759 *
3760 * Return the number of bytes read from or written to a
3761 * /proc/scsi/advansys/[0...] file.
3762 */
3763static int
3764advansys_show_info(struct seq_file *m, struct Scsi_Host *shost)
3765{
3766        struct asc_board *boardp = shost_priv(shost);
3767
3768        ASC_DBG(1, "begin\n");
3769
3770        /*
3771         * User read of /proc/scsi/advansys/[0...] file.
3772         */
3773
3774        /*
3775         * Get board configuration information.
3776         *
3777         * advansys_info() returns the board string from its own static buffer.
3778         */
3779        /* Copy board information. */
3780        seq_printf(m, "%s\n", (char *)advansys_info(shost));
3781        /*
3782         * Display Wide Board BIOS Information.
3783         */
3784        if (!ASC_NARROW_BOARD(boardp))
3785                asc_prt_adv_bios(m, shost);
3786
3787        /*
3788         * Display driver information for each device attached to the board.
3789         */
3790        asc_prt_board_devices(m, shost);
3791
3792        /*
3793         * Display EEPROM configuration for the board.
3794         */
3795        if (ASC_NARROW_BOARD(boardp))
3796                asc_prt_asc_board_eeprom(m, shost);
3797        else
3798                asc_prt_adv_board_eeprom(m, shost);
3799
3800        /*
3801         * Display driver configuration and information for the board.
3802         */
3803        asc_prt_driver_conf(m, shost);
3804
3805#ifdef ADVANSYS_STATS
3806        /*
3807         * Display driver statistics for the board.
3808         */
3809        asc_prt_board_stats(m, shost);
3810#endif /* ADVANSYS_STATS */
3811
3812        /*
3813         * Display Asc Library dynamic configuration information
3814         * for the board.
3815         */
3816        if (ASC_NARROW_BOARD(boardp))
3817                asc_prt_asc_board_info(m, shost);
3818        else
3819                asc_prt_adv_board_info(m, shost);
3820        return 0;
3821}
3822#endif /* CONFIG_PROC_FS */
3823
3824static void asc_scsi_done(struct scsi_cmnd *scp)
3825{
3826        scsi_dma_unmap(scp);
3827        ASC_STATS(scp->device->host, done);
3828        scp->scsi_done(scp);
3829}
3830
3831static void AscSetBank(PortAddr iop_base, uchar bank)
3832{
3833        uchar val;
3834
3835        val = AscGetChipControl(iop_base) &
3836            (~
3837             (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
3838              CC_CHIP_RESET));
3839        if (bank == 1) {
3840                val |= CC_BANK_ONE;
3841        } else if (bank == 2) {
3842                val |= CC_DIAG | CC_BANK_ONE;
3843        } else {
3844                val &= ~CC_BANK_ONE;
3845        }
3846        AscSetChipControl(iop_base, val);
3847}
3848
3849static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
3850{
3851        AscSetBank(iop_base, 1);
3852        AscWriteChipIH(iop_base, ins_code);
3853        AscSetBank(iop_base, 0);
3854}
3855
3856static int AscStartChip(PortAddr iop_base)
3857{
3858        AscSetChipControl(iop_base, 0);
3859        if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3860                return (0);
3861        }
3862        return (1);
3863}
3864
3865static int AscStopChip(PortAddr iop_base)
3866{
3867        uchar cc_val;
3868
3869        cc_val =
3870            AscGetChipControl(iop_base) &
3871            (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
3872        AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
3873        AscSetChipIH(iop_base, INS_HALT);
3874        AscSetChipIH(iop_base, INS_RFLAG_WTM);
3875        if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
3876                return (0);
3877        }
3878        return (1);
3879}
3880
3881static int AscIsChipHalted(PortAddr iop_base)
3882{
3883        if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3884                if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
3885                        return (1);
3886                }
3887        }
3888        return (0);
3889}
3890
3891static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
3892{
3893        PortAddr iop_base;
3894        int i = 10;
3895
3896        iop_base = asc_dvc->iop_base;
3897        while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
3898               && (i-- > 0)) {
3899                mdelay(100);
3900        }
3901        AscStopChip(iop_base);
3902        AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
3903        udelay(60);
3904        AscSetChipIH(iop_base, INS_RFLAG_WTM);
3905        AscSetChipIH(iop_base, INS_HALT);
3906        AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
3907        AscSetChipControl(iop_base, CC_HALT);
3908        mdelay(200);
3909        AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
3910        AscSetChipStatus(iop_base, 0);
3911        return (AscIsChipHalted(iop_base));
3912}
3913
3914static int AscFindSignature(PortAddr iop_base)
3915{
3916        ushort sig_word;
3917
3918        ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
3919                 iop_base, AscGetChipSignatureByte(iop_base));
3920        if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
3921                ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
3922                         iop_base, AscGetChipSignatureWord(iop_base));
3923                sig_word = AscGetChipSignatureWord(iop_base);
3924                if ((sig_word == (ushort)ASC_1000_ID0W) ||
3925                    (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
3926                        return (1);
3927                }
3928        }
3929        return (0);
3930}
3931
3932static void AscEnableInterrupt(PortAddr iop_base)
3933{
3934        ushort cfg;
3935
3936        cfg = AscGetChipCfgLsw(iop_base);
3937        AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
3938}
3939
3940static void AscDisableInterrupt(PortAddr iop_base)
3941{
3942        ushort cfg;
3943
3944        cfg = AscGetChipCfgLsw(iop_base);
3945        AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
3946}
3947
3948static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
3949{
3950        unsigned char byte_data;
3951        unsigned short word_data;
3952
3953        if (isodd_word(addr)) {
3954                AscSetChipLramAddr(iop_base, addr - 1);
3955                word_data = AscGetChipLramData(iop_base);
3956                byte_data = (word_data >> 8) & 0xFF;
3957        } else {
3958                AscSetChipLramAddr(iop_base, addr);
3959                word_data = AscGetChipLramData(iop_base);
3960                byte_data = word_data & 0xFF;
3961        }
3962        return byte_data;
3963}
3964
3965static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
3966{
3967        ushort word_data;
3968
3969        AscSetChipLramAddr(iop_base, addr);
3970        word_data = AscGetChipLramData(iop_base);
3971        return (word_data);
3972}
3973
3974#if CC_VERY_LONG_SG_LIST
3975static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
3976{
3977        ushort val_low, val_high;
3978        ASC_DCNT dword_data;
3979
3980        AscSetChipLramAddr(iop_base, addr);
3981        val_low = AscGetChipLramData(iop_base);
3982        val_high = AscGetChipLramData(iop_base);
3983        dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
3984        return (dword_data);
3985}
3986#endif /* CC_VERY_LONG_SG_LIST */
3987
3988static void
3989AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
3990{
3991        int i;
3992
3993        AscSetChipLramAddr(iop_base, s_addr);
3994        for (i = 0; i < words; i++) {
3995                AscSetChipLramData(iop_base, set_wval);
3996        }
3997}
3998
3999static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
4000{
4001        AscSetChipLramAddr(iop_base, addr);
4002        AscSetChipLramData(iop_base, word_val);
4003}
4004
4005static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
4006{
4007        ushort word_data;
4008
4009        if (isodd_word(addr)) {
4010                addr--;
4011                word_data = AscReadLramWord(iop_base, addr);
4012                word_data &= 0x00FF;
4013                word_data |= (((ushort)byte_val << 8) & 0xFF00);
4014        } else {
4015                word_data = AscReadLramWord(iop_base, addr);
4016                word_data &= 0xFF00;
4017                word_data |= ((ushort)byte_val & 0x00FF);
4018        }
4019        AscWriteLramWord(iop_base, addr, word_data);
4020}
4021
4022/*
4023 * Copy 2 bytes to LRAM.
4024 *
4025 * The source data is assumed to be in little-endian order in memory
4026 * and is maintained in little-endian order when written to LRAM.
4027 */
4028static void
4029AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
4030                        const uchar *s_buffer, int words)
4031{
4032        int i;
4033
4034        AscSetChipLramAddr(iop_base, s_addr);
4035        for (i = 0; i < 2 * words; i += 2) {
4036                /*
4037                 * On a little-endian system the second argument below
4038                 * produces a little-endian ushort which is written to
4039                 * LRAM in little-endian order. On a big-endian system
4040                 * the second argument produces a big-endian ushort which
4041                 * is "transparently" byte-swapped by outpw() and written
4042                 * in little-endian order to LRAM.
4043                 */
4044                outpw(iop_base + IOP_RAM_DATA,
4045                      ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
4046        }
4047}
4048
4049/*
4050 * Copy 4 bytes to LRAM.
4051 *
4052 * The source data is assumed to be in little-endian order in memory
4053 * and is maintained in little-endian order when written to LRAM.
4054 */
4055static void
4056AscMemDWordCopyPtrToLram(PortAddr iop_base,
4057                         ushort s_addr, uchar *s_buffer, int dwords)
4058{
4059        int i;
4060
4061        AscSetChipLramAddr(iop_base, s_addr);
4062        for (i = 0; i < 4 * dwords; i += 4) {
4063                outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);   /* LSW */
4064                outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]);       /* MSW */
4065        }
4066}
4067
4068/*
4069 * Copy 2 bytes from LRAM.
4070 *
4071 * The source data is assumed to be in little-endian order in LRAM
4072 * and is maintained in little-endian order when written to memory.
4073 */
4074static void
4075AscMemWordCopyPtrFromLram(PortAddr iop_base,
4076                          ushort s_addr, uchar *d_buffer, int words)
4077{
4078        int i;
4079        ushort word;
4080
4081        AscSetChipLramAddr(iop_base, s_addr);
4082        for (i = 0; i < 2 * words; i += 2) {
4083                word = inpw(iop_base + IOP_RAM_DATA);
4084                d_buffer[i] = word & 0xff;
4085                d_buffer[i + 1] = (word >> 8) & 0xff;
4086        }
4087}
4088
4089static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
4090{
4091        ASC_DCNT sum;
4092        int i;
4093
4094        sum = 0L;
4095        for (i = 0; i < words; i++, s_addr += 2) {
4096                sum += AscReadLramWord(iop_base, s_addr);
4097        }
4098        return (sum);
4099}
4100
4101static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
4102{
4103        uchar i;
4104        ushort s_addr;
4105        PortAddr iop_base;
4106        ushort warn_code;
4107
4108        iop_base = asc_dvc->iop_base;
4109        warn_code = 0;
4110        AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
4111                          (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
4112                                    64) >> 1));
4113        i = ASC_MIN_ACTIVE_QNO;
4114        s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
4115        AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4116                         (uchar)(i + 1));
4117        AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4118                         (uchar)(asc_dvc->max_total_qng));
4119        AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4120                         (uchar)i);
4121        i++;
4122        s_addr += ASC_QBLK_SIZE;
4123        for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4124                AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4125                                 (uchar)(i + 1));
4126                AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4127                                 (uchar)(i - 1));
4128                AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4129                                 (uchar)i);
4130        }
4131        AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4132                         (uchar)ASC_QLINK_END);
4133        AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4134                         (uchar)(asc_dvc->max_total_qng - 1));
4135        AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4136                         (uchar)asc_dvc->max_total_qng);
4137        i++;
4138        s_addr += ASC_QBLK_SIZE;
4139        for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4140             i++, s_addr += ASC_QBLK_SIZE) {
4141                AscWriteLramByte(iop_base,
4142                                 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4143                AscWriteLramByte(iop_base,
4144                                 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4145                AscWriteLramByte(iop_base,
4146                                 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
4147        }
4148        return warn_code;
4149}
4150
4151static ASC_DCNT
4152AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
4153                 const uchar *mcode_buf, ushort mcode_size)
4154{
4155        ASC_DCNT chksum;
4156        ushort mcode_word_size;
4157        ushort mcode_chksum;
4158
4159        /* Write the microcode buffer starting at LRAM address 0. */
4160        mcode_word_size = (ushort)(mcode_size >> 1);
4161        AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4162        AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
4163
4164        chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
4165        ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
4166        mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4167                                                 (ushort)ASC_CODE_SEC_BEG,
4168                                                 (ushort)((mcode_size -
4169                                                           s_addr - (ushort)
4170                                                           ASC_CODE_SEC_BEG) /
4171                                                          2));
4172        ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
4173        AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4174        AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
4175        return chksum;
4176}
4177
4178static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
4179{
4180        PortAddr iop_base;
4181        int i;
4182        ushort lram_addr;
4183
4184        iop_base = asc_dvc->iop_base;
4185        AscPutRiscVarFreeQHead(iop_base, 1);
4186        AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4187        AscPutVarFreeQHead(iop_base, 1);
4188        AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4189        AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
4190                         (uchar)((int)asc_dvc->max_total_qng + 1));
4191        AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
4192                         (uchar)((int)asc_dvc->max_total_qng + 2));
4193        AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
4194                         asc_dvc->max_total_qng);
4195        AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
4196        AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
4197        AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
4198        AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
4199        AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
4200        AscPutQDoneInProgress(iop_base, 0);
4201        lram_addr = ASC_QADR_BEG;
4202        for (i = 0; i < 32; i++, lram_addr += 2) {
4203                AscWriteLramWord(iop_base, lram_addr, 0);
4204        }
4205}
4206
4207static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
4208{
4209        int i;
4210        ushort warn_code;
4211        PortAddr iop_base;
4212        ASC_PADDR phy_addr;
4213        ASC_DCNT phy_size;
4214        struct asc_board *board = asc_dvc_to_board(asc_dvc);
4215
4216        iop_base = asc_dvc->iop_base;
4217        warn_code = 0;
4218        for (i = 0; i <= ASC_MAX_TID; i++) {
4219                AscPutMCodeInitSDTRAtID(iop_base, i,
4220                                        asc_dvc->cfg->sdtr_period_offset[i]);
4221        }
4222
4223        AscInitQLinkVar(asc_dvc);
4224        AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
4225                         asc_dvc->cfg->disc_enable);
4226        AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
4227                         ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
4228
4229        /* Ensure overrun buffer is aligned on an 8 byte boundary. */
4230        BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
4231        asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
4232                                        ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4233        if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
4234                warn_code = -ENOMEM;
4235                goto err_dma_map;
4236        }
4237        phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
4238        AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
4239                                 (uchar *)&phy_addr, 1);
4240        phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
4241        AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
4242                                 (uchar *)&phy_size, 1);
4243
4244        asc_dvc->cfg->mcode_date =
4245            AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
4246        asc_dvc->cfg->mcode_version =
4247            AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
4248
4249        AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
4250        if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4251                asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
4252                warn_code = UW_ERR;
4253                goto err_mcode_start;
4254        }
4255        if (AscStartChip(iop_base) != 1) {
4256                asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
4257                warn_code = UW_ERR;
4258                goto err_mcode_start;
4259        }
4260
4261        return warn_code;
4262
4263err_mcode_start:
4264        dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4265                         ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4266err_dma_map:
4267        asc_dvc->overrun_dma = 0;
4268        return warn_code;
4269}
4270
4271static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
4272{
4273        const struct firmware *fw;
4274        const char fwname[] = "advansys/mcode.bin";
4275        int err;
4276        unsigned long chksum;
4277        ushort warn_code;
4278        PortAddr iop_base;
4279
4280        iop_base = asc_dvc->iop_base;
4281        warn_code = 0;
4282        if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4283            !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4284                AscResetChipAndScsiBus(asc_dvc);
4285                mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4286        }
4287        asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4288        if (asc_dvc->err_code != 0)
4289                return UW_ERR;
4290        if (!AscFindSignature(asc_dvc->iop_base)) {
4291                asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4292                return warn_code;
4293        }
4294        AscDisableInterrupt(iop_base);
4295        warn_code |= AscInitLram(asc_dvc);
4296        if (asc_dvc->err_code != 0)
4297                return UW_ERR;
4298
4299        err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4300        if (err) {
4301                printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4302                       fwname, err);
4303                asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4304                return err;
4305        }
4306        if (fw->size < 4) {
4307                printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4308                       fw->size, fwname);
4309                release_firmware(fw);
4310                asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4311                return -EINVAL;
4312        }
4313        chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4314                 (fw->data[1] << 8) | fw->data[0];
4315        ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4316        if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4317                             fw->size - 4) != chksum) {
4318                asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4319                release_firmware(fw);
4320                return warn_code;
4321        }
4322        release_firmware(fw);
4323        warn_code |= AscInitMicroCodeVar(asc_dvc);
4324        if (!asc_dvc->overrun_dma)
4325                return warn_code;
4326        asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4327        AscEnableInterrupt(iop_base);
4328        return warn_code;
4329}
4330
4331/*
4332 * Load the Microcode
4333 *
4334 * Write the microcode image to RISC memory starting at address 0.
4335 *
4336 * The microcode is stored compressed in the following format:
4337 *
4338 *  254 word (508 byte) table indexed by byte code followed
4339 *  by the following byte codes:
4340 *
4341 *    1-Byte Code:
4342 *      00: Emit word 0 in table.
4343 *      01: Emit word 1 in table.
4344 *      .
4345 *      FD: Emit word 253 in table.
4346 *
4347 *    Multi-Byte Code:
4348 *      FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4349 *      FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4350 *
4351 * Returns 0 or an error if the checksum doesn't match
4352 */
4353static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4354                            int size, int memsize, int chksum)
4355{
4356        int i, j, end, len = 0;
4357        ADV_DCNT sum;
4358
4359        AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4360
4361        for (i = 253 * 2; i < size; i++) {
4362                if (buf[i] == 0xff) {
4363                        unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4364                        for (j = 0; j < buf[i + 1]; j++) {
4365                                AdvWriteWordAutoIncLram(iop_base, word);
4366                                len += 2;
4367                        }
4368                        i += 3;
4369                } else if (buf[i] == 0xfe) {
4370                        unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4371                        AdvWriteWordAutoIncLram(iop_base, word);
4372                        i += 2;
4373                        len += 2;
4374                } else {
4375                        unsigned int off = buf[i] * 2;
4376                        unsigned short word = (buf[off + 1] << 8) | buf[off];
4377                        AdvWriteWordAutoIncLram(iop_base, word);
4378                        len += 2;
4379                }
4380        }
4381
4382        end = len;
4383
4384        while (len < memsize) {
4385                AdvWriteWordAutoIncLram(iop_base, 0);
4386                len += 2;
4387        }
4388
4389        /* Verify the microcode checksum. */
4390        sum = 0;
4391        AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4392
4393        for (len = 0; len < end; len += 2) {
4394                sum += AdvReadWordAutoIncLram(iop_base);
4395        }
4396
4397        if (sum != chksum)
4398                return ASC_IERR_MCODE_CHKSUM;
4399
4400        return 0;
4401}
4402
4403static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc)
4404{
4405        ADV_CARR_T *carrp;
4406        ADV_SDCNT buf_size;
4407        ADV_PADDR carr_paddr;
4408
4409        carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
4410        asc_dvc->carr_freelist = NULL;
4411        if (carrp == asc_dvc->carrier_buf) {
4412                buf_size = ADV_CARRIER_BUFSIZE;
4413        } else {
4414                buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
4415        }
4416
4417        do {
4418                /* Get physical address of the carrier 'carrp'. */
4419                carr_paddr = cpu_to_le32(virt_to_bus(carrp));
4420
4421                buf_size -= sizeof(ADV_CARR_T);
4422
4423                carrp->carr_pa = carr_paddr;
4424                carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
4425
4426                /*
4427                 * Insert the carrier at the beginning of the freelist.
4428                 */
4429                carrp->next_vpa =
4430                        cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
4431                asc_dvc->carr_freelist = carrp;
4432
4433                carrp++;
4434        } while (buf_size > 0);
4435}
4436
4437/*
4438 * Send an idle command to the chip and wait for completion.
4439 *
4440 * Command completion is polled for once per microsecond.
4441 *
4442 * The function can be called from anywhere including an interrupt handler.
4443 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4444 * functions to prevent reentrancy.
4445 *
4446 * Return Values:
4447 *   ADV_TRUE - command completed successfully
4448 *   ADV_FALSE - command failed
4449 *   ADV_ERROR - command timed out
4450 */
4451static int
4452AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
4453               ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
4454{
4455        int result;
4456        ADV_DCNT i, j;
4457        AdvPortAddr iop_base;
4458
4459        iop_base = asc_dvc->iop_base;
4460
4461        /*
4462         * Clear the idle command status which is set by the microcode
4463         * to a non-zero value to indicate when the command is completed.
4464         * The non-zero result is one of the IDLE_CMD_STATUS_* values
4465         */
4466        AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4467
4468        /*
4469         * Write the idle command value after the idle command parameter
4470         * has been written to avoid a race condition. If the order is not
4471         * followed, the microcode may process the idle command before the
4472         * parameters have been written to LRAM.
4473         */
4474        AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4475                                cpu_to_le32(idle_cmd_parameter));
4476        AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4477
4478        /*
4479         * Tickle the RISC to tell it to process the idle command.
4480         */
4481        AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4482        if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4483                /*
4484                 * Clear the tickle value. In the ASC-3550 the RISC flag
4485                 * command 'clr_tickle_b' does not work unless the host
4486                 * value is cleared.
4487                 */
4488                AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4489        }
4490
4491        /* Wait for up to 100 millisecond for the idle command to timeout. */
4492        for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4493                /* Poll once each microsecond for command completion. */
4494                for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4495                        AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4496                                        result);
4497                        if (result != 0)
4498                                return result;
4499                        udelay(1);
4500                }
4501        }
4502
4503        BUG();          /* The idle command should never timeout. */
4504        return ADV_ERROR;
4505}
4506
4507/*
4508 * Reset SCSI Bus and purge all outstanding requests.
4509 *
4510 * Return Value:
4511 *      ADV_TRUE(1) -   All requests are purged and SCSI Bus is reset.
4512 *      ADV_FALSE(0) -  Microcode command failed.
4513 *      ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
4514 *                      may be hung which requires driver recovery.
4515 */
4516static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
4517{
4518        int status;
4519
4520        /*
4521         * Send the SCSI Bus Reset idle start idle command which asserts
4522         * the SCSI Bus Reset signal.
4523         */
4524        status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
4525        if (status != ADV_TRUE) {
4526                return status;
4527        }
4528
4529        /*
4530         * Delay for the specified SCSI Bus Reset hold time.
4531         *
4532         * The hold time delay is done on the host because the RISC has no
4533         * microsecond accurate timer.
4534         */
4535        udelay(ASC_SCSI_RESET_HOLD_TIME_US);
4536
4537        /*
4538         * Send the SCSI Bus Reset end idle command which de-asserts
4539         * the SCSI Bus Reset signal and purges any pending requests.
4540         */
4541        status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
4542        if (status != ADV_TRUE) {
4543                return status;
4544        }
4545
4546        mdelay(asc_dvc->scsi_reset_wait * 1000);        /* XXX: msleep? */
4547
4548        return status;
4549}
4550
4551/*
4552 * Initialize the ASC-3550.
4553 *
4554 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4555 *
4556 * For a non-fatal error return a warning code. If there are no warnings
4557 * then 0 is returned.
4558 *
4559 * Needed after initialization for error recovery.
4560 */
4561static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
4562{
4563        const struct firmware *fw;
4564        const char fwname[] = "advansys/3550.bin";
4565        AdvPortAddr iop_base;
4566        ushort warn_code;
4567        int begin_addr;
4568        int end_addr;
4569        ushort code_sum;
4570        int word;
4571        int i;
4572        int err;
4573        unsigned long chksum;
4574        ushort scsi_cfg1;
4575        uchar tid;
4576        ushort bios_mem[ASC_MC_BIOSLEN / 2];    /* BIOS RISC Memory 0x40-0x8F. */
4577        ushort wdtr_able = 0, sdtr_able, tagqng_able;
4578        uchar max_cmd[ADV_MAX_TID + 1];
4579
4580        /* If there is already an error, don't continue. */
4581        if (asc_dvc->err_code != 0)
4582                return ADV_ERROR;
4583
4584        /*
4585         * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
4586         */
4587        if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
4588                asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4589                return ADV_ERROR;
4590        }
4591
4592        warn_code = 0;
4593        iop_base = asc_dvc->iop_base;
4594
4595        /*
4596         * Save the RISC memory BIOS region before writing the microcode.
4597         * The BIOS may already be loaded and using its RISC LRAM region
4598         * so its region must be saved and restored.
4599         *
4600         * Note: This code makes the assumption, which is currently true,
4601         * that a chip reset does not clear RISC LRAM.
4602         */
4603        for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4604                AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4605                                bios_mem[i]);
4606        }
4607
4608        /*
4609         * Save current per TID negotiated values.
4610         */
4611        if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
4612                ushort bios_version, major, minor;
4613
4614                bios_version =
4615                    bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
4616                major = (bios_version >> 12) & 0xF;
4617                minor = (bios_version >> 8) & 0xF;
4618                if (major < 3 || (major == 3 && minor == 1)) {
4619                        /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
4620                        AdvReadWordLram(iop_base, 0x120, wdtr_able);
4621                } else {
4622                        AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4623                }
4624        }
4625        AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4626        AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4627        for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4628                AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4629                                max_cmd[tid]);
4630        }
4631
4632        err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4633        if (err) {
4634                printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4635                       fwname, err);
4636                asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4637                return err;
4638        }
4639        if (fw->size < 4) {
4640                printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4641                       fw->size, fwname);
4642                release_firmware(fw);
4643                asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4644                return -EINVAL;
4645        }
4646        chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4647                 (fw->data[1] << 8) | fw->data[0];
4648        asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4649                                             fw->size - 4, ADV_3550_MEMSIZE,
4650                                             chksum);
4651        release_firmware(fw);
4652        if (asc_dvc->err_code)
4653                return ADV_ERROR;
4654
4655        /*
4656         * Restore the RISC memory BIOS region.
4657         */
4658        for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4659                AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4660                                 bios_mem[i]);
4661        }
4662
4663        /*
4664         * Calculate and write the microcode code checksum to the microcode
4665         * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
4666         */
4667        AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
4668        AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
4669        code_sum = 0;
4670        AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
4671        for (word = begin_addr; word < end_addr; word += 2) {
4672                code_sum += AdvReadWordAutoIncLram(iop_base);
4673        }
4674        AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
4675
4676        /*
4677         * Read and save microcode version and date.
4678         */
4679        AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
4680                        asc_dvc->cfg->mcode_date);
4681        AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
4682                        asc_dvc->cfg->mcode_version);
4683
4684        /*
4685         * Set the chip type to indicate the ASC3550.
4686         */
4687        AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
4688
4689        /*
4690         * If the PCI Configuration Command Register "Parity Error Response
4691         * Control" Bit was clear (0), then set the microcode variable
4692         * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
4693         * to ignore DMA parity errors.
4694         */
4695        if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
4696                AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4697                word |= CONTROL_FLAG_IGNORE_PERR;
4698                AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4699        }
4700
4701        /*
4702         * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
4703         * threshold of 128 bytes. This register is only accessible to the host.
4704         */
4705        AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
4706                             START_CTL_EMFU | READ_CMD_MRM);
4707
4708        /*
4709         * Microcode operating variables for WDTR, SDTR, and command tag
4710         * queuing will be set in slave_configure() based on what a
4711         * device reports it is capable of in Inquiry byte 7.
4712         *
4713         * If SCSI Bus Resets have been disabled, then directly set
4714         * SDTR and WDTR from the EEPROM configuration. This will allow
4715         * the BIOS and warm boot to work without a SCSI bus hang on
4716         * the Inquiry caused by host and target mismatched DTR values.
4717         * Without the SCSI Bus Reset, before an Inquiry a device can't
4718         * be assumed to be in Asynchronous, Narrow mode.
4719         */
4720        if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
4721                AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
4722                                 asc_dvc->wdtr_able);
4723                AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
4724                                 asc_dvc->sdtr_able);
4725        }
4726
4727        /*
4728         * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
4729         * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
4730         * bitmask. These values determine the maximum SDTR speed negotiated
4731         * with a device.
4732         *
4733         * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
4734         * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
4735         * without determining here whether the device supports SDTR.
4736         *
4737         * 4-bit speed  SDTR speed name
4738         * ===========  ===============
4739         * 0000b (0x0)  SDTR disabled
4740         * 0001b (0x1)  5 Mhz
4741         * 0010b (0x2)  10 Mhz
4742         * 0011b (0x3)  20 Mhz (Ultra)
4743         * 0100b (0x4)  40 Mhz (LVD/Ultra2)
4744         * 0101b (0x5)  80 Mhz (LVD2/Ultra3)
4745         * 0110b (0x6)  Undefined
4746         * .
4747         * 1111b (0xF)  Undefined
4748         */
4749        word = 0;
4750        for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4751                if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
4752                        /* Set Ultra speed for TID 'tid'. */
4753                        word |= (0x3 << (4 * (tid % 4)));
4754                } else {
4755                        /* Set Fast speed for TID 'tid'. */
4756                        word |= (0x2 << (4 * (tid % 4)));
4757                }
4758                if (tid == 3) { /* Check if done with sdtr_speed1. */
4759                        AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
4760                        word = 0;
4761                } else if (tid == 7) {  /* Check if done with sdtr_speed2. */
4762                        AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
4763                        word = 0;
4764                } else if (tid == 11) { /* Check if done with sdtr_speed3. */
4765                        AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
4766                        word = 0;
4767                } else if (tid == 15) { /* Check if done with sdtr_speed4. */
4768                        AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
4769                        /* End of loop. */
4770                }
4771        }
4772
4773        /*
4774         * Set microcode operating variable for the disconnect per TID bitmask.
4775         */
4776        AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
4777                         asc_dvc->cfg->disc_enable);
4778
4779        /*
4780         * Set SCSI_CFG0 Microcode Default Value.
4781         *
4782         * The microcode will set the SCSI_CFG0 register using this value
4783         * after it is started below.
4784         */
4785        AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
4786                         PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
4787                         asc_dvc->chip_scsi_id);
4788
4789        /*
4790         * Determine SCSI_CFG1 Microcode Default Value.
4791         *
4792         * The microcode will set the SCSI_CFG1 register using this value
4793         * after it is started below.
4794         */
4795
4796        /* Read current SCSI_CFG1 Register value. */
4797        scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
4798
4799        /*
4800         * If all three connectors are in use, return an error.
4801         */
4802        if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
4803            (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
4804                asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
4805                return ADV_ERROR;
4806        }
4807
4808        /*
4809         * If the internal narrow cable is reversed all of the SCSI_CTRL
4810         * register signals will be set. Check for and return an error if
4811         * this condition is found.
4812         */
4813        if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
4814                asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
4815                return ADV_ERROR;
4816        }
4817
4818        /*
4819         * If this is a differential board and a single-ended device
4820         * is attached to one of the connectors, return an error.
4821         */
4822        if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
4823                asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
4824                return ADV_ERROR;
4825        }
4826
4827        /*
4828         * If automatic termination control is enabled, then set the
4829         * termination value based on a table listed in a_condor.h.
4830         *
4831         * If manual termination was specified with an EEPROM setting
4832         * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
4833         * is ready to be 'ored' into SCSI_CFG1.
4834         */
4835        if (asc_dvc->cfg->termination == 0) {
4836                /*
4837                 * The software always controls termination by setting TERM_CTL_SEL.
4838                 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
4839                 */
4840                asc_dvc->cfg->termination |= TERM_CTL_SEL;
4841
4842                switch (scsi_cfg1 & CABLE_DETECT) {
4843                        /* TERM_CTL_H: on, TERM_CTL_L: on */
4844                case 0x3:
4845                case 0x7:
4846                case 0xB:
4847                case 0xD:
4848                case 0xE:
4849                case 0xF:
4850                        asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
4851                        break;
4852
4853                        /* TERM_CTL_H: on, TERM_CTL_L: off */
4854                case 0x1:
4855                case 0x5:
4856                case 0x9:
4857                case 0xA:
4858                case 0xC:
4859                        asc_dvc->cfg->termination |= TERM_CTL_H;
4860                        break;
4861
4862                        /* TERM_CTL_H: off, TERM_CTL_L: off */
4863                case 0x2:
4864                case 0x6:
4865                        break;
4866                }
4867        }
4868
4869        /*
4870         * Clear any set TERM_CTL_H and TERM_CTL_L bits.
4871         */
4872        scsi_cfg1 &= ~TERM_CTL;
4873
4874        /*
4875         * Invert the TERM_CTL_H and TERM_CTL_L bits and then
4876         * set 'scsi_cfg1'. The TERM_POL bit does not need to be
4877         * referenced, because the hardware internally inverts
4878         * the Termination High and Low bits if TERM_POL is set.
4879         */
4880        scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
4881
4882        /*
4883         * Set SCSI_CFG1 Microcode Default Value
4884         *
4885         * Set filter value and possibly modified termination control
4886         * bits in the Microcode SCSI_CFG1 Register Value.
4887         *
4888         * The microcode will set the SCSI_CFG1 register using this value
4889         * after it is started below.
4890         */
4891        AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
4892                         FLTR_DISABLE | scsi_cfg1);
4893
4894        /*
4895         * Set MEM_CFG Microcode Default Value
4896         *
4897         * The microcode will set the MEM_CFG register using this value
4898         * after it is started below.
4899         *
4900         * MEM_CFG may be accessed as a word or byte, but only bits 0-7
4901         * are defined.
4902         *
4903         * ASC-3550 has 8KB internal memory.
4904         */
4905        AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
4906                         BIOS_EN | RAM_SZ_8KB);
4907
4908        /*
4909         * Set SEL_MASK Microcode Default Value
4910         *
4911         * The microcode will set the SEL_MASK register using this value
4912         * after it is started below.
4913         */
4914        AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
4915                         ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
4916
4917        AdvBuildCarrierFreelist(asc_dvc);
4918
4919        /*
4920         * Set-up the Host->RISC Initiator Command Queue (ICQ).
4921         */
4922
4923        if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
4924                asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4925                return ADV_ERROR;
4926        }
4927        asc_dvc->carr_freelist = (ADV_CARR_T *)
4928            ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
4929
4930        /*
4931         * The first command issued will be placed in the stopper carrier.
4932         */
4933        asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4934
4935        /*
4936         * Set RISC ICQ physical address start value.
4937         */
4938        AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
4939
4940        /*
4941         * Set-up the RISC->Host Initiator Response Queue (IRQ).
4942         */
4943        if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
4944                asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4945                return ADV_ERROR;
4946        }
4947        asc_dvc->carr_freelist = (ADV_CARR_T *)
4948            ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
4949
4950        /*
4951         * The first command completed by the RISC will be placed in
4952         * the stopper.
4953         *
4954         * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
4955         * completed the RISC will set the ASC_RQ_STOPPER bit.
4956         */
4957        asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4958
4959        /*
4960         * Set RISC IRQ physical address start value.
4961         */
4962        AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
4963        asc_dvc->carr_pending_cnt = 0;
4964
4965        AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
4966                             (ADV_INTR_ENABLE_HOST_INTR |
4967                              ADV_INTR_ENABLE_GLOBAL_INTR));
4968
4969        AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
4970        AdvWriteWordRegister(iop_base, IOPW_PC, word);
4971
4972        /* finally, finally, gentlemen, start your engine */
4973        AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
4974
4975        /*
4976         * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
4977         * Resets should be performed. The RISC has to be running
4978         * to issue a SCSI Bus Reset.
4979         */
4980        if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
4981                /*
4982                 * If the BIOS Signature is present in memory, restore the
4983                 * BIOS Handshake Configuration Table and do not perform
4984                 * a SCSI Bus Reset.
4985                 */
4986                if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
4987                    0x55AA) {
4988                        /*
4989                         * Restore per TID negotiated values.
4990                         */
4991                        AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4992                        AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4993                        AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
4994                                         tagqng_able);
4995                        for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4996                                AdvWriteByteLram(iop_base,
4997                                                 ASC_MC_NUMBER_OF_MAX_CMD + tid,
4998                                                 max_cmd[tid]);
4999                        }
5000                } else {
5001                        if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5002                                warn_code = ASC_WARN_BUSRESET_ERROR;
5003                        }
5004                }
5005        }
5006
5007        return warn_code;
5008}
5009
5010/*
5011 * Initialize the ASC-38C0800.
5012 *
5013 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
5014 *
5015 * For a non-fatal error return a warning code. If there are no warnings
5016 * then 0 is returned.
5017 *
5018 * Needed after initialization for error recovery.
5019 */
5020static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
5021{
5022        const struct firmware *fw;
5023        const char fwname[] = "advansys/38C0800.bin";
5024        AdvPortAddr iop_base;
5025        ushort warn_code;
5026        int begin_addr;
5027        int end_addr;
5028        ushort code_sum;
5029        int word;
5030        int i;
5031        int err;
5032        unsigned long chksum;
5033        ushort scsi_cfg1;
5034        uchar byte;
5035        uchar tid;
5036        ushort bios_mem[ASC_MC_BIOSLEN / 2];    /* BIOS RISC Memory 0x40-0x8F. */
5037        ushort wdtr_able, sdtr_able, tagqng_able;
5038        uchar max_cmd[ADV_MAX_TID + 1];
5039
5040        /* If there is already an error, don't continue. */
5041        if (asc_dvc->err_code != 0)
5042                return ADV_ERROR;
5043
5044        /*
5045         * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
5046         */
5047        if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
5048                asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5049                return ADV_ERROR;
5050        }
5051
5052        warn_code = 0;
5053        iop_base = asc_dvc->iop_base;
5054
5055        /*
5056         * Save the RISC memory BIOS region before writing the microcode.
5057         * The BIOS may already be loaded and using its RISC LRAM region
5058         * so its region must be saved and restored.
5059         *
5060         * Note: This code makes the assumption, which is currently true,
5061         * that a chip reset does not clear RISC LRAM.
5062         */
5063        for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5064                AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5065                                bios_mem[i]);
5066        }
5067
5068        /*
5069         * Save current per TID negotiated values.
5070         */
5071        AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5072        AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5073        AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5074        for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5075                AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5076                                max_cmd[tid]);
5077        }
5078
5079        /*
5080         * RAM BIST (RAM Built-In Self Test)
5081         *
5082         * Address : I/O base + offset 0x38h register (byte).
5083         * Function: Bit 7-6(RW) : RAM mode
5084         *                          Normal Mode   : 0x00
5085         *                          Pre-test Mode : 0x40
5086         *                          RAM Test Mode : 0x80
5087         *           Bit 5       : unused
5088         *           Bit 4(RO)   : Done bit
5089         *           Bit 3-0(RO) : Status
5090         *                          Host Error    : 0x08
5091         *                          Int_RAM Error : 0x04
5092         *                          RISC Error    : 0x02
5093         *                          SCSI Error    : 0x01
5094         *                          No Error      : 0x00
5095         *
5096         * Note: RAM BIST code should be put right here, before loading the
5097         * microcode and after saving the RISC memory BIOS region.
5098         */
5099
5100        /*
5101         * LRAM Pre-test
5102         *
5103         * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5104         * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5105         * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5106         * to NORMAL_MODE, return an error too.
5107         */
5108        for (i = 0; i < 2; i++) {
5109                AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5110                mdelay(10);     /* Wait for 10ms before reading back. */
5111                byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5112                if ((byte & RAM_TEST_DONE) == 0
5113                    || (byte & 0x0F) != PRE_TEST_VALUE) {
5114                        asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5115                        return ADV_ERROR;
5116                }
5117
5118                AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5119                mdelay(10);     /* Wait for 10ms before reading back. */
5120                if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5121                    != NORMAL_VALUE) {
5122                        asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5123                        return ADV_ERROR;
5124                }
5125        }
5126
5127        /*
5128         * LRAM Test - It takes about 1.5 ms to run through the test.
5129         *
5130         * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5131         * If Done bit not set or Status not 0, save register byte, set the
5132         * err_code, and return an error.
5133         */
5134        AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5135        mdelay(10);     /* Wa