linux/drivers/pinctrl/pinctrl-at91.c
<<
>>
Prefs
   1/*
   2 * at91 pinctrl driver based on at91 pinmux core
   3 *
   4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   5 *
   6 * Under GPLv2 only
   7 */
   8
   9#include <linux/clk.h>
  10#include <linux/err.h>
  11#include <linux/init.h>
  12#include <linux/module.h>
  13#include <linux/of.h>
  14#include <linux/of_device.h>
  15#include <linux/of_address.h>
  16#include <linux/of_irq.h>
  17#include <linux/slab.h>
  18#include <linux/interrupt.h>
  19#include <linux/irq.h>
  20#include <linux/irqdomain.h>
  21#include <linux/irqchip/chained_irq.h>
  22#include <linux/io.h>
  23#include <linux/gpio.h>
  24#include <linux/pinctrl/machine.h>
  25#include <linux/pinctrl/pinconf.h>
  26#include <linux/pinctrl/pinctrl.h>
  27#include <linux/pinctrl/pinmux.h>
  28/* Since we request GPIOs from ourself */
  29#include <linux/pinctrl/consumer.h>
  30
  31#include <mach/hardware.h>
  32#include <mach/at91_pio.h>
  33
  34#include "core.h"
  35
  36#define MAX_NB_GPIO_PER_BANK    32
  37
  38struct at91_pinctrl_mux_ops;
  39
  40struct at91_gpio_chip {
  41        struct gpio_chip        chip;
  42        struct pinctrl_gpio_range range;
  43        struct at91_gpio_chip   *next;          /* Bank sharing same clock */
  44        int                     pioc_hwirq;     /* PIO bank interrupt identifier on AIC */
  45        int                     pioc_virq;      /* PIO bank Linux virtual interrupt */
  46        int                     pioc_idx;       /* PIO bank index */
  47        void __iomem            *regbase;       /* PIO bank virtual address */
  48        struct clk              *clock;         /* associated clock */
  49        struct irq_domain       *domain;        /* associated irq domain */
  50        struct at91_pinctrl_mux_ops *ops;       /* ops */
  51};
  52
  53#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
  54
  55static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
  56
  57static int gpio_banks;
  58
  59#define PULL_UP         (1 << 0)
  60#define MULTI_DRIVE     (1 << 1)
  61#define DEGLITCH        (1 << 2)
  62#define PULL_DOWN       (1 << 3)
  63#define DIS_SCHMIT      (1 << 4)
  64#define DEBOUNCE        (1 << 16)
  65#define DEBOUNCE_VAL_SHIFT      17
  66#define DEBOUNCE_VAL    (0x3fff << DEBOUNCE_VAL_SHIFT)
  67
  68/**
  69 * struct at91_pmx_func - describes AT91 pinmux functions
  70 * @name: the name of this specific function
  71 * @groups: corresponding pin groups
  72 * @ngroups: the number of groups
  73 */
  74struct at91_pmx_func {
  75        const char      *name;
  76        const char      **groups;
  77        unsigned        ngroups;
  78};
  79
  80enum at91_mux {
  81        AT91_MUX_GPIO = 0,
  82        AT91_MUX_PERIPH_A = 1,
  83        AT91_MUX_PERIPH_B = 2,
  84        AT91_MUX_PERIPH_C = 3,
  85        AT91_MUX_PERIPH_D = 4,
  86};
  87
  88/**
  89 * struct at91_pmx_pin - describes an At91 pin mux
  90 * @bank: the bank of the pin
  91 * @pin: the pin number in the @bank
  92 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
  93 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
  94 */
  95struct at91_pmx_pin {
  96        uint32_t        bank;
  97        uint32_t        pin;
  98        enum at91_mux   mux;
  99        unsigned long   conf;
 100};
 101
 102/**
 103 * struct at91_pin_group - describes an At91 pin group
 104 * @name: the name of this specific pin group
 105 * @pins_conf: the mux mode for each pin in this group. The size of this
 106 *      array is the same as pins.
 107 * @pins: an array of discrete physical pins used in this group, taken
 108 *      from the driver-local pin enumeration space
 109 * @npins: the number of pins in this group array, i.e. the number of
 110 *      elements in .pins so we can iterate over that array
 111 */
 112struct at91_pin_group {
 113        const char              *name;
 114        struct at91_pmx_pin     *pins_conf;
 115        unsigned int            *pins;
 116        unsigned                npins;
 117};
 118
 119/**
 120 * struct at91_pinctrl_mux_ops - describes an At91 mux ops group
 121 * on new IP with support for periph C and D the way to mux in
 122 * periph A and B has changed
 123 * So provide the right call back
 124 * if not present means the IP does not support it
 125 * @get_periph: return the periph mode configured
 126 * @mux_A_periph: mux as periph A
 127 * @mux_B_periph: mux as periph B
 128 * @mux_C_periph: mux as periph C
 129 * @mux_D_periph: mux as periph D
 130 * @get_deglitch: get deglitch status
 131 * @set_deglitch: enable/disable deglitch
 132 * @get_debounce: get debounce status
 133 * @set_debounce: enable/disable debounce
 134 * @get_pulldown: get pulldown status
 135 * @set_pulldown: enable/disable pulldown
 136 * @get_schmitt_trig: get schmitt trigger status
 137 * @disable_schmitt_trig: disable schmitt trigger
 138 * @irq_type: return irq type
 139 */
 140struct at91_pinctrl_mux_ops {
 141        enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
 142        void (*mux_A_periph)(void __iomem *pio, unsigned mask);
 143        void (*mux_B_periph)(void __iomem *pio, unsigned mask);
 144        void (*mux_C_periph)(void __iomem *pio, unsigned mask);
 145        void (*mux_D_periph)(void __iomem *pio, unsigned mask);
 146        bool (*get_deglitch)(void __iomem *pio, unsigned pin);
 147        void (*set_deglitch)(void __iomem *pio, unsigned mask, bool in_on);
 148        bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
 149        void (*set_debounce)(void __iomem *pio, unsigned mask, bool in_on, u32 div);
 150        bool (*get_pulldown)(void __iomem *pio, unsigned pin);
 151        void (*set_pulldown)(void __iomem *pio, unsigned mask, bool in_on);
 152        bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
 153        void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
 154        /* irq */
 155        int (*irq_type)(struct irq_data *d, unsigned type);
 156};
 157
 158static int gpio_irq_type(struct irq_data *d, unsigned type);
 159static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
 160
 161struct at91_pinctrl {
 162        struct device           *dev;
 163        struct pinctrl_dev      *pctl;
 164
 165        int                     nbanks;
 166
 167        uint32_t                *mux_mask;
 168        int                     nmux;
 169
 170        struct at91_pmx_func    *functions;
 171        int                     nfunctions;
 172
 173        struct at91_pin_group   *groups;
 174        int                     ngroups;
 175
 176        struct at91_pinctrl_mux_ops *ops;
 177};
 178
 179static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name(
 180                                const struct at91_pinctrl *info,
 181                                const char *name)
 182{
 183        const struct at91_pin_group *grp = NULL;
 184        int i;
 185
 186        for (i = 0; i < info->ngroups; i++) {
 187                if (strcmp(info->groups[i].name, name))
 188                        continue;
 189
 190                grp = &info->groups[i];
 191                dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
 192                break;
 193        }
 194
 195        return grp;
 196}
 197
 198static int at91_get_groups_count(struct pinctrl_dev *pctldev)
 199{
 200        struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 201
 202        return info->ngroups;
 203}
 204
 205static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
 206                                       unsigned selector)
 207{
 208        struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 209
 210        return info->groups[selector].name;
 211}
 212
 213static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 214                               const unsigned **pins,
 215                               unsigned *npins)
 216{
 217        struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 218
 219        if (selector >= info->ngroups)
 220                return -EINVAL;
 221
 222        *pins = info->groups[selector].pins;
 223        *npins = info->groups[selector].npins;
 224
 225        return 0;
 226}
 227
 228static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 229                   unsigned offset)
 230{
 231        seq_printf(s, "%s", dev_name(pctldev->dev));
 232}
 233
 234static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
 235                        struct device_node *np,
 236                        struct pinctrl_map **map, unsigned *num_maps)
 237{
 238        struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 239        const struct at91_pin_group *grp;
 240        struct pinctrl_map *new_map;
 241        struct device_node *parent;
 242        int map_num = 1;
 243        int i;
 244
 245        /*
 246         * first find the group of this node and check if we need create
 247         * config maps for pins
 248         */
 249        grp = at91_pinctrl_find_group_by_name(info, np->name);
 250        if (!grp) {
 251                dev_err(info->dev, "unable to find group for node %s\n",
 252                        np->name);
 253                return -EINVAL;
 254        }
 255
 256        map_num += grp->npins;
 257        new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL);
 258        if (!new_map)
 259                return -ENOMEM;
 260
 261        *map = new_map;
 262        *num_maps = map_num;
 263
 264        /* create mux map */
 265        parent = of_get_parent(np);
 266        if (!parent) {
 267                devm_kfree(pctldev->dev, new_map);
 268                return -EINVAL;
 269        }
 270        new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 271        new_map[0].data.mux.function = parent->name;
 272        new_map[0].data.mux.group = np->name;
 273        of_node_put(parent);
 274
 275        /* create config map */
 276        new_map++;
 277        for (i = 0; i < grp->npins; i++) {
 278                new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 279                new_map[i].data.configs.group_or_pin =
 280                                pin_get_name(pctldev, grp->pins[i]);
 281                new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
 282                new_map[i].data.configs.num_configs = 1;
 283        }
 284
 285        dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 286                (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 287
 288        return 0;
 289}
 290
 291static void at91_dt_free_map(struct pinctrl_dev *pctldev,
 292                                struct pinctrl_map *map, unsigned num_maps)
 293{
 294}
 295
 296static const struct pinctrl_ops at91_pctrl_ops = {
 297        .get_groups_count       = at91_get_groups_count,
 298        .get_group_name         = at91_get_group_name,
 299        .get_group_pins         = at91_get_group_pins,
 300        .pin_dbg_show           = at91_pin_dbg_show,
 301        .dt_node_to_map         = at91_dt_node_to_map,
 302        .dt_free_map            = at91_dt_free_map,
 303};
 304
 305static void __iomem *pin_to_controller(struct at91_pinctrl *info,
 306                                 unsigned int bank)
 307{
 308        return gpio_chips[bank]->regbase;
 309}
 310
 311static inline int pin_to_bank(unsigned pin)
 312{
 313        return pin /= MAX_NB_GPIO_PER_BANK;
 314}
 315
 316static unsigned pin_to_mask(unsigned int pin)
 317{
 318        return 1 << pin;
 319}
 320
 321static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
 322{
 323        writel_relaxed(mask, pio + PIO_IDR);
 324}
 325
 326static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
 327{
 328        return (readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1;
 329}
 330
 331static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
 332{
 333        writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
 334}
 335
 336static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
 337{
 338        return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
 339}
 340
 341static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
 342{
 343        writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
 344}
 345
 346static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
 347{
 348        writel_relaxed(mask, pio + PIO_ASR);
 349}
 350
 351static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
 352{
 353        writel_relaxed(mask, pio + PIO_BSR);
 354}
 355
 356static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
 357{
 358
 359        writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
 360                                                pio + PIO_ABCDSR1);
 361        writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
 362                                                pio + PIO_ABCDSR2);
 363}
 364
 365static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
 366{
 367        writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
 368                                                pio + PIO_ABCDSR1);
 369        writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
 370                                                pio + PIO_ABCDSR2);
 371}
 372
 373static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
 374{
 375        writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
 376        writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
 377}
 378
 379static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
 380{
 381        writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
 382        writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
 383}
 384
 385static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
 386{
 387        unsigned select;
 388
 389        if (readl_relaxed(pio + PIO_PSR) & mask)
 390                return AT91_MUX_GPIO;
 391
 392        select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
 393        select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
 394
 395        return select + 1;
 396}
 397
 398static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
 399{
 400        unsigned select;
 401
 402        if (readl_relaxed(pio + PIO_PSR) & mask)
 403                return AT91_MUX_GPIO;
 404
 405        select = readl_relaxed(pio + PIO_ABSR) & mask;
 406
 407        return select + 1;
 408}
 409
 410static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
 411{
 412        return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1;
 413}
 414
 415static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
 416{
 417        __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
 418}
 419
 420static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
 421{
 422        if (is_on)
 423                __raw_writel(mask, pio + PIO_IFSCDR);
 424        at91_mux_set_deglitch(pio, mask, is_on);
 425}
 426
 427static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
 428{
 429        *div = __raw_readl(pio + PIO_SCDR);
 430
 431        return (__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1;
 432}
 433
 434static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
 435                                bool is_on, u32 div)
 436{
 437        if (is_on) {
 438                __raw_writel(mask, pio + PIO_IFSCER);
 439                __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
 440                __raw_writel(mask, pio + PIO_IFER);
 441        } else {
 442                __raw_writel(mask, pio + PIO_IFDR);
 443        }
 444}
 445
 446static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
 447{
 448        return (__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1;
 449}
 450
 451static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
 452{
 453        __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
 454}
 455
 456static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
 457{
 458        __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
 459}
 460
 461static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
 462{
 463        return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1;
 464}
 465
 466static struct at91_pinctrl_mux_ops at91rm9200_ops = {
 467        .get_periph     = at91_mux_get_periph,
 468        .mux_A_periph   = at91_mux_set_A_periph,
 469        .mux_B_periph   = at91_mux_set_B_periph,
 470        .get_deglitch   = at91_mux_get_deglitch,
 471        .set_deglitch   = at91_mux_set_deglitch,
 472        .irq_type       = gpio_irq_type,
 473};
 474
 475static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
 476        .get_periph     = at91_mux_pio3_get_periph,
 477        .mux_A_periph   = at91_mux_pio3_set_A_periph,
 478        .mux_B_periph   = at91_mux_pio3_set_B_periph,
 479        .mux_C_periph   = at91_mux_pio3_set_C_periph,
 480        .mux_D_periph   = at91_mux_pio3_set_D_periph,
 481        .get_deglitch   = at91_mux_get_deglitch,
 482        .set_deglitch   = at91_mux_pio3_set_deglitch,
 483        .get_debounce   = at91_mux_pio3_get_debounce,
 484        .set_debounce   = at91_mux_pio3_set_debounce,
 485        .get_pulldown   = at91_mux_pio3_get_pulldown,
 486        .set_pulldown   = at91_mux_pio3_set_pulldown,
 487        .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
 488        .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
 489        .irq_type       = alt_gpio_irq_type,
 490};
 491
 492static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
 493{
 494        if (pin->mux) {
 495                dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n",
 496                        pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
 497        } else {
 498                dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n",
 499                        pin->bank + 'A', pin->pin, pin->conf);
 500        }
 501}
 502
 503static int pin_check_config(struct at91_pinctrl *info, const char *name,
 504                            int index, const struct at91_pmx_pin *pin)
 505{
 506        int mux;
 507
 508        /* check if it's a valid config */
 509        if (pin->bank >= info->nbanks) {
 510                dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
 511                        name, index, pin->bank, info->nbanks);
 512                return -EINVAL;
 513        }
 514
 515        if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
 516                dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
 517                        name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
 518                return -EINVAL;
 519        }
 520
 521        if (!pin->mux)
 522                return 0;
 523
 524        mux = pin->mux - 1;
 525
 526        if (mux >= info->nmux) {
 527                dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
 528                        name, index, mux, info->nmux);
 529                return -EINVAL;
 530        }
 531
 532        if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
 533                dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
 534                        name, index, mux, pin->bank + 'A', pin->pin);
 535                return -EINVAL;
 536        }
 537
 538        return 0;
 539}
 540
 541static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
 542{
 543        writel_relaxed(mask, pio + PIO_PDR);
 544}
 545
 546static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
 547{
 548        writel_relaxed(mask, pio + PIO_PER);
 549        writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
 550}
 551
 552static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 553                           unsigned group)
 554{
 555        struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 556        const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
 557        const struct at91_pmx_pin *pin;
 558        uint32_t npins = info->groups[group].npins;
 559        int i, ret;
 560        unsigned mask;
 561        void __iomem *pio;
 562
 563        dev_dbg(info->dev, "enable function %s group %s\n",
 564                info->functions[selector].name, info->groups[group].name);
 565
 566        /* first check that all the pins of the group are valid with a valid
 567         * paramter */
 568        for (i = 0; i < npins; i++) {
 569                pin = &pins_conf[i];
 570                ret = pin_check_config(info, info->groups[group].name, i, pin);
 571                if (ret)
 572                        return ret;
 573        }
 574
 575        for (i = 0; i < npins; i++) {
 576                pin = &pins_conf[i];
 577                at91_pin_dbg(info->dev, pin);
 578                pio = pin_to_controller(info, pin->bank);
 579                mask = pin_to_mask(pin->pin);
 580                at91_mux_disable_interrupt(pio, mask);
 581                switch (pin->mux) {
 582                case AT91_MUX_GPIO:
 583                        at91_mux_gpio_enable(pio, mask, 1);
 584                        break;
 585                case AT91_MUX_PERIPH_A:
 586                        info->ops->mux_A_periph(pio, mask);
 587                        break;
 588                case AT91_MUX_PERIPH_B:
 589                        info->ops->mux_B_periph(pio, mask);
 590                        break;
 591                case AT91_MUX_PERIPH_C:
 592                        if (!info->ops->mux_C_periph)
 593                                return -EINVAL;
 594                        info->ops->mux_C_periph(pio, mask);
 595                        break;
 596                case AT91_MUX_PERIPH_D:
 597                        if (!info->ops->mux_D_periph)
 598                                return -EINVAL;
 599                        info->ops->mux_D_periph(pio, mask);
 600                        break;
 601                }
 602                if (pin->mux)
 603                        at91_mux_gpio_disable(pio, mask);
 604        }
 605
 606        return 0;
 607}
 608
 609static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
 610                           unsigned group)
 611{
 612        struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 613        const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
 614        const struct at91_pmx_pin *pin;
 615        uint32_t npins = info->groups[group].npins;
 616        int i;
 617        unsigned mask;
 618        void __iomem *pio;
 619
 620        for (i = 0; i < npins; i++) {
 621                pin = &pins_conf[i];
 622                at91_pin_dbg(info->dev, pin);
 623                pio = pin_to_controller(info, pin->bank);
 624                mask = pin_to_mask(pin->pin);
 625                at91_mux_gpio_enable(pio, mask, 1);
 626        }
 627}
 628
 629static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 630{
 631        struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 632
 633        return info->nfunctions;
 634}
 635
 636static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
 637                                          unsigned selector)
 638{
 639        struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 640
 641        return info->functions[selector].name;
 642}
 643
 644static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
 645                               const char * const **groups,
 646                               unsigned * const num_groups)
 647{
 648        struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 649
 650        *groups = info->functions[selector].groups;
 651        *num_groups = info->functions[selector].ngroups;
 652
 653        return 0;
 654}
 655
 656static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
 657                                    struct pinctrl_gpio_range *range,
 658                                    unsigned offset)
 659{
 660        struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
 661        struct at91_gpio_chip *at91_chip;
 662        struct gpio_chip *chip;
 663        unsigned mask;
 664
 665        if (!range) {
 666                dev_err(npct->dev, "invalid range\n");
 667                return -EINVAL;
 668        }
 669        if (!range->gc) {
 670                dev_err(npct->dev, "missing GPIO chip in range\n");
 671                return -EINVAL;
 672        }
 673        chip = range->gc;
 674        at91_chip = container_of(chip, struct at91_gpio_chip, chip);
 675
 676        dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
 677
 678        mask = 1 << (offset - chip->base);
 679
 680        dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
 681                offset, 'A' + range->id, offset - chip->base, mask);
 682
 683        writel_relaxed(mask, at91_chip->regbase + PIO_PER);
 684
 685        return 0;
 686}
 687
 688static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
 689                                   struct pinctrl_gpio_range *range,
 690                                   unsigned offset)
 691{
 692        struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
 693
 694        dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
 695        /* Set the pin to some default state, GPIO is usually default */
 696}
 697
 698static const struct pinmux_ops at91_pmx_ops = {
 699        .get_functions_count    = at91_pmx_get_funcs_count,
 700        .get_function_name      = at91_pmx_get_func_name,
 701        .get_function_groups    = at91_pmx_get_groups,
 702        .enable                 = at91_pmx_enable,
 703        .disable                = at91_pmx_disable,
 704        .gpio_request_enable    = at91_gpio_request_enable,
 705        .gpio_disable_free      = at91_gpio_disable_free,
 706};
 707
 708static int at91_pinconf_get(struct pinctrl_dev *pctldev,
 709                             unsigned pin_id, unsigned long *config)
 710{
 711        struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 712        void __iomem *pio;
 713        unsigned pin;
 714        int div;
 715
 716        dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config);
 717        pio = pin_to_controller(info, pin_to_bank(pin_id));
 718        pin = pin_id % MAX_NB_GPIO_PER_BANK;
 719
 720        if (at91_mux_get_multidrive(pio, pin))
 721                *config |= MULTI_DRIVE;
 722
 723        if (at91_mux_get_pullup(pio, pin))
 724                *config |= PULL_UP;
 725
 726        if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
 727                *config |= DEGLITCH;
 728        if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
 729                *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
 730        if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
 731                *config |= PULL_DOWN;
 732        if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
 733                *config |= DIS_SCHMIT;
 734
 735        return 0;
 736}
 737
 738static int at91_pinconf_set(struct pinctrl_dev *pctldev,
 739                             unsigned pin_id, unsigned long config)
 740{
 741        struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 742        unsigned mask;
 743        void __iomem *pio;
 744
 745        dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, config);
 746        pio = pin_to_controller(info, pin_to_bank(pin_id));
 747        mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
 748
 749        if (config & PULL_UP && config & PULL_DOWN)
 750                return -EINVAL;
 751
 752        at91_mux_set_pullup(pio, mask, config & PULL_UP);
 753        at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
 754        if (info->ops->set_deglitch)
 755                info->ops->set_deglitch(pio, mask, config & DEGLITCH);
 756        if (info->ops->set_debounce)
 757                info->ops->set_debounce(pio, mask, config & DEBOUNCE,
 758                                (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
 759        if (info->ops->set_pulldown)
 760                info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
 761        if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
 762                info->ops->disable_schmitt_trig(pio, mask);
 763
 764        return 0;
 765}
 766
 767static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 768                                   struct seq_file *s, unsigned pin_id)
 769{
 770
 771}
 772
 773static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 774                                         struct seq_file *s, unsigned group)
 775{
 776}
 777
 778static const struct pinconf_ops at91_pinconf_ops = {
 779        .pin_config_get                 = at91_pinconf_get,
 780        .pin_config_set                 = at91_pinconf_set,
 781        .pin_config_dbg_show            = at91_pinconf_dbg_show,
 782        .pin_config_group_dbg_show      = at91_pinconf_group_dbg_show,
 783};
 784
 785static struct pinctrl_desc at91_pinctrl_desc = {
 786        .pctlops        = &at91_pctrl_ops,
 787        .pmxops         = &at91_pmx_ops,
 788        .confops        = &at91_pinconf_ops,
 789        .owner          = THIS_MODULE,
 790};
 791
 792static const char *gpio_compat = "atmel,at91rm9200-gpio";
 793
 794static void at91_pinctrl_child_count(struct at91_pinctrl *info,
 795                                     struct device_node *np)
 796{
 797        struct device_node *child;
 798
 799        for_each_child_of_node(np, child) {
 800                if (of_device_is_compatible(child, gpio_compat)) {
 801                        info->nbanks++;
 802                } else {
 803                        info->nfunctions++;
 804                        info->ngroups += of_get_child_count(child);
 805                }
 806        }
 807}
 808
 809static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
 810                                 struct device_node *np)
 811{
 812        int ret = 0;
 813        int size;
 814        const __be32 *list;
 815
 816        list = of_get_property(np, "atmel,mux-mask", &size);
 817        if (!list) {
 818                dev_err(info->dev, "can not read the mux-mask of %d\n", size);
 819                return -EINVAL;
 820        }
 821
 822        size /= sizeof(*list);
 823        if (!size || size % info->nbanks) {
 824                dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks);
 825                return -EINVAL;
 826        }
 827        info->nmux = size / info->nbanks;
 828
 829        info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
 830        if (!info->mux_mask) {
 831                dev_err(info->dev, "could not alloc mux_mask\n");
 832                return -ENOMEM;
 833        }
 834
 835        ret = of_property_read_u32_array(np, "atmel,mux-mask",
 836                                          info->mux_mask, size);
 837        if (ret)
 838                dev_err(info->dev, "can not read the mux-mask of %d\n", size);
 839        return ret;
 840}
 841
 842static int at91_pinctrl_parse_groups(struct device_node *np,
 843                                     struct at91_pin_group *grp,
 844                                     struct at91_pinctrl *info, u32 index)
 845{
 846        struct at91_pmx_pin *pin;
 847        int size;
 848        const __be32 *list;
 849        int i, j;
 850
 851        dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
 852
 853        /* Initialise group */
 854        grp->name = np->name;
 855
 856        /*
 857         * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
 858         * do sanity check and calculate pins number
 859         */
 860        list = of_get_property(np, "atmel,pins", &size);
 861        /* we do not check return since it's safe node passed down */
 862        size /= sizeof(*list);
 863        if (!size || size % 4) {
 864                dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
 865                return -EINVAL;
 866        }
 867
 868        grp->npins = size / 4;
 869        pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin),
 870                                GFP_KERNEL);
 871        grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
 872                                GFP_KERNEL);
 873        if (!grp->pins_conf || !grp->pins)
 874                return -ENOMEM;
 875
 876        for (i = 0, j = 0; i < size; i += 4, j++) {
 877                pin->bank = be32_to_cpu(*list++);
 878                pin->pin = be32_to_cpu(*list++);
 879                grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
 880                pin->mux = be32_to_cpu(*list++);
 881                pin->conf = be32_to_cpu(*list++);
 882
 883                at91_pin_dbg(info->dev, pin);
 884                pin++;
 885        }
 886
 887        return 0;
 888}
 889
 890static int at91_pinctrl_parse_functions(struct device_node *np,
 891                                        struct at91_pinctrl *info, u32 index)
 892{
 893        struct device_node *child;
 894        struct at91_pmx_func *func;
 895        struct at91_pin_group *grp;
 896        int ret;
 897        static u32 grp_index;
 898        u32 i = 0;
 899
 900        dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
 901
 902        func = &info->functions[index];
 903
 904        /* Initialise function */
 905        func->name = np->name;
 906        func->ngroups = of_get_child_count(np);
 907        if (func->ngroups <= 0) {
 908                dev_err(info->dev, "no groups defined\n");
 909                return -EINVAL;
 910        }
 911        func->groups = devm_kzalloc(info->dev,
 912                        func->ngroups * sizeof(char *), GFP_KERNEL);
 913        if (!func->groups)
 914                return -ENOMEM;
 915
 916        for_each_child_of_node(np, child) {
 917                func->groups[i] = child->name;
 918                grp = &info->groups[grp_index++];
 919                ret = at91_pinctrl_parse_groups(child, grp, info, i++);
 920                if (ret)
 921                        return ret;
 922        }
 923
 924        return 0;
 925}
 926
 927static struct of_device_id at91_pinctrl_of_match[] = {
 928        { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
 929        { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
 930        { /* sentinel */ }
 931};
 932
 933static int at91_pinctrl_probe_dt(struct platform_device *pdev,
 934                                 struct at91_pinctrl *info)
 935{
 936        int ret = 0;
 937        int i, j;
 938        uint32_t *tmp;
 939        struct device_node *np = pdev->dev.of_node;
 940        struct device_node *child;
 941
 942        if (!np)
 943                return -ENODEV;
 944
 945        info->dev = &pdev->dev;
 946        info->ops = (struct at91_pinctrl_mux_ops *)
 947                of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
 948        at91_pinctrl_child_count(info, np);
 949
 950        if (info->nbanks < 1) {
 951                dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n");
 952                return -EINVAL;
 953        }
 954
 955        ret = at91_pinctrl_mux_mask(info, np);
 956        if (ret)
 957                return ret;
 958
 959        dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
 960
 961        dev_dbg(&pdev->dev, "mux-mask\n");
 962        tmp = info->mux_mask;
 963        for (i = 0; i < info->nbanks; i++) {
 964                for (j = 0; j < info->nmux; j++, tmp++) {
 965                        dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
 966                }
 967        }
 968
 969        dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
 970        dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
 971        info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func),
 972                                        GFP_KERNEL);
 973        if (!info->functions)
 974                return -ENOMEM;
 975
 976        info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group),
 977                                        GFP_KERNEL);
 978        if (!info->groups)
 979                return -ENOMEM;
 980
 981        dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);
 982        dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
 983        dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
 984
 985        i = 0;
 986
 987        for_each_child_of_node(np, child) {
 988                if (of_device_is_compatible(child, gpio_compat))
 989                        continue;
 990                ret = at91_pinctrl_parse_functions(child, info, i++);
 991                if (ret) {
 992                        dev_err(&pdev->dev, "failed to parse function\n");
 993                        return ret;
 994                }
 995        }
 996
 997        return 0;
 998}
 999
1000static int at91_pinctrl_probe(struct platform_device *pdev)
1001{
1002        struct at91_pinctrl *info;
1003        struct pinctrl_pin_desc *pdesc;
1004        int ret, i, j, k;
1005
1006        info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1007        if (!info)
1008                return -ENOMEM;
1009
1010        ret = at91_pinctrl_probe_dt(pdev, info);
1011        if (ret)
1012                return ret;
1013
1014        /*
1015         * We need all the GPIO drivers to probe FIRST, or we will not be able
1016         * to obtain references to the struct gpio_chip * for them, and we
1017         * need this to proceed.
1018         */
1019        for (i = 0; i < info->nbanks; i++) {
1020                if (!gpio_chips[i]) {
1021                        dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1022                        devm_kfree(&pdev->dev, info);
1023                        return -EPROBE_DEFER;
1024                }
1025        }
1026
1027        at91_pinctrl_desc.name = dev_name(&pdev->dev);
1028        at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;
1029        at91_pinctrl_desc.pins = pdesc =
1030                devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
1031
1032        if (!at91_pinctrl_desc.pins)
1033                return -ENOMEM;
1034
1035        for (i = 0 , k = 0; i < info->nbanks; i++) {
1036                for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1037                        pdesc->number = k;
1038                        pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1039                        pdesc++;
1040                }
1041        }
1042
1043        platform_set_drvdata(pdev, info);
1044        info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info);
1045
1046        if (!info->pctl) {
1047                dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1048                ret = -EINVAL;
1049                goto err;
1050        }
1051
1052        /* We will handle a range of GPIO pins */
1053        for (i = 0; i < info->nbanks; i++)
1054                pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1055
1056        dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1057
1058        return 0;
1059
1060err:
1061        return ret;
1062}
1063
1064static int at91_pinctrl_remove(struct platform_device *pdev)
1065{
1066        struct at91_pinctrl *info = platform_get_drvdata(pdev);
1067
1068        pinctrl_unregister(info->pctl);
1069
1070        return 0;
1071}
1072
1073static int at91_gpio_request(struct gpio_chip *chip, unsigned offset)
1074{
1075        /*
1076         * Map back to global GPIO space and request muxing, the direction
1077         * parameter does not matter for this controller.
1078         */
1079        int gpio = chip->base + offset;
1080        int bank = chip->base / chip->ngpio;
1081
1082        dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__,
1083                 'A' + bank, offset, gpio);
1084
1085        return pinctrl_request_gpio(gpio);
1086}
1087
1088static void at91_gpio_free(struct gpio_chip *chip, unsigned offset)
1089{
1090        int gpio = chip->base + offset;
1091
1092        pinctrl_free_gpio(gpio);
1093}
1094
1095static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1096{
1097        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1098        void __iomem *pio = at91_gpio->regbase;
1099        unsigned mask = 1 << offset;
1100
1101        writel_relaxed(mask, pio + PIO_ODR);
1102        return 0;
1103}
1104
1105static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1106{
1107        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1108        void __iomem *pio = at91_gpio->regbase;
1109        unsigned mask = 1 << offset;
1110        u32 pdsr;
1111
1112        pdsr = readl_relaxed(pio + PIO_PDSR);
1113        return (pdsr & mask) != 0;
1114}
1115
1116static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1117                                int val)
1118{
1119        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1120        void __iomem *pio = at91_gpio->regbase;
1121        unsigned mask = 1 << offset;
1122
1123        writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1124}
1125
1126static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1127                                int val)
1128{
1129        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1130        void __iomem *pio = at91_gpio->regbase;
1131        unsigned mask = 1 << offset;
1132
1133        writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1134        writel_relaxed(mask, pio + PIO_OER);
1135
1136        return 0;
1137}
1138
1139static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1140{
1141        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1142        int virq;
1143
1144        if (offset < chip->ngpio)
1145                virq = irq_create_mapping(at91_gpio->domain, offset);
1146        else
1147                virq = -ENXIO;
1148
1149        dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
1150                                chip->label, offset + chip->base, virq);
1151        return virq;
1152}
1153
1154#ifdef CONFIG_DEBUG_FS
1155static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1156{
1157        enum at91_mux mode;
1158        int i;
1159        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1160        void __iomem *pio = at91_gpio->regbase;
1161
1162        for (i = 0; i < chip->ngpio; i++) {
1163                unsigned pin = chip->base + i;
1164                unsigned mask = pin_to_mask(pin);
1165                const char *gpio_label;
1166                u32 pdsr;
1167
1168                gpio_label = gpiochip_is_requested(chip, i);
1169                if (!gpio_label)
1170                        continue;
1171                mode = at91_gpio->ops->get_periph(pio, mask);
1172                seq_printf(s, "[%s] GPIO%s%d: ",
1173                           gpio_label, chip->label, i);
1174                if (mode == AT91_MUX_GPIO) {
1175                        pdsr = readl_relaxed(pio + PIO_PDSR);
1176
1177                        seq_printf(s, "[gpio] %s\n",
1178                                   pdsr & mask ?
1179                                   "set" : "clear");
1180                } else {
1181                        seq_printf(s, "[periph %c]\n",
1182                                   mode + 'A' - 1);
1183                }
1184        }
1185}
1186#else
1187#define at91_gpio_dbg_show      NULL
1188#endif
1189
1190/* Several AIC controller irqs are dispatched through this GPIO handler.
1191 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1192 * at91_set_gpio_input() then maybe enable its glitch filter.
1193 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1194 * handler.
1195 * First implementation always triggers on rising and falling edges
1196 * whereas the newer PIO3 can be additionally configured to trigger on
1197 * level, edge with any polarity.
1198 *
1199 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1200 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1201 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1202 */
1203
1204static void gpio_irq_mask(struct irq_data *d)
1205{
1206        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1207        void __iomem    *pio = at91_gpio->regbase;
1208        unsigned        mask = 1 << d->hwirq;
1209
1210        if (pio)
1211                writel_relaxed(mask, pio + PIO_IDR);
1212}
1213
1214static void gpio_irq_unmask(struct irq_data *d)
1215{
1216        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1217        void __iomem    *pio = at91_gpio->regbase;
1218        unsigned        mask = 1 << d->hwirq;
1219
1220        if (pio)
1221                writel_relaxed(mask, pio + PIO_IER);
1222}
1223
1224static int gpio_irq_type(struct irq_data *d, unsigned type)
1225{
1226        switch (type) {
1227        case IRQ_TYPE_NONE:
1228        case IRQ_TYPE_EDGE_BOTH:
1229                return 0;
1230        default:
1231                return -EINVAL;
1232        }
1233}
1234
1235/* Alternate irq type for PIO3 support */
1236static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1237{
1238        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1239        void __iomem    *pio = at91_gpio->regbase;
1240        unsigned        mask = 1 << d->hwirq;
1241
1242        switch (type) {
1243        case IRQ_TYPE_EDGE_RISING:
1244                writel_relaxed(mask, pio + PIO_ESR);
1245                writel_relaxed(mask, pio + PIO_REHLSR);
1246                break;
1247        case IRQ_TYPE_EDGE_FALLING:
1248                writel_relaxed(mask, pio + PIO_ESR);
1249                writel_relaxed(mask, pio + PIO_FELLSR);
1250                break;
1251        case IRQ_TYPE_LEVEL_LOW:
1252                writel_relaxed(mask, pio + PIO_LSR);
1253                writel_relaxed(mask, pio + PIO_FELLSR);
1254                break;
1255        case IRQ_TYPE_LEVEL_HIGH:
1256                writel_relaxed(mask, pio + PIO_LSR);
1257                writel_relaxed(mask, pio + PIO_REHLSR);
1258                break;
1259        case IRQ_TYPE_EDGE_BOTH:
1260                /*
1261                 * disable additional interrupt modes:
1262                 * fall back to default behavior
1263                 */
1264                writel_relaxed(mask, pio + PIO_AIMDR);
1265                return 0;
1266        case IRQ_TYPE_NONE:
1267        default:
1268                pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
1269                return -EINVAL;
1270        }
1271
1272        /* enable additional interrupt modes */
1273        writel_relaxed(mask, pio + PIO_AIMER);
1274
1275        return 0;
1276}
1277
1278#ifdef CONFIG_PM
1279
1280static u32 wakeups[MAX_GPIO_BANKS];
1281static u32 backups[MAX_GPIO_BANKS];
1282
1283static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1284{
1285        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1286        unsigned        bank = at91_gpio->pioc_idx;
1287        unsigned mask = 1 << d->hwirq;
1288
1289        if (unlikely(bank >= MAX_GPIO_BANKS))
1290                return -EINVAL;
1291
1292        if (state)
1293                wakeups[bank] |= mask;
1294        else
1295                wakeups[bank] &= ~mask;
1296
1297        irq_set_irq_wake(at91_gpio->pioc_virq, state);
1298
1299        return 0;
1300}
1301
1302void at91_pinctrl_gpio_suspend(void)
1303{
1304        int i;
1305
1306        for (i = 0; i < gpio_banks; i++) {
1307                void __iomem  *pio;
1308
1309                if (!gpio_chips[i])
1310                        continue;
1311
1312                pio = gpio_chips[i]->regbase;
1313
1314                backups[i] = __raw_readl(pio + PIO_IMR);
1315                __raw_writel(backups[i], pio + PIO_IDR);
1316                __raw_writel(wakeups[i], pio + PIO_IER);
1317
1318                if (!wakeups[i]) {
1319                        clk_unprepare(gpio_chips[i]->clock);
1320                        clk_disable(gpio_chips[i]->clock);
1321                } else {
1322                        printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
1323                               'A'+i, wakeups[i]);
1324                }
1325        }
1326}
1327
1328void at91_pinctrl_gpio_resume(void)
1329{
1330        int i;
1331
1332        for (i = 0; i < gpio_banks; i++) {
1333                void __iomem  *pio;
1334
1335                if (!gpio_chips[i])
1336                        continue;
1337
1338                pio = gpio_chips[i]->regbase;
1339
1340                if (!wakeups[i]) {
1341                        if (clk_prepare(gpio_chips[i]->clock) == 0)
1342                                clk_enable(gpio_chips[i]->clock);
1343                }
1344
1345                __raw_writel(wakeups[i], pio + PIO_IDR);
1346                __raw_writel(backups[i], pio + PIO_IER);
1347        }
1348}
1349
1350#else
1351#define gpio_irq_set_wake       NULL
1352#endif /* CONFIG_PM */
1353
1354static struct irq_chip gpio_irqchip = {
1355        .name           = "GPIO",
1356        .irq_disable    = gpio_irq_mask,
1357        .irq_mask       = gpio_irq_mask,
1358        .irq_unmask     = gpio_irq_unmask,
1359        /* .irq_set_type is set dynamically */
1360        .irq_set_wake   = gpio_irq_set_wake,
1361};
1362
1363static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1364{
1365        struct irq_chip *chip = irq_desc_get_chip(desc);
1366        struct irq_data *idata = irq_desc_get_irq_data(desc);
1367        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
1368        void __iomem    *pio = at91_gpio->regbase;
1369        unsigned long   isr;
1370        int             n;
1371
1372        chained_irq_enter(chip, desc);
1373        for (;;) {
1374                /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1375                 * When there none are pending, we're finished unless we need
1376                 * to process multiple banks (like ID_PIOCDE on sam9263).
1377                 */
1378                isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1379                if (!isr) {
1380                        if (!at91_gpio->next)
1381                                break;
1382                        at91_gpio = at91_gpio->next;
1383                        pio = at91_gpio->regbase;
1384                        continue;
1385                }
1386
1387                for_each_set_bit(n, &isr, BITS_PER_LONG) {
1388                        generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
1389                }
1390        }
1391        chained_irq_exit(chip, desc);
1392        /* now it may re-trigger */
1393}
1394
1395/*
1396 * This lock class tells lockdep that GPIO irqs are in a different
1397 * category than their parents, so it won't report false recursion.
1398 */
1399static struct lock_class_key gpio_lock_class;
1400
1401static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
1402                                                        irq_hw_number_t hw)
1403{
1404        struct at91_gpio_chip   *at91_gpio = h->host_data;
1405
1406        irq_set_lockdep_class(virq, &gpio_lock_class);
1407
1408        /*
1409         * Can use the "simple" and not "edge" handler since it's
1410         * shorter, and the AIC handles interrupts sanely.
1411         */
1412        irq_set_chip_and_handler(virq, &gpio_irqchip,
1413                                 handle_simple_irq);
1414        set_irq_flags(virq, IRQF_VALID);
1415        irq_set_chip_data(virq, at91_gpio);
1416
1417        return 0;
1418}
1419
1420static int at91_gpio_irq_domain_xlate(struct irq_domain *d,
1421                                      struct device_node *ctrlr,
1422                                      const u32 *intspec, unsigned int intsize,
1423                                      irq_hw_number_t *out_hwirq,
1424                                      unsigned int *out_type)
1425{
1426        struct at91_gpio_chip *at91_gpio = d->host_data;
1427        int ret;
1428        int pin = at91_gpio->chip.base + intspec[0];
1429
1430        if (WARN_ON(intsize < 2))
1431                return -EINVAL;
1432        *out_hwirq = intspec[0];
1433        *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
1434
1435        ret = gpio_request(pin, ctrlr->full_name);
1436        if (ret)
1437                return ret;
1438
1439        ret = gpio_direction_input(pin);
1440        if (ret)
1441                return ret;
1442
1443        return 0;
1444}
1445
1446static struct irq_domain_ops at91_gpio_ops = {
1447        .map    = at91_gpio_irq_map,
1448        .xlate  = at91_gpio_irq_domain_xlate,
1449};
1450
1451static int at91_gpio_of_irq_setup(struct device_node *node,
1452                                  struct at91_gpio_chip *at91_gpio)
1453{
1454        struct at91_gpio_chip   *prev = NULL;
1455        struct irq_data         *d = irq_get_irq_data(at91_gpio->pioc_virq);
1456
1457        at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1458
1459        /* Setup proper .irq_set_type function */
1460        gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type;
1461
1462        /* Disable irqs of this PIO controller */
1463        writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1464
1465        /* Setup irq domain */
1466        at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
1467                                                &at91_gpio_ops, at91_gpio);
1468        if (!at91_gpio->domain)
1469                panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
1470                        at91_gpio->pioc_idx);
1471
1472        /* Setup chained handler */
1473        if (at91_gpio->pioc_idx)
1474                prev = gpio_chips[at91_gpio->pioc_idx - 1];
1475
1476        /* The toplevel handler handles one bank of GPIOs, except
1477         * on some SoC it can handles up to three...
1478         * We only set up the handler for the first of the list.
1479         */
1480        if (prev && prev->next == at91_gpio)
1481                return 0;
1482
1483        irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
1484        irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
1485
1486        return 0;
1487}
1488
1489/* This structure is replicated for each GPIO block allocated at probe time */
1490static struct gpio_chip at91_gpio_template = {
1491        .request                = at91_gpio_request,
1492        .free                   = at91_gpio_free,
1493        .direction_input        = at91_gpio_direction_input,
1494        .get                    = at91_gpio_get,
1495        .direction_output       = at91_gpio_direction_output,
1496        .set                    = at91_gpio_set,
1497        .to_irq                 = at91_gpio_to_irq,
1498        .dbg_show               = at91_gpio_dbg_show,
1499        .can_sleep              = 0,
1500        .ngpio                  = MAX_NB_GPIO_PER_BANK,
1501};
1502
1503static void at91_gpio_probe_fixup(void)
1504{
1505        unsigned i;
1506        struct at91_gpio_chip *at91_gpio, *last = NULL;
1507
1508        for (i = 0; i < gpio_banks; i++) {
1509                at91_gpio = gpio_chips[i];
1510
1511                /*
1512                 * GPIO controller are grouped on some SoC:
1513                 * PIOC, PIOD and PIOE can share the same IRQ line
1514                 */
1515                if (last && last->pioc_virq == at91_gpio->pioc_virq)
1516                        last->next = at91_gpio;
1517                last = at91_gpio;
1518        }
1519}
1520
1521static struct of_device_id at91_gpio_of_match[] = {
1522        { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1523        { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1524        { /* sentinel */ }
1525};
1526
1527static int at91_gpio_probe(struct platform_device *pdev)
1528{
1529        struct device_node *np = pdev->dev.of_node;
1530        struct resource *res;
1531        struct at91_gpio_chip *at91_chip = NULL;
1532        struct gpio_chip *chip;
1533        struct pinctrl_gpio_range *range;
1534        int ret = 0;
1535        int irq, i;
1536        int alias_idx = of_alias_get_id(np, "gpio");
1537        uint32_t ngpio;
1538        char **names;
1539
1540        BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1541        if (gpio_chips[alias_idx]) {
1542                ret = -EBUSY;
1543                goto err;
1544        }
1545
1546        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1547        if (!res) {
1548                ret = -ENOENT;
1549                goto err;
1550        }
1551
1552        irq = platform_get_irq(pdev, 0);
1553        if (irq < 0) {
1554                ret = irq;
1555                goto err;
1556        }
1557
1558        at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1559        if (!at91_chip) {
1560                ret = -ENOMEM;
1561                goto err;
1562        }
1563
1564        at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1565        if (IS_ERR(at91_chip->regbase)) {
1566                ret = PTR_ERR(at91_chip->regbase);
1567                goto err;
1568        }
1569
1570        at91_chip->ops = (struct at91_pinctrl_mux_ops *)
1571                of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1572        at91_chip->pioc_virq = irq;
1573        at91_chip->pioc_idx = alias_idx;
1574
1575        at91_chip->clock = clk_get(&pdev->dev, NULL);
1576        if (IS_ERR(at91_chip->clock)) {
1577                dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1578                goto err;
1579        }
1580
1581        if (clk_prepare(at91_chip->clock))
1582                goto clk_prep_err;
1583
1584        /* enable PIO controller's clock */
1585        if (clk_enable(at91_chip->clock)) {
1586                dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
1587                goto clk_err;
1588        }
1589
1590        at91_chip->chip = at91_gpio_template;
1591
1592        chip = &at91_chip->chip;
1593        chip->of_node = np;
1594        chip->label = dev_name(&pdev->dev);
1595        chip->dev = &pdev->dev;
1596        chip->owner = THIS_MODULE;
1597        chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1598
1599        if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1600                if (ngpio >= MAX_NB_GPIO_PER_BANK)
1601                        pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1602                               alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1603                else
1604                        chip->ngpio = ngpio;
1605        }
1606
1607        names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio,
1608                             GFP_KERNEL);
1609
1610        if (!names) {
1611                ret = -ENOMEM;
1612                goto clk_err;
1613        }
1614
1615        for (i = 0; i < chip->ngpio; i++)
1616                names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1617
1618        chip->names = (const char *const *)names;
1619
1620        range = &at91_chip->range;
1621        range->name = chip->label;
1622        range->id = alias_idx;
1623        range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1624
1625        range->npins = chip->ngpio;
1626        range->gc = chip;
1627
1628        ret = gpiochip_add(chip);
1629        if (ret)
1630                goto clk_err;
1631
1632        gpio_chips[alias_idx] = at91_chip;
1633        gpio_banks = max(gpio_banks, alias_idx + 1);
1634
1635        at91_gpio_probe_fixup();
1636
1637        at91_gpio_of_irq_setup(np, at91_chip);
1638
1639        dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1640
1641        return 0;
1642
1643clk_err:
1644        clk_unprepare(at91_chip->clock);
1645clk_prep_err:
1646        clk_put(at91_chip->clock);
1647err:
1648        dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1649
1650        return ret;
1651}
1652
1653static struct platform_driver at91_gpio_driver = {
1654        .driver = {
1655                .name = "gpio-at91",
1656                .owner = THIS_MODULE,
1657                .of_match_table = of_match_ptr(at91_gpio_of_match),
1658        },
1659        .probe = at91_gpio_probe,
1660};
1661
1662static struct platform_driver at91_pinctrl_driver = {
1663        .driver = {
1664                .name = "pinctrl-at91",
1665                .owner = THIS_MODULE,
1666                .of_match_table = of_match_ptr(at91_pinctrl_of_match),
1667        },
1668        .probe = at91_pinctrl_probe,
1669        .remove = at91_pinctrl_remove,
1670};
1671
1672static int __init at91_pinctrl_init(void)
1673{
1674        int ret;
1675
1676        ret = platform_driver_register(&at91_gpio_driver);
1677        if (ret)
1678                return ret;
1679        return platform_driver_register(&at91_pinctrl_driver);
1680}
1681arch_initcall(at91_pinctrl_init);
1682
1683static void __exit at91_pinctrl_exit(void)
1684{
1685        platform_driver_unregister(&at91_pinctrl_driver);
1686}
1687
1688module_exit(at91_pinctrl_exit);
1689MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>");
1690MODULE_DESCRIPTION("Atmel AT91 pinctrl driver");
1691MODULE_LICENSE("GPL v2");
1692
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.