linux/drivers/pci/quirks.c
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   1/*
   2 *  This file contains work-arounds for many known PCI hardware
   3 *  bugs.  Devices present only on certain architectures (host
   4 *  bridges et cetera) should be handled in arch-specific code.
   5 *
   6 *  Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
   7 *
   8 *  Copyright (c) 1999 Martin Mares <mj@ucw.cz>
   9 *
  10 *  Init/reset quirks for USB host controllers should be in the
  11 *  USB quirks file, where their drivers can access reuse it.
  12 *
  13 *  The bridge optimization stuff has been removed. If you really
  14 *  have a silly BIOS which is unable to set your host bridge right,
  15 *  use the PowerTweak utility (see http://powertweak.sourceforge.net).
  16 */
  17
  18#include <linux/types.h>
  19#include <linux/kernel.h>
  20#include <linux/export.h>
  21#include <linux/pci.h>
  22#include <linux/init.h>
  23#include <linux/delay.h>
  24#include <linux/acpi.h>
  25#include <linux/kallsyms.h>
  26#include <linux/dmi.h>
  27#include <linux/pci-aspm.h>
  28#include <linux/ioport.h>
  29#include <linux/sched.h>
  30#include <linux/ktime.h>
  31#include <asm/dma.h>    /* isa_dma_bridge_buggy */
  32#include "pci.h"
  33
  34/*
  35 * Decoding should be disabled for a PCI device during BAR sizing to avoid
  36 * conflict. But doing so may cause problems on host bridge and perhaps other
  37 * key system devices. For devices that need to have mmio decoding always-on,
  38 * we need to set the dev->mmio_always_on bit.
  39 */
  40static void quirk_mmio_always_on(struct pci_dev *dev)
  41{
  42        dev->mmio_always_on = 1;
  43}
  44DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
  45                                PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
  46
  47/* The Mellanox Tavor device gives false positive parity errors
  48 * Mark this device with a broken_parity_status, to allow
  49 * PCI scanning code to "skip" this now blacklisted device.
  50 */
  51static void quirk_mellanox_tavor(struct pci_dev *dev)
  52{
  53        dev->broken_parity_status = 1;  /* This device gives false positives */
  54}
  55DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
  56DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
  57
  58/* Deal with broken BIOS'es that neglect to enable passive release,
  59   which can cause problems in combination with the 82441FX/PPro MTRRs */
  60static void quirk_passive_release(struct pci_dev *dev)
  61{
  62        struct pci_dev *d = NULL;
  63        unsigned char dlc;
  64
  65        /* We have to make sure a particular bit is set in the PIIX3
  66           ISA bridge, so we have to go out and find it. */
  67        while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
  68                pci_read_config_byte(d, 0x82, &dlc);
  69                if (!(dlc & 1<<1)) {
  70                        dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
  71                        dlc |= 1<<1;
  72                        pci_write_config_byte(d, 0x82, dlc);
  73                }
  74        }
  75}
  76DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82441,      quirk_passive_release);
  77DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82441,      quirk_passive_release);
  78
  79/*  The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
  80    but VIA don't answer queries. If you happen to have good contacts at VIA
  81    ask them for me please -- Alan 
  82    
  83    This appears to be BIOS not version dependent. So presumably there is a 
  84    chipset level fix */
  85    
  86static void quirk_isa_dma_hangs(struct pci_dev *dev)
  87{
  88        if (!isa_dma_bridge_buggy) {
  89                isa_dma_bridge_buggy=1;
  90                dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
  91        }
  92}
  93        /*
  94         * Its not totally clear which chipsets are the problematic ones
  95         * We know 82C586 and 82C596 variants are affected.
  96         */
  97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C586_0,     quirk_isa_dma_hangs);
  98DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C596,       quirk_isa_dma_hangs);
  99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371SB_0,  quirk_isa_dma_hangs);
 100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1533,         quirk_isa_dma_hangs);
 101DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_1,       quirk_isa_dma_hangs);
 102DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_2,       quirk_isa_dma_hangs);
 103DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,      PCI_DEVICE_ID_NEC_CBUS_3,       quirk_isa_dma_hangs);
 104
 105/*
 106 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
 107 * for some HT machines to use C4 w/o hanging.
 108 */
 109static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
 110{
 111        u32 pmbase;
 112        u16 pm1a;
 113
 114        pci_read_config_dword(dev, 0x40, &pmbase);
 115        pmbase = pmbase & 0xff80;
 116        pm1a = inw(pmbase);
 117
 118        if (pm1a & 0x10) {
 119                dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
 120                outw(0x10, pmbase);
 121        }
 122}
 123DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
 124
 125/*
 126 *      Chipsets where PCI->PCI transfers vanish or hang
 127 */
 128static void quirk_nopcipci(struct pci_dev *dev)
 129{
 130        if ((pci_pci_problems & PCIPCI_FAIL)==0) {
 131                dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
 132                pci_pci_problems |= PCIPCI_FAIL;
 133        }
 134}
 135DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_5597,          quirk_nopcipci);
 136DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,       PCI_DEVICE_ID_SI_496,           quirk_nopcipci);
 137
 138static void quirk_nopciamd(struct pci_dev *dev)
 139{
 140        u8 rev;
 141        pci_read_config_byte(dev, 0x08, &rev);
 142        if (rev == 0x13) {
 143                /* Erratum 24 */
 144                dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
 145                pci_pci_problems |= PCIAGP_FAIL;
 146        }
 147}
 148DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_8151_0,       quirk_nopciamd);
 149
 150/*
 151 *      Triton requires workarounds to be used by the drivers
 152 */
 153static void quirk_triton(struct pci_dev *dev)
 154{
 155        if ((pci_pci_problems&PCIPCI_TRITON)==0) {
 156                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
 157                pci_pci_problems |= PCIPCI_TRITON;
 158        }
 159}
 160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82437,      quirk_triton);
 161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82437VX,    quirk_triton);
 162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82439,      quirk_triton);
 163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82439TX,    quirk_triton);
 164
 165/*
 166 *      VIA Apollo KT133 needs PCI latency patch
 167 *      Made according to a windows driver based patch by George E. Breese
 168 *      see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
 169 *      and http://www.georgebreese.com/net/software/#PCI
 170 *      Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
 171 *      the info on which Mr Breese based his work.
 172 *
 173 *      Updated based on further information from the site and also on
 174 *      information provided by VIA 
 175 */
 176static void quirk_vialatency(struct pci_dev *dev)
 177{
 178        struct pci_dev *p;
 179        u8 busarb;
 180        /* Ok we have a potential problem chipset here. Now see if we have
 181           a buggy southbridge */
 182           
 183        p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
 184        if (p!=NULL) {
 185                /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
 186                /* Check for buggy part revisions */
 187                if (p->revision < 0x40 || p->revision > 0x42)
 188                        goto exit;
 189        } else {
 190                p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
 191                if (p==NULL)    /* No problem parts */
 192                        goto exit;
 193                /* Check for buggy part revisions */
 194                if (p->revision < 0x10 || p->revision > 0x12)
 195                        goto exit;
 196        }
 197        
 198        /*
 199         *      Ok we have the problem. Now set the PCI master grant to 
 200         *      occur every master grant. The apparent bug is that under high
 201         *      PCI load (quite common in Linux of course) you can get data
 202         *      loss when the CPU is held off the bus for 3 bus master requests
 203         *      This happens to include the IDE controllers....
 204         *
 205         *      VIA only apply this fix when an SB Live! is present but under
 206         *      both Linux and Windows this isn't enough, and we have seen
 207         *      corruption without SB Live! but with things like 3 UDMA IDE
 208         *      controllers. So we ignore that bit of the VIA recommendation..
 209         */
 210
 211        pci_read_config_byte(dev, 0x76, &busarb);
 212        /* Set bit 4 and bi 5 of byte 76 to 0x01 
 213           "Master priority rotation on every PCI master grant */
 214        busarb &= ~(1<<5);
 215        busarb |= (1<<4);
 216        pci_write_config_byte(dev, 0x76, busarb);
 217        dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
 218exit:
 219        pci_dev_put(p);
 220}
 221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8363_0,       quirk_vialatency);
 222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8371_1,       quirk_vialatency);
 223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8361,         quirk_vialatency);
 224/* Must restore this on a resume from RAM */
 225DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8363_0,       quirk_vialatency);
 226DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8371_1,       quirk_vialatency);
 227DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8361,         quirk_vialatency);
 228
 229/*
 230 *      VIA Apollo VP3 needs ETBF on BT848/878
 231 */
 232static void quirk_viaetbf(struct pci_dev *dev)
 233{
 234        if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
 235                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
 236                pci_pci_problems |= PCIPCI_VIAETBF;
 237        }
 238}
 239DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C597_0,     quirk_viaetbf);
 240
 241static void quirk_vsfx(struct pci_dev *dev)
 242{
 243        if ((pci_pci_problems&PCIPCI_VSFX)==0) {
 244                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
 245                pci_pci_problems |= PCIPCI_VSFX;
 246        }
 247}
 248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C576,       quirk_vsfx);
 249
 250/*
 251 *      Ali Magik requires workarounds to be used by the drivers
 252 *      that DMA to AGP space. Latency must be set to 0xA and triton
 253 *      workaround applied too
 254 *      [Info kindly provided by ALi]
 255 */     
 256static void quirk_alimagik(struct pci_dev *dev)
 257{
 258        if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
 259                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
 260                pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
 261        }
 262}
 263DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1647,         quirk_alimagik);
 264DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1651,         quirk_alimagik);
 265
 266/*
 267 *      Natoma has some interesting boundary conditions with Zoran stuff
 268 *      at least
 269 */
 270static void quirk_natoma(struct pci_dev *dev)
 271{
 272        if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
 273                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
 274                pci_pci_problems |= PCIPCI_NATOMA;
 275        }
 276}
 277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82441,      quirk_natoma);
 278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443LX_0,  quirk_natoma);
 279DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443LX_1,  quirk_natoma);
 280DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_0,  quirk_natoma);
 281DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_1,  quirk_natoma);
 282DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82443BX_2,  quirk_natoma);
 283
 284/*
 285 *  This chip can cause PCI parity errors if config register 0xA0 is read
 286 *  while DMAs are occurring.
 287 */
 288static void quirk_citrine(struct pci_dev *dev)
 289{
 290        dev->cfg_size = 0xA0;
 291}
 292DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM,     PCI_DEVICE_ID_IBM_CITRINE,      quirk_citrine);
 293
 294/*
 295 *  S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
 296 *  If it's needed, re-allocate the region.
 297 */
 298static void quirk_s3_64M(struct pci_dev *dev)
 299{
 300        struct resource *r = &dev->resource[0];
 301
 302        if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
 303                r->start = 0;
 304                r->end = 0x3ffffff;
 305        }
 306}
 307DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,      PCI_DEVICE_ID_S3_868,           quirk_s3_64M);
 308DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,      PCI_DEVICE_ID_S3_968,           quirk_s3_64M);
 309
 310/*
 311 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
 312 * ver. 1.33  20070103) don't set the correct ISA PCI region header info.
 313 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
 314 * (which conflicts w/ BAR1's memory range).
 315 */
 316static void quirk_cs5536_vsa(struct pci_dev *dev)
 317{
 318        if (pci_resource_len(dev, 0) != 8) {
 319                struct resource *res = &dev->resource[0];
 320                res->end = res->start + 8 - 1;
 321                dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
 322                                "(incorrect header); workaround applied.\n");
 323        }
 324}
 325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
 326
 327static void quirk_io_region(struct pci_dev *dev, int port,
 328                                unsigned size, int nr, const char *name)
 329{
 330        u16 region;
 331        struct pci_bus_region bus_region;
 332        struct resource *res = dev->resource + nr;
 333
 334        pci_read_config_word(dev, port, &region);
 335        region &= ~(size - 1);
 336
 337        if (!region)
 338                return;
 339
 340        res->name = pci_name(dev);
 341        res->flags = IORESOURCE_IO;
 342
 343        /* Convert from PCI bus to resource space */
 344        bus_region.start = region;
 345        bus_region.end = region + size - 1;
 346        pcibios_bus_to_resource(dev, res, &bus_region);
 347
 348        if (!pci_claim_resource(dev, nr))
 349                dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
 350}
 351
 352/*
 353 *      ATI Northbridge setups MCE the processor if you even
 354 *      read somewhere between 0x3b0->0x3bb or read 0x3d3
 355 */
 356static void quirk_ati_exploding_mce(struct pci_dev *dev)
 357{
 358        dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
 359        /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
 360        request_region(0x3b0, 0x0C, "RadeonIGP");
 361        request_region(0x3d3, 0x01, "RadeonIGP");
 362}
 363DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI,      PCI_DEVICE_ID_ATI_RS100,   quirk_ati_exploding_mce);
 364
 365/*
 366 * Let's make the southbridge information explicit instead
 367 * of having to worry about people probing the ACPI areas,
 368 * for example.. (Yes, it happens, and if you read the wrong
 369 * ACPI register it will put the machine to sleep with no
 370 * way of waking it up again. Bummer).
 371 *
 372 * ALI M7101: Two IO regions pointed to by words at
 373 *      0xE0 (64 bytes of ACPI registers)
 374 *      0xE2 (32 bytes of SMB registers)
 375 */
 376static void quirk_ali7101_acpi(struct pci_dev *dev)
 377{
 378        quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
 379        quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
 380}
 381DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL,      PCI_DEVICE_ID_AL_M7101,         quirk_ali7101_acpi);
 382
 383static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
 384{
 385        u32 devres;
 386        u32 mask, size, base;
 387
 388        pci_read_config_dword(dev, port, &devres);
 389        if ((devres & enable) != enable)
 390                return;
 391        mask = (devres >> 16) & 15;
 392        base = devres & 0xffff;
 393        size = 16;
 394        for (;;) {
 395                unsigned bit = size >> 1;
 396                if ((bit & mask) == bit)
 397                        break;
 398                size = bit;
 399        }
 400        /*
 401         * For now we only print it out. Eventually we'll want to
 402         * reserve it (at least if it's in the 0x1000+ range), but
 403         * let's get enough confirmation reports first. 
 404         */
 405        base &= -size;
 406        dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
 407}
 408
 409static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
 410{
 411        u32 devres;
 412        u32 mask, size, base;
 413
 414        pci_read_config_dword(dev, port, &devres);
 415        if ((devres & enable) != enable)
 416                return;
 417        base = devres & 0xffff0000;
 418        mask = (devres & 0x3f) << 16;
 419        size = 128 << 16;
 420        for (;;) {
 421                unsigned bit = size >> 1;
 422                if ((bit & mask) == bit)
 423                        break;
 424                size = bit;
 425        }
 426        /*
 427         * For now we only print it out. Eventually we'll want to
 428         * reserve it, but let's get enough confirmation reports first. 
 429         */
 430        base &= -size;
 431        dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
 432}
 433
 434/*
 435 * PIIX4 ACPI: Two IO regions pointed to by longwords at
 436 *      0x40 (64 bytes of ACPI registers)
 437 *      0x90 (16 bytes of SMB registers)
 438 * and a few strange programmable PIIX4 device resources.
 439 */
 440static void quirk_piix4_acpi(struct pci_dev *dev)
 441{
 442        u32 res_a;
 443
 444        quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
 445        quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
 446
 447        /* Device resource A has enables for some of the other ones */
 448        pci_read_config_dword(dev, 0x5c, &res_a);
 449
 450        piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
 451        piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
 452
 453        /* Device resource D is just bitfields for static resources */
 454
 455        /* Device 12 enabled? */
 456        if (res_a & (1 << 29)) {
 457                piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
 458                piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
 459        }
 460        /* Device 13 enabled? */
 461        if (res_a & (1 << 30)) {
 462                piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
 463                piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
 464        }
 465        piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
 466        piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
 467}
 468DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82371AB_3,  quirk_piix4_acpi);
 469DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82443MX_3,  quirk_piix4_acpi);
 470
 471#define ICH_PMBASE      0x40
 472#define ICH_ACPI_CNTL   0x44
 473#define  ICH4_ACPI_EN   0x10
 474#define  ICH6_ACPI_EN   0x80
 475#define ICH4_GPIOBASE   0x58
 476#define ICH4_GPIO_CNTL  0x5c
 477#define  ICH4_GPIO_EN   0x10
 478#define ICH6_GPIOBASE   0x48
 479#define ICH6_GPIO_CNTL  0x4c
 480#define  ICH6_GPIO_EN   0x10
 481
 482/*
 483 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
 484 *      0x40 (128 bytes of ACPI, GPIO & TCO registers)
 485 *      0x58 (64 bytes of GPIO I/O space)
 486 */
 487static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
 488{
 489        u8 enable;
 490
 491        /*
 492         * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
 493         * with low legacy (and fixed) ports. We don't know the decoding
 494         * priority and can't tell whether the legacy device or the one created
 495         * here is really at that address.  This happens on boards with broken
 496         * BIOSes.
 497        */
 498
 499        pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
 500        if (enable & ICH4_ACPI_EN)
 501                quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
 502                                 "ICH4 ACPI/GPIO/TCO");
 503
 504        pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
 505        if (enable & ICH4_GPIO_EN)
 506                quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
 507                                "ICH4 GPIO");
 508}
 509DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AA_0,         quirk_ich4_lpc_acpi);
 510DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AB_0,         quirk_ich4_lpc_acpi);
 511DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_0,         quirk_ich4_lpc_acpi);
 512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_10,        quirk_ich4_lpc_acpi);
 513DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_0,         quirk_ich4_lpc_acpi);
 514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_12,        quirk_ich4_lpc_acpi);
 515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_0,         quirk_ich4_lpc_acpi);
 516DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_12,        quirk_ich4_lpc_acpi);
 517DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801EB_0,         quirk_ich4_lpc_acpi);
 518DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_ESB_1,             quirk_ich4_lpc_acpi);
 519
 520static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
 521{
 522        u8 enable;
 523
 524        pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
 525        if (enable & ICH6_ACPI_EN)
 526                quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
 527                                 "ICH6 ACPI/GPIO/TCO");
 528
 529        pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
 530        if (enable & ICH6_GPIO_EN)
 531                quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
 532                                "ICH6 GPIO");
 533}
 534
 535static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
 536{
 537        u32 val;
 538        u32 size, base;
 539
 540        pci_read_config_dword(dev, reg, &val);
 541
 542        /* Enabled? */
 543        if (!(val & 1))
 544                return;
 545        base = val & 0xfffc;
 546        if (dynsize) {
 547                /*
 548                 * This is not correct. It is 16, 32 or 64 bytes depending on
 549                 * register D31:F0:ADh bits 5:4.
 550                 *
 551                 * But this gets us at least _part_ of it.
 552                 */
 553                size = 16;
 554        } else {
 555                size = 128;
 556        }
 557        base &= ~(size-1);
 558
 559        /* Just print it out for now. We should reserve it after more debugging */
 560        dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
 561}
 562
 563static void quirk_ich6_lpc(struct pci_dev *dev)
 564{
 565        /* Shared ACPI/GPIO decode with all ICH6+ */
 566        ich6_lpc_acpi_gpio(dev);
 567
 568        /* ICH6-specific generic IO decode */
 569        ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
 570        ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
 571}
 572DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
 573DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
 574
 575static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
 576{
 577        u32 val;
 578        u32 mask, base;
 579
 580        pci_read_config_dword(dev, reg, &val);
 581
 582        /* Enabled? */
 583        if (!(val & 1))
 584                return;
 585
 586        /*
 587         * IO base in bits 15:2, mask in bits 23:18, both
 588         * are dword-based
 589         */
 590        base = val & 0xfffc;
 591        mask = (val >> 16) & 0xfc;
 592        mask |= 3;
 593
 594        /* Just print it out for now. We should reserve it after more debugging */
 595        dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
 596}
 597
 598/* ICH7-10 has the same common LPC generic IO decode registers */
 599static void quirk_ich7_lpc(struct pci_dev *dev)
 600{
 601        /* We share the common ACPI/GPIO decode with ICH6 */
 602        ich6_lpc_acpi_gpio(dev);
 603
 604        /* And have 4 ICH7+ generic decodes */
 605        ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
 606        ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
 607        ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
 608        ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
 609}
 610DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
 611DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
 612DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
 613DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
 614DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
 615DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
 616DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
 617DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
 618DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
 619DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
 620DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
 621DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
 622DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
 623
 624/*
 625 * VIA ACPI: One IO region pointed to by longword at
 626 *      0x48 or 0x20 (256 bytes of ACPI registers)
 627 */
 628static void quirk_vt82c586_acpi(struct pci_dev *dev)
 629{
 630        if (dev->revision & 0x10)
 631                quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
 632                                "vt82c586 ACPI");
 633}
 634DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C586_3,     quirk_vt82c586_acpi);
 635
 636/*
 637 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
 638 *      0x48 (256 bytes of ACPI registers)
 639 *      0x70 (128 bytes of hardware monitoring register)
 640 *      0x90 (16 bytes of SMB registers)
 641 */
 642static void quirk_vt82c686_acpi(struct pci_dev *dev)
 643{
 644        quirk_vt82c586_acpi(dev);
 645
 646        quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
 647                                 "vt82c686 HW-mon");
 648
 649        quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
 650}
 651DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C686_4,     quirk_vt82c686_acpi);
 652
 653/*
 654 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
 655 *      0x88 (128 bytes of power management registers)
 656 *      0xd0 (16 bytes of SMB registers)
 657 */
 658static void quirk_vt8235_acpi(struct pci_dev *dev)
 659{
 660        quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
 661        quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
 662}
 663DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
 664
 665/*
 666 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
 667 *      Disable fast back-to-back on the secondary bus segment
 668 */
 669static void quirk_xio2000a(struct pci_dev *dev)
 670{
 671        struct pci_dev *pdev;
 672        u16 command;
 673
 674        dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
 675                "secondary bus fast back-to-back transfers disabled\n");
 676        list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
 677                pci_read_config_word(pdev, PCI_COMMAND, &command);
 678                if (command & PCI_COMMAND_FAST_BACK)
 679                        pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
 680        }
 681}
 682DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
 683                        quirk_xio2000a);
 684
 685#ifdef CONFIG_X86_IO_APIC 
 686
 687#include <asm/io_apic.h>
 688
 689/*
 690 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
 691 * devices to the external APIC.
 692 *
 693 * TODO: When we have device-specific interrupt routers,
 694 * this code will go away from quirks.
 695 */
 696static void quirk_via_ioapic(struct pci_dev *dev)
 697{
 698        u8 tmp;
 699        
 700        if (nr_ioapics < 1)
 701                tmp = 0;    /* nothing routed to external APIC */
 702        else
 703                tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
 704                
 705        dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
 706               tmp == 0 ? "Disa" : "Ena");
 707
 708        /* Offset 0x58: External APIC IRQ output control */
 709        pci_write_config_byte (dev, 0x58, tmp);
 710}
 711DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_82C686,       quirk_via_ioapic);
 712DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,       PCI_DEVICE_ID_VIA_82C686,       quirk_via_ioapic);
 713
 714/*
 715 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
 716 * This leads to doubled level interrupt rates.
 717 * Set this bit to get rid of cycle wastage.
 718 * Otherwise uncritical.
 719 */
 720static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
 721{
 722        u8 misc_control2;
 723#define BYPASS_APIC_DEASSERT 8
 724
 725        pci_read_config_byte(dev, 0x5B, &misc_control2);
 726        if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
 727                dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
 728                pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
 729        }
 730}
 731DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,      PCI_DEVICE_ID_VIA_8237,         quirk_via_vt8237_bypass_apic_deassert);
 732DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,       PCI_DEVICE_ID_VIA_8237,         quirk_via_vt8237_bypass_apic_deassert);
 733
 734/*
 735 * The AMD io apic can hang the box when an apic irq is masked.
 736 * We check all revs >= B0 (yet not in the pre production!) as the bug
 737 * is currently marked NoFix
 738 *
 739 * We have multiple reports of hangs with this chipset that went away with
 740 * noapic specified. For the moment we assume it's the erratum. We may be wrong
 741 * of course. However the advice is demonstrably good even if so..
 742 */
 743static void quirk_amd_ioapic(struct pci_dev *dev)
 744{
 745        if (dev->revision >= 0x02) {
 746                dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
 747                dev_warn(&dev->dev, "        : booting with the \"noapic\" option\n");
 748        }
 749}
 750DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_VIPER_7410,   quirk_amd_ioapic);
 751
 752static void quirk_ioapic_rmw(struct pci_dev *dev)
 753{
 754        if (dev->devfn == 0 && dev->bus->number == 0)
 755                sis_apic_bug = 1;
 756}
 757DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,       PCI_ANY_ID,                     quirk_ioapic_rmw);
 758#endif /* CONFIG_X86_IO_APIC */
 759
 760/*
 761 * Some settings of MMRBC can lead to data corruption so block changes.
 762 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
 763 */
 764static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
 765{
 766        if (dev->subordinate && dev->revision <= 0x12) {
 767                dev_info(&dev->dev, "AMD8131 rev %x detected; "
 768                        "disabling PCI-X MMRBC\n", dev->revision);
 769                dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
 770        }
 771}
 772DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
 773
 774/*
 775 * FIXME: it is questionable that quirk_via_acpi
 776 * is needed.  It shows up as an ISA bridge, and does not
 777 * support the PCI_INTERRUPT_LINE register at all.  Therefore
 778 * it seems like setting the pci_dev's 'irq' to the
 779 * value of the ACPI SCI interrupt is only done for convenience.
 780 *      -jgarzik
 781 */
 782static void quirk_via_acpi(struct pci_dev *d)
 783{
 784        /*
 785         * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
 786         */
 787        u8 irq;
 788        pci_read_config_byte(d, 0x42, &irq);
 789        irq &= 0xf;
 790        if (irq && (irq != 2))
 791                d->irq = irq;
 792}
 793DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C586_3,     quirk_via_acpi);
 794DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C686_4,     quirk_via_acpi);
 795
 796
 797/*
 798 *      VIA bridges which have VLink
 799 */
 800
 801static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
 802
 803static void quirk_via_bridge(struct pci_dev *dev)
 804{
 805        /* See what bridge we have and find the device ranges */
 806        switch (dev->device) {
 807        case PCI_DEVICE_ID_VIA_82C686:
 808                /* The VT82C686 is special, it attaches to PCI and can have
 809                   any device number. All its subdevices are functions of
 810                   that single device. */
 811                via_vlink_dev_lo = PCI_SLOT(dev->devfn);
 812                via_vlink_dev_hi = PCI_SLOT(dev->devfn);
 813                break;
 814        case PCI_DEVICE_ID_VIA_8237:
 815        case PCI_DEVICE_ID_VIA_8237A:
 816                via_vlink_dev_lo = 15;
 817                break;
 818        case PCI_DEVICE_ID_VIA_8235:
 819                via_vlink_dev_lo = 16;
 820                break;
 821        case PCI_DEVICE_ID_VIA_8231:
 822        case PCI_DEVICE_ID_VIA_8233_0:
 823        case PCI_DEVICE_ID_VIA_8233A:
 824        case PCI_DEVICE_ID_VIA_8233C_0:
 825                via_vlink_dev_lo = 17;
 826                break;
 827        }
 828}
 829DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C686,       quirk_via_bridge);
 830DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8231,         quirk_via_bridge);
 831DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8233_0,       quirk_via_bridge);
 832DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8233A,        quirk_via_bridge);
 833DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8233C_0,      quirk_via_bridge);
 834DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8235,         quirk_via_bridge);
 835DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8237,         quirk_via_bridge);
 836DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8237A,        quirk_via_bridge);
 837
 838/**
 839 *      quirk_via_vlink         -       VIA VLink IRQ number update
 840 *      @dev: PCI device
 841 *
 842 *      If the device we are dealing with is on a PIC IRQ we need to
 843 *      ensure that the IRQ line register which usually is not relevant
 844 *      for PCI cards, is actually written so that interrupts get sent
 845 *      to the right place.
 846 *      We only do this on systems where a VIA south bridge was detected,
 847 *      and only for VIA devices on the motherboard (see quirk_via_bridge
 848 *      above).
 849 */
 850
 851static void quirk_via_vlink(struct pci_dev *dev)
 852{
 853        u8 irq, new_irq;
 854
 855        /* Check if we have VLink at all */
 856        if (via_vlink_dev_lo == -1)
 857                return;
 858
 859        new_irq = dev->irq;
 860
 861        /* Don't quirk interrupts outside the legacy IRQ range */
 862        if (!new_irq || new_irq > 15)
 863                return;
 864
 865        /* Internal device ? */
 866        if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
 867            PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
 868                return;
 869
 870        /* This is an internal VLink device on a PIC interrupt. The BIOS
 871           ought to have set this but may not have, so we redo it */
 872
 873        pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 874        if (new_irq != irq) {
 875                dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
 876                        irq, new_irq);
 877                udelay(15);     /* unknown if delay really needed */
 878                pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
 879        }
 880}
 881DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
 882
 883/*
 884 * VIA VT82C598 has its device ID settable and many BIOSes
 885 * set it to the ID of VT82C597 for backward compatibility.
 886 * We need to switch it off to be able to recognize the real
 887 * type of the chip.
 888 */
 889static void quirk_vt82c598_id(struct pci_dev *dev)
 890{
 891        pci_write_config_byte(dev, 0xfc, 0);
 892        pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
 893}
 894DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C597_0,     quirk_vt82c598_id);
 895
 896/*
 897 * CardBus controllers have a legacy base address that enables them
 898 * to respond as i82365 pcmcia controllers.  We don't want them to
 899 * do this even if the Linux CardBus driver is not loaded, because
 900 * the Linux i82365 driver does not (and should not) handle CardBus.
 901 */
 902static void quirk_cardbus_legacy(struct pci_dev *dev)
 903{
 904        pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
 905}
 906DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
 907                        PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
 908DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
 909                        PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
 910
 911/*
 912 * Following the PCI ordering rules is optional on the AMD762. I'm not
 913 * sure what the designers were smoking but let's not inhale...
 914 *
 915 * To be fair to AMD, it follows the spec by default, its BIOS people
 916 * who turn it off!
 917 */
 918static void quirk_amd_ordering(struct pci_dev *dev)
 919{
 920        u32 pcic;
 921        pci_read_config_dword(dev, 0x4C, &pcic);
 922        if ((pcic&6)!=6) {
 923                pcic |= 6;
 924                dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
 925                pci_write_config_dword(dev, 0x4C, pcic);
 926                pci_read_config_dword(dev, 0x84, &pcic);
 927                pcic |= (1<<23);        /* Required in this mode */
 928                pci_write_config_dword(dev, 0x84, pcic);
 929        }
 930}
 931DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
 932DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD,       PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
 933
 934/*
 935 *      DreamWorks provided workaround for Dunord I-3000 problem
 936 *
 937 *      This card decodes and responds to addresses not apparently
 938 *      assigned to it. We force a larger allocation to ensure that
 939 *      nothing gets put too close to it.
 940 */
 941static void quirk_dunord(struct pci_dev *dev)
 942{
 943        struct resource *r = &dev->resource [1];
 944        r->start = 0;
 945        r->end = 0xffffff;
 946}
 947DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD,  PCI_DEVICE_ID_DUNORD_I3000,     quirk_dunord);
 948
 949/*
 950 * i82380FB mobile docking controller: its PCI-to-PCI bridge
 951 * is subtractive decoding (transparent), and does indicate this
 952 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
 953 * instead of 0x01.
 954 */
 955static void quirk_transparent_bridge(struct pci_dev *dev)
 956{
 957        dev->transparent = 1;
 958}
 959DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82380FB,    quirk_transparent_bridge);
 960DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605,  quirk_transparent_bridge);
 961
 962/*
 963 * Common misconfiguration of the MediaGX/Geode PCI master that will
 964 * reduce PCI bandwidth from 70MB/s to 25MB/s.  See the GXM/GXLV/GX1
 965 * datasheets found at http://www.national.com/analog for info on what
 966 * these bits do.  <christer@weinigel.se>
 967 */
 968static void quirk_mediagx_master(struct pci_dev *dev)
 969{
 970        u8 reg;
 971        pci_read_config_byte(dev, 0x41, &reg);
 972        if (reg & 2) {
 973                reg &= ~2;
 974                dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
 975                pci_write_config_byte(dev, 0x41, reg);
 976        }
 977}
 978DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX,    PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
 979DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX,   PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
 980
 981/*
 982 *      Ensure C0 rev restreaming is off. This is normally done by
 983 *      the BIOS but in the odd case it is not the results are corruption
 984 *      hence the presence of a Linux check
 985 */
 986static void quirk_disable_pxb(struct pci_dev *pdev)
 987{
 988        u16 config;
 989        
 990        if (pdev->revision != 0x04)             /* Only C0 requires this */
 991                return;
 992        pci_read_config_word(pdev, 0x40, &config);
 993        if (config & (1<<6)) {
 994                config &= ~(1<<6);
 995                pci_write_config_word(pdev, 0x40, config);
 996                dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
 997        }
 998}
 999DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82454NX,    quirk_disable_pxb);
1000DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82454NX,    quirk_disable_pxb);
1001
1002static void quirk_amd_ide_mode(struct pci_dev *pdev)
1003{
1004        /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1005        u8 tmp;
1006
1007        pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1008        if (tmp == 0x01) {
1009                pci_read_config_byte(pdev, 0x40, &tmp);
1010                pci_write_config_byte(pdev, 0x40, tmp|1);
1011                pci_write_config_byte(pdev, 0x9, 1);
1012                pci_write_config_byte(pdev, 0xa, 6);
1013                pci_write_config_byte(pdev, 0x40, tmp);
1014
1015                pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1016                dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1017        }
1018}
1019DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1020DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1021DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1022DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1023DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1024DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1025
1026/*
1027 *      Serverworks CSB5 IDE does not fully support native mode
1028 */
1029static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1030{
1031        u8 prog;
1032        pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1033        if (prog & 5) {
1034                prog &= ~5;
1035                pdev->class &= ~5;
1036                pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1037                /* PCI layer will sort out resources */
1038        }
1039}
1040DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1041
1042/*
1043 *      Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1044 */
1045static void quirk_ide_samemode(struct pci_dev *pdev)
1046{
1047        u8 prog;
1048
1049        pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1050
1051        if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1052                dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1053                prog &= ~5;
1054                pdev->class &= ~5;
1055                pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1056        }
1057}
1058DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1059
1060/*
1061 * Some ATA devices break if put into D3
1062 */
1063
1064static void quirk_no_ata_d3(struct pci_dev *pdev)
1065{
1066        pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1067}
1068/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1069DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1070                                PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1071DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1072                                PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1073/* ALi loses some register settings that we cannot then restore */
1074DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1075                                PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1076/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1077   occur when mode detecting */
1078DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1079                                PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1080
1081/* This was originally an Alpha specific thing, but it really fits here.
1082 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1083 */
1084static void quirk_eisa_bridge(struct pci_dev *dev)
1085{
1086        dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1087}
1088DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82375,      quirk_eisa_bridge);
1089
1090
1091/*
1092 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1093 * is not activated. The myth is that Asus said that they do not want the
1094 * users to be irritated by just another PCI Device in the Win98 device
1095 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 
1096 * package 2.7.0 for details)
1097 *
1098 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 
1099 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 
1100 * becomes necessary to do this tweak in two steps -- the chosen trigger
1101 * is either the Host bridge (preferred) or on-board VGA controller.
1102 *
1103 * Note that we used to unhide the SMBus that way on Toshiba laptops
1104 * (Satellite A40 and Tecra M2) but then found that the thermal management
1105 * was done by SMM code, which could cause unsynchronized concurrent
1106 * accesses to the SMBus registers, with potentially bad effects. Thus you
1107 * should be very careful when adding new entries: if SMM is accessing the
1108 * Intel SMBus, this is a very good reason to leave it hidden.
1109 *
1110 * Likewise, many recent laptops use ACPI for thermal management. If the
1111 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1112 * natively, and keeping the SMBus hidden is the right thing to do. If you
1113 * are about to add an entry in the table below, please first disassemble
1114 * the DSDT and double-check that there is no code accessing the SMBus.
1115 */
1116static int asus_hides_smbus;
1117
1118static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1119{
1120        if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1121                if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1122                        switch(dev->subsystem_device) {
1123                        case 0x8025: /* P4B-LX */
1124                        case 0x8070: /* P4B */
1125                        case 0x8088: /* P4B533 */
1126                        case 0x1626: /* L3C notebook */
1127                                asus_hides_smbus = 1;
1128                        }
1129                else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1130                        switch(dev->subsystem_device) {
1131                        case 0x80b1: /* P4GE-V */
1132                        case 0x80b2: /* P4PE */
1133                        case 0x8093: /* P4B533-V */
1134                                asus_hides_smbus = 1;
1135                        }
1136                else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1137                        switch(dev->subsystem_device) {
1138                        case 0x8030: /* P4T533 */
1139                                asus_hides_smbus = 1;
1140                        }
1141                else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1142                        switch (dev->subsystem_device) {
1143                        case 0x8070: /* P4G8X Deluxe */
1144                                asus_hides_smbus = 1;
1145                        }
1146                else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1147                        switch (dev->subsystem_device) {
1148                        case 0x80c9: /* PU-DLS */
1149                                asus_hides_smbus = 1;
1150                        }
1151                else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1152                        switch (dev->subsystem_device) {
1153                        case 0x1751: /* M2N notebook */
1154                        case 0x1821: /* M5N notebook */
1155                        case 0x1897: /* A6L notebook */
1156                                asus_hides_smbus = 1;
1157                        }
1158                else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1159                        switch (dev->subsystem_device) {
1160                        case 0x184b: /* W1N notebook */
1161                        case 0x186a: /* M6Ne notebook */
1162                                asus_hides_smbus = 1;
1163                        }
1164                else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1165                        switch (dev->subsystem_device) {
1166                        case 0x80f2: /* P4P800-X */
1167                                asus_hides_smbus = 1;
1168                        }
1169                else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1170                        switch (dev->subsystem_device) {
1171                        case 0x1882: /* M6V notebook */
1172                        case 0x1977: /* A6VA notebook */
1173                                asus_hides_smbus = 1;
1174                        }
1175        } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1176                if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)
1177                        switch(dev->subsystem_device) {
1178                        case 0x088C: /* HP Compaq nc8000 */
1179                        case 0x0890: /* HP Compaq nc6000 */
1180                                asus_hides_smbus = 1;
1181                        }
1182                else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1183                        switch (dev->subsystem_device) {
1184                        case 0x12bc: /* HP D330L */
1185                        case 0x12bd: /* HP D530 */
1186                        case 0x006a: /* HP Compaq nx9500 */
1187                                asus_hides_smbus = 1;
1188                        }
1189                else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1190                        switch (dev->subsystem_device) {
1191                        case 0x12bf: /* HP xw4100 */
1192                                asus_hides_smbus = 1;
1193                        }
1194       } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1195               if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)
1196                       switch(dev->subsystem_device) {
1197                       case 0xC00C: /* Samsung P35 notebook */
1198                               asus_hides_smbus = 1;
1199                       }
1200        } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1201                if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1202                        switch(dev->subsystem_device) {
1203                        case 0x0058: /* Compaq Evo N620c */
1204                                asus_hides_smbus = 1;
1205                        }
1206                else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1207                        switch(dev->subsystem_device) {
1208                        case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1209                                /* Motherboard doesn't have Host bridge
1210                                 * subvendor/subdevice IDs, therefore checking
1211                                 * its on-board VGA controller */
1212                                asus_hides_smbus = 1;
1213                        }
1214                else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1215                        switch(dev->subsystem_device) {
1216                        case 0x00b8: /* Compaq Evo D510 CMT */
1217                        case 0x00b9: /* Compaq Evo D510 SFF */
1218                        case 0x00ba: /* Compaq Evo D510 USDT */
1219                                /* Motherboard doesn't have Host bridge
1220                                 * subvendor/subdevice IDs and on-board VGA
1221                                 * controller is disabled if an AGP card is
1222                                 * inserted, therefore checking USB UHCI
1223                                 * Controller #1 */
1224                                asus_hides_smbus = 1;
1225                        }
1226                else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1227                        switch (dev->subsystem_device) {
1228                        case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1229                                /* Motherboard doesn't have host bridge
1230                                 * subvendor/subdevice IDs, therefore checking
1231                                 * its on-board VGA controller */
1232                                asus_hides_smbus = 1;
1233                        }
1234        }
1235}
1236DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82845_HB,   asus_hides_smbus_hostbridge);
1237DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82845G_HB,  asus_hides_smbus_hostbridge);
1238DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82850_HB,   asus_hides_smbus_hostbridge);
1239DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82865_HB,   asus_hides_smbus_hostbridge);
1240DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82875_HB,   asus_hides_smbus_hostbridge);
1241DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_7205_0,     asus_hides_smbus_hostbridge);
1242DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_E7501_MCH,  asus_hides_smbus_hostbridge);
1243DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1244DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1245DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1246
1247DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82810_IG3,  asus_hides_smbus_hostbridge);
1248DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801DB_2,  asus_hides_smbus_hostbridge);
1249DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82815_CGC,  asus_hides_smbus_hostbridge);
1250
1251static void asus_hides_smbus_lpc(struct pci_dev *dev)
1252{
1253        u16 val;
1254        
1255        if (likely(!asus_hides_smbus))
1256                return;
1257
1258        pci_read_config_word(dev, 0xF2, &val);
1259        if (val & 0x8) {
1260                pci_write_config_word(dev, 0xF2, val & (~0x8));
1261                pci_read_config_word(dev, 0xF2, &val);
1262                if (val & 0x8)
1263                        dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1264                else
1265                        dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1266        }
1267}
1268DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801AA_0,  asus_hides_smbus_lpc);
1269DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801DB_0,  asus_hides_smbus_lpc);
1270DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801BA_0,  asus_hides_smbus_lpc);
1271DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801CA_0,  asus_hides_smbus_lpc);
1272DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1273DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1274DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801EB_0,  asus_hides_smbus_lpc);
1275DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801AA_0,  asus_hides_smbus_lpc);
1276DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801DB_0,  asus_hides_smbus_lpc);
1277DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801BA_0,  asus_hides_smbus_lpc);
1278DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801CA_0,  asus_hides_smbus_lpc);
1279DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1280DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1281DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82801EB_0,  asus_hides_smbus_lpc);
1282
1283/* It appears we just have one such device. If not, we have a warning */
1284static void __iomem *asus_rcba_base;
1285static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1286{
1287        u32 rcba;
1288
1289        if (likely(!asus_hides_smbus))
1290                return;
1291        WARN_ON(asus_rcba_base);
1292
1293        pci_read_config_dword(dev, 0xF0, &rcba);
1294        /* use bits 31:14, 16 kB aligned */
1295        asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1296        if (asus_rcba_base == NULL)
1297                return;
1298}
1299
1300static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1301{
1302        u32 val;
1303
1304        if (likely(!asus_hides_smbus || !asus_rcba_base))
1305                return;
1306        /* read the Function Disable register, dword mode only */
1307        val = readl(asus_rcba_base + 0x3418);
1308        writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1309}
1310
1311static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1312{
1313        if (likely(!asus_hides_smbus || !asus_rcba_base))
1314                return;
1315        iounmap(asus_rcba_base);
1316        asus_rcba_base = NULL;
1317        dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1318}
1319
1320static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1321{
1322        asus_hides_smbus_lpc_ich6_suspend(dev);
1323        asus_hides_smbus_lpc_ich6_resume_early(dev);
1324        asus_hides_smbus_lpc_ich6_resume(dev);
1325}
1326DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH6_1,     asus_hides_smbus_lpc_ich6);
1327DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL,  PCI_DEVICE_ID_INTEL_ICH6_1,     asus_hides_smbus_lpc_ich6_suspend);
1328DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH6_1,     asus_hides_smbus_lpc_ich6_resume);
1329DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_ICH6_1,     asus_hides_smbus_lpc_ich6_resume_early);
1330
1331/*
1332 * SiS 96x south bridge: BIOS typically hides SMBus device...
1333 */
1334static void quirk_sis_96x_smbus(struct pci_dev *dev)
1335{
1336        u8 val = 0;
1337        pci_read_config_byte(dev, 0x77, &val);
1338        if (val & 0x10) {
1339                dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1340                pci_write_config_byte(dev, 0x77, val & ~0x10);
1341        }
1342}
1343DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_961,           quirk_sis_96x_smbus);
1344DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_962,           quirk_sis_96x_smbus);
1345DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_963,           quirk_sis_96x_smbus);
1346DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_LPC,           quirk_sis_96x_smbus);
1347DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,        PCI_DEVICE_ID_SI_961,           quirk_sis_96x_smbus);
1348DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,        PCI_DEVICE_ID_SI_962,           quirk_sis_96x_smbus);
1349DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,        PCI_DEVICE_ID_SI_963,           quirk_sis_96x_smbus);
1350DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,        PCI_DEVICE_ID_SI_LPC,           quirk_sis_96x_smbus);
1351
1352/*
1353 * ... This is further complicated by the fact that some SiS96x south
1354 * bridges pretend to be 85C503/5513 instead.  In that case see if we
1355 * spotted a compatible north bridge to make sure.
1356 * (pci_find_device doesn't work yet)
1357 *
1358 * We can also enable the sis96x bit in the discovery register..
1359 */
1360#define SIS_DETECT_REGISTER 0x40
1361
1362static void quirk_sis_503(struct pci_dev *dev)
1363{
1364        u8 reg;
1365        u16 devid;
1366
1367        pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1368        pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1369        pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1370        if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1371                pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1372                return;
1373        }
1374
1375        /*
1376         * Ok, it now shows up as a 96x.. run the 96x quirk by
1377         * hand in case it has already been processed.
1378         * (depends on link order, which is apparently not guaranteed)
1379         */
1380        dev->device = devid;
1381        quirk_sis_96x_smbus(dev);
1382}
1383DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_503,           quirk_sis_503);
1384DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,        PCI_DEVICE_ID_SI_503,           quirk_sis_503);
1385
1386
1387/*
1388 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1389 * and MC97 modem controller are disabled when a second PCI soundcard is
1390 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1391 * -- bjd
1392 */
1393static void asus_hides_ac97_lpc(struct pci_dev *dev)
1394{
1395        u8 val;
1396        int asus_hides_ac97 = 0;
1397
1398        if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1399                if (dev->device == PCI_DEVICE_ID_VIA_8237)
1400                        asus_hides_ac97 = 1;
1401        }
1402
1403        if (!asus_hides_ac97)
1404                return;
1405
1406        pci_read_config_byte(dev, 0x50, &val);
1407        if (val & 0xc0) {
1408                pci_write_config_byte(dev, 0x50, val & (~0xc0));
1409                pci_read_config_byte(dev, 0x50, &val);
1410                if (val & 0xc0)
1411                        dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1412                else
1413                        dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1414        }
1415}
1416DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1417DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,       PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1418
1419#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1420
1421/*
1422 *      If we are using libata we can drive this chip properly but must
1423 *      do this early on to make the additional device appear during
1424 *      the PCI scanning.
1425 */
1426static void quirk_jmicron_ata(struct pci_dev *pdev)
1427{
1428        u32 conf1, conf5, class;
1429        u8 hdr;
1430
1431        /* Only poke fn 0 */
1432        if (PCI_FUNC(pdev->devfn))
1433                return;
1434
1435        pci_read_config_dword(pdev, 0x40, &conf1);
1436        pci_read_config_dword(pdev, 0x80, &conf5);
1437
1438        conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1439        conf5 &= ~(1 << 24);  /* Clear bit 24 */
1440
1441        switch (pdev->device) {
1442        case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1443        case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1444        case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1445                /* The controller should be in single function ahci mode */
1446                conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1447                break;
1448
1449        case PCI_DEVICE_ID_JMICRON_JMB365:
1450        case PCI_DEVICE_ID_JMICRON_JMB366:
1451                /* Redirect IDE second PATA port to the right spot */
1452                conf5 |= (1 << 24);
1453                /* Fall through */
1454        case PCI_DEVICE_ID_JMICRON_JMB361:
1455        case PCI_DEVICE_ID_JMICRON_JMB363:
1456        case PCI_DEVICE_ID_JMICRON_JMB369:
1457                /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1458                /* Set the class codes correctly and then direct IDE 0 */
1459                conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1460                break;
1461
1462        case PCI_DEVICE_ID_JMICRON_JMB368:
1463                /* The controller should be in single function IDE mode */
1464                conf1 |= 0x00C00000; /* Set 22, 23 */
1465                break;
1466        }
1467
1468        pci_write_config_dword(pdev, 0x40, conf1);
1469        pci_write_config_dword(pdev, 0x80, conf5);
1470
1471        /* Update pdev accordingly */
1472        pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1473        pdev->hdr_type = hdr & 0x7f;
1474        pdev->multifunction = !!(hdr & 0x80);
1475
1476        pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1477        pdev->class = class >> 8;
1478}
1479DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1480DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1481DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1482DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1483DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1484DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1485DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1486DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1487DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1488DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1489DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1490DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1491DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1492DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1493DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1494DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1495DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1496DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1497
1498#endif
1499
1500#ifdef CONFIG_X86_IO_APIC
1501static void quirk_alder_ioapic(struct pci_dev *pdev)
1502{
1503        int i;
1504
1505        if ((pdev->class >> 8) != 0xff00)
1506                return;
1507
1508        /* the first BAR is the location of the IO APIC...we must
1509         * not touch this (and it's already covered by the fixmap), so
1510         * forcibly insert it into the resource tree */
1511        if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1512                insert_resource(&iomem_resource, &pdev->resource[0]);
1513
1514        /* The next five BARs all seem to be rubbish, so just clean
1515         * them out */
1516        for (i=1; i < 6; i++) {
1517                memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1518        }
1519
1520}
1521DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_EESSC,      quirk_alder_ioapic);
1522#endif
1523
1524static void quirk_pcie_mch(struct pci_dev *pdev)
1525{
1526        pci_msi_off(pdev);
1527        pdev->no_msi = 1;
1528}
1529DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_E7520_MCH,  quirk_pcie_mch);
1530DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_E7320_MCH,  quirk_pcie_mch);
1531DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_E7525_MCH,  quirk_pcie_mch);
1532
1533
1534/*
1535 * It's possible for the MSI to get corrupted if shpc and acpi
1536 * are used together on certain PXH-based systems.
1537 */
1538static void quirk_pcie_pxh(struct pci_dev *dev)
1539{
1540        pci_msi_off(dev);
1541        dev->no_msi = 1;
1542        dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1543}
1544DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHD_0,     quirk_pcie_pxh);
1545DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHD_1,     quirk_pcie_pxh);
1546DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXH_0,      quirk_pcie_pxh);
1547DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXH_1,      quirk_pcie_pxh);
1548DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHV,       quirk_pcie_pxh);
1549
1550/*
1551 * Some Intel PCI Express chipsets have trouble with downstream
1552 * device power management.
1553 */
1554static void quirk_intel_pcie_pm(struct pci_dev * dev)
1555{
1556        pci_pm_d3_delay = 120;
1557        dev->no_d1d2 = 1;
1558}
1559
1560DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e2, quirk_intel_pcie_pm);
1561DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e3, quirk_intel_pcie_pm);
1562DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e4, quirk_intel_pcie_pm);
1563DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e5, quirk_intel_pcie_pm);
1564DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e6, quirk_intel_pcie_pm);
1565DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25e7, quirk_intel_pcie_pm);
1566DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25f7, quirk_intel_pcie_pm);
1567DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25f8, quirk_intel_pcie_pm);
1568DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25f9, quirk_intel_pcie_pm);
1569DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x25fa, quirk_intel_pcie_pm);
1570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2601, quirk_intel_pcie_pm);
1571DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2602, quirk_intel_pcie_pm);
1572DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2603, quirk_intel_pcie_pm);
1573DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2604, quirk_intel_pcie_pm);
1574DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2605, quirk_intel_pcie_pm);
1575DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2606, quirk_intel_pcie_pm);
1576DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2607, quirk_intel_pcie_pm);
1577DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2608, quirk_intel_pcie_pm);
1578DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x2609, quirk_intel_pcie_pm);
1579DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x260a, quirk_intel_pcie_pm);
1580DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    0x260b, quirk_intel_pcie_pm);
1581
1582#ifdef CONFIG_X86_IO_APIC
1583/*
1584 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1585 * remap the original interrupt in the linux kernel to the boot interrupt, so
1586 * that a PCI device's interrupt handler is installed on the boot interrupt
1587 * line instead.
1588 */
1589static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1590{
1591        if (noioapicquirk || noioapicreroute)
1592                return;
1593
1594        dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1595        dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1596                 dev->vendor, dev->device);
1597}
1598DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80333_0,    quirk_reroute_to_boot_interrupts_intel);
1599DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80333_1,    quirk_reroute_to_boot_interrupts_intel);
1600DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_ESB2_0,     quirk_reroute_to_boot_interrupts_intel);
1601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXH_0,      quirk_reroute_to_boot_interrupts_intel);
1602DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXH_1,      quirk_reroute_to_boot_interrupts_intel);
1603DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHV,       quirk_reroute_to_boot_interrupts_intel);
1604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80332_0,    quirk_reroute_to_boot_interrupts_intel);
1605DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80332_1,    quirk_reroute_to_boot_interrupts_intel);
1606DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_80333_0,    quirk_reroute_to_boot_interrupts_intel);
1607DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_80333_1,    quirk_reroute_to_boot_interrupts_intel);
1608DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB2_0,     quirk_reroute_to_boot_interrupts_intel);
1609DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_PXH_0,      quirk_reroute_to_boot_interrupts_intel);
1610DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_PXH_1,      quirk_reroute_to_boot_interrupts_intel);
1611DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_PXHV,       quirk_reroute_to_boot_interrupts_intel);
1612DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_80332_0,    quirk_reroute_to_boot_interrupts_intel);
1613DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_80332_1,    quirk_reroute_to_boot_interrupts_intel);
1614
1615/*
1616 * On some chipsets we can disable the generation of legacy INTx boot
1617 * interrupts.
1618 */
1619
1620/*
1621 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1622 * 300641-004US, section 5.7.3.
1623 */
1624#define INTEL_6300_IOAPIC_ABAR          0x40
1625#define INTEL_6300_DISABLE_BOOT_IRQ     (1<<14)
1626
1627static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1628{
1629        u16 pci_config_word;
1630
1631        if (noioapicquirk)
1632                return;
1633
1634        pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1635        pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1636        pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1637
1638        dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1639                 dev->vendor, dev->device);
1640}
1641DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10,      quirk_disable_intel_boot_interrupt);
1642DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10,     quirk_disable_intel_boot_interrupt);
1643
1644/*
1645 * disable boot interrupts on HT-1000
1646 */
1647#define BC_HT1000_FEATURE_REG           0x64
1648#define BC_HT1000_PIC_REGS_ENABLE       (1<<0)
1649#define BC_HT1000_MAP_IDX               0xC00
1650#define BC_HT1000_MAP_DATA              0xC01
1651
1652static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1653{
1654        u32 pci_config_dword;
1655        u8 irq;
1656
1657        if (noioapicquirk)
1658                return;
1659
1660        pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1661        pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1662                        BC_HT1000_PIC_REGS_ENABLE);
1663
1664        for (irq = 0x10; irq < 0x10 + 32; irq++) {
1665                outb(irq, BC_HT1000_MAP_IDX);
1666                outb(0x00, BC_HT1000_MAP_DATA);
1667        }
1668
1669        pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1670
1671        dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1672                 dev->vendor, dev->device);
1673}
1674DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB,        quirk_disable_broadcom_boot_interrupt);
1675DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB,       quirk_disable_broadcom_boot_interrupt);
1676
1677/*
1678 * disable boot interrupts on AMD and ATI chipsets
1679 */
1680/*
1681 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1682 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1683 * (due to an erratum).
1684 */
1685#define AMD_813X_MISC                   0x40
1686#define AMD_813X_NOIOAMODE              (1<<0)
1687#define AMD_813X_REV_B1                 0x12
1688#define AMD_813X_REV_B2                 0x13
1689
1690static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1691{
1692        u32 pci_config_dword;
1693
1694        if (noioapicquirk)
1695                return;
1696        if ((dev->revision == AMD_813X_REV_B1) ||
1697            (dev->revision == AMD_813X_REV_B2))
1698                return;
1699
1700        pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1701        pci_config_dword &= ~AMD_813X_NOIOAMODE;
1702        pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1703
1704        dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1705                 dev->vendor, dev->device);
1706}
1707DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_8131_BRIDGE,  quirk_disable_amd_813x_boot_interrupt);
1708DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,     PCI_DEVICE_ID_AMD_8131_BRIDGE,  quirk_disable_amd_813x_boot_interrupt);
1709DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_8132_BRIDGE,  quirk_disable_amd_813x_boot_interrupt);
1710DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,     PCI_DEVICE_ID_AMD_8132_BRIDGE,  quirk_disable_amd_813x_boot_interrupt);
1711
1712#define AMD_8111_PCI_IRQ_ROUTING        0x56
1713
1714static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1715{
1716        u16 pci_config_word;
1717
1718        if (noioapicquirk)
1719                return;
1720
1721        pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1722        if (!pci_config_word) {
1723                dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1724                         "already disabled\n", dev->vendor, dev->device);
1725                return;
1726        }
1727        pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1728        dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1729                 dev->vendor, dev->device);
1730}
1731DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS,      quirk_disable_amd_8111_boot_interrupt);
1732DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS,     quirk_disable_amd_8111_boot_interrupt);
1733#endif /* CONFIG_X86_IO_APIC */
1734
1735/*
1736 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1737 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1738 * Re-allocate the region if needed...
1739 */
1740static void quirk_tc86c001_ide(struct pci_dev *dev)
1741{
1742        struct resource *r = &dev->resource[0];
1743
1744        if (r->start & 0x8) {
1745                r->start = 0;
1746                r->end = 0xf;
1747        }
1748}
1749DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1750                         PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1751                         quirk_tc86c001_ide);
1752
1753/*
1754 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1755 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1756 * being read correctly if bit 7 of the base address is set.
1757 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1758 * Re-allocate the regions to a 256-byte boundary if necessary.
1759 */
1760static void quirk_plx_pci9050(struct pci_dev *dev)
1761{
1762        unsigned int bar;
1763
1764        /* Fixed in revision 2 (PCI 9052). */
1765        if (dev->revision >= 2)
1766                return;
1767        for (bar = 0; bar <= 1; bar++)
1768                if (pci_resource_len(dev, bar) == 0x80 &&
1769                    (pci_resource_start(dev, bar) & 0x80)) {
1770                        struct resource *r = &dev->resource[bar];
1771                        dev_info(&dev->dev,
1772                                 "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1773                                 bar);
1774                        r->start = 0;
1775                        r->end = 0xff;
1776                }
1777}
1778DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1779                         quirk_plx_pci9050);
1780/*
1781 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1782 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1783 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1784 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1785 *
1786 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1787 * driver.
1788 */
1789DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1790DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1791
1792static void quirk_netmos(struct pci_dev *dev)
1793{
1794        unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1795        unsigned int num_serial = dev->subsystem_device & 0xf;
1796
1797        /*
1798         * These Netmos parts are multiport serial devices with optional
1799         * parallel ports.  Even when parallel ports are present, they
1800         * are identified as class SERIAL, which means the serial driver
1801         * will claim them.  To prevent this, mark them as class OTHER.
1802         * These combo devices should be claimed by parport_serial.
1803         *
1804         * The subdevice ID is of the form 0x00PS, where <P> is the number
1805         * of parallel ports and <S> is the number of serial ports.
1806         */
1807        switch (dev->device) {
1808        case PCI_DEVICE_ID_NETMOS_9835:
1809                /* Well, this rule doesn't hold for the following 9835 device */
1810                if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1811                                dev->subsystem_device == 0x0299)
1812                        return;
1813        case PCI_DEVICE_ID_NETMOS_9735:
1814        case PCI_DEVICE_ID_NETMOS_9745:
1815        case PCI_DEVICE_ID_NETMOS_9845:
1816        case PCI_DEVICE_ID_NETMOS_9855:
1817                if (num_parallel) {
1818                        dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1819                                "%u serial); changing class SERIAL to OTHER "
1820                                "(use parport_serial)\n",
1821                                dev->device, num_parallel, num_serial);
1822                        dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1823                            (dev->class & 0xff);
1824                }
1825        }
1826}
1827DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1828                         PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1829
1830static void quirk_e100_interrupt(struct pci_dev *dev)
1831{
1832        u16 command, pmcsr;
1833        u8 __iomem *csr;
1834        u8 cmd_hi;
1835        int pm;
1836
1837        switch (dev->device) {
1838        /* PCI IDs taken from drivers/net/e100.c */
1839        case 0x1029:
1840        case 0x1030 ... 0x1034:
1841        case 0x1038 ... 0x103E:
1842        case 0x1050 ... 0x1057:
1843        case 0x1059:
1844        case 0x1064 ... 0x106B:
1845        case 0x1091 ... 0x1095:
1846        case 0x1209:
1847        case 0x1229:
1848        case 0x2449:
1849        case 0x2459:
1850        case 0x245D:
1851        case 0x27DC:
1852                break;
1853        default:
1854                return;
1855        }
1856
1857        /*
1858         * Some firmware hands off the e100 with interrupts enabled,
1859         * which can cause a flood of interrupts if packets are
1860         * received before the driver attaches to the device.  So
1861         * disable all e100 interrupts here.  The driver will
1862         * re-enable them when it's ready.
1863         */
1864        pci_read_config_word(dev, PCI_COMMAND, &command);
1865
1866        if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1867                return;
1868
1869        /*
1870         * Check that the device is in the D0 power state. If it's not,
1871         * there is no point to look any further.
1872         */
1873        pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1874        if (pm) {
1875                pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1876                if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1877                        return;
1878        }
1879
1880        /* Convert from PCI bus to resource space.  */
1881        csr = ioremap(pci_resource_start(dev, 0), 8);
1882        if (!csr) {
1883                dev_warn(&dev->dev, "Can't map e100 registers\n");
1884                return;
1885        }
1886
1887        cmd_hi = readb(csr + 3);
1888        if (cmd_hi == 0) {
1889                dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1890                        "disabling\n");
1891                writeb(1, csr + 3);
1892        }
1893
1894        iounmap(csr);
1895}
1896DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1897                        PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
1898
1899/*
1900 * The 82575 and 82598 may experience data corruption issues when transitioning
1901 * out of L0S.  To prevent this we need to disable L0S on the pci-e link
1902 */
1903static void quirk_disable_aspm_l0s(struct pci_dev *dev)
1904{
1905        dev_info(&dev->dev, "Disabling L0s\n");
1906        pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1907}
1908DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1909DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1910DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1911DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1912DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1913DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1914DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1915DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1916DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1917DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1918DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1919DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1920DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1921DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1922
1923static void fixup_rev1_53c810(struct pci_dev *dev)
1924{
1925        /* rev 1 ncr53c810 chips don't set the class at all which means
1926         * they don't get their resources remapped. Fix that here.
1927         */
1928
1929        if (dev->class == PCI_CLASS_NOT_DEFINED) {
1930                dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1931                dev->class = PCI_CLASS_STORAGE_SCSI;
1932        }
1933}
1934DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1935
1936/* Enable 1k I/O space granularity on the Intel P64H2 */
1937static void quirk_p64h2_1k_io(struct pci_dev *dev)
1938{
1939        u16 en1k;
1940
1941        pci_read_config_word(dev, 0x40, &en1k);
1942
1943        if (en1k & 0x200) {
1944                dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1945                dev->io_window_1k = 1;
1946        }
1947}
1948DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   0x1460,         quirk_p64h2_1k_io);
1949
1950/* Under some circumstances, AER is not linked with extended capabilities.
1951 * Force it to be linked by setting the corresponding control bit in the
1952 * config space.
1953 */
1954static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1955{
1956        uint8_t b;
1957        if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1958                if (!(b & 0x20)) {
1959                        pci_write_config_byte(dev, 0xf41, b | 0x20);
1960                        dev_info(&dev->dev,
1961                               "Linking AER extended capability\n");
1962                }
1963        }
1964}
1965DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1966                        quirk_nvidia_ck804_pcie_aer_ext_cap);
1967DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1968                        quirk_nvidia_ck804_pcie_aer_ext_cap);
1969
1970static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1971{
1972        /*
1973         * Disable PCI Bus Parking and PCI Master read caching on CX700
1974         * which causes unspecified timing errors with a VT6212L on the PCI
1975         * bus leading to USB2.0 packet loss.
1976         *
1977         * This quirk is only enabled if a second (on the external PCI bus)
1978         * VT6212L is found -- the CX700 core itself also contains a USB
1979         * host controller with the same PCI ID as the VT6212L.
1980         */
1981
1982        /* Count VT6212L instances */
1983        struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
1984                PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
1985        uint8_t b;
1986
1987        /* p should contain the first (internal) VT6212L -- see if we have
1988           an external one by searching again */
1989        p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
1990        if (!p)
1991                return;
1992        pci_dev_put(p);
1993
1994        if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1995                if (b & 0x40) {
1996                        /* Turn off PCI Bus Parking */
1997                        pci_write_config_byte(dev, 0x76, b ^ 0x40);
1998
1999                        dev_info(&dev->dev,
2000                                "Disabling VIA CX700 PCI parking\n");
2001                }
2002        }
2003
2004        if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2005                if (b != 0) {
2006                        /* Turn off PCI Master read caching */
2007                        pci_write_config_byte(dev, 0x72, 0x0);
2008
2009                        /* Set PCI Master Bus time-out to "1x16 PCLK" */
2010                        pci_write_config_byte(dev, 0x75, 0x1);
2011
2012                        /* Disable "Read FIFO Timer" */
2013                        pci_write_config_byte(dev, 0x77, 0x0);
2014
2015                        dev_info(&dev->dev,
2016                                "Disabling VIA CX700 PCI caching\n");
2017                }
2018        }
2019}
2020DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2021
2022/*
2023 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2024 * VPD end tag will hang the device.  This problem was initially
2025 * observed when a vpd entry was created in sysfs
2026 * ('/sys/bus/pci/devices/<id>/vpd').   A read to this sysfs entry
2027 * will dump 32k of data.  Reading a full 32k will cause an access
2028 * beyond the VPD end tag causing the device to hang.  Once the device
2029 * is hung, the bnx2 driver will not be able to reset the device.
2030 * We believe that it is legal to read beyond the end tag and
2031 * therefore the solution is to limit the read/write length.
2032 */
2033static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2034{
2035        /*
2036         * Only disable the VPD capability for 5706, 5706S, 5708,
2037         * 5708S and 5709 rev. A
2038         */
2039        if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2040            (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2041            (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2042            (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2043            ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2044             (dev->revision & 0xf0) == 0x0)) {
2045                if (dev->vpd)
2046                        dev->vpd->len = 0x80;
2047        }
2048}
2049
2050DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2051                        PCI_DEVICE_ID_NX2_5706,
2052                        quirk_brcm_570x_limit_vpd);
2053DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2054                        PCI_DEVICE_ID_NX2_5706S,
2055                        quirk_brcm_570x_limit_vpd);
2056DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2057                        PCI_DEVICE_ID_NX2_5708,
2058                        quirk_brcm_570x_limit_vpd);
2059DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2060                        PCI_DEVICE_ID_NX2_5708S,
2061                        quirk_brcm_570x_limit_vpd);
2062DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2063                        PCI_DEVICE_ID_NX2_5709,
2064                        quirk_brcm_570x_limit_vpd);
2065DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2066                        PCI_DEVICE_ID_NX2_5709S,
2067                        quirk_brcm_570x_limit_vpd);
2068
2069static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2070{
2071        u32 rev;
2072
2073        pci_read_config_dword(dev, 0xf4, &rev);
2074
2075        /* Only CAP the MRRS if the device is a 5719 A0 */
2076        if (rev == 0x05719000) {
2077                int readrq = pcie_get_readrq(dev);
2078                if (readrq > 2048)
2079                        pcie_set_readrq(dev, 2048);
2080        }
2081}
2082
2083DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2084                         PCI_DEVICE_ID_TIGON3_5719,
2085                         quirk_brcm_5719_limit_mrrs);
2086
2087/* Originally in EDAC sources for i82875P:
2088 * Intel tells BIOS developers to hide device 6 which
2089 * configures the overflow device access containing
2090 * the DRBs - this is where we expose device 6.
2091 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2092 */
2093static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2094{
2095        u8 reg;
2096
2097        if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2098                dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2099                pci_write_config_byte(dev, 0xF4, reg | 0x02);
2100        }
2101}
2102
2103DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2104                        quirk_unhide_mch_dev6);
2105DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2106                        quirk_unhide_mch_dev6);
2107
2108#ifdef CONFIG_TILEPRO
2109/*
2110 * The Tilera TILEmpower tilepro platform needs to set the link speed
2111 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2112 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2113 * capability register of the PEX8624 PCIe switch. The switch
2114 * supports link speed auto negotiation, but falsely sets
2115 * the link speed to 5GT/s.
2116 */
2117static void quirk_tile_plx_gen1(struct pci_dev *dev)
2118{
2119        if (tile_plx_gen1) {
2120                pci_write_config_dword(dev, 0x98, 0x1);
2121                mdelay(50);
2122        }
2123}
2124DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2125#endif /* CONFIG_TILEPRO */
2126
2127#ifdef CONFIG_PCI_MSI
2128/* Some chipsets do not support MSI. We cannot easily rely on setting
2129 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2130 * some other busses controlled by the chipset even if Linux is not
2131 * aware of it.  Instead of setting the flag on all busses in the
2132 * machine, simply disable MSI globally.
2133 */
2134static void quirk_disable_all_msi(struct pci_dev *dev)
2135{
2136        pci_no_msi();
2137        dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2138}
2139DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2140DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2141DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2142DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2143DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2144DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2145DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2146
2147/* Disable MSI on chipsets that are known to not support it */
2148static void quirk_disable_msi(struct pci_dev *dev)
2149{
2150        if (dev->subordinate) {
2151                dev_warn(&dev->dev, "MSI quirk detected; "
2152                        "subordinate MSI disabled\n");
2153                dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2154        }
2155}
2156DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2159
2160/*
2161 * The APC bridge device in AMD 780 family northbridges has some random
2162 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2163 * we use the possible vendor/device IDs of the host bridge for the
2164 * declared quirk, and search for the APC bridge by slot number.
2165 */
2166static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2167{
2168        struct pci_dev *apc_bridge;
2169
2170        apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2171        if (apc_bridge) {
2172                if (apc_bridge->device == 0x9602)
2173                        quirk_disable_msi(apc_bridge);
2174                pci_dev_put(apc_bridge);
2175        }
2176}
2177DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2178DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2179
2180/* Go through the list of Hypertransport capabilities and
2181 * return 1 if a HT MSI capability is found and enabled */
2182static int msi_ht_cap_enabled(struct pci_dev *dev)
2183{
2184        int pos, ttl = 48;
2185
2186        pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2187        while (pos && ttl--) {
2188                u8 flags;
2189
2190                if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2191                                         &flags) == 0)
2192                {
2193                        dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2194                                flags & HT_MSI_FLAGS_ENABLE ?
2195                                "enabled" : "disabled");
2196                        return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2197                }
2198
2199                pos = pci_find_next_ht_capability(dev, pos,
2200                                                  HT_CAPTYPE_MSI_MAPPING);
2201        }
2202        return 0;
2203}
2204
2205/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2206static void quirk_msi_ht_cap(struct pci_dev *dev)
2207{
2208        if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2209                dev_warn(&dev->dev, "MSI quirk detected; "
2210                        "subordinate MSI disabled\n");
2211                dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2212        }
2213}
2214DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2215                        quirk_msi_ht_cap);
2216
2217/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2218 * MSI are supported if the MSI capability set in any of these mappings.
2219 */
2220static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2221{
2222        struct pci_dev *pdev;
2223
2224        if (!dev->subordinate)
2225                return;
2226
2227        /* check HT MSI cap on this chipset and the root one.
2228         * a single one having MSI is enough to be sure that MSI are supported.
2229         */
2230        pdev = pci_get_slot(dev->bus, 0);
2231        if (!pdev)
2232                return;
2233        if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2234                dev_warn(&dev->dev, "MSI quirk detected; "
2235                        "subordinate MSI disabled\n");
2236                dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2237        }
2238        pci_dev_put(pdev);
2239}
2240DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2241                        quirk_nvidia_ck804_msi_ht_cap);
2242
2243/* Force enable MSI mapping capability on HT bridges */
2244static void ht_enable_msi_mapping(struct pci_dev *dev)
2245{
2246        int pos, ttl = 48;
2247
2248        pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2249        while (pos && ttl--) {
2250                u8 flags;
2251
2252                if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2253                                         &flags) == 0) {
2254                        dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2255
2256                        pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2257                                              flags | HT_MSI_FLAGS_ENABLE);
2258                }
2259                pos = pci_find_next_ht_capability(dev, pos,
2260                                                  HT_CAPTYPE_MSI_MAPPING);
2261        }
2262}
2263DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2264                         PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2265                         ht_enable_msi_mapping);
2266
2267DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2268                         ht_enable_msi_mapping);
2269
2270/* The P5N32-SLI motherboards from Asus have a problem with msi
2271 * for the MCP55 NIC. It is not yet determined whether the msi problem
2272 * also affects other devices. As for now, turn off msi for this device.
2273 */
2274static void nvenet_msi_disable(struct pci_dev *dev)
2275{
2276        const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2277
2278        if (board_name &&
2279            (strstr(board_name, "P5N32-SLI PREMIUM") ||
2280             strstr(board_name, "P5N32-E SLI"))) {
2281                dev_info(&dev->dev,
2282                         "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2283                dev->no_msi = 1;
2284        }
2285}
2286DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2287                        PCI_DEVICE_ID_NVIDIA_NVENET_15,
2288                        nvenet_msi_disable);
2289
2290/*
2291 * Some versions of the MCP55 bridge from nvidia have a legacy irq routing
2292 * config register.  This register controls the routing of legacy interrupts
2293 * from devices that route through the MCP55.  If this register is misprogramed
2294 * interrupts are only sent to the bsp, unlike conventional systems where the
2295 * irq is broadxast to all online cpus.  Not having this register set
2296 * properly prevents kdump from booting up properly, so lets make sure that
2297 * we have it set correctly.
2298 * Note this is an undocumented register.
2299 */
2300static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2301{
2302        u32 cfg;
2303
2304        if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2305                return;
2306
2307        pci_read_config_dword(dev, 0x74, &cfg);
2308
2309        if (cfg & ((1 << 2) | (1 << 15))) {
2310                printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2311                cfg &= ~((1 << 2) | (1 << 15));
2312                pci_write_config_dword(dev, 0x74, cfg);
2313        }
2314}
2315
2316DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2317                        PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2318                        nvbridge_check_legacy_irq_routing);
2319
2320DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2321                        PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2322                        nvbridge_check_legacy_irq_routing);
2323
2324static int ht_check_msi_mapping(struct pci_dev *dev)
2325{
2326        int pos, ttl = 48;
2327        int found = 0;
2328
2329        /* check if there is HT MSI cap or enabled on this device */
2330        pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2331        while (pos && ttl--) {
2332                u8 flags;
2333
2334                if (found < 1)
2335                        found = 1;
2336                if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2337                                         &flags) == 0) {
2338                        if (flags & HT_MSI_FLAGS_ENABLE) {
2339                                if (found < 2) {
2340                                        found = 2;
2341                                        break;
2342                                }
2343                        }
2344                }
2345                pos = pci_find_next_ht_capability(dev, pos,
2346                                                  HT_CAPTYPE_MSI_MAPPING);
2347        }
2348
2349        return found;
2350}
2351
2352static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2353{
2354        struct pci_dev *dev;
2355        int pos;
2356        int i, dev_no;
2357        int found = 0;
2358
2359        dev_no = host_bridge->devfn >> 3;
2360        for (i = dev_no + 1; i < 0x20; i++) {
2361                dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2362                if (!dev)
2363                        continue;
2364
2365                /* found next host bridge ?*/
2366                pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2367                if (pos != 0) {
2368                        pci_dev_put(dev);
2369                        break;
2370                }
2371
2372                if (ht_check_msi_mapping(dev)) {
2373                        found = 1;
2374                        pci_dev_put(dev);
2375                        break;
2376                }
2377                pci_dev_put(dev);
2378        }
2379
2380        return found;
2381}
2382
2383#define PCI_HT_CAP_SLAVE_CTRL0     4    /* link control */
2384#define PCI_HT_CAP_SLAVE_CTRL1     8    /* link control to */
2385
2386static int is_end_of_ht_chain(struct pci_dev *dev)
2387{
2388        int pos, ctrl_off;
2389        int end = 0;
2390        u16 flags, ctrl;
2391
2392        pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2393
2394        if (!pos)
2395                goto out;
2396
2397        pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2398
2399        ctrl_off = ((flags >> 10) & 1) ?
2400                        PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2401        pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2402
2403        if (ctrl & (1 << 6))
2404                end = 1;
2405
2406out:
2407        return end;
2408}
2409
2410static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2411{
2412        struct pci_dev *host_bridge;
2413        int pos;
2414        int i, dev_no;
2415        int found = 0;
2416
2417        dev_no = dev->devfn >> 3;
2418        for (i = dev_no; i >= 0; i--) {
2419                host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2420                if (!host_bridge)
2421                        continue;
2422
2423                pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2424                if (pos != 0) {
2425                        found = 1;
2426                        break;
2427                }
2428                pci_dev_put(host_bridge);
2429        }
2430
2431        if (!found)
2432                return;
2433
2434        /* don't enable end_device/host_bridge with leaf directly here */
2435        if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2436            host_bridge_with_leaf(host_bridge))
2437                goto out;
2438
2439        /* root did that ! */
2440        if (msi_ht_cap_enabled(host_bridge))
2441                goto out;
2442
2443        ht_enable_msi_mapping(dev);
2444
2445out:
2446        pci_dev_put(host_bridge);
2447}
2448
2449static void ht_disable_msi_mapping(struct pci_dev *dev)
2450{
2451        int pos, ttl = 48;
2452
2453        pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2454        while (pos && ttl--) {
2455                u8 flags;
2456
2457                if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2458                                         &flags) == 0) {
2459                        dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2460
2461                        pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2462                                              flags & ~HT_MSI_FLAGS_ENABLE);
2463                }
2464                pos = pci_find_next_ht_capability(dev, pos,
2465                                                  HT_CAPTYPE_MSI_MAPPING);
2466        }
2467}
2468
2469static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2470{
2471        struct pci_dev *host_bridge;
2472        int pos;
2473        int found;
2474
2475        if (!pci_msi_enabled())
2476                return;
2477
2478        /* check if there is HT MSI cap or enabled on this device */
2479        found = ht_check_msi_mapping(dev);
2480
2481        /* no HT MSI CAP */
2482        if (found == 0)
2483                return;
2484
2485        /*
2486         * HT MSI mapping should be disabled on devices that are below
2487         * a non-Hypertransport host bridge. Locate the host bridge...
2488         */
2489        host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2490        if (host_bridge == NULL) {
2491                dev_warn(&dev->dev,
2492                         "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2493                return;
2494        }
2495
2496        pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2497        if (pos != 0) {
2498                /* Host bridge is to HT */
2499                if (found == 1) {
2500                        /* it is not enabled, try to enable it */
2501                        if (all)
2502                                ht_enable_msi_mapping(dev);
2503                        else
2504                                nv_ht_enable_msi_mapping(dev);
2505                }
2506                goto out;
2507        }
2508
2509        /* HT MSI is not enabled */
2510        if (found == 1)
2511                goto out;
2512
2513        /* Host bridge is not to HT, disable HT MSI mapping on this device */
2514        ht_disable_msi_mapping(dev);
2515
2516out:
2517        pci_dev_put(host_bridge);
2518}
2519
2520static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2521{
2522        return __nv_msi_ht_cap_quirk(dev, 1);
2523}
2524
2525static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2526{
2527        return __nv_msi_ht_cap_quirk(dev, 0);
2528}
2529
2530DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2531DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2532
2533DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2534DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2535
2536static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2537{
2538        dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2539}
2540static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2541{
2542        struct pci_dev *p;
2543
2544        /* SB700 MSI issue will be fixed at HW level from revision A21,
2545         * we need check PCI REVISION ID of SMBus controller to get SB700
2546         * revision.
2547         */
2548        p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2549                           NULL);
2550        if (!p)
2551                return;
2552
2553        if ((p->revision < 0x3B) && (p->revision >= 0x30))
2554                dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2555        pci_dev_put(p);
2556}
2557static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2558{
2559        /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2560        if (dev->revision < 0x18) {
2561                dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2562                dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2563        }
2564}
2565DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2566                        PCI_DEVICE_ID_TIGON3_5780,
2567                        quirk_msi_intx_disable_bug);
2568DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2569                        PCI_DEVICE_ID_TIGON3_5780S,
2570                        quirk_msi_intx_disable_bug);
2571DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2572                        PCI_DEVICE_ID_TIGON3_5714,
2573                        quirk_msi_intx_disable_bug);
2574DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2575                        PCI_DEVICE_ID_TIGON3_5714S,
2576                        quirk_msi_intx_disable_bug);
2577DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2578                        PCI_DEVICE_ID_TIGON3_5715,
2579                        quirk_msi_intx_disable_bug);
2580DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2581                        PCI_DEVICE_ID_TIGON3_5715S,
2582                        quirk_msi_intx_disable_bug);
2583
2584DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2585                        quirk_msi_intx_disable_ati_bug);
2586DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2587                        quirk_msi_intx_disable_ati_bug);
2588DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2589                        quirk_msi_intx_disable_ati_bug);
2590DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2591                        quirk_msi_intx_disable_ati_bug);
2592DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2593                        quirk_msi_intx_disable_ati_bug);
2594
2595DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2596                        quirk_msi_intx_disable_bug);
2597DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2598                        quirk_msi_intx_disable_bug);
2599DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2600                        quirk_msi_intx_disable_bug);
2601
2602DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2603                        quirk_msi_intx_disable_bug);
2604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2605                        quirk_msi_intx_disable_bug);
2606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2607                        quirk_msi_intx_disable_bug);
2608DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2609                        quirk_msi_intx_disable_bug);
2610DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2611                        quirk_msi_intx_disable_bug);
2612DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2613                        quirk_msi_intx_disable_bug);
2614DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2615                        quirk_msi_intx_disable_qca_bug);
2616DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2617                        quirk_msi_intx_disable_qca_bug);
2618DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2619                        quirk_msi_intx_disable_qca_bug);
2620DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2621                        quirk_msi_intx_disable_qca_bug);
2622DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2623                        quirk_msi_intx_disable_qca_bug);
2624#endif /* CONFIG_PCI_MSI */
2625
2626/* Allow manual resource allocation for PCI hotplug bridges
2627 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2628 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2629 * kernel fails to allocate resources when hotplug device is 
2630 * inserted and PCI bus is rescanned.
2631 */
2632static void quirk_hotplug_bridge(struct pci_dev *dev)
2633{
2634        dev->is_hotplug_bridge = 1;
2635}
2636
2637DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2638
2639/*
2640 * This is a quirk for the Ricoh MMC controller found as a part of
2641 * some mulifunction chips.
2642
2643 * This is very similar and based on the ricoh_mmc driver written by
2644 * Philip Langdale. Thank you for these magic sequences.
2645 *
2646 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2647 * and one or both of cardbus or firewire.
2648 *
2649 * It happens that they implement SD and MMC
2650 * support as separate controllers (and PCI functions). The linux SDHCI
2651 * driver supports MMC cards but the chip detects MMC cards in hardware
2652 * and directs them to the MMC controller - so the SDHCI driver never sees
2653 * them.
2654 *
2655 * To get around this, we must disable the useless MMC controller.
2656 * At that point, the SDHCI controller will start seeing them
2657 * It seems to be the case that the relevant PCI registers to deactivate the
2658 * MMC controller live on PCI function 0, which might be the cardbus controller
2659 * or the firewire controller, depending on the particular chip in question
2660 *
2661 * This has to be done early, because as soon as we disable the MMC controller
2662 * other pci functions shift up one level, e.g. function #2 becomes function
2663 * #1, and this will confuse the pci core.
2664 */
2665
2666#ifdef CONFIG_MMC_RICOH_MMC
2667static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2668{
2669        /* disable via cardbus interface */
2670        u8 write_enable;
2671        u8 write_target;
2672        u8 disable;
2673
2674        /* disable must be done via function #0 */
2675        if (PCI_FUNC(dev->devfn))
2676                return;
2677
2678        pci_read_config_byte(dev, 0xB7, &disable);
2679        if (disable & 0x02)
2680                return;
2681
2682        pci_read_config_byte(dev, 0x8E, &write_enable);
2683        pci_write_config_byte(dev, 0x8E, 0xAA);
2684        pci_read_config_byte(dev, 0x8D, &write_target);
2685        pci_write_config_byte(dev, 0x8D, 0xB7);
2686        pci_write_config_byte(dev, 0xB7, disable | 0x02);
2687        pci_write_config_byte(dev, 0x8E, write_enable);
2688        pci_write_config_byte(dev, 0x8D, write_target);
2689
2690        dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2691        dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2692}
2693DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2694DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2695
2696static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2697{
2698        /* disable via firewire interface */
2699        u8 write_enable;
2700        u8 disable;
2701
2702        /* disable must be done via function #0 */
2703        if (PCI_FUNC(dev->devfn))
2704                return;
2705        /*
2706         * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2707         * certain types of SD/MMC cards. Lowering the SD base
2708         * clock frequency from 200Mhz to 50Mhz fixes this issue.
2709         *
2710         * 0x150 - SD2.0 mode enable for changing base clock
2711         *         frequency to 50Mhz
2712         * 0xe1  - Base clock frequency
2713         * 0x32  - 50Mhz new clock frequency
2714         * 0xf9  - Key register for 0x150
2715         * 0xfc  - key register for 0xe1
2716         */
2717        if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2718            dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2719                pci_write_config_byte(dev, 0xf9, 0xfc);
2720                pci_write_config_byte(dev, 0x150, 0x10);
2721                pci_write_config_byte(dev, 0xf9, 0x00);
2722                pci_write_config_byte(dev, 0xfc, 0x01);
2723                pci_write_config_byte(dev, 0xe1, 0x32);
2724                pci_write_config_byte(dev, 0xfc, 0x00);
2725
2726                dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2727        }
2728
2729        pci_read_config_byte(dev, 0xCB, &disable);
2730
2731        if (disable & 0x02)
2732                return;
2733
2734        pci_read_config_byte(dev, 0xCA, &write_enable);
2735        pci_write_config_byte(dev, 0xCA, 0x57);
2736        pci_write_config_byte(dev, 0xCB, disable | 0x02);
2737        pci_write_config_byte(dev, 0xCA, write_enable);
2738
2739        dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2740        dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2741
2742}
2743DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2744DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2745DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2746DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2747DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2748DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2749#endif /*CONFIG_MMC_RICOH_MMC*/
2750
2751#ifdef CONFIG_DMAR_TABLE
2752#define VTUNCERRMSK_REG 0x1ac
2753#define VTD_MSK_SPEC_ERRORS     (1 << 31)
2754/*
2755 * This is a quirk for masking vt-d spec defined errors to platform error
2756 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2757 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2758 * on the RAS config settings of the platform) when a vt-d fault happens.
2759 * The resulting SMI caused the system to hang.
2760 *
2761 * VT-d spec related errors are already handled by the VT-d OS code, so no
2762 * need to report the same error through other channels.
2763 */
2764static void vtd_mask_spec_errors(struct pci_dev *dev)
2765{
2766        u32 word;
2767
2768        pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2769        pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2770}
2771DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2772DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2773#endif
2774
2775static void fixup_ti816x_class(struct pci_dev *dev)
2776{
2777        /* TI 816x devices do not have class code set when in PCIe boot mode */
2778        dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
2779        dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
2780}
2781DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2782                                 PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class);
2783
2784/* Some PCIe devices do not work reliably with the claimed maximum
2785 * payload size supported.
2786 */
2787static void fixup_mpss_256(struct pci_dev *dev)
2788{
2789        dev->pcie_mpss = 1; /* 256 bytes */
2790}
2791DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2792                         PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2793DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2794                         PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2795DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2796                         PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2797
2798/* Intel 5000 and 5100 Memory controllers have an errata with read completion
2799 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2800 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2801 * until all of the devices are discovered and buses walked, read completion
2802 * coalescing must be disabled.  Unfortunately, it cannot be re-enabled because
2803 * it is possible to hotplug a device with MPS of 256B.
2804 */
2805static void quirk_intel_mc_errata(struct pci_dev *dev)
2806{
2807        int err;
2808        u16 rcc;
2809
2810        if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
2811                return;
2812
2813        /* Intel errata specifies bits to change but does not say what they are.
2814         * Keeping them magical until such time as the registers and values can
2815         * be explained.
2816         */
2817        err = pci_read_config_word(dev, 0x48, &rcc);
2818        if (err) {
2819                dev_err(&dev->dev, "Error attempting to read the read "
2820                        "completion coalescing register.\n");
2821                return;
2822        }
2823
2824        if (!(rcc & (1 << 10)))
2825                return;
2826
2827        rcc &= ~(1 << 10);
2828
2829        err = pci_write_config_word(dev, 0x48, rcc);
2830        if (err) {
2831                dev_err(&dev->dev, "Error attempting to write the read "
2832                        "completion coalescing register.\n");
2833                return;
2834        }
2835
2836        pr_info_once("Read completion coalescing disabled due to hardware "
2837                     "errata relating to 256B MPS.\n");
2838}
2839/* Intel 5000 series memory controllers and ports 2-7 */
2840DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2841DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2842DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2843DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2844DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2845DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2846DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2847DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2848DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2849DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2850DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2851DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2852DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2853DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2854/* Intel 5100 series memory controllers and ports 2-7 */
2855DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2856DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2857DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2858DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2859DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2860DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2861DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2862DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2863DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2864DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2865DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2866
2867
2868static ktime_t fixup_debug_start(struct pci_dev *dev,
2869                                 void (*fn)(struct pci_dev *dev))
2870{
2871        ktime_t calltime = ktime_set(0, 0);
2872
2873        dev_dbg(&dev->dev, "calling %pF\n", fn);
2874        if (initcall_debug) {
2875                pr_debug("calling  %pF @ %i for %s\n",
2876                         fn, task_pid_nr(current), dev_name(&dev->dev));
2877                calltime = ktime_get();
2878        }
2879
2880        return calltime;
2881}
2882
2883static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
2884                               void (*fn)(struct pci_dev *dev))
2885{
2886        ktime_t delta, rettime;
2887        unsigned long long duration;
2888
2889        if (initcall_debug) {
2890                rettime = ktime_get();
2891                delta = ktime_sub(rettime, calltime);
2892                duration = (unsigned long long) ktime_to_ns(delta) >> 10;
2893                pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
2894                         fn, duration, dev_name(&dev->dev));
2895        }
2896}
2897
2898/*
2899 * Some BIOS implementations leave the Intel GPU interrupts enabled,
2900 * even though no one is handling them (f.e. i915 driver is never loaded).
2901 * Additionally the interrupt destination is not set up properly
2902 * and the interrupt ends up -somewhere-.
2903 *
2904 * These spurious interrupts are "sticky" and the kernel disables
2905 * the (shared) interrupt line after 100.000+ generated interrupts.
2906 *
2907 * Fix it by disabling the still enabled interrupts.
2908 * This resolves crashes often seen on monitor unplug.
2909 */
2910#define I915_DEIER_REG 0x4400c
2911static void disable_igfx_irq(struct pci_dev *dev)
2912{
2913        void __iomem *regs = pci_iomap(dev, 0, 0);
2914        if (regs == NULL) {
2915                dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
2916                return;
2917        }
2918
2919        /* Check if any interrupt line is still enabled */
2920        if (readl(regs + I915_DEIER_REG) != 0) {
2921                dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; "
2922                        "disabling\n");
2923
2924                writel(0, regs + I915_DEIER_REG);
2925        }
2926
2927        pci_iounmap(dev, regs);
2928}
2929DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
2930DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
2931
2932/*
2933 * Some devices may pass our check in pci_intx_mask_supported if
2934 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
2935 * support this feature.
2936 */
2937static void quirk_broken_intx_masking(struct pci_dev *dev)
2938{
2939        dev->broken_intx_masking = 1;
2940}
2941DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030,
2942                         quirk_broken_intx_masking);
2943DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
2944                         quirk_broken_intx_masking);
2945
2946static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2947                          struct pci_fixup *end)
2948{
2949        ktime_t calltime;
2950
2951        for (; f < end; f++)
2952                if ((f->class == (u32) (dev->class >> f->class_shift) ||
2953                     f->class == (u32) PCI_ANY_ID) &&
2954                    (f->vendor == dev->vendor ||
2955                     f->vendor == (u16) PCI_ANY_ID) &&
2956                    (f->device == dev->device ||
2957                     f->device == (u16) PCI_ANY_ID)) {
2958                        calltime = fixup_debug_start(dev, f->hook);
2959                        f->hook(dev);
2960                        fixup_debug_report(dev, calltime, f->hook);
2961                }
2962}
2963
2964extern struct pci_fixup __start_pci_fixups_early[];
2965extern struct pci_fixup __end_pci_fixups_early[];
2966extern struct pci_fixup __start_pci_fixups_header[];
2967extern struct pci_fixup __end_pci_fixups_header[];
2968extern struct pci_fixup __start_pci_fixups_final[];
2969extern struct pci_fixup __end_pci_fixups_final[];
2970extern struct pci_fixup __start_pci_fixups_enable[];
2971extern struct pci_fixup __end_pci_fixups_enable[];
2972extern struct pci_fixup __start_pci_fixups_resume[];
2973extern struct pci_fixup __end_pci_fixups_resume[];
2974extern struct pci_fixup __start_pci_fixups_resume_early[];
2975extern struct pci_fixup __end_pci_fixups_resume_early[];
2976extern struct pci_fixup __start_pci_fixups_suspend[];
2977extern struct pci_fixup __end_pci_fixups_suspend[];
2978
2979static bool pci_apply_fixup_final_quirks;
2980
2981void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2982{
2983        struct pci_fixup *start, *end;
2984
2985        switch(pass) {
2986        case pci_fixup_early:
2987                start = __start_pci_fixups_early;
2988                end = __end_pci_fixups_early;
2989                break;
2990
2991        case pci_fixup_header:
2992                start = __start_pci_fixups_header;
2993                end = __end_pci_fixups_header;
2994                break;
2995
2996        case pci_fixup_final:
2997                if (!pci_apply_fixup_final_quirks)
2998                        return;
2999                start = __start_pci_fixups_final;
3000                end = __end_pci_fixups_final;
3001                break;
3002
3003        case pci_fixup_enable:
3004                start = __start_pci_fixups_enable;
3005                end = __end_pci_fixups_enable;
3006                break;
3007
3008        case pci_fixup_resume:
3009                start = __start_pci_fixups_resume;
3010                end = __end_pci_fixups_resume;
3011                break;
3012
3013        case pci_fixup_resume_early:
3014                start = __start_pci_fixups_resume_early;
3015                end = __end_pci_fixups_resume_early;
3016                break;
3017
3018        case pci_fixup_suspend:
3019                start = __start_pci_fixups_suspend;
3020                end = __end_pci_fixups_suspend;
3021                break;
3022
3023        default:
3024                /* stupid compiler warning, you would think with an enum... */
3025                return;
3026        }
3027        pci_do_fixups(dev, start, end);
3028}
3029EXPORT_SYMBOL(pci_fixup_device);
3030
3031
3032static int __init pci_apply_final_quirks(void)
3033{
3034        struct pci_dev *dev = NULL;
3035        u8 cls = 0;
3036        u8 tmp;
3037
3038        if (pci_cache_line_size)
3039                printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3040                       pci_cache_line_size << 2);
3041
3042        pci_apply_fixup_final_quirks = true;
3043        for_each_pci_dev(dev) {
3044                pci_fixup_device(pci_fixup_final, dev);
3045                /*
3046                 * If arch hasn't set it explicitly yet, use the CLS
3047                 * value shared by all PCI devices.  If there's a
3048                 * mismatch, fall back to the default value.
3049                 */
3050                if (!pci_cache_line_size) {
3051                        pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3052                        if (!cls)
3053                                cls = tmp;
3054                        if (!tmp || cls == tmp)
3055                                continue;
3056
3057                        printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
3058                               "using %u bytes\n", cls << 2, tmp << 2,
3059                               pci_dfl_cache_line_size << 2);
3060                        pci_cache_line_size = pci_dfl_cache_line_size;
3061                }
3062        }
3063
3064        if (!pci_cache_line_size) {
3065                printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3066                       cls << 2, pci_dfl_cache_line_size << 2);
3067                pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3068        }
3069
3070        return 0;
3071}
3072
3073fs_initcall_sync(pci_apply_final_quirks);
3074
3075/*
3076 * Followings are device-specific reset methods which can be used to
3077 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3078 * not available.
3079 */
3080static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
3081{
3082        int pos;
3083
3084        /* only implement PCI_CLASS_SERIAL_USB at present */
3085        if (dev->class == PCI_CLASS_SERIAL_USB) {
3086                pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
3087                if (!pos)
3088                        return -ENOTTY;
3089
3090                if (probe)
3091                        return 0;
3092
3093                pci_write_config_byte(dev, pos + 0x4, 1);
3094                msleep(100);
3095
3096                return 0;
3097        } else {
3098                return -ENOTTY;
3099        }
3100}
3101
3102static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3103{
3104        int i;
3105        u16 status;
3106
3107        /*
3108         * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3109         *
3110         * The 82599 supports FLR on VFs, but FLR support is reported only
3111         * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3112         * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3113         */
3114
3115        if (probe)
3116                return 0;
3117
3118        /* Wait for Transaction Pending bit clean */
3119        for (i = 0; i < 4; i++) {
3120                if (i)
3121                        msleep((1 << (i - 1)) * 100);
3122
3123                pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
3124                if (!(status & PCI_EXP_DEVSTA_TRPND))
3125                        goto clear;
3126        }
3127
3128        dev_err(&dev->dev, "transaction is not cleared; "
3129                        "proceeding with reset anyway\n");
3130
3131clear:
3132        pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3133
3134        msleep(100);
3135
3136        return 0;
3137}
3138
3139#include "../gpu/drm/i915/i915_reg.h"
3140#define MSG_CTL                 0x45010
3141#define NSDE_PWR_STATE          0xd0100
3142#define IGD_OPERATION_TIMEOUT   10000     /* set timeout 10 seconds */
3143
3144static int reset_ivb_igd(struct pci_dev *dev, int probe)
3145{
3146        void __iomem *mmio_base;
3147        unsigned long timeout;
3148        u32 val;
3149
3150        if (probe)
3151                return 0;
3152
3153        mmio_base = pci_iomap(dev, 0, 0);
3154        if (!mmio_base)
3155                return -ENOMEM;
3156
3157        iowrite32(0x00000002, mmio_base + MSG_CTL);
3158
3159        /*
3160         * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3161         * driver loaded sets the right bits. However, this's a reset and
3162         * the bits have been set by i915 previously, so we clobber
3163         * SOUTH_CHICKEN2 register directly here.
3164         */
3165        iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3166
3167        val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3168        iowrite32(val, mmio_base + PCH_PP_CONTROL);
3169
3170        timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3171        do {
3172                val = ioread32(mmio_base + PCH_PP_STATUS);
3173                if ((val & 0xb0000000) == 0)
3174                        goto reset_complete;
3175                msleep(10);
3176        } while (time_before(jiffies, timeout));
3177        dev_warn(&dev->dev, "timeout during reset\n");
3178
3179reset_complete:
3180        iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3181
3182        pci_iounmap(dev, mmio_base);
3183        return 0;
3184}
3185
3186#define PCI_DEVICE_ID_INTEL_82599_SFP_VF   0x10ed
3187#define PCI_DEVICE_ID_INTEL_IVB_M_VGA      0x0156
3188#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA     0x0166
3189
3190static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3191        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3192                 reset_intel_82599_sfp_virtfn },
3193        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3194                reset_ivb_igd },
3195        { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3196                reset_ivb_igd },
3197        { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
3198                reset_intel_generic_dev },
3199        { 0 }
3200};
3201
3202/*
3203 * These device-specific reset methods are here rather than in a driver
3204 * because when a host assigns a device to a guest VM, the host may need
3205 * to reset the device but probably doesn't have a driver for it.
3206 */
3207int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3208{
3209        const struct pci_dev_reset_methods *i;
3210
3211        for (i = pci_dev_reset_methods; i->reset; i++) {
3212                if ((i->vendor == dev->vendor ||
3213                     i->vendor == (u16)PCI_ANY_ID) &&
3214                    (i->device == dev->device ||
3215                     i->device == (u16)PCI_ANY_ID))
3216                        return i->reset(dev, probe);
3217        }
3218
3219        return -ENOTTY;
3220}
3221
3222static struct pci_dev *pci_func_0_dma_source(struct pci_dev *dev)
3223{
3224        if (!PCI_FUNC(dev->devfn))
3225                return pci_dev_get(dev);
3226
3227        return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3228}
3229
3230static const struct pci_dev_dma_source {
3231        u16 vendor;
3232        u16 device;
3233        struct pci_dev *(*dma_source)(struct pci_dev *dev);
3234} pci_dev_dma_source[] = {
3235        /*
3236         * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3237         *
3238         * Some Ricoh devices use the function 0 source ID for DMA on
3239         * other functions of a multifunction device.  The DMA devices
3240         * is therefore function 0, which will have implications of the
3241         * iommu grouping of these devices.
3242         */
3243        { PCI_VENDOR_ID_RICOH, 0xe822, pci_func_0_dma_source },
3244        { PCI_VENDOR_ID_RICOH, 0xe230, pci_func_0_dma_source },
3245        { PCI_VENDOR_ID_RICOH, 0xe832, pci_func_0_dma_source },
3246        { PCI_VENDOR_ID_RICOH, 0xe476, pci_func_0_dma_source },
3247        { 0 }
3248};
3249
3250/*
3251 * IOMMUs with isolation capabilities need to be programmed with the
3252 * correct source ID of a device.  In most cases, the source ID matches
3253 * the device doing the DMA, but sometimes hardware is broken and will
3254 * tag the DMA as being sourced from a different device.  This function
3255 * allows that translation.  Note that the reference count of the
3256 * returned device is incremented on all paths.
3257 */
3258struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
3259{
3260        const struct pci_dev_dma_source *i;
3261
3262        for (i = pci_dev_dma_source; i->dma_source; i++) {
3263                if ((i->vendor == dev->vendor ||
3264                     i->vendor == (u16)PCI_ANY_ID) &&
3265                    (i->device == dev->device ||
3266                     i->device == (u16)PCI_ANY_ID))
3267                        return i->dma_source(dev);
3268        }
3269
3270        return pci_dev_get(dev);
3271}
3272
3273static const struct pci_dev_acs_enabled {
3274        u16 vendor;
3275        u16 device;
3276        int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
3277} pci_dev_acs_enabled[] = {
3278        { 0 }
3279};
3280
3281int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
3282{
3283        const struct pci_dev_acs_enabled *i;
3284        int ret;
3285
3286        /*
3287         * Allow devices that do not expose standard PCIe ACS capabilities
3288         * or control to indicate their support here.  Multi-function express
3289         * devices which do not allow internal peer-to-peer between functions,
3290         * but do not implement PCIe ACS may wish to return true here.
3291         */
3292        for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
3293                if ((i->vendor == dev->vendor ||
3294                     i->vendor == (u16)PCI_ANY_ID) &&
3295                    (i->device == dev->device ||
3296                     i->device == (u16)PCI_ANY_ID)) {
3297                        ret = i->acs_enabled(dev, acs_flags);
3298                        if (ret >= 0)
3299                                return ret;
3300                }
3301        }
3302
3303        return -ENOTTY;
3304}
3305
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