linux/drivers/pci/msi.c
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   1/*
   2 * File:        msi.c
   3 * Purpose:     PCI Message Signaled Interrupt (MSI)
   4 *
   5 * Copyright (C) 2003-2004 Intel
   6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
   7 */
   8
   9#include <linux/err.h>
  10#include <linux/mm.h>
  11#include <linux/irq.h>
  12#include <linux/interrupt.h>
  13#include <linux/init.h>
  14#include <linux/export.h>
  15#include <linux/ioport.h>
  16#include <linux/pci.h>
  17#include <linux/proc_fs.h>
  18#include <linux/msi.h>
  19#include <linux/smp.h>
  20#include <linux/errno.h>
  21#include <linux/io.h>
  22#include <linux/slab.h>
  23
  24#include "pci.h"
  25
  26static int pci_msi_enable = 1;
  27
  28#define msix_table_size(flags)  ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
  29
  30
  31/* Arch hooks */
  32
  33#ifndef arch_msi_check_device
  34int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
  35{
  36        return 0;
  37}
  38#endif
  39
  40#ifndef arch_setup_msi_irqs
  41# define arch_setup_msi_irqs default_setup_msi_irqs
  42# define HAVE_DEFAULT_MSI_SETUP_IRQS
  43#endif
  44
  45#ifdef HAVE_DEFAULT_MSI_SETUP_IRQS
  46int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
  47{
  48        struct msi_desc *entry;
  49        int ret;
  50
  51        /*
  52         * If an architecture wants to support multiple MSI, it needs to
  53         * override arch_setup_msi_irqs()
  54         */
  55        if (type == PCI_CAP_ID_MSI && nvec > 1)
  56                return 1;
  57
  58        list_for_each_entry(entry, &dev->msi_list, list) {
  59                ret = arch_setup_msi_irq(dev, entry);
  60                if (ret < 0)
  61                        return ret;
  62                if (ret > 0)
  63                        return -ENOSPC;
  64        }
  65
  66        return 0;
  67}
  68#endif
  69
  70#ifndef arch_teardown_msi_irqs
  71# define arch_teardown_msi_irqs default_teardown_msi_irqs
  72# define HAVE_DEFAULT_MSI_TEARDOWN_IRQS
  73#endif
  74
  75#ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS
  76void default_teardown_msi_irqs(struct pci_dev *dev)
  77{
  78        struct msi_desc *entry;
  79
  80        list_for_each_entry(entry, &dev->msi_list, list) {
  81                int i, nvec;
  82                if (entry->irq == 0)
  83                        continue;
  84                nvec = 1 << entry->msi_attrib.multiple;
  85                for (i = 0; i < nvec; i++)
  86                        arch_teardown_msi_irq(entry->irq + i);
  87        }
  88}
  89#endif
  90
  91#ifndef arch_restore_msi_irqs
  92# define arch_restore_msi_irqs default_restore_msi_irqs
  93# define HAVE_DEFAULT_MSI_RESTORE_IRQS
  94#endif
  95
  96#ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS
  97void default_restore_msi_irqs(struct pci_dev *dev, int irq)
  98{
  99        struct msi_desc *entry;
 100
 101        entry = NULL;
 102        if (dev->msix_enabled) {
 103                list_for_each_entry(entry, &dev->msi_list, list) {
 104                        if (irq == entry->irq)
 105                                break;
 106                }
 107        } else if (dev->msi_enabled)  {
 108                entry = irq_get_msi_desc(irq);
 109        }
 110
 111        if (entry)
 112                write_msi_msg(irq, &entry->msg);
 113}
 114#endif
 115
 116static void msi_set_enable(struct pci_dev *dev, int enable)
 117{
 118        u16 control;
 119
 120        pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
 121        control &= ~PCI_MSI_FLAGS_ENABLE;
 122        if (enable)
 123                control |= PCI_MSI_FLAGS_ENABLE;
 124        pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
 125}
 126
 127static void msix_set_enable(struct pci_dev *dev, int enable)
 128{
 129        u16 control;
 130
 131        pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
 132        control &= ~PCI_MSIX_FLAGS_ENABLE;
 133        if (enable)
 134                control |= PCI_MSIX_FLAGS_ENABLE;
 135        pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
 136}
 137
 138static inline __attribute_const__ u32 msi_mask(unsigned x)
 139{
 140        /* Don't shift by >= width of type */
 141        if (x >= 5)
 142                return 0xffffffff;
 143        return (1 << (1 << x)) - 1;
 144}
 145
 146static inline __attribute_const__ u32 msi_capable_mask(u16 control)
 147{
 148        return msi_mask((control >> 1) & 7);
 149}
 150
 151static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
 152{
 153        return msi_mask((control >> 4) & 7);
 154}
 155
 156/*
 157 * PCI 2.3 does not specify mask bits for each MSI interrupt.  Attempting to
 158 * mask all MSI interrupts by clearing the MSI enable bit does not work
 159 * reliably as devices without an INTx disable bit will then generate a
 160 * level IRQ which will never be cleared.
 161 */
 162static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
 163{
 164        u32 mask_bits = desc->masked;
 165
 166        if (!desc->msi_attrib.maskbit)
 167                return 0;
 168
 169        mask_bits &= ~mask;
 170        mask_bits |= flag;
 171        pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
 172
 173        return mask_bits;
 174}
 175
 176static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
 177{
 178        desc->masked = __msi_mask_irq(desc, mask, flag);
 179}
 180
 181/*
 182 * This internal function does not flush PCI writes to the device.
 183 * All users must ensure that they read from the device before either
 184 * assuming that the device state is up to date, or returning out of this
 185 * file.  This saves a few milliseconds when initialising devices with lots
 186 * of MSI-X interrupts.
 187 */
 188static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
 189{
 190        u32 mask_bits = desc->masked;
 191        unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
 192                                                PCI_MSIX_ENTRY_VECTOR_CTRL;
 193        mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
 194        if (flag)
 195                mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
 196        writel(mask_bits, desc->mask_base + offset);
 197
 198        return mask_bits;
 199}
 200
 201static void msix_mask_irq(struct msi_desc *desc, u32 flag)
 202{
 203        desc->masked = __msix_mask_irq(desc, flag);
 204}
 205
 206#ifdef CONFIG_GENERIC_HARDIRQS
 207
 208static void msi_set_mask_bit(struct irq_data *data, u32 flag)
 209{
 210        struct msi_desc *desc = irq_data_get_msi(data);
 211
 212        if (desc->msi_attrib.is_msix) {
 213                msix_mask_irq(desc, flag);
 214                readl(desc->mask_base);         /* Flush write to device */
 215        } else {
 216                unsigned offset = data->irq - desc->dev->irq;
 217                msi_mask_irq(desc, 1 << offset, flag << offset);
 218        }
 219}
 220
 221void mask_msi_irq(struct irq_data *data)
 222{
 223        msi_set_mask_bit(data, 1);
 224}
 225
 226void unmask_msi_irq(struct irq_data *data)
 227{
 228        msi_set_mask_bit(data, 0);
 229}
 230
 231#endif /* CONFIG_GENERIC_HARDIRQS */
 232
 233void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
 234{
 235        BUG_ON(entry->dev->current_state != PCI_D0);
 236
 237        if (entry->msi_attrib.is_msix) {
 238                void __iomem *base = entry->mask_base +
 239                        entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 240
 241                msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
 242                msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
 243                msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
 244        } else {
 245                struct pci_dev *dev = entry->dev;
 246                int pos = dev->msi_cap;
 247                u16 data;
 248
 249                pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
 250                                      &msg->address_lo);
 251                if (entry->msi_attrib.is_64) {
 252                        pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
 253                                              &msg->address_hi);
 254                        pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
 255                } else {
 256                        msg->address_hi = 0;
 257                        pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
 258                }
 259                msg->data = data;
 260        }
 261}
 262
 263void read_msi_msg(unsigned int irq, struct msi_msg *msg)
 264{
 265        struct msi_desc *entry = irq_get_msi_desc(irq);
 266
 267        __read_msi_msg(entry, msg);
 268}
 269
 270void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
 271{
 272        /* Assert that the cache is valid, assuming that
 273         * valid messages are not all-zeroes. */
 274        BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
 275                 entry->msg.data));
 276
 277        *msg = entry->msg;
 278}
 279
 280void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
 281{
 282        struct msi_desc *entry = irq_get_msi_desc(irq);
 283
 284        __get_cached_msi_msg(entry, msg);
 285}
 286
 287void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
 288{
 289        if (entry->dev->current_state != PCI_D0) {
 290                /* Don't touch the hardware now */
 291        } else if (entry->msi_attrib.is_msix) {
 292                void __iomem *base;
 293                base = entry->mask_base +
 294                        entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 295
 296                writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
 297                writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
 298                writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
 299        } else {
 300                struct pci_dev *dev = entry->dev;
 301                int pos = dev->msi_cap;
 302                u16 msgctl;
 303
 304                pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
 305                msgctl &= ~PCI_MSI_FLAGS_QSIZE;
 306                msgctl |= entry->msi_attrib.multiple << 4;
 307                pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
 308
 309                pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
 310                                       msg->address_lo);
 311                if (entry->msi_attrib.is_64) {
 312                        pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
 313                                               msg->address_hi);
 314                        pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
 315                                              msg->data);
 316                } else {
 317                        pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
 318                                              msg->data);
 319                }
 320        }
 321        entry->msg = *msg;
 322}
 323
 324void write_msi_msg(unsigned int irq, struct msi_msg *msg)
 325{
 326        struct msi_desc *entry = irq_get_msi_desc(irq);
 327
 328        __write_msi_msg(entry, msg);
 329}
 330
 331static void free_msi_irqs(struct pci_dev *dev)
 332{
 333        struct msi_desc *entry, *tmp;
 334
 335        list_for_each_entry(entry, &dev->msi_list, list) {
 336                int i, nvec;
 337                if (!entry->irq)
 338                        continue;
 339                nvec = 1 << entry->msi_attrib.multiple;
 340#ifdef CONFIG_GENERIC_HARDIRQS
 341                for (i = 0; i < nvec; i++)
 342                        BUG_ON(irq_has_action(entry->irq + i));
 343#endif
 344        }
 345
 346        arch_teardown_msi_irqs(dev);
 347
 348        list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
 349                if (entry->msi_attrib.is_msix) {
 350                        if (list_is_last(&entry->list, &dev->msi_list))
 351                                iounmap(entry->mask_base);
 352                }
 353
 354                /*
 355                 * Its possible that we get into this path
 356                 * When populate_msi_sysfs fails, which means the entries
 357                 * were not registered with sysfs.  In that case don't
 358                 * unregister them.
 359                 */
 360                if (entry->kobj.parent) {
 361                        kobject_del(&entry->kobj);
 362                        kobject_put(&entry->kobj);
 363                }
 364
 365                list_del(&entry->list);
 366                kfree(entry);
 367        }
 368}
 369
 370static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
 371{
 372        struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
 373        if (!desc)
 374                return NULL;
 375
 376        INIT_LIST_HEAD(&desc->list);
 377        desc->dev = dev;
 378
 379        return desc;
 380}
 381
 382static void pci_intx_for_msi(struct pci_dev *dev, int enable)
 383{
 384        if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
 385                pci_intx(dev, enable);
 386}
 387
 388static void __pci_restore_msi_state(struct pci_dev *dev)
 389{
 390        u16 control;
 391        struct msi_desc *entry;
 392
 393        if (!dev->msi_enabled)
 394                return;
 395
 396        entry = irq_get_msi_desc(dev->irq);
 397
 398        pci_intx_for_msi(dev, 0);
 399        msi_set_enable(dev, 0);
 400        arch_restore_msi_irqs(dev, dev->irq);
 401
 402        pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
 403        msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
 404        control &= ~PCI_MSI_FLAGS_QSIZE;
 405        control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
 406        pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
 407}
 408
 409static void __pci_restore_msix_state(struct pci_dev *dev)
 410{
 411        struct msi_desc *entry;
 412        u16 control;
 413
 414        if (!dev->msix_enabled)
 415                return;
 416        BUG_ON(list_empty(&dev->msi_list));
 417        entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
 418        pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
 419
 420        /* route the table */
 421        pci_intx_for_msi(dev, 0);
 422        control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL;
 423        pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
 424
 425        list_for_each_entry(entry, &dev->msi_list, list) {
 426                arch_restore_msi_irqs(dev, entry->irq);
 427                msix_mask_irq(entry, entry->masked);
 428        }
 429
 430        control &= ~PCI_MSIX_FLAGS_MASKALL;
 431        pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
 432}
 433
 434void pci_restore_msi_state(struct pci_dev *dev)
 435{
 436        __pci_restore_msi_state(dev);
 437        __pci_restore_msix_state(dev);
 438}
 439EXPORT_SYMBOL_GPL(pci_restore_msi_state);
 440
 441
 442#define to_msi_attr(obj) container_of(obj, struct msi_attribute, attr)
 443#define to_msi_desc(obj) container_of(obj, struct msi_desc, kobj)
 444
 445struct msi_attribute {
 446        struct attribute        attr;
 447        ssize_t (*show)(struct msi_desc *entry, struct msi_attribute *attr,
 448                        char *buf);
 449        ssize_t (*store)(struct msi_desc *entry, struct msi_attribute *attr,
 450                         const char *buf, size_t count);
 451};
 452
 453static ssize_t show_msi_mode(struct msi_desc *entry, struct msi_attribute *atr,
 454                             char *buf)
 455{
 456        return sprintf(buf, "%s\n", entry->msi_attrib.is_msix ? "msix" : "msi");
 457}
 458
 459static ssize_t msi_irq_attr_show(struct kobject *kobj,
 460                                 struct attribute *attr, char *buf)
 461{
 462        struct msi_attribute *attribute = to_msi_attr(attr);
 463        struct msi_desc *entry = to_msi_desc(kobj);
 464
 465        if (!attribute->show)
 466                return -EIO;
 467
 468        return attribute->show(entry, attribute, buf);
 469}
 470
 471static const struct sysfs_ops msi_irq_sysfs_ops = {
 472        .show = msi_irq_attr_show,
 473};
 474
 475static struct msi_attribute mode_attribute =
 476        __ATTR(mode, S_IRUGO, show_msi_mode, NULL);
 477
 478
 479static struct attribute *msi_irq_default_attrs[] = {
 480        &mode_attribute.attr,
 481        NULL
 482};
 483
 484static void msi_kobj_release(struct kobject *kobj)
 485{
 486        struct msi_desc *entry = to_msi_desc(kobj);
 487
 488        pci_dev_put(entry->dev);
 489}
 490
 491static struct kobj_type msi_irq_ktype = {
 492        .release = msi_kobj_release,
 493        .sysfs_ops = &msi_irq_sysfs_ops,
 494        .default_attrs = msi_irq_default_attrs,
 495};
 496
 497static int populate_msi_sysfs(struct pci_dev *pdev)
 498{
 499        struct msi_desc *entry;
 500        struct kobject *kobj;
 501        int ret;
 502        int count = 0;
 503
 504        pdev->msi_kset = kset_create_and_add("msi_irqs", NULL, &pdev->dev.kobj);
 505        if (!pdev->msi_kset)
 506                return -ENOMEM;
 507
 508        list_for_each_entry(entry, &pdev->msi_list, list) {
 509                kobj = &entry->kobj;
 510                kobj->kset = pdev->msi_kset;
 511                pci_dev_get(pdev);
 512                ret = kobject_init_and_add(kobj, &msi_irq_ktype, NULL,
 513                                     "%u", entry->irq);
 514                if (ret)
 515                        goto out_unroll;
 516
 517                count++;
 518        }
 519
 520        return 0;
 521
 522out_unroll:
 523        list_for_each_entry(entry, &pdev->msi_list, list) {
 524                if (!count)
 525                        break;
 526                kobject_del(&entry->kobj);
 527                kobject_put(&entry->kobj);
 528                count--;
 529        }
 530        return ret;
 531}
 532
 533/**
 534 * msi_capability_init - configure device's MSI capability structure
 535 * @dev: pointer to the pci_dev data structure of MSI device function
 536 * @nvec: number of interrupts to allocate
 537 *
 538 * Setup the MSI capability structure of the device with the requested
 539 * number of interrupts.  A return value of zero indicates the successful
 540 * setup of an entry with the new MSI irq.  A negative return value indicates
 541 * an error, and a positive return value indicates the number of interrupts
 542 * which could have been allocated.
 543 */
 544static int msi_capability_init(struct pci_dev *dev, int nvec)
 545{
 546        struct msi_desc *entry;
 547        int ret;
 548        u16 control;
 549        unsigned mask;
 550
 551        msi_set_enable(dev, 0); /* Disable MSI during set up */
 552
 553        pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
 554        /* MSI Entry Initialization */
 555        entry = alloc_msi_entry(dev);
 556        if (!entry)
 557                return -ENOMEM;
 558
 559        entry->msi_attrib.is_msix       = 0;
 560        entry->msi_attrib.is_64         = !!(control & PCI_MSI_FLAGS_64BIT);
 561        entry->msi_attrib.entry_nr      = 0;
 562        entry->msi_attrib.maskbit       = !!(control & PCI_MSI_FLAGS_MASKBIT);
 563        entry->msi_attrib.default_irq   = dev->irq;     /* Save IOAPIC IRQ */
 564        entry->msi_attrib.pos           = dev->msi_cap;
 565
 566        if (control & PCI_MSI_FLAGS_64BIT)
 567                entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
 568        else
 569                entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
 570        /* All MSIs are unmasked by default, Mask them all */
 571        if (entry->msi_attrib.maskbit)
 572                pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
 573        mask = msi_capable_mask(control);
 574        msi_mask_irq(entry, mask, mask);
 575
 576        list_add_tail(&entry->list, &dev->msi_list);
 577
 578        /* Configure MSI capability structure */
 579        ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
 580        if (ret) {
 581                msi_mask_irq(entry, mask, ~mask);
 582                free_msi_irqs(dev);
 583                return ret;
 584        }
 585
 586        ret = populate_msi_sysfs(dev);
 587        if (ret) {
 588                msi_mask_irq(entry, mask, ~mask);
 589                free_msi_irqs(dev);
 590                return ret;
 591        }
 592
 593        /* Set MSI enabled bits  */
 594        pci_intx_for_msi(dev, 0);
 595        msi_set_enable(dev, 1);
 596        dev->msi_enabled = 1;
 597
 598        dev->irq = entry->irq;
 599        return 0;
 600}
 601
 602static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
 603{
 604        resource_size_t phys_addr;
 605        u32 table_offset;
 606        u8 bir;
 607
 608        pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
 609                              &table_offset);
 610        bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
 611        table_offset &= PCI_MSIX_TABLE_OFFSET;
 612        phys_addr = pci_resource_start(dev, bir) + table_offset;
 613
 614        return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
 615}
 616
 617static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
 618                              struct msix_entry *entries, int nvec)
 619{
 620        struct msi_desc *entry;
 621        int i;
 622
 623        for (i = 0; i < nvec; i++) {
 624                entry = alloc_msi_entry(dev);
 625                if (!entry) {
 626                        if (!i)
 627                                iounmap(base);
 628                        else
 629                                free_msi_irqs(dev);
 630                        /* No enough memory. Don't try again */
 631                        return -ENOMEM;
 632                }
 633
 634                entry->msi_attrib.is_msix       = 1;
 635                entry->msi_attrib.is_64         = 1;
 636                entry->msi_attrib.entry_nr      = entries[i].entry;
 637                entry->msi_attrib.default_irq   = dev->irq;
 638                entry->msi_attrib.pos           = dev->msix_cap;
 639                entry->mask_base                = base;
 640
 641                list_add_tail(&entry->list, &dev->msi_list);
 642        }
 643
 644        return 0;
 645}
 646
 647static void msix_program_entries(struct pci_dev *dev,
 648                                 struct msix_entry *entries)
 649{
 650        struct msi_desc *entry;
 651        int i = 0;
 652
 653        list_for_each_entry(entry, &dev->msi_list, list) {
 654                int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
 655                                                PCI_MSIX_ENTRY_VECTOR_CTRL;
 656
 657                entries[i].vector = entry->irq;
 658                irq_set_msi_desc(entry->irq, entry);
 659                entry->masked = readl(entry->mask_base + offset);
 660                msix_mask_irq(entry, 1);
 661                i++;
 662        }
 663}
 664
 665/**
 666 * msix_capability_init - configure device's MSI-X capability
 667 * @dev: pointer to the pci_dev data structure of MSI-X device function
 668 * @entries: pointer to an array of struct msix_entry entries
 669 * @nvec: number of @entries
 670 *
 671 * Setup the MSI-X capability structure of device function with a
 672 * single MSI-X irq. A return of zero indicates the successful setup of
 673 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
 674 **/
 675static int msix_capability_init(struct pci_dev *dev,
 676                                struct msix_entry *entries, int nvec)
 677{
 678        int ret;
 679        u16 control;
 680        void __iomem *base;
 681
 682        pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
 683
 684        /* Ensure MSI-X is disabled while it is set up */
 685        control &= ~PCI_MSIX_FLAGS_ENABLE;
 686        pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
 687
 688        /* Request & Map MSI-X table region */
 689        base = msix_map_region(dev, msix_table_size(control));
 690        if (!base)
 691                return -ENOMEM;
 692
 693        ret = msix_setup_entries(dev, base, entries, nvec);
 694        if (ret)
 695                return ret;
 696
 697        ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
 698        if (ret)
 699                goto error;
 700
 701        /*
 702         * Some devices require MSI-X to be enabled before we can touch the
 703         * MSI-X registers.  We need to mask all the vectors to prevent
 704         * interrupts coming in before they're fully set up.
 705         */
 706        control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
 707        pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
 708
 709        msix_program_entries(dev, entries);
 710
 711        ret = populate_msi_sysfs(dev);
 712        if (ret) {
 713                ret = 0;
 714                goto error;
 715        }
 716
 717        /* Set MSI-X enabled bits and unmask the function */
 718        pci_intx_for_msi(dev, 0);
 719        dev->msix_enabled = 1;
 720
 721        control &= ~PCI_MSIX_FLAGS_MASKALL;
 722        pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
 723
 724        return 0;
 725
 726error:
 727        if (ret < 0) {
 728                /*
 729                 * If we had some success, report the number of irqs
 730                 * we succeeded in setting up.
 731                 */
 732                struct msi_desc *entry;
 733                int avail = 0;
 734
 735                list_for_each_entry(entry, &dev->msi_list, list) {
 736                        if (entry->irq != 0)
 737                                avail++;
 738                }
 739                if (avail != 0)
 740                        ret = avail;
 741        }
 742
 743        free_msi_irqs(dev);
 744
 745        return ret;
 746}
 747
 748/**
 749 * pci_msi_check_device - check whether MSI may be enabled on a device
 750 * @dev: pointer to the pci_dev data structure of MSI device function
 751 * @nvec: how many MSIs have been requested ?
 752 * @type: are we checking for MSI or MSI-X ?
 753 *
 754 * Look at global flags, the device itself, and its parent busses
 755 * to determine if MSI/-X are supported for the device. If MSI/-X is
 756 * supported return 0, else return an error code.
 757 **/
 758static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type)
 759{
 760        struct pci_bus *bus;
 761        int ret;
 762
 763        /* MSI must be globally enabled and supported by the device */
 764        if (!pci_msi_enable || !dev || dev->no_msi)
 765                return -EINVAL;
 766
 767        /*
 768         * You can't ask to have 0 or less MSIs configured.
 769         *  a) it's stupid ..
 770         *  b) the list manipulation code assumes nvec >= 1.
 771         */
 772        if (nvec < 1)
 773                return -ERANGE;
 774
 775        /*
 776         * Any bridge which does NOT route MSI transactions from its
 777         * secondary bus to its primary bus must set NO_MSI flag on
 778         * the secondary pci_bus.
 779         * We expect only arch-specific PCI host bus controller driver
 780         * or quirks for specific PCI bridges to be setting NO_MSI.
 781         */
 782        for (bus = dev->bus; bus; bus = bus->parent)
 783                if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
 784                        return -EINVAL;
 785
 786        ret = arch_msi_check_device(dev, nvec, type);
 787        if (ret)
 788                return ret;
 789
 790        return 0;
 791}
 792
 793/**
 794 * pci_enable_msi_block - configure device's MSI capability structure
 795 * @dev: device to configure
 796 * @nvec: number of interrupts to configure
 797 *
 798 * Allocate IRQs for a device with the MSI capability.
 799 * This function returns a negative errno if an error occurs.  If it
 800 * is unable to allocate the number of interrupts requested, it returns
 801 * the number of interrupts it might be able to allocate.  If it successfully
 802 * allocates at least the number of interrupts requested, it returns 0 and
 803 * updates the @dev's irq member to the lowest new interrupt number; the
 804 * other interrupt numbers allocated to this device are consecutive.
 805 */
 806int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
 807{
 808        int status, maxvec;
 809        u16 msgctl;
 810
 811        if (!dev->msi_cap)
 812                return -EINVAL;
 813
 814        pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
 815        maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
 816        if (nvec > maxvec)
 817                return maxvec;
 818
 819        status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI);
 820        if (status)
 821                return status;
 822
 823        WARN_ON(!!dev->msi_enabled);
 824
 825        /* Check whether driver already requested MSI-X irqs */
 826        if (dev->msix_enabled) {
 827                dev_info(&dev->dev, "can't enable MSI "
 828                         "(MSI-X already enabled)\n");
 829                return -EINVAL;
 830        }
 831
 832        status = msi_capability_init(dev, nvec);
 833        return status;
 834}
 835EXPORT_SYMBOL(pci_enable_msi_block);
 836
 837int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec)
 838{
 839        int ret, nvec;
 840        u16 msgctl;
 841
 842        if (!dev->msi_cap)
 843                return -EINVAL;
 844
 845        pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
 846        ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
 847
 848        if (maxvec)
 849                *maxvec = ret;
 850
 851        do {
 852                nvec = ret;
 853                ret = pci_enable_msi_block(dev, nvec);
 854        } while (ret > 0);
 855
 856        if (ret < 0)
 857                return ret;
 858        return nvec;
 859}
 860EXPORT_SYMBOL(pci_enable_msi_block_auto);
 861
 862void pci_msi_shutdown(struct pci_dev *dev)
 863{
 864        struct msi_desc *desc;
 865        u32 mask;
 866        u16 ctrl;
 867
 868        if (!pci_msi_enable || !dev || !dev->msi_enabled)
 869                return;
 870
 871        BUG_ON(list_empty(&dev->msi_list));
 872        desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
 873
 874        msi_set_enable(dev, 0);
 875        pci_intx_for_msi(dev, 1);
 876        dev->msi_enabled = 0;
 877
 878        /* Return the device with MSI unmasked as initial states */
 879        pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl);
 880        mask = msi_capable_mask(ctrl);
 881        /* Keep cached state to be restored */
 882        __msi_mask_irq(desc, mask, ~mask);
 883
 884        /* Restore dev->irq to its default pin-assertion irq */
 885        dev->irq = desc->msi_attrib.default_irq;
 886}
 887
 888void pci_disable_msi(struct pci_dev *dev)
 889{
 890        if (!pci_msi_enable || !dev || !dev->msi_enabled)
 891                return;
 892
 893        pci_msi_shutdown(dev);
 894        free_msi_irqs(dev);
 895        kset_unregister(dev->msi_kset);
 896        dev->msi_kset = NULL;
 897}
 898EXPORT_SYMBOL(pci_disable_msi);
 899
 900/**
 901 * pci_msix_table_size - return the number of device's MSI-X table entries
 902 * @dev: pointer to the pci_dev data structure of MSI-X device function
 903 */
 904int pci_msix_table_size(struct pci_dev *dev)
 905{
 906        u16 control;
 907
 908        if (!dev->msix_cap)
 909                return 0;
 910
 911        pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
 912        return msix_table_size(control);
 913}
 914
 915/**
 916 * pci_enable_msix - configure device's MSI-X capability structure
 917 * @dev: pointer to the pci_dev data structure of MSI-X device function
 918 * @entries: pointer to an array of MSI-X entries
 919 * @nvec: number of MSI-X irqs requested for allocation by device driver
 920 *
 921 * Setup the MSI-X capability structure of device function with the number
 922 * of requested irqs upon its software driver call to request for
 923 * MSI-X mode enabled on its hardware device function. A return of zero
 924 * indicates the successful configuration of MSI-X capability structure
 925 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
 926 * Or a return of > 0 indicates that driver request is exceeding the number
 927 * of irqs or MSI-X vectors available. Driver should use the returned value to
 928 * re-send its request.
 929 **/
 930int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
 931{
 932        int status, nr_entries;
 933        int i, j;
 934
 935        if (!entries || !dev->msix_cap)
 936                return -EINVAL;
 937
 938        status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
 939        if (status)
 940                return status;
 941
 942        nr_entries = pci_msix_table_size(dev);
 943        if (nvec > nr_entries)
 944                return nr_entries;
 945
 946        /* Check for any invalid entries */
 947        for (i = 0; i < nvec; i++) {
 948                if (entries[i].entry >= nr_entries)
 949                        return -EINVAL;         /* invalid entry */
 950                for (j = i + 1; j < nvec; j++) {
 951                        if (entries[i].entry == entries[j].entry)
 952                                return -EINVAL; /* duplicate entry */
 953                }
 954        }
 955        WARN_ON(!!dev->msix_enabled);
 956
 957        /* Check whether driver already requested for MSI irq */
 958        if (dev->msi_enabled) {
 959                dev_info(&dev->dev, "can't enable MSI-X "
 960                       "(MSI IRQ already assigned)\n");
 961                return -EINVAL;
 962        }
 963        status = msix_capability_init(dev, entries, nvec);
 964        return status;
 965}
 966EXPORT_SYMBOL(pci_enable_msix);
 967
 968void pci_msix_shutdown(struct pci_dev *dev)
 969{
 970        struct msi_desc *entry;
 971
 972        if (!pci_msi_enable || !dev || !dev->msix_enabled)
 973                return;
 974
 975        /* Return the device with MSI-X masked as initial states */
 976        list_for_each_entry(entry, &dev->msi_list, list) {
 977                /* Keep cached states to be restored */
 978                __msix_mask_irq(entry, 1);
 979        }
 980
 981        msix_set_enable(dev, 0);
 982        pci_intx_for_msi(dev, 1);
 983        dev->msix_enabled = 0;
 984}
 985
 986void pci_disable_msix(struct pci_dev *dev)
 987{
 988        if (!pci_msi_enable || !dev || !dev->msix_enabled)
 989                return;
 990
 991        pci_msix_shutdown(dev);
 992        free_msi_irqs(dev);
 993        kset_unregister(dev->msi_kset);
 994        dev->msi_kset = NULL;
 995}
 996EXPORT_SYMBOL(pci_disable_msix);
 997
 998/**
 999 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
1000 * @dev: pointer to the pci_dev data structure of MSI(X) device function
1001 *
1002 * Being called during hotplug remove, from which the device function
1003 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
1004 * allocated for this device function, are reclaimed to unused state,
1005 * which may be used later on.
1006 **/
1007void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1008{
1009        if (!pci_msi_enable || !dev)
1010                return;
1011
1012        if (dev->msi_enabled || dev->msix_enabled)
1013                free_msi_irqs(dev);
1014}
1015
1016void pci_no_msi(void)
1017{
1018        pci_msi_enable = 0;
1019}
1020
1021/**
1022 * pci_msi_enabled - is MSI enabled?
1023 *
1024 * Returns true if MSI has not been disabled by the command-line option
1025 * pci=nomsi.
1026 **/
1027int pci_msi_enabled(void)
1028{
1029        return pci_msi_enable;
1030}
1031EXPORT_SYMBOL(pci_msi_enabled);
1032
1033void pci_msi_init_pci_dev(struct pci_dev *dev)
1034{
1035        INIT_LIST_HEAD(&dev->msi_list);
1036
1037        /* Disable the msi hardware to avoid screaming interrupts
1038         * during boot.  This is the power on reset default so
1039         * usually this should be a noop.
1040         */
1041        dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1042        if (dev->msi_cap)
1043                msi_set_enable(dev, 0);
1044
1045        dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1046        if (dev->msix_cap)
1047                msix_set_enable(dev, 0);
1048}
1049
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