linux/drivers/mfd/rtsx_pcr.c
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   1/* Driver for Realtek PCI-Express card reader
   2 *
   3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of the GNU General Public License as published by the
   7 * Free Software Foundation; either version 2, or (at your option) any
   8 * later version.
   9 *
  10 * This program is distributed in the hope that it will be useful, but
  11 * WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13 * General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License along
  16 * with this program; if not, see <http://www.gnu.org/licenses/>.
  17 *
  18 * Author:
  19 *   Wei WANG <wei_wang@realsil.com.cn>
  20 *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  21 */
  22
  23#include <linux/pci.h>
  24#include <linux/module.h>
  25#include <linux/slab.h>
  26#include <linux/dma-mapping.h>
  27#include <linux/highmem.h>
  28#include <linux/interrupt.h>
  29#include <linux/delay.h>
  30#include <linux/idr.h>
  31#include <linux/platform_device.h>
  32#include <linux/mfd/core.h>
  33#include <linux/mfd/rtsx_pci.h>
  34#include <asm/unaligned.h>
  35
  36#include "rtsx_pcr.h"
  37
  38static bool msi_en = true;
  39module_param(msi_en, bool, S_IRUGO | S_IWUSR);
  40MODULE_PARM_DESC(msi_en, "Enable MSI");
  41
  42static DEFINE_IDR(rtsx_pci_idr);
  43static DEFINE_SPINLOCK(rtsx_pci_lock);
  44
  45static struct mfd_cell rtsx_pcr_cells[] = {
  46        [RTSX_SD_CARD] = {
  47                .name = DRV_NAME_RTSX_PCI_SDMMC,
  48        },
  49        [RTSX_MS_CARD] = {
  50                .name = DRV_NAME_RTSX_PCI_MS,
  51        },
  52};
  53
  54static DEFINE_PCI_DEVICE_TABLE(rtsx_pci_ids) = {
  55        { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  56        { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  57        { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  58        { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  59        { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  60        { 0, }
  61};
  62
  63MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
  64
  65void rtsx_pci_start_run(struct rtsx_pcr *pcr)
  66{
  67        /* If pci device removed, don't queue idle work any more */
  68        if (pcr->remove_pci)
  69                return;
  70
  71        if (pcr->state != PDEV_STAT_RUN) {
  72                pcr->state = PDEV_STAT_RUN;
  73                if (pcr->ops->enable_auto_blink)
  74                        pcr->ops->enable_auto_blink(pcr);
  75        }
  76
  77        mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
  78}
  79EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
  80
  81int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
  82{
  83        int i;
  84        u32 val = HAIMR_WRITE_START;
  85
  86        val |= (u32)(addr & 0x3FFF) << 16;
  87        val |= (u32)mask << 8;
  88        val |= (u32)data;
  89
  90        rtsx_pci_writel(pcr, RTSX_HAIMR, val);
  91
  92        for (i = 0; i < MAX_RW_REG_CNT; i++) {
  93                val = rtsx_pci_readl(pcr, RTSX_HAIMR);
  94                if ((val & HAIMR_TRANS_END) == 0) {
  95                        if (data != (u8)val)
  96                                return -EIO;
  97                        return 0;
  98                }
  99        }
 100
 101        return -ETIMEDOUT;
 102}
 103EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
 104
 105int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
 106{
 107        u32 val = HAIMR_READ_START;
 108        int i;
 109
 110        val |= (u32)(addr & 0x3FFF) << 16;
 111        rtsx_pci_writel(pcr, RTSX_HAIMR, val);
 112
 113        for (i = 0; i < MAX_RW_REG_CNT; i++) {
 114                val = rtsx_pci_readl(pcr, RTSX_HAIMR);
 115                if ((val & HAIMR_TRANS_END) == 0)
 116                        break;
 117        }
 118
 119        if (i >= MAX_RW_REG_CNT)
 120                return -ETIMEDOUT;
 121
 122        if (data)
 123                *data = (u8)(val & 0xFF);
 124
 125        return 0;
 126}
 127EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
 128
 129int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
 130{
 131        int err, i, finished = 0;
 132        u8 tmp;
 133
 134        rtsx_pci_init_cmd(pcr);
 135
 136        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
 137        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
 138        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
 139        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
 140
 141        err = rtsx_pci_send_cmd(pcr, 100);
 142        if (err < 0)
 143                return err;
 144
 145        for (i = 0; i < 100000; i++) {
 146                err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
 147                if (err < 0)
 148                        return err;
 149
 150                if (!(tmp & 0x80)) {
 151                        finished = 1;
 152                        break;
 153                }
 154        }
 155
 156        if (!finished)
 157                return -ETIMEDOUT;
 158
 159        return 0;
 160}
 161EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
 162
 163int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
 164{
 165        int err, i, finished = 0;
 166        u16 data;
 167        u8 *ptr, tmp;
 168
 169        rtsx_pci_init_cmd(pcr);
 170
 171        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
 172        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
 173
 174        err = rtsx_pci_send_cmd(pcr, 100);
 175        if (err < 0)
 176                return err;
 177
 178        for (i = 0; i < 100000; i++) {
 179                err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
 180                if (err < 0)
 181                        return err;
 182
 183                if (!(tmp & 0x80)) {
 184                        finished = 1;
 185                        break;
 186                }
 187        }
 188
 189        if (!finished)
 190                return -ETIMEDOUT;
 191
 192        rtsx_pci_init_cmd(pcr);
 193
 194        rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
 195        rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
 196
 197        err = rtsx_pci_send_cmd(pcr, 100);
 198        if (err < 0)
 199                return err;
 200
 201        ptr = rtsx_pci_get_cmd_data(pcr);
 202        data = ((u16)ptr[1] << 8) | ptr[0];
 203
 204        if (val)
 205                *val = data;
 206
 207        return 0;
 208}
 209EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
 210
 211void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
 212{
 213        rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
 214        rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
 215
 216        rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
 217        rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
 218}
 219EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
 220
 221void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
 222                u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
 223{
 224        unsigned long flags;
 225        u32 val = 0;
 226        u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
 227
 228        val |= (u32)(cmd_type & 0x03) << 30;
 229        val |= (u32)(reg_addr & 0x3FFF) << 16;
 230        val |= (u32)mask << 8;
 231        val |= (u32)data;
 232
 233        spin_lock_irqsave(&pcr->lock, flags);
 234        ptr += pcr->ci;
 235        if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
 236                put_unaligned_le32(val, ptr);
 237                ptr++;
 238                pcr->ci++;
 239        }
 240        spin_unlock_irqrestore(&pcr->lock, flags);
 241}
 242EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
 243
 244void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
 245{
 246        u32 val = 1 << 31;
 247
 248        rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 249
 250        val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
 251        /* Hardware Auto Response */
 252        val |= 0x40000000;
 253        rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
 254}
 255EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
 256
 257int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
 258{
 259        struct completion trans_done;
 260        u32 val = 1 << 31;
 261        long timeleft;
 262        unsigned long flags;
 263        int err = 0;
 264
 265        spin_lock_irqsave(&pcr->lock, flags);
 266
 267        /* set up data structures for the wakeup system */
 268        pcr->done = &trans_done;
 269        pcr->trans_result = TRANS_NOT_READY;
 270        init_completion(&trans_done);
 271
 272        rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 273
 274        val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
 275        /* Hardware Auto Response */
 276        val |= 0x40000000;
 277        rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
 278
 279        spin_unlock_irqrestore(&pcr->lock, flags);
 280
 281        /* Wait for TRANS_OK_INT */
 282        timeleft = wait_for_completion_interruptible_timeout(
 283                        &trans_done, msecs_to_jiffies(timeout));
 284        if (timeleft <= 0) {
 285                dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
 286                                __func__, __LINE__);
 287                err = -ETIMEDOUT;
 288                goto finish_send_cmd;
 289        }
 290
 291        spin_lock_irqsave(&pcr->lock, flags);
 292        if (pcr->trans_result == TRANS_RESULT_FAIL)
 293                err = -EINVAL;
 294        else if (pcr->trans_result == TRANS_RESULT_OK)
 295                err = 0;
 296        else if (pcr->trans_result == TRANS_NO_DEVICE)
 297                err = -ENODEV;
 298        spin_unlock_irqrestore(&pcr->lock, flags);
 299
 300finish_send_cmd:
 301        spin_lock_irqsave(&pcr->lock, flags);
 302        pcr->done = NULL;
 303        spin_unlock_irqrestore(&pcr->lock, flags);
 304
 305        if ((err < 0) && (err != -ENODEV))
 306                rtsx_pci_stop_cmd(pcr);
 307
 308        if (pcr->finish_me)
 309                complete(pcr->finish_me);
 310
 311        return err;
 312}
 313EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
 314
 315static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
 316                dma_addr_t addr, unsigned int len, int end)
 317{
 318        u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
 319        u64 val;
 320        u8 option = SG_VALID | SG_TRANS_DATA;
 321
 322        dev_dbg(&(pcr->pci->dev), "DMA addr: 0x%x, Len: 0x%x\n",
 323                        (unsigned int)addr, len);
 324
 325        if (end)
 326                option |= SG_END;
 327        val = ((u64)addr << 32) | ((u64)len << 12) | option;
 328
 329        put_unaligned_le64(val, ptr);
 330        pcr->sgi++;
 331}
 332
 333int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
 334                int num_sg, bool read, int timeout)
 335{
 336        struct completion trans_done;
 337        u8 dir;
 338        int err = 0, i, count;
 339        long timeleft;
 340        unsigned long flags;
 341        struct scatterlist *sg;
 342        enum dma_data_direction dma_dir;
 343        u32 val;
 344        dma_addr_t addr;
 345        unsigned int len;
 346
 347        dev_dbg(&(pcr->pci->dev), "--> %s: num_sg = %d\n", __func__, num_sg);
 348
 349        /* don't transfer data during abort processing */
 350        if (pcr->remove_pci)
 351                return -EINVAL;
 352
 353        if ((sglist == NULL) || (num_sg <= 0))
 354                return -EINVAL;
 355
 356        if (read) {
 357                dir = DEVICE_TO_HOST;
 358                dma_dir = DMA_FROM_DEVICE;
 359        } else {
 360                dir = HOST_TO_DEVICE;
 361                dma_dir = DMA_TO_DEVICE;
 362        }
 363
 364        count = dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
 365        if (count < 1) {
 366                dev_err(&(pcr->pci->dev), "scatterlist map failed\n");
 367                return -EINVAL;
 368        }
 369        dev_dbg(&(pcr->pci->dev), "DMA mapping count: %d\n", count);
 370
 371        val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
 372        pcr->sgi = 0;
 373        for_each_sg(sglist, sg, count, i) {
 374                addr = sg_dma_address(sg);
 375                len = sg_dma_len(sg);
 376                rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
 377        }
 378
 379        spin_lock_irqsave(&pcr->lock, flags);
 380
 381        pcr->done = &trans_done;
 382        pcr->trans_result = TRANS_NOT_READY;
 383        init_completion(&trans_done);
 384        rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
 385        rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
 386
 387        spin_unlock_irqrestore(&pcr->lock, flags);
 388
 389        timeleft = wait_for_completion_interruptible_timeout(
 390                        &trans_done, msecs_to_jiffies(timeout));
 391        if (timeleft <= 0) {
 392                dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
 393                                __func__, __LINE__);
 394                err = -ETIMEDOUT;
 395                goto out;
 396        }
 397
 398        spin_lock_irqsave(&pcr->lock, flags);
 399
 400        if (pcr->trans_result == TRANS_RESULT_FAIL)
 401                err = -EINVAL;
 402        else if (pcr->trans_result == TRANS_NO_DEVICE)
 403                err = -ENODEV;
 404
 405        spin_unlock_irqrestore(&pcr->lock, flags);
 406
 407out:
 408        spin_lock_irqsave(&pcr->lock, flags);
 409        pcr->done = NULL;
 410        spin_unlock_irqrestore(&pcr->lock, flags);
 411
 412        dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
 413
 414        if ((err < 0) && (err != -ENODEV))
 415                rtsx_pci_stop_cmd(pcr);
 416
 417        if (pcr->finish_me)
 418                complete(pcr->finish_me);
 419
 420        return err;
 421}
 422EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
 423
 424int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
 425{
 426        int err;
 427        int i, j;
 428        u16 reg;
 429        u8 *ptr;
 430
 431        if (buf_len > 512)
 432                buf_len = 512;
 433
 434        ptr = buf;
 435        reg = PPBUF_BASE2;
 436        for (i = 0; i < buf_len / 256; i++) {
 437                rtsx_pci_init_cmd(pcr);
 438
 439                for (j = 0; j < 256; j++)
 440                        rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
 441
 442                err = rtsx_pci_send_cmd(pcr, 250);
 443                if (err < 0)
 444                        return err;
 445
 446                memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
 447                ptr += 256;
 448        }
 449
 450        if (buf_len % 256) {
 451                rtsx_pci_init_cmd(pcr);
 452
 453                for (j = 0; j < buf_len % 256; j++)
 454                        rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
 455
 456                err = rtsx_pci_send_cmd(pcr, 250);
 457                if (err < 0)
 458                        return err;
 459        }
 460
 461        memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
 462
 463        return 0;
 464}
 465EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
 466
 467int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
 468{
 469        int err;
 470        int i, j;
 471        u16 reg;
 472        u8 *ptr;
 473
 474        if (buf_len > 512)
 475                buf_len = 512;
 476
 477        ptr = buf;
 478        reg = PPBUF_BASE2;
 479        for (i = 0; i < buf_len / 256; i++) {
 480                rtsx_pci_init_cmd(pcr);
 481
 482                for (j = 0; j < 256; j++) {
 483                        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 484                                        reg++, 0xFF, *ptr);
 485                        ptr++;
 486                }
 487
 488                err = rtsx_pci_send_cmd(pcr, 250);
 489                if (err < 0)
 490                        return err;
 491        }
 492
 493        if (buf_len % 256) {
 494                rtsx_pci_init_cmd(pcr);
 495
 496                for (j = 0; j < buf_len % 256; j++) {
 497                        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 498                                        reg++, 0xFF, *ptr);
 499                        ptr++;
 500                }
 501
 502                err = rtsx_pci_send_cmd(pcr, 250);
 503                if (err < 0)
 504                        return err;
 505        }
 506
 507        return 0;
 508}
 509EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
 510
 511static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
 512{
 513        int err;
 514
 515        rtsx_pci_init_cmd(pcr);
 516
 517        while (*tbl & 0xFFFF0000) {
 518                rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 519                                (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
 520                tbl++;
 521        }
 522
 523        err = rtsx_pci_send_cmd(pcr, 100);
 524        if (err < 0)
 525                return err;
 526
 527        return 0;
 528}
 529
 530int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
 531{
 532        const u32 *tbl;
 533
 534        if (card == RTSX_SD_CARD)
 535                tbl = pcr->sd_pull_ctl_enable_tbl;
 536        else if (card == RTSX_MS_CARD)
 537                tbl = pcr->ms_pull_ctl_enable_tbl;
 538        else
 539                return -EINVAL;
 540
 541        return rtsx_pci_set_pull_ctl(pcr, tbl);
 542}
 543EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
 544
 545int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
 546{
 547        const u32 *tbl;
 548
 549        if (card == RTSX_SD_CARD)
 550                tbl = pcr->sd_pull_ctl_disable_tbl;
 551        else if (card == RTSX_MS_CARD)
 552                tbl = pcr->ms_pull_ctl_disable_tbl;
 553        else
 554                return -EINVAL;
 555
 556
 557        return rtsx_pci_set_pull_ctl(pcr, tbl);
 558}
 559EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
 560
 561static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
 562{
 563        pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
 564
 565        if (pcr->num_slots > 1)
 566                pcr->bier |= MS_INT_EN;
 567
 568        /* Enable Bus Interrupt */
 569        rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
 570
 571        dev_dbg(&(pcr->pci->dev), "RTSX_BIER: 0x%08x\n", pcr->bier);
 572}
 573
 574static inline u8 double_ssc_depth(u8 depth)
 575{
 576        return ((depth > 1) ? (depth - 1) : depth);
 577}
 578
 579static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
 580{
 581        if (div > CLK_DIV_1) {
 582                if (ssc_depth > (div - 1))
 583                        ssc_depth -= (div - 1);
 584                else
 585                        ssc_depth = SSC_DEPTH_4M;
 586        }
 587
 588        return ssc_depth;
 589}
 590
 591int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
 592                u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
 593{
 594        int err, clk;
 595        u8 n, clk_divider, mcu_cnt, div;
 596        u8 depth[] = {
 597                [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
 598                [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
 599                [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
 600                [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
 601                [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
 602        };
 603
 604        if (initial_mode) {
 605                /* We use 250k(around) here, in initial stage */
 606                clk_divider = SD_CLK_DIVIDE_128;
 607                card_clock = 30000000;
 608        } else {
 609                clk_divider = SD_CLK_DIVIDE_0;
 610        }
 611        err = rtsx_pci_write_register(pcr, SD_CFG1,
 612                        SD_CLK_DIVIDE_MASK, clk_divider);
 613        if (err < 0)
 614                return err;
 615
 616        card_clock /= 1000000;
 617        dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock);
 618
 619        clk = card_clock;
 620        if (!initial_mode && double_clk)
 621                clk = card_clock * 2;
 622        dev_dbg(&(pcr->pci->dev),
 623                        "Internal SSC clock: %dMHz (cur_clock = %d)\n",
 624                        clk, pcr->cur_clock);
 625
 626        if (clk == pcr->cur_clock)
 627                return 0;
 628
 629        if (pcr->ops->conv_clk_and_div_n)
 630                n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
 631        else
 632                n = (u8)(clk - 2);
 633        if ((clk <= 2) || (n > MAX_DIV_N_PCR))
 634                return -EINVAL;
 635
 636        mcu_cnt = (u8)(125/clk + 3);
 637        if (mcu_cnt > 15)
 638                mcu_cnt = 15;
 639
 640        /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
 641        div = CLK_DIV_1;
 642        while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
 643                if (pcr->ops->conv_clk_and_div_n) {
 644                        int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
 645                                        DIV_N_TO_CLK) * 2;
 646                        n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
 647                                        CLK_TO_DIV_N);
 648                } else {
 649                        n = (n + 2) * 2 - 2;
 650                }
 651                div++;
 652        }
 653        dev_dbg(&(pcr->pci->dev), "n = %d, div = %d\n", n, div);
 654
 655        ssc_depth = depth[ssc_depth];
 656        if (double_clk)
 657                ssc_depth = double_ssc_depth(ssc_depth);
 658
 659        ssc_depth = revise_ssc_depth(ssc_depth, div);
 660        dev_dbg(&(pcr->pci->dev), "ssc_depth = %d\n", ssc_depth);
 661
 662        rtsx_pci_init_cmd(pcr);
 663        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
 664                        CLK_LOW_FREQ, CLK_LOW_FREQ);
 665        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
 666                        0xFF, (div << 4) | mcu_cnt);
 667        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
 668        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
 669                        SSC_DEPTH_MASK, ssc_depth);
 670        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
 671        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
 672        if (vpclk) {
 673                rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 674                                PHASE_NOT_RESET, 0);
 675                rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 676                                PHASE_NOT_RESET, PHASE_NOT_RESET);
 677        }
 678
 679        err = rtsx_pci_send_cmd(pcr, 2000);
 680        if (err < 0)
 681                return err;
 682
 683        /* Wait SSC clock stable */
 684        udelay(10);
 685        err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
 686        if (err < 0)
 687                return err;
 688
 689        pcr->cur_clock = clk;
 690        return 0;
 691}
 692EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
 693
 694int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
 695{
 696        if (pcr->ops->card_power_on)
 697                return pcr->ops->card_power_on(pcr, card);
 698
 699        return 0;
 700}
 701EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
 702
 703int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
 704{
 705        if (pcr->ops->card_power_off)
 706                return pcr->ops->card_power_off(pcr, card);
 707
 708        return 0;
 709}
 710EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
 711
 712int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
 713{
 714        unsigned int cd_mask[] = {
 715                [RTSX_SD_CARD] = SD_EXIST,
 716                [RTSX_MS_CARD] = MS_EXIST
 717        };
 718
 719        if (!pcr->ms_pmos) {
 720                /* When using single PMOS, accessing card is not permitted
 721                 * if the existing card is not the designated one.
 722                 */
 723                if (pcr->card_exist & (~cd_mask[card]))
 724                        return -EIO;
 725        }
 726
 727        return 0;
 728}
 729EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
 730
 731int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 732{
 733        if (pcr->ops->switch_output_voltage)
 734                return pcr->ops->switch_output_voltage(pcr, voltage);
 735
 736        return 0;
 737}
 738EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
 739
 740unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
 741{
 742        unsigned int val;
 743
 744        val = rtsx_pci_readl(pcr, RTSX_BIPR);
 745        if (pcr->ops->cd_deglitch)
 746                val = pcr->ops->cd_deglitch(pcr);
 747
 748        return val;
 749}
 750EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
 751
 752void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
 753{
 754        struct completion finish;
 755
 756        pcr->finish_me = &finish;
 757        init_completion(&finish);
 758
 759        if (pcr->done)
 760                complete(pcr->done);
 761
 762        if (!pcr->remove_pci)
 763                rtsx_pci_stop_cmd(pcr);
 764
 765        wait_for_completion_interruptible_timeout(&finish,
 766                        msecs_to_jiffies(2));
 767        pcr->finish_me = NULL;
 768}
 769EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
 770
 771static void rtsx_pci_card_detect(struct work_struct *work)
 772{
 773        struct delayed_work *dwork;
 774        struct rtsx_pcr *pcr;
 775        unsigned long flags;
 776        unsigned int card_detect = 0, card_inserted, card_removed;
 777        u32 irq_status;
 778
 779        dwork = to_delayed_work(work);
 780        pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
 781
 782        dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
 783
 784        mutex_lock(&pcr->pcr_mutex);
 785        spin_lock_irqsave(&pcr->lock, flags);
 786
 787        irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
 788        dev_dbg(&(pcr->pci->dev), "irq_status: 0x%08x\n", irq_status);
 789
 790        irq_status &= CARD_EXIST;
 791        card_inserted = pcr->card_inserted & irq_status;
 792        card_removed = pcr->card_removed;
 793        pcr->card_inserted = 0;
 794        pcr->card_removed = 0;
 795
 796        spin_unlock_irqrestore(&pcr->lock, flags);
 797
 798        if (card_inserted || card_removed) {
 799                dev_dbg(&(pcr->pci->dev),
 800                                "card_inserted: 0x%x, card_removed: 0x%x\n",
 801                                card_inserted, card_removed);
 802
 803                if (pcr->ops->cd_deglitch)
 804                        card_inserted = pcr->ops->cd_deglitch(pcr);
 805
 806                card_detect = card_inserted | card_removed;
 807
 808                pcr->card_exist |= card_inserted;
 809                pcr->card_exist &= ~card_removed;
 810        }
 811
 812        mutex_unlock(&pcr->pcr_mutex);
 813
 814        if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
 815                pcr->slots[RTSX_SD_CARD].card_event(
 816                                pcr->slots[RTSX_SD_CARD].p_dev);
 817        if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
 818                pcr->slots[RTSX_MS_CARD].card_event(
 819                                pcr->slots[RTSX_MS_CARD].p_dev);
 820}
 821
 822static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
 823{
 824        struct rtsx_pcr *pcr = dev_id;
 825        u32 int_reg;
 826
 827        if (!pcr)
 828                return IRQ_NONE;
 829
 830        spin_lock(&pcr->lock);
 831
 832        int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
 833        /* Clear interrupt flag */
 834        rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
 835        if ((int_reg & pcr->bier) == 0) {
 836                spin_unlock(&pcr->lock);
 837                return IRQ_NONE;
 838        }
 839        if (int_reg == 0xFFFFFFFF) {
 840                spin_unlock(&pcr->lock);
 841                return IRQ_HANDLED;
 842        }
 843
 844        int_reg &= (pcr->bier | 0x7FFFFF);
 845
 846        if (int_reg & SD_INT) {
 847                if (int_reg & SD_EXIST) {
 848                        pcr->card_inserted |= SD_EXIST;
 849                } else {
 850                        pcr->card_removed |= SD_EXIST;
 851                        pcr->card_inserted &= ~SD_EXIST;
 852                }
 853        }
 854
 855        if (int_reg & MS_INT) {
 856                if (int_reg & MS_EXIST) {
 857                        pcr->card_inserted |= MS_EXIST;
 858                } else {
 859                        pcr->card_removed |= MS_EXIST;
 860                        pcr->card_inserted &= ~MS_EXIST;
 861                }
 862        }
 863
 864        if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
 865                if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
 866                        pcr->trans_result = TRANS_RESULT_FAIL;
 867                        if (pcr->done)
 868                                complete(pcr->done);
 869                } else if (int_reg & TRANS_OK_INT) {
 870                        pcr->trans_result = TRANS_RESULT_OK;
 871                        if (pcr->done)
 872                                complete(pcr->done);
 873                }
 874        }
 875
 876        if (pcr->card_inserted || pcr->card_removed)
 877                schedule_delayed_work(&pcr->carddet_work,
 878                                msecs_to_jiffies(200));
 879
 880        spin_unlock(&pcr->lock);
 881        return IRQ_HANDLED;
 882}
 883
 884static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
 885{
 886        dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n",
 887                        __func__, pcr->msi_en, pcr->pci->irq);
 888
 889        if (request_irq(pcr->pci->irq, rtsx_pci_isr,
 890                        pcr->msi_en ? 0 : IRQF_SHARED,
 891                        DRV_NAME_RTSX_PCI, pcr)) {
 892                dev_err(&(pcr->pci->dev),
 893                        "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
 894                        pcr->pci->irq);
 895                return -1;
 896        }
 897
 898        pcr->irq = pcr->pci->irq;
 899        pci_intx(pcr->pci, !pcr->msi_en);
 900
 901        return 0;
 902}
 903
 904static void rtsx_pci_idle_work(struct work_struct *work)
 905{
 906        struct delayed_work *dwork = to_delayed_work(work);
 907        struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
 908
 909        dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
 910
 911        mutex_lock(&pcr->pcr_mutex);
 912
 913        pcr->state = PDEV_STAT_IDLE;
 914
 915        if (pcr->ops->disable_auto_blink)
 916                pcr->ops->disable_auto_blink(pcr);
 917        if (pcr->ops->turn_off_led)
 918                pcr->ops->turn_off_led(pcr);
 919
 920        mutex_unlock(&pcr->pcr_mutex);
 921}
 922
 923static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
 924{
 925        int err;
 926
 927        rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 928
 929        rtsx_pci_enable_bus_int(pcr);
 930
 931        /* Power on SSC */
 932        err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
 933        if (err < 0)
 934                return err;
 935
 936        /* Wait SSC power stable */
 937        udelay(200);
 938
 939        if (pcr->ops->optimize_phy) {
 940                err = pcr->ops->optimize_phy(pcr);
 941                if (err < 0)
 942                        return err;
 943        }
 944
 945        rtsx_pci_init_cmd(pcr);
 946
 947        /* Set mcu_cnt to 7 to ensure data can be sampled properly */
 948        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
 949
 950        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
 951        /* Disable card clock */
 952        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
 953        /* Reset ASPM state to default value */
 954        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
 955        /* Reset delink mode */
 956        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
 957        /* Card driving select */
 958        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
 959                        0x07, DRIVER_TYPE_D);
 960        /* Enable SSC Clock */
 961        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
 962                        0xFF, SSC_8X_EN | SSC_SEL_4M);
 963        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
 964        /* Disable cd_pwr_save */
 965        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
 966        /* Clear Link Ready Interrupt */
 967        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 968                        LINK_RDY_INT, LINK_RDY_INT);
 969        /* Enlarge the estimation window of PERST# glitch
 970         * to reduce the chance of invalid card interrupt
 971         */
 972        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
 973        /* Update RC oscillator to 400k
 974         * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
 975         *                1: 2M  0: 400k
 976         */
 977        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
 978        /* Set interrupt write clear
 979         * bit 1: U_elbi_if_rd_clr_en
 980         *      1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
 981         *      0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
 982         */
 983        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
 984        /* Force CLKREQ# PIN to drive 0 to request clock */
 985        rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
 986
 987        err = rtsx_pci_send_cmd(pcr, 100);
 988        if (err < 0)
 989                return err;
 990
 991        /* Enable clk_request_n to enable clock power management */
 992        rtsx_pci_write_config_byte(pcr, 0x81, 1);
 993        /* Enter L1 when host tx idle */
 994        rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
 995
 996        if (pcr->ops->extra_init_hw) {
 997                err = pcr->ops->extra_init_hw(pcr);
 998                if (err < 0)
 999                        return err;
1000        }
1001
1002        /* No CD interrupt if probing driver with card inserted.
1003         * So we need to initialize pcr->card_exist here.
1004         */
1005        if (pcr->ops->cd_deglitch)
1006                pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1007        else
1008                pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1009
1010        return 0;
1011}
1012
1013static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1014{
1015        int err;
1016
1017        spin_lock_init(&pcr->lock);
1018        mutex_init(&pcr->pcr_mutex);
1019
1020        switch (PCI_PID(pcr)) {
1021        default:
1022        case 0x5209:
1023                rts5209_init_params(pcr);
1024                break;
1025
1026        case 0x5229:
1027                rts5229_init_params(pcr);
1028                break;
1029
1030        case 0x5289:
1031                rtl8411_init_params(pcr);
1032                break;
1033
1034        case 0x5227:
1035                rts5227_init_params(pcr);
1036                break;
1037
1038        case 0x5249:
1039                rts5249_init_params(pcr);
1040                break;
1041        }
1042
1043        dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n",
1044                        PCI_PID(pcr), pcr->ic_version);
1045
1046        pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1047                        GFP_KERNEL);
1048        if (!pcr->slots)
1049                return -ENOMEM;
1050
1051        pcr->state = PDEV_STAT_IDLE;
1052        err = rtsx_pci_init_hw(pcr);
1053        if (err < 0) {
1054                kfree(pcr->slots);
1055                return err;
1056        }
1057
1058        return 0;
1059}
1060
1061static int rtsx_pci_probe(struct pci_dev *pcidev,
1062                          const struct pci_device_id *id)
1063{
1064        struct rtsx_pcr *pcr;
1065        struct pcr_handle *handle;
1066        u32 base, len;
1067        int ret, i;
1068
1069        dev_dbg(&(pcidev->dev),
1070                ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1071                pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1072                (int)pcidev->revision);
1073
1074        ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
1075        if (ret < 0)
1076                return ret;
1077
1078        ret = pci_enable_device(pcidev);
1079        if (ret)
1080                return ret;
1081
1082        ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1083        if (ret)
1084                goto disable;
1085
1086        pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1087        if (!pcr) {
1088                ret = -ENOMEM;
1089                goto release_pci;
1090        }
1091
1092        handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1093        if (!handle) {
1094                ret = -ENOMEM;
1095                goto free_pcr;
1096        }
1097        handle->pcr = pcr;
1098
1099        idr_preload(GFP_KERNEL);
1100        spin_lock(&rtsx_pci_lock);
1101        ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
1102        if (ret >= 0)
1103                pcr->id = ret;
1104        spin_unlock(&rtsx_pci_lock);
1105        idr_preload_end();
1106        if (ret < 0)
1107                goto free_handle;
1108
1109        pcr->pci = pcidev;
1110        dev_set_drvdata(&pcidev->dev, handle);
1111
1112        len = pci_resource_len(pcidev, 0);
1113        base = pci_resource_start(pcidev, 0);
1114        pcr->remap_addr = ioremap_nocache(base, len);
1115        if (!pcr->remap_addr) {
1116                ret = -ENOMEM;
1117                goto free_host;
1118        }
1119
1120        pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1121                        RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1122                        GFP_KERNEL);
1123        if (pcr->rtsx_resv_buf == NULL) {
1124                ret = -ENXIO;
1125                goto unmap;
1126        }
1127        pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1128        pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1129        pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1130        pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1131
1132        pcr->card_inserted = 0;
1133        pcr->card_removed = 0;
1134        INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1135        INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1136
1137        pcr->msi_en = msi_en;
1138        if (pcr->msi_en) {
1139                ret = pci_enable_msi(pcidev);
1140                if (ret < 0)
1141                        pcr->msi_en = false;
1142        }
1143
1144        ret = rtsx_pci_acquire_irq(pcr);
1145        if (ret < 0)
1146                goto disable_msi;
1147
1148        pci_set_master(pcidev);
1149        synchronize_irq(pcr->irq);
1150
1151        ret = rtsx_pci_init_chip(pcr);
1152        if (ret < 0)
1153                goto disable_irq;
1154
1155        for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1156                rtsx_pcr_cells[i].platform_data = handle;
1157                rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1158        }
1159        ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1160                        ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1161        if (ret < 0)
1162                goto disable_irq;
1163
1164        schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1165
1166        return 0;
1167
1168disable_irq:
1169        free_irq(pcr->irq, (void *)pcr);
1170disable_msi:
1171        if (pcr->msi_en)
1172                pci_disable_msi(pcr->pci);
1173        dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1174                        pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1175unmap:
1176        iounmap(pcr->remap_addr);
1177free_host:
1178        dev_set_drvdata(&pcidev->dev, NULL);
1179free_handle:
1180        kfree(handle);
1181free_pcr:
1182        kfree(pcr);
1183release_pci:
1184        pci_release_regions(pcidev);
1185disable:
1186        pci_disable_device(pcidev);
1187
1188        return ret;
1189}
1190
1191static void rtsx_pci_remove(struct pci_dev *pcidev)
1192{
1193        struct pcr_handle *handle = pci_get_drvdata(pcidev);
1194        struct rtsx_pcr *pcr = handle->pcr;
1195
1196        pcr->remove_pci = true;
1197
1198        cancel_delayed_work(&pcr->carddet_work);
1199        cancel_delayed_work(&pcr->idle_work);
1200
1201        mfd_remove_devices(&pcidev->dev);
1202
1203        dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1204                        pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1205        free_irq(pcr->irq, (void *)pcr);
1206        if (pcr->msi_en)
1207                pci_disable_msi(pcr->pci);
1208        iounmap(pcr->remap_addr);
1209
1210        dev_set_drvdata(&pcidev->dev, NULL);
1211        pci_release_regions(pcidev);
1212        pci_disable_device(pcidev);
1213
1214        spin_lock(&rtsx_pci_lock);
1215        idr_remove(&rtsx_pci_idr, pcr->id);
1216        spin_unlock(&rtsx_pci_lock);
1217
1218        kfree(pcr->slots);
1219        kfree(pcr);
1220        kfree(handle);
1221
1222        dev_dbg(&(pcidev->dev),
1223                ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1224                pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1225}
1226
1227#ifdef CONFIG_PM
1228
1229static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1230{
1231        struct pcr_handle *handle;
1232        struct rtsx_pcr *pcr;
1233        int ret = 0;
1234
1235        dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1236
1237        handle = pci_get_drvdata(pcidev);
1238        pcr = handle->pcr;
1239
1240        cancel_delayed_work(&pcr->carddet_work);
1241        cancel_delayed_work(&pcr->idle_work);
1242
1243        mutex_lock(&pcr->pcr_mutex);
1244
1245        if (pcr->ops->turn_off_led)
1246                pcr->ops->turn_off_led(pcr);
1247
1248        rtsx_pci_writel(pcr, RTSX_BIER, 0);
1249        pcr->bier = 0;
1250
1251        rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
1252        rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x02);
1253
1254        pci_save_state(pcidev);
1255        pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1256        pci_disable_device(pcidev);
1257        pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1258
1259        mutex_unlock(&pcr->pcr_mutex);
1260        return ret;
1261}
1262
1263static int rtsx_pci_resume(struct pci_dev *pcidev)
1264{
1265        struct pcr_handle *handle;
1266        struct rtsx_pcr *pcr;
1267        int ret = 0;
1268
1269        dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1270
1271        handle = pci_get_drvdata(pcidev);
1272        pcr = handle->pcr;
1273
1274        mutex_lock(&pcr->pcr_mutex);
1275
1276        pci_set_power_state(pcidev, PCI_D0);
1277        pci_restore_state(pcidev);
1278        ret = pci_enable_device(pcidev);
1279        if (ret)
1280                goto out;
1281        pci_set_master(pcidev);
1282
1283        ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1284        if (ret)
1285                goto out;
1286
1287        ret = rtsx_pci_init_hw(pcr);
1288        if (ret)
1289                goto out;
1290
1291        schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1292
1293out:
1294        mutex_unlock(&pcr->pcr_mutex);
1295        return ret;
1296}
1297
1298#else /* CONFIG_PM */
1299
1300#define rtsx_pci_suspend NULL
1301#define rtsx_pci_resume NULL
1302
1303#endif /* CONFIG_PM */
1304
1305static struct pci_driver rtsx_pci_driver = {
1306        .name = DRV_NAME_RTSX_PCI,
1307        .id_table = rtsx_pci_ids,
1308        .probe = rtsx_pci_probe,
1309        .remove = rtsx_pci_remove,
1310        .suspend = rtsx_pci_suspend,
1311        .resume = rtsx_pci_resume,
1312};
1313module_pci_driver(rtsx_pci_driver);
1314
1315MODULE_LICENSE("GPL");
1316MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1317MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");
1318
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