linux/drivers/mfd/db8500-prcmu.c
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   1/*
   2 * Copyright (C) STMicroelectronics 2009
   3 * Copyright (C) ST-Ericsson SA 2010
   4 *
   5 * License Terms: GNU General Public License v2
   6 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
   7 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
   8 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
   9 *
  10 * U8500 PRCM Unit interface driver
  11 *
  12 */
  13#include <linux/module.h>
  14#include <linux/kernel.h>
  15#include <linux/delay.h>
  16#include <linux/errno.h>
  17#include <linux/err.h>
  18#include <linux/spinlock.h>
  19#include <linux/io.h>
  20#include <linux/slab.h>
  21#include <linux/mutex.h>
  22#include <linux/completion.h>
  23#include <linux/irq.h>
  24#include <linux/jiffies.h>
  25#include <linux/bitops.h>
  26#include <linux/fs.h>
  27#include <linux/of.h>
  28#include <linux/platform_device.h>
  29#include <linux/uaccess.h>
  30#include <linux/mfd/core.h>
  31#include <linux/mfd/dbx500-prcmu.h>
  32#include <linux/mfd/abx500/ab8500.h>
  33#include <linux/regulator/db8500-prcmu.h>
  34#include <linux/regulator/machine.h>
  35#include <linux/cpufreq.h>
  36#include <linux/platform_data/ux500_wdt.h>
  37#include <linux/platform_data/db8500_thermal.h>
  38#include "dbx500-prcmu-regs.h"
  39
  40/* Index of different voltages to be used when accessing AVSData */
  41#define PRCM_AVS_BASE           0x2FC
  42#define PRCM_AVS_VBB_RET        (PRCM_AVS_BASE + 0x0)
  43#define PRCM_AVS_VBB_MAX_OPP    (PRCM_AVS_BASE + 0x1)
  44#define PRCM_AVS_VBB_100_OPP    (PRCM_AVS_BASE + 0x2)
  45#define PRCM_AVS_VBB_50_OPP     (PRCM_AVS_BASE + 0x3)
  46#define PRCM_AVS_VARM_MAX_OPP   (PRCM_AVS_BASE + 0x4)
  47#define PRCM_AVS_VARM_100_OPP   (PRCM_AVS_BASE + 0x5)
  48#define PRCM_AVS_VARM_50_OPP    (PRCM_AVS_BASE + 0x6)
  49#define PRCM_AVS_VARM_RET       (PRCM_AVS_BASE + 0x7)
  50#define PRCM_AVS_VAPE_100_OPP   (PRCM_AVS_BASE + 0x8)
  51#define PRCM_AVS_VAPE_50_OPP    (PRCM_AVS_BASE + 0x9)
  52#define PRCM_AVS_VMOD_100_OPP   (PRCM_AVS_BASE + 0xA)
  53#define PRCM_AVS_VMOD_50_OPP    (PRCM_AVS_BASE + 0xB)
  54#define PRCM_AVS_VSAFE          (PRCM_AVS_BASE + 0xC)
  55
  56#define PRCM_AVS_VOLTAGE                0
  57#define PRCM_AVS_VOLTAGE_MASK           0x3f
  58#define PRCM_AVS_ISSLOWSTARTUP          6
  59#define PRCM_AVS_ISSLOWSTARTUP_MASK     (1 << PRCM_AVS_ISSLOWSTARTUP)
  60#define PRCM_AVS_ISMODEENABLE           7
  61#define PRCM_AVS_ISMODEENABLE_MASK      (1 << PRCM_AVS_ISMODEENABLE)
  62
  63#define PRCM_BOOT_STATUS        0xFFF
  64#define PRCM_ROMCODE_A2P        0xFFE
  65#define PRCM_ROMCODE_P2A        0xFFD
  66#define PRCM_XP70_CUR_PWR_STATE 0xFFC      /* 4 BYTES */
  67
  68#define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
  69
  70#define _PRCM_MBOX_HEADER               0xFE8 /* 16 bytes */
  71#define PRCM_MBOX_HEADER_REQ_MB0        (_PRCM_MBOX_HEADER + 0x0)
  72#define PRCM_MBOX_HEADER_REQ_MB1        (_PRCM_MBOX_HEADER + 0x1)
  73#define PRCM_MBOX_HEADER_REQ_MB2        (_PRCM_MBOX_HEADER + 0x2)
  74#define PRCM_MBOX_HEADER_REQ_MB3        (_PRCM_MBOX_HEADER + 0x3)
  75#define PRCM_MBOX_HEADER_REQ_MB4        (_PRCM_MBOX_HEADER + 0x4)
  76#define PRCM_MBOX_HEADER_REQ_MB5        (_PRCM_MBOX_HEADER + 0x5)
  77#define PRCM_MBOX_HEADER_ACK_MB0        (_PRCM_MBOX_HEADER + 0x8)
  78
  79/* Req Mailboxes */
  80#define PRCM_REQ_MB0 0xFDC /* 12 bytes  */
  81#define PRCM_REQ_MB1 0xFD0 /* 12 bytes  */
  82#define PRCM_REQ_MB2 0xFC0 /* 16 bytes  */
  83#define PRCM_REQ_MB3 0xE4C /* 372 bytes  */
  84#define PRCM_REQ_MB4 0xE48 /* 4 bytes  */
  85#define PRCM_REQ_MB5 0xE44 /* 4 bytes  */
  86
  87/* Ack Mailboxes */
  88#define PRCM_ACK_MB0 0xE08 /* 52 bytes  */
  89#define PRCM_ACK_MB1 0xE04 /* 4 bytes */
  90#define PRCM_ACK_MB2 0xE00 /* 4 bytes */
  91#define PRCM_ACK_MB3 0xDFC /* 4 bytes */
  92#define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
  93#define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
  94
  95/* Mailbox 0 headers */
  96#define MB0H_POWER_STATE_TRANS          0
  97#define MB0H_CONFIG_WAKEUPS_EXE         1
  98#define MB0H_READ_WAKEUP_ACK            3
  99#define MB0H_CONFIG_WAKEUPS_SLEEP       4
 100
 101#define MB0H_WAKEUP_EXE 2
 102#define MB0H_WAKEUP_SLEEP 5
 103
 104/* Mailbox 0 REQs */
 105#define PRCM_REQ_MB0_AP_POWER_STATE     (PRCM_REQ_MB0 + 0x0)
 106#define PRCM_REQ_MB0_AP_PLL_STATE       (PRCM_REQ_MB0 + 0x1)
 107#define PRCM_REQ_MB0_ULP_CLOCK_STATE    (PRCM_REQ_MB0 + 0x2)
 108#define PRCM_REQ_MB0_DO_NOT_WFI         (PRCM_REQ_MB0 + 0x3)
 109#define PRCM_REQ_MB0_WAKEUP_8500        (PRCM_REQ_MB0 + 0x4)
 110#define PRCM_REQ_MB0_WAKEUP_4500        (PRCM_REQ_MB0 + 0x8)
 111
 112/* Mailbox 0 ACKs */
 113#define PRCM_ACK_MB0_AP_PWRSTTR_STATUS  (PRCM_ACK_MB0 + 0x0)
 114#define PRCM_ACK_MB0_READ_POINTER       (PRCM_ACK_MB0 + 0x1)
 115#define PRCM_ACK_MB0_WAKEUP_0_8500      (PRCM_ACK_MB0 + 0x4)
 116#define PRCM_ACK_MB0_WAKEUP_0_4500      (PRCM_ACK_MB0 + 0x8)
 117#define PRCM_ACK_MB0_WAKEUP_1_8500      (PRCM_ACK_MB0 + 0x1C)
 118#define PRCM_ACK_MB0_WAKEUP_1_4500      (PRCM_ACK_MB0 + 0x20)
 119#define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
 120
 121/* Mailbox 1 headers */
 122#define MB1H_ARM_APE_OPP 0x0
 123#define MB1H_RESET_MODEM 0x2
 124#define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
 125#define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
 126#define MB1H_RELEASE_USB_WAKEUP 0x5
 127#define MB1H_PLL_ON_OFF 0x6
 128
 129/* Mailbox 1 Requests */
 130#define PRCM_REQ_MB1_ARM_OPP                    (PRCM_REQ_MB1 + 0x0)
 131#define PRCM_REQ_MB1_APE_OPP                    (PRCM_REQ_MB1 + 0x1)
 132#define PRCM_REQ_MB1_PLL_ON_OFF                 (PRCM_REQ_MB1 + 0x4)
 133#define PLL_SOC0_OFF    0x1
 134#define PLL_SOC0_ON     0x2
 135#define PLL_SOC1_OFF    0x4
 136#define PLL_SOC1_ON     0x8
 137
 138/* Mailbox 1 ACKs */
 139#define PRCM_ACK_MB1_CURRENT_ARM_OPP    (PRCM_ACK_MB1 + 0x0)
 140#define PRCM_ACK_MB1_CURRENT_APE_OPP    (PRCM_ACK_MB1 + 0x1)
 141#define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
 142#define PRCM_ACK_MB1_DVFS_STATUS        (PRCM_ACK_MB1 + 0x3)
 143
 144/* Mailbox 2 headers */
 145#define MB2H_DPS        0x0
 146#define MB2H_AUTO_PWR   0x1
 147
 148/* Mailbox 2 REQs */
 149#define PRCM_REQ_MB2_SVA_MMDSP          (PRCM_REQ_MB2 + 0x0)
 150#define PRCM_REQ_MB2_SVA_PIPE           (PRCM_REQ_MB2 + 0x1)
 151#define PRCM_REQ_MB2_SIA_MMDSP          (PRCM_REQ_MB2 + 0x2)
 152#define PRCM_REQ_MB2_SIA_PIPE           (PRCM_REQ_MB2 + 0x3)
 153#define PRCM_REQ_MB2_SGA                (PRCM_REQ_MB2 + 0x4)
 154#define PRCM_REQ_MB2_B2R2_MCDE          (PRCM_REQ_MB2 + 0x5)
 155#define PRCM_REQ_MB2_ESRAM12            (PRCM_REQ_MB2 + 0x6)
 156#define PRCM_REQ_MB2_ESRAM34            (PRCM_REQ_MB2 + 0x7)
 157#define PRCM_REQ_MB2_AUTO_PM_SLEEP      (PRCM_REQ_MB2 + 0x8)
 158#define PRCM_REQ_MB2_AUTO_PM_IDLE       (PRCM_REQ_MB2 + 0xC)
 159
 160/* Mailbox 2 ACKs */
 161#define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
 162#define HWACC_PWR_ST_OK 0xFE
 163
 164/* Mailbox 3 headers */
 165#define MB3H_ANC        0x0
 166#define MB3H_SIDETONE   0x1
 167#define MB3H_SYSCLK     0xE
 168
 169/* Mailbox 3 Requests */
 170#define PRCM_REQ_MB3_ANC_FIR_COEFF      (PRCM_REQ_MB3 + 0x0)
 171#define PRCM_REQ_MB3_ANC_IIR_COEFF      (PRCM_REQ_MB3 + 0x20)
 172#define PRCM_REQ_MB3_ANC_SHIFTER        (PRCM_REQ_MB3 + 0x60)
 173#define PRCM_REQ_MB3_ANC_WARP           (PRCM_REQ_MB3 + 0x64)
 174#define PRCM_REQ_MB3_SIDETONE_FIR_GAIN  (PRCM_REQ_MB3 + 0x68)
 175#define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
 176#define PRCM_REQ_MB3_SYSCLK_MGT         (PRCM_REQ_MB3 + 0x16C)
 177
 178/* Mailbox 4 headers */
 179#define MB4H_DDR_INIT   0x0
 180#define MB4H_MEM_ST     0x1
 181#define MB4H_HOTDOG     0x12
 182#define MB4H_HOTMON     0x13
 183#define MB4H_HOT_PERIOD 0x14
 184#define MB4H_A9WDOG_CONF 0x16
 185#define MB4H_A9WDOG_EN   0x17
 186#define MB4H_A9WDOG_DIS  0x18
 187#define MB4H_A9WDOG_LOAD 0x19
 188#define MB4H_A9WDOG_KICK 0x20
 189
 190/* Mailbox 4 Requests */
 191#define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE       (PRCM_REQ_MB4 + 0x0)
 192#define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE        (PRCM_REQ_MB4 + 0x1)
 193#define PRCM_REQ_MB4_ESRAM0_ST                  (PRCM_REQ_MB4 + 0x3)
 194#define PRCM_REQ_MB4_HOTDOG_THRESHOLD           (PRCM_REQ_MB4 + 0x0)
 195#define PRCM_REQ_MB4_HOTMON_LOW                 (PRCM_REQ_MB4 + 0x0)
 196#define PRCM_REQ_MB4_HOTMON_HIGH                (PRCM_REQ_MB4 + 0x1)
 197#define PRCM_REQ_MB4_HOTMON_CONFIG              (PRCM_REQ_MB4 + 0x2)
 198#define PRCM_REQ_MB4_HOT_PERIOD                 (PRCM_REQ_MB4 + 0x0)
 199#define HOTMON_CONFIG_LOW                       BIT(0)
 200#define HOTMON_CONFIG_HIGH                      BIT(1)
 201#define PRCM_REQ_MB4_A9WDOG_0                   (PRCM_REQ_MB4 + 0x0)
 202#define PRCM_REQ_MB4_A9WDOG_1                   (PRCM_REQ_MB4 + 0x1)
 203#define PRCM_REQ_MB4_A9WDOG_2                   (PRCM_REQ_MB4 + 0x2)
 204#define PRCM_REQ_MB4_A9WDOG_3                   (PRCM_REQ_MB4 + 0x3)
 205#define A9WDOG_AUTO_OFF_EN                      BIT(7)
 206#define A9WDOG_AUTO_OFF_DIS                     0
 207#define A9WDOG_ID_MASK                          0xf
 208
 209/* Mailbox 5 Requests */
 210#define PRCM_REQ_MB5_I2C_SLAVE_OP       (PRCM_REQ_MB5 + 0x0)
 211#define PRCM_REQ_MB5_I2C_HW_BITS        (PRCM_REQ_MB5 + 0x1)
 212#define PRCM_REQ_MB5_I2C_REG            (PRCM_REQ_MB5 + 0x2)
 213#define PRCM_REQ_MB5_I2C_VAL            (PRCM_REQ_MB5 + 0x3)
 214#define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
 215#define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
 216#define PRCMU_I2C_STOP_EN               BIT(3)
 217
 218/* Mailbox 5 ACKs */
 219#define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
 220#define PRCM_ACK_MB5_I2C_VAL    (PRCM_ACK_MB5 + 0x3)
 221#define I2C_WR_OK 0x1
 222#define I2C_RD_OK 0x2
 223
 224#define NUM_MB 8
 225#define MBOX_BIT BIT
 226#define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
 227
 228/*
 229 * Wakeups/IRQs
 230 */
 231
 232#define WAKEUP_BIT_RTC BIT(0)
 233#define WAKEUP_BIT_RTT0 BIT(1)
 234#define WAKEUP_BIT_RTT1 BIT(2)
 235#define WAKEUP_BIT_HSI0 BIT(3)
 236#define WAKEUP_BIT_HSI1 BIT(4)
 237#define WAKEUP_BIT_CA_WAKE BIT(5)
 238#define WAKEUP_BIT_USB BIT(6)
 239#define WAKEUP_BIT_ABB BIT(7)
 240#define WAKEUP_BIT_ABB_FIFO BIT(8)
 241#define WAKEUP_BIT_SYSCLK_OK BIT(9)
 242#define WAKEUP_BIT_CA_SLEEP BIT(10)
 243#define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
 244#define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
 245#define WAKEUP_BIT_ANC_OK BIT(13)
 246#define WAKEUP_BIT_SW_ERROR BIT(14)
 247#define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
 248#define WAKEUP_BIT_ARM BIT(17)
 249#define WAKEUP_BIT_HOTMON_LOW BIT(18)
 250#define WAKEUP_BIT_HOTMON_HIGH BIT(19)
 251#define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
 252#define WAKEUP_BIT_GPIO0 BIT(23)
 253#define WAKEUP_BIT_GPIO1 BIT(24)
 254#define WAKEUP_BIT_GPIO2 BIT(25)
 255#define WAKEUP_BIT_GPIO3 BIT(26)
 256#define WAKEUP_BIT_GPIO4 BIT(27)
 257#define WAKEUP_BIT_GPIO5 BIT(28)
 258#define WAKEUP_BIT_GPIO6 BIT(29)
 259#define WAKEUP_BIT_GPIO7 BIT(30)
 260#define WAKEUP_BIT_GPIO8 BIT(31)
 261
 262static struct {
 263        bool valid;
 264        struct prcmu_fw_version version;
 265} fw_info;
 266
 267static struct irq_domain *db8500_irq_domain;
 268
 269/*
 270 * This vector maps irq numbers to the bits in the bit field used in
 271 * communication with the PRCMU firmware.
 272 *
 273 * The reason for having this is to keep the irq numbers contiguous even though
 274 * the bits in the bit field are not. (The bits also have a tendency to move
 275 * around, to further complicate matters.)
 276 */
 277#define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name))
 278#define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
 279
 280#define IRQ_PRCMU_RTC 0
 281#define IRQ_PRCMU_RTT0 1
 282#define IRQ_PRCMU_RTT1 2
 283#define IRQ_PRCMU_HSI0 3
 284#define IRQ_PRCMU_HSI1 4
 285#define IRQ_PRCMU_CA_WAKE 5
 286#define IRQ_PRCMU_USB 6
 287#define IRQ_PRCMU_ABB 7
 288#define IRQ_PRCMU_ABB_FIFO 8
 289#define IRQ_PRCMU_ARM 9
 290#define IRQ_PRCMU_MODEM_SW_RESET_REQ 10
 291#define IRQ_PRCMU_GPIO0 11
 292#define IRQ_PRCMU_GPIO1 12
 293#define IRQ_PRCMU_GPIO2 13
 294#define IRQ_PRCMU_GPIO3 14
 295#define IRQ_PRCMU_GPIO4 15
 296#define IRQ_PRCMU_GPIO5 16
 297#define IRQ_PRCMU_GPIO6 17
 298#define IRQ_PRCMU_GPIO7 18
 299#define IRQ_PRCMU_GPIO8 19
 300#define IRQ_PRCMU_CA_SLEEP 20
 301#define IRQ_PRCMU_HOTMON_LOW 21
 302#define IRQ_PRCMU_HOTMON_HIGH 22
 303#define NUM_PRCMU_WAKEUPS 23
 304
 305static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
 306        IRQ_ENTRY(RTC),
 307        IRQ_ENTRY(RTT0),
 308        IRQ_ENTRY(RTT1),
 309        IRQ_ENTRY(HSI0),
 310        IRQ_ENTRY(HSI1),
 311        IRQ_ENTRY(CA_WAKE),
 312        IRQ_ENTRY(USB),
 313        IRQ_ENTRY(ABB),
 314        IRQ_ENTRY(ABB_FIFO),
 315        IRQ_ENTRY(CA_SLEEP),
 316        IRQ_ENTRY(ARM),
 317        IRQ_ENTRY(HOTMON_LOW),
 318        IRQ_ENTRY(HOTMON_HIGH),
 319        IRQ_ENTRY(MODEM_SW_RESET_REQ),
 320        IRQ_ENTRY(GPIO0),
 321        IRQ_ENTRY(GPIO1),
 322        IRQ_ENTRY(GPIO2),
 323        IRQ_ENTRY(GPIO3),
 324        IRQ_ENTRY(GPIO4),
 325        IRQ_ENTRY(GPIO5),
 326        IRQ_ENTRY(GPIO6),
 327        IRQ_ENTRY(GPIO7),
 328        IRQ_ENTRY(GPIO8)
 329};
 330
 331#define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
 332#define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
 333static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
 334        WAKEUP_ENTRY(RTC),
 335        WAKEUP_ENTRY(RTT0),
 336        WAKEUP_ENTRY(RTT1),
 337        WAKEUP_ENTRY(HSI0),
 338        WAKEUP_ENTRY(HSI1),
 339        WAKEUP_ENTRY(USB),
 340        WAKEUP_ENTRY(ABB),
 341        WAKEUP_ENTRY(ABB_FIFO),
 342        WAKEUP_ENTRY(ARM)
 343};
 344
 345/*
 346 * mb0_transfer - state needed for mailbox 0 communication.
 347 * @lock:               The transaction lock.
 348 * @dbb_events_lock:    A lock used to handle concurrent access to (parts of)
 349 *                      the request data.
 350 * @mask_work:          Work structure used for (un)masking wakeup interrupts.
 351 * @req:                Request data that need to persist between requests.
 352 */
 353static struct {
 354        spinlock_t lock;
 355        spinlock_t dbb_irqs_lock;
 356        struct work_struct mask_work;
 357        struct mutex ac_wake_lock;
 358        struct completion ac_wake_work;
 359        struct {
 360                u32 dbb_irqs;
 361                u32 dbb_wakeups;
 362                u32 abb_events;
 363        } req;
 364} mb0_transfer;
 365
 366/*
 367 * mb1_transfer - state needed for mailbox 1 communication.
 368 * @lock:       The transaction lock.
 369 * @work:       The transaction completion structure.
 370 * @ape_opp:    The current APE OPP.
 371 * @ack:        Reply ("acknowledge") data.
 372 */
 373static struct {
 374        struct mutex lock;
 375        struct completion work;
 376        u8 ape_opp;
 377        struct {
 378                u8 header;
 379                u8 arm_opp;
 380                u8 ape_opp;
 381                u8 ape_voltage_status;
 382        } ack;
 383} mb1_transfer;
 384
 385/*
 386 * mb2_transfer - state needed for mailbox 2 communication.
 387 * @lock:            The transaction lock.
 388 * @work:            The transaction completion structure.
 389 * @auto_pm_lock:    The autonomous power management configuration lock.
 390 * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
 391 * @req:             Request data that need to persist between requests.
 392 * @ack:             Reply ("acknowledge") data.
 393 */
 394static struct {
 395        struct mutex lock;
 396        struct completion work;
 397        spinlock_t auto_pm_lock;
 398        bool auto_pm_enabled;
 399        struct {
 400                u8 status;
 401        } ack;
 402} mb2_transfer;
 403
 404/*
 405 * mb3_transfer - state needed for mailbox 3 communication.
 406 * @lock:               The request lock.
 407 * @sysclk_lock:        A lock used to handle concurrent sysclk requests.
 408 * @sysclk_work:        Work structure used for sysclk requests.
 409 */
 410static struct {
 411        spinlock_t lock;
 412        struct mutex sysclk_lock;
 413        struct completion sysclk_work;
 414} mb3_transfer;
 415
 416/*
 417 * mb4_transfer - state needed for mailbox 4 communication.
 418 * @lock:       The transaction lock.
 419 * @work:       The transaction completion structure.
 420 */
 421static struct {
 422        struct mutex lock;
 423        struct completion work;
 424} mb4_transfer;
 425
 426/*
 427 * mb5_transfer - state needed for mailbox 5 communication.
 428 * @lock:       The transaction lock.
 429 * @work:       The transaction completion structure.
 430 * @ack:        Reply ("acknowledge") data.
 431 */
 432static struct {
 433        struct mutex lock;
 434        struct completion work;
 435        struct {
 436                u8 status;
 437                u8 value;
 438        } ack;
 439} mb5_transfer;
 440
 441static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
 442
 443/* Spinlocks */
 444static DEFINE_SPINLOCK(prcmu_lock);
 445static DEFINE_SPINLOCK(clkout_lock);
 446
 447/* Global var to runtime determine TCDM base for v2 or v1 */
 448static __iomem void *tcdm_base;
 449static __iomem void *prcmu_base;
 450
 451struct clk_mgt {
 452        u32 offset;
 453        u32 pllsw;
 454        int branch;
 455        bool clk38div;
 456};
 457
 458enum {
 459        PLL_RAW,
 460        PLL_FIX,
 461        PLL_DIV
 462};
 463
 464static DEFINE_SPINLOCK(clk_mgt_lock);
 465
 466#define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
 467        { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
 468struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
 469        CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
 470        CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
 471        CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
 472        CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
 473        CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
 474        CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
 475        CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
 476        CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
 477        CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
 478        CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
 479        CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
 480        CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
 481        CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
 482        CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
 483        CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
 484        CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
 485        CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
 486        CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
 487        CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
 488        CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
 489        CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
 490        CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
 491        CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
 492        CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
 493        CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
 494        CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
 495        CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
 496        CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
 497        CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
 498};
 499
 500struct dsiclk {
 501        u32 divsel_mask;
 502        u32 divsel_shift;
 503        u32 divsel;
 504};
 505
 506static struct dsiclk dsiclk[2] = {
 507        {
 508                .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
 509                .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
 510                .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
 511        },
 512        {
 513                .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
 514                .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
 515                .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
 516        }
 517};
 518
 519struct dsiescclk {
 520        u32 en;
 521        u32 div_mask;
 522        u32 div_shift;
 523};
 524
 525static struct dsiescclk dsiescclk[3] = {
 526        {
 527                .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
 528                .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
 529                .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
 530        },
 531        {
 532                .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
 533                .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
 534                .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
 535        },
 536        {
 537                .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
 538                .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
 539                .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
 540        }
 541};
 542
 543
 544/*
 545* Used by MCDE to setup all necessary PRCMU registers
 546*/
 547#define PRCMU_RESET_DSIPLL              0x00004000
 548#define PRCMU_UNCLAMP_DSIPLL            0x00400800
 549
 550#define PRCMU_CLK_PLL_DIV_SHIFT         0
 551#define PRCMU_CLK_PLL_SW_SHIFT          5
 552#define PRCMU_CLK_38                    (1 << 9)
 553#define PRCMU_CLK_38_SRC                (1 << 10)
 554#define PRCMU_CLK_38_DIV                (1 << 11)
 555
 556/* PLLDIV=12, PLLSW=4 (PLLDDR) */
 557#define PRCMU_DSI_CLOCK_SETTING         0x0000008C
 558
 559/* DPI 50000000 Hz */
 560#define PRCMU_DPI_CLOCK_SETTING         ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
 561                                          (16 << PRCMU_CLK_PLL_DIV_SHIFT))
 562#define PRCMU_DSI_LP_CLOCK_SETTING      0x00000E00
 563
 564/* D=101, N=1, R=4, SELDIV2=0 */
 565#define PRCMU_PLLDSI_FREQ_SETTING       0x00040165
 566
 567#define PRCMU_ENABLE_PLLDSI             0x00000001
 568#define PRCMU_DISABLE_PLLDSI            0x00000000
 569#define PRCMU_RELEASE_RESET_DSS         0x0000400C
 570#define PRCMU_DSI_PLLOUT_SEL_SETTING    0x00000202
 571/* ESC clk, div0=1, div1=1, div2=3 */
 572#define PRCMU_ENABLE_ESCAPE_CLOCK_DIV   0x07030101
 573#define PRCMU_DISABLE_ESCAPE_CLOCK_DIV  0x00030101
 574#define PRCMU_DSI_RESET_SW              0x00000007
 575
 576#define PRCMU_PLLDSI_LOCKP_LOCKED       0x3
 577
 578int db8500_prcmu_enable_dsipll(void)
 579{
 580        int i;
 581
 582        /* Clear DSIPLL_RESETN */
 583        writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
 584        /* Unclamp DSIPLL in/out */
 585        writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
 586
 587        /* Set DSI PLL FREQ */
 588        writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
 589        writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
 590        /* Enable Escape clocks */
 591        writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
 592
 593        /* Start DSI PLL */
 594        writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
 595        /* Reset DSI PLL */
 596        writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
 597        for (i = 0; i < 10; i++) {
 598                if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
 599                                        == PRCMU_PLLDSI_LOCKP_LOCKED)
 600                        break;
 601                udelay(100);
 602        }
 603        /* Set DSIPLL_RESETN */
 604        writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
 605        return 0;
 606}
 607
 608int db8500_prcmu_disable_dsipll(void)
 609{
 610        /* Disable dsi pll */
 611        writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
 612        /* Disable  escapeclock */
 613        writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
 614        return 0;
 615}
 616
 617int db8500_prcmu_set_display_clocks(void)
 618{
 619        unsigned long flags;
 620
 621        spin_lock_irqsave(&clk_mgt_lock, flags);
 622
 623        /* Grab the HW semaphore. */
 624        while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
 625                cpu_relax();
 626
 627        writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT);
 628        writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT);
 629        writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT);
 630
 631        /* Release the HW semaphore. */
 632        writel(0, PRCM_SEM);
 633
 634        spin_unlock_irqrestore(&clk_mgt_lock, flags);
 635
 636        return 0;
 637}
 638
 639u32 db8500_prcmu_read(unsigned int reg)
 640{
 641        return readl(prcmu_base + reg);
 642}
 643
 644void db8500_prcmu_write(unsigned int reg, u32 value)
 645{
 646        unsigned long flags;
 647
 648        spin_lock_irqsave(&prcmu_lock, flags);
 649        writel(value, (prcmu_base + reg));
 650        spin_unlock_irqrestore(&prcmu_lock, flags);
 651}
 652
 653void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
 654{
 655        u32 val;
 656        unsigned long flags;
 657
 658        spin_lock_irqsave(&prcmu_lock, flags);
 659        val = readl(prcmu_base + reg);
 660        val = ((val & ~mask) | (value & mask));
 661        writel(val, (prcmu_base + reg));
 662        spin_unlock_irqrestore(&prcmu_lock, flags);
 663}
 664
 665struct prcmu_fw_version *prcmu_get_fw_version(void)
 666{
 667        return fw_info.valid ? &fw_info.version : NULL;
 668}
 669
 670bool prcmu_has_arm_maxopp(void)
 671{
 672        return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
 673                PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
 674}
 675
 676/**
 677 * prcmu_get_boot_status - PRCMU boot status checking
 678 * Returns: the current PRCMU boot status
 679 */
 680int prcmu_get_boot_status(void)
 681{
 682        return readb(tcdm_base + PRCM_BOOT_STATUS);
 683}
 684
 685/**
 686 * prcmu_set_rc_a2p - This function is used to run few power state sequences
 687 * @val: Value to be set, i.e. transition requested
 688 * Returns: 0 on success, -EINVAL on invalid argument
 689 *
 690 * This function is used to run the following power state sequences -
 691 * any state to ApReset,  ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
 692 */
 693int prcmu_set_rc_a2p(enum romcode_write val)
 694{
 695        if (val < RDY_2_DS || val > RDY_2_XP70_RST)
 696                return -EINVAL;
 697        writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
 698        return 0;
 699}
 700
 701/**
 702 * prcmu_get_rc_p2a - This function is used to get power state sequences
 703 * Returns: the power transition that has last happened
 704 *
 705 * This function can return the following transitions-
 706 * any state to ApReset,  ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
 707 */
 708enum romcode_read prcmu_get_rc_p2a(void)
 709{
 710        return readb(tcdm_base + PRCM_ROMCODE_P2A);
 711}
 712
 713/**
 714 * prcmu_get_current_mode - Return the current XP70 power mode
 715 * Returns: Returns the current AP(ARM) power mode: init,
 716 * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
 717 */
 718enum ap_pwrst prcmu_get_xp70_current_state(void)
 719{
 720        return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
 721}
 722
 723/**
 724 * prcmu_config_clkout - Configure one of the programmable clock outputs.
 725 * @clkout:     The CLKOUT number (0 or 1).
 726 * @source:     The clock to be used (one of the PRCMU_CLKSRC_*).
 727 * @div:        The divider to be applied.
 728 *
 729 * Configures one of the programmable clock outputs (CLKOUTs).
 730 * @div should be in the range [1,63] to request a configuration, or 0 to
 731 * inform that the configuration is no longer requested.
 732 */
 733int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
 734{
 735        static int requests[2];
 736        int r = 0;
 737        unsigned long flags;
 738        u32 val;
 739        u32 bits;
 740        u32 mask;
 741        u32 div_mask;
 742
 743        BUG_ON(clkout > 1);
 744        BUG_ON(div > 63);
 745        BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
 746
 747        if (!div && !requests[clkout])
 748                return -EINVAL;
 749
 750        switch (clkout) {
 751        case 0:
 752                div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
 753                mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
 754                bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
 755                        (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
 756                break;
 757        case 1:
 758                div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
 759                mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
 760                        PRCM_CLKOCR_CLK1TYPE);
 761                bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
 762                        (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
 763                break;
 764        }
 765        bits &= mask;
 766
 767        spin_lock_irqsave(&clkout_lock, flags);
 768
 769        val = readl(PRCM_CLKOCR);
 770        if (val & div_mask) {
 771                if (div) {
 772                        if ((val & mask) != bits) {
 773                                r = -EBUSY;
 774                                goto unlock_and_return;
 775                        }
 776                } else {
 777                        if ((val & mask & ~div_mask) != bits) {
 778                                r = -EINVAL;
 779                                goto unlock_and_return;
 780                        }
 781                }
 782        }
 783        writel((bits | (val & ~mask)), PRCM_CLKOCR);
 784        requests[clkout] += (div ? 1 : -1);
 785
 786unlock_and_return:
 787        spin_unlock_irqrestore(&clkout_lock, flags);
 788
 789        return r;
 790}
 791
 792int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
 793{
 794        unsigned long flags;
 795
 796        BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
 797
 798        spin_lock_irqsave(&mb0_transfer.lock, flags);
 799
 800        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
 801                cpu_relax();
 802
 803        writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
 804        writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
 805        writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
 806        writeb((keep_ulp_clk ? 1 : 0),
 807                (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
 808        writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
 809        writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
 810
 811        spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 812
 813        return 0;
 814}
 815
 816u8 db8500_prcmu_get_power_state_result(void)
 817{
 818        return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
 819}
 820
 821/* This function should only be called while mb0_transfer.lock is held. */
 822static void config_wakeups(void)
 823{
 824        const u8 header[2] = {
 825                MB0H_CONFIG_WAKEUPS_EXE,
 826                MB0H_CONFIG_WAKEUPS_SLEEP
 827        };
 828        static u32 last_dbb_events;
 829        static u32 last_abb_events;
 830        u32 dbb_events;
 831        u32 abb_events;
 832        unsigned int i;
 833
 834        dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
 835        dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
 836
 837        abb_events = mb0_transfer.req.abb_events;
 838
 839        if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
 840                return;
 841
 842        for (i = 0; i < 2; i++) {
 843                while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
 844                        cpu_relax();
 845                writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
 846                writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
 847                writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
 848                writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
 849        }
 850        last_dbb_events = dbb_events;
 851        last_abb_events = abb_events;
 852}
 853
 854void db8500_prcmu_enable_wakeups(u32 wakeups)
 855{
 856        unsigned long flags;
 857        u32 bits;
 858        int i;
 859
 860        BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
 861
 862        for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
 863                if (wakeups & BIT(i))
 864                        bits |= prcmu_wakeup_bit[i];
 865        }
 866
 867        spin_lock_irqsave(&mb0_transfer.lock, flags);
 868
 869        mb0_transfer.req.dbb_wakeups = bits;
 870        config_wakeups();
 871
 872        spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 873}
 874
 875void db8500_prcmu_config_abb_event_readout(u32 abb_events)
 876{
 877        unsigned long flags;
 878
 879        spin_lock_irqsave(&mb0_transfer.lock, flags);
 880
 881        mb0_transfer.req.abb_events = abb_events;
 882        config_wakeups();
 883
 884        spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 885}
 886
 887void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
 888{
 889        if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
 890                *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
 891        else
 892                *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
 893}
 894
 895/**
 896 * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
 897 * @opp: The new ARM operating point to which transition is to be made
 898 * Returns: 0 on success, non-zero on failure
 899 *
 900 * This function sets the the operating point of the ARM.
 901 */
 902int db8500_prcmu_set_arm_opp(u8 opp)
 903{
 904        int r;
 905
 906        if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
 907                return -EINVAL;
 908
 909        r = 0;
 910
 911        mutex_lock(&mb1_transfer.lock);
 912
 913        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
 914                cpu_relax();
 915
 916        writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
 917        writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
 918        writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
 919
 920        writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
 921        wait_for_completion(&mb1_transfer.work);
 922
 923        if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
 924                (mb1_transfer.ack.arm_opp != opp))
 925                r = -EIO;
 926
 927        mutex_unlock(&mb1_transfer.lock);
 928
 929        return r;
 930}
 931
 932/**
 933 * db8500_prcmu_get_arm_opp - get the current ARM OPP
 934 *
 935 * Returns: the current ARM OPP
 936 */
 937int db8500_prcmu_get_arm_opp(void)
 938{
 939        return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
 940}
 941
 942/**
 943 * db8500_prcmu_get_ddr_opp - get the current DDR OPP
 944 *
 945 * Returns: the current DDR OPP
 946 */
 947int db8500_prcmu_get_ddr_opp(void)
 948{
 949        return readb(PRCM_DDR_SUBSYS_APE_MINBW);
 950}
 951
 952/**
 953 * db8500_set_ddr_opp - set the appropriate DDR OPP
 954 * @opp: The new DDR operating point to which transition is to be made
 955 * Returns: 0 on success, non-zero on failure
 956 *
 957 * This function sets the operating point of the DDR.
 958 */
 959static bool enable_set_ddr_opp;
 960int db8500_prcmu_set_ddr_opp(u8 opp)
 961{
 962        if (opp < DDR_100_OPP || opp > DDR_25_OPP)
 963                return -EINVAL;
 964        /* Changing the DDR OPP can hang the hardware pre-v21 */
 965        if (enable_set_ddr_opp)
 966                writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);
 967
 968        return 0;
 969}
 970
 971/* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
 972static void request_even_slower_clocks(bool enable)
 973{
 974        u32 clock_reg[] = {
 975                PRCM_ACLK_MGT,
 976                PRCM_DMACLK_MGT
 977        };
 978        unsigned long flags;
 979        unsigned int i;
 980
 981        spin_lock_irqsave(&clk_mgt_lock, flags);
 982
 983        /* Grab the HW semaphore. */
 984        while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
 985                cpu_relax();
 986
 987        for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
 988                u32 val;
 989                u32 div;
 990
 991                val = readl(prcmu_base + clock_reg[i]);
 992                div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
 993                if (enable) {
 994                        if ((div <= 1) || (div > 15)) {
 995                                pr_err("prcmu: Bad clock divider %d in %s\n",
 996                                        div, __func__);
 997                                goto unlock_and_return;
 998                        }
 999                        div <<= 1;
1000                } else {
1001                        if (div <= 2)
1002                                goto unlock_and_return;
1003                        div >>= 1;
1004                }
1005                val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
1006                        (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
1007                writel(val, prcmu_base + clock_reg[i]);
1008        }
1009
1010unlock_and_return:
1011        /* Release the HW semaphore. */
1012        writel(0, PRCM_SEM);
1013
1014        spin_unlock_irqrestore(&clk_mgt_lock, flags);
1015}
1016
1017/**
1018 * db8500_set_ape_opp - set the appropriate APE OPP
1019 * @opp: The new APE operating point to which transition is to be made
1020 * Returns: 0 on success, non-zero on failure
1021 *
1022 * This function sets the operating point of the APE.
1023 */
1024int db8500_prcmu_set_ape_opp(u8 opp)
1025{
1026        int r = 0;
1027
1028        if (opp == mb1_transfer.ape_opp)
1029                return 0;
1030
1031        mutex_lock(&mb1_transfer.lock);
1032
1033        if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
1034                request_even_slower_clocks(false);
1035
1036        if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
1037                goto skip_message;
1038
1039        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1040                cpu_relax();
1041
1042        writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1043        writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1044        writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
1045                (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1046
1047        writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1048        wait_for_completion(&mb1_transfer.work);
1049
1050        if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1051                (mb1_transfer.ack.ape_opp != opp))
1052                r = -EIO;
1053
1054skip_message:
1055        if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
1056                (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
1057                request_even_slower_clocks(true);
1058        if (!r)
1059                mb1_transfer.ape_opp = opp;
1060
1061        mutex_unlock(&mb1_transfer.lock);
1062
1063        return r;
1064}
1065
1066/**
1067 * db8500_prcmu_get_ape_opp - get the current APE OPP
1068 *
1069 * Returns: the current APE OPP
1070 */
1071int db8500_prcmu_get_ape_opp(void)
1072{
1073        return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
1074}
1075
1076/**
1077 * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
1078 * @enable: true to request the higher voltage, false to drop a request.
1079 *
1080 * Calls to this function to enable and disable requests must be balanced.
1081 */
1082int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
1083{
1084        int r = 0;
1085        u8 header;
1086        static unsigned int requests;
1087
1088        mutex_lock(&mb1_transfer.lock);
1089
1090        if (enable) {
1091                if (0 != requests++)
1092                        goto unlock_and_return;
1093                header = MB1H_REQUEST_APE_OPP_100_VOLT;
1094        } else {
1095                if (requests == 0) {
1096                        r = -EIO;
1097                        goto unlock_and_return;
1098                } else if (1 != requests--) {
1099                        goto unlock_and_return;
1100                }
1101                header = MB1H_RELEASE_APE_OPP_100_VOLT;
1102        }
1103
1104        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1105                cpu_relax();
1106
1107        writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1108
1109        writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1110        wait_for_completion(&mb1_transfer.work);
1111
1112        if ((mb1_transfer.ack.header != header) ||
1113                ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1114                r = -EIO;
1115
1116unlock_and_return:
1117        mutex_unlock(&mb1_transfer.lock);
1118
1119        return r;
1120}
1121
1122/**
1123 * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1124 *
1125 * This function releases the power state requirements of a USB wakeup.
1126 */
1127int prcmu_release_usb_wakeup_state(void)
1128{
1129        int r = 0;
1130
1131        mutex_lock(&mb1_transfer.lock);
1132
1133        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1134                cpu_relax();
1135
1136        writeb(MB1H_RELEASE_USB_WAKEUP,
1137                (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1138
1139        writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1140        wait_for_completion(&mb1_transfer.work);
1141
1142        if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1143                ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1144                r = -EIO;
1145
1146        mutex_unlock(&mb1_transfer.lock);
1147
1148        return r;
1149}
1150
1151static int request_pll(u8 clock, bool enable)
1152{
1153        int r = 0;
1154
1155        if (clock == PRCMU_PLLSOC0)
1156                clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1157        else if (clock == PRCMU_PLLSOC1)
1158                clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1159        else
1160                return -EINVAL;
1161
1162        mutex_lock(&mb1_transfer.lock);
1163
1164        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1165                cpu_relax();
1166
1167        writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1168        writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1169
1170        writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1171        wait_for_completion(&mb1_transfer.work);
1172
1173        if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1174                r = -EIO;
1175
1176        mutex_unlock(&mb1_transfer.lock);
1177
1178        return r;
1179}
1180
1181/**
1182 * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1183 * @epod_id: The EPOD to set
1184 * @epod_state: The new EPOD state
1185 *
1186 * This function sets the state of a EPOD (power domain). It may not be called
1187 * from interrupt context.
1188 */
1189int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
1190{
1191        int r = 0;
1192        bool ram_retention = false;
1193        int i;
1194
1195        /* check argument */
1196        BUG_ON(epod_id >= NUM_EPOD_ID);
1197
1198        /* set flag if retention is possible */
1199        switch (epod_id) {
1200        case EPOD_ID_SVAMMDSP:
1201        case EPOD_ID_SIAMMDSP:
1202        case EPOD_ID_ESRAM12:
1203        case EPOD_ID_ESRAM34:
1204                ram_retention = true;
1205                break;
1206        }
1207
1208        /* check argument */
1209        BUG_ON(epod_state > EPOD_STATE_ON);
1210        BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1211
1212        /* get lock */
1213        mutex_lock(&mb2_transfer.lock);
1214
1215        /* wait for mailbox */
1216        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
1217                cpu_relax();
1218
1219        /* fill in mailbox */
1220        for (i = 0; i < NUM_EPOD_ID; i++)
1221                writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1222        writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1223
1224        writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1225
1226        writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
1227
1228        /*
1229         * The current firmware version does not handle errors correctly,
1230         * and we cannot recover if there is an error.
1231         * This is expected to change when the firmware is updated.
1232         */
1233        if (!wait_for_completion_timeout(&mb2_transfer.work,
1234                        msecs_to_jiffies(20000))) {
1235                pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1236                        __func__);
1237                r = -EIO;
1238                goto unlock_and_return;
1239        }
1240
1241        if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1242                r = -EIO;
1243
1244unlock_and_return:
1245        mutex_unlock(&mb2_transfer.lock);
1246        return r;
1247}
1248
1249/**
1250 * prcmu_configure_auto_pm - Configure autonomous power management.
1251 * @sleep: Configuration for ApSleep.
1252 * @idle:  Configuration for ApIdle.
1253 */
1254void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1255        struct prcmu_auto_pm_config *idle)
1256{
1257        u32 sleep_cfg;
1258        u32 idle_cfg;
1259        unsigned long flags;
1260
1261        BUG_ON((sleep == NULL) || (idle == NULL));
1262
1263        sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1264        sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1265        sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1266        sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1267        sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1268        sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1269
1270        idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1271        idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1272        idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1273        idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1274        idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1275        idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1276
1277        spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1278
1279        /*
1280         * The autonomous power management configuration is done through
1281         * fields in mailbox 2, but these fields are only used as shared
1282         * variables - i.e. there is no need to send a message.
1283         */
1284        writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1285        writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1286
1287        mb2_transfer.auto_pm_enabled =
1288                ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1289                 (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1290                 (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1291                 (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1292
1293        spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1294}
1295EXPORT_SYMBOL(prcmu_configure_auto_pm);
1296
1297bool prcmu_is_auto_pm_enabled(void)
1298{
1299        return mb2_transfer.auto_pm_enabled;
1300}
1301
1302static int request_sysclk(bool enable)
1303{
1304        int r;
1305        unsigned long flags;
1306
1307        r = 0;
1308
1309        mutex_lock(&mb3_transfer.sysclk_lock);
1310
1311        spin_lock_irqsave(&mb3_transfer.lock, flags);
1312
1313        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
1314                cpu_relax();
1315
1316        writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1317
1318        writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1319        writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
1320
1321        spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1322
1323        /*
1324         * The firmware only sends an ACK if we want to enable the
1325         * SysClk, and it succeeds.
1326         */
1327        if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1328                        msecs_to_jiffies(20000))) {
1329                pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1330                        __func__);
1331                r = -EIO;
1332        }
1333
1334        mutex_unlock(&mb3_transfer.sysclk_lock);
1335
1336        return r;
1337}
1338
1339static int request_timclk(bool enable)
1340{
1341        u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1342
1343        if (!enable)
1344                val |= PRCM_TCR_STOP_TIMERS;
1345        writel(val, PRCM_TCR);
1346
1347        return 0;
1348}
1349
1350static int request_clock(u8 clock, bool enable)
1351{
1352        u32 val;
1353        unsigned long flags;
1354
1355        spin_lock_irqsave(&clk_mgt_lock, flags);
1356
1357        /* Grab the HW semaphore. */
1358        while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1359                cpu_relax();
1360
1361        val = readl(prcmu_base + clk_mgt[clock].offset);
1362        if (enable) {
1363                val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1364        } else {
1365                clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1366                val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1367        }
1368        writel(val, prcmu_base + clk_mgt[clock].offset);
1369
1370        /* Release the HW semaphore. */
1371        writel(0, PRCM_SEM);
1372
1373        spin_unlock_irqrestore(&clk_mgt_lock, flags);
1374
1375        return 0;
1376}
1377
1378static int request_sga_clock(u8 clock, bool enable)
1379{
1380        u32 val;
1381        int ret;
1382
1383        if (enable) {
1384                val = readl(PRCM_CGATING_BYPASS);
1385                writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1386        }
1387
1388        ret = request_clock(clock, enable);
1389
1390        if (!ret && !enable) {
1391                val = readl(PRCM_CGATING_BYPASS);
1392                writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1393        }
1394
1395        return ret;
1396}
1397
1398static inline bool plldsi_locked(void)
1399{
1400        return (readl(PRCM_PLLDSI_LOCKP) &
1401                (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1402                 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
1403                (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1404                 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
1405}
1406
1407static int request_plldsi(bool enable)
1408{
1409        int r = 0;
1410        u32 val;
1411
1412        writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1413                PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
1414                PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
1415
1416        val = readl(PRCM_PLLDSI_ENABLE);
1417        if (enable)
1418                val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1419        else
1420                val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1421        writel(val, PRCM_PLLDSI_ENABLE);
1422
1423        if (enable) {
1424                unsigned int i;
1425                bool locked = plldsi_locked();
1426
1427                for (i = 10; !locked && (i > 0); --i) {
1428                        udelay(100);
1429                        locked = plldsi_locked();
1430                }
1431                if (locked) {
1432                        writel(PRCM_APE_RESETN_DSIPLL_RESETN,
1433                                PRCM_APE_RESETN_SET);
1434                } else {
1435                        writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1436                                PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
1437                                PRCM_MMIP_LS_CLAMP_SET);
1438                        val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1439                        writel(val, PRCM_PLLDSI_ENABLE);
1440                        r = -EAGAIN;
1441                }
1442        } else {
1443                writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
1444        }
1445        return r;
1446}
1447
1448static int request_dsiclk(u8 n, bool enable)
1449{
1450        u32 val;
1451
1452        val = readl(PRCM_DSI_PLLOUT_SEL);
1453        val &= ~dsiclk[n].divsel_mask;
1454        val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1455                dsiclk[n].divsel_shift);
1456        writel(val, PRCM_DSI_PLLOUT_SEL);
1457        return 0;
1458}
1459
1460static int request_dsiescclk(u8 n, bool enable)
1461{
1462        u32 val;
1463
1464        val = readl(PRCM_DSITVCLK_DIV);
1465        enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1466        writel(val, PRCM_DSITVCLK_DIV);
1467        return 0;
1468}
1469
1470/**
1471 * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1472 * @clock:      The clock for which the request is made.
1473 * @enable:     Whether the clock should be enabled (true) or disabled (false).
1474 *
1475 * This function should only be used by the clock implementation.
1476 * Do not use it from any other place!
1477 */
1478int db8500_prcmu_request_clock(u8 clock, bool enable)
1479{
1480        if (clock == PRCMU_SGACLK)
1481                return request_sga_clock(clock, enable);
1482        else if (clock < PRCMU_NUM_REG_CLOCKS)
1483                return request_clock(clock, enable);
1484        else if (clock == PRCMU_TIMCLK)
1485                return request_timclk(enable);
1486        else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1487                return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
1488        else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1489                return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
1490        else if (clock == PRCMU_PLLDSI)
1491                return request_plldsi(enable);
1492        else if (clock == PRCMU_SYSCLK)
1493                return request_sysclk(enable);
1494        else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
1495                return request_pll(clock, enable);
1496        else
1497                return -EINVAL;
1498}
1499
1500static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1501        int branch)
1502{
1503        u64 rate;
1504        u32 val;
1505        u32 d;
1506        u32 div = 1;
1507
1508        val = readl(reg);
1509
1510        rate = src_rate;
1511        rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1512
1513        d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1514        if (d > 1)
1515                div *= d;
1516
1517        d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1518        if (d > 1)
1519                div *= d;
1520
1521        if (val & PRCM_PLL_FREQ_SELDIV2)
1522                div *= 2;
1523
1524        if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1525                (val & PRCM_PLL_FREQ_DIV2EN) &&
1526                ((reg == PRCM_PLLSOC0_FREQ) ||
1527                 (reg == PRCM_PLLARM_FREQ) ||
1528                 (reg == PRCM_PLLDDR_FREQ))))
1529                div *= 2;
1530
1531        (void)do_div(rate, div);
1532
1533        return (unsigned long)rate;
1534}
1535
1536#define ROOT_CLOCK_RATE 38400000
1537
1538static unsigned long clock_rate(u8 clock)
1539{
1540        u32 val;
1541        u32 pllsw;
1542        unsigned long rate = ROOT_CLOCK_RATE;
1543
1544        val = readl(prcmu_base + clk_mgt[clock].offset);
1545
1546        if (val & PRCM_CLK_MGT_CLK38) {
1547                if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1548                        rate /= 2;
1549                return rate;
1550        }
1551
1552        val |= clk_mgt[clock].pllsw;
1553        pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1554
1555        if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1556                rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1557        else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1558                rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1559        else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
1560                rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1561        else
1562                return 0;
1563
1564        if ((clock == PRCMU_SGACLK) &&
1565                (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1566                u64 r = (rate * 10);
1567
1568                (void)do_div(r, 25);
1569                return (unsigned long)r;
1570        }
1571        val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1572        if (val)
1573                return rate / val;
1574        else
1575                return 0;
1576}
1577
1578static unsigned long armss_rate(void)
1579{
1580        u32 r;
1581        unsigned long rate;
1582
1583        r = readl(PRCM_ARM_CHGCLKREQ);
1584
1585        if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
1586                /* External ARMCLKFIX clock */
1587
1588                rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
1589
1590                /* Check PRCM_ARM_CHGCLKREQ divider */
1591                if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
1592                        rate /= 2;
1593
1594                /* Check PRCM_ARMCLKFIX_MGT divider */
1595                r = readl(PRCM_ARMCLKFIX_MGT);
1596                r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1597                rate /= r;
1598
1599        } else {/* ARM PLL */
1600                rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
1601        }
1602
1603        return rate;
1604}
1605
1606static unsigned long dsiclk_rate(u8 n)
1607{
1608        u32 divsel;
1609        u32 div = 1;
1610
1611        divsel = readl(PRCM_DSI_PLLOUT_SEL);
1612        divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
1613
1614        if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
1615                divsel = dsiclk[n].divsel;
1616        else
1617                dsiclk[n].divsel = divsel;
1618
1619        switch (divsel) {
1620        case PRCM_DSI_PLLOUT_SEL_PHI_4:
1621                div *= 2;
1622        case PRCM_DSI_PLLOUT_SEL_PHI_2:
1623                div *= 2;
1624        case PRCM_DSI_PLLOUT_SEL_PHI:
1625                return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1626                        PLL_RAW) / div;
1627        default:
1628                return 0;
1629        }
1630}
1631
1632static unsigned long dsiescclk_rate(u8 n)
1633{
1634        u32 div;
1635
1636        div = readl(PRCM_DSITVCLK_DIV);
1637        div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1638        return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1639}
1640
1641unsigned long prcmu_clock_rate(u8 clock)
1642{
1643        if (clock < PRCMU_NUM_REG_CLOCKS)
1644                return clock_rate(clock);
1645        else if (clock == PRCMU_TIMCLK)
1646                return ROOT_CLOCK_RATE / 16;
1647        else if (clock == PRCMU_SYSCLK)
1648                return ROOT_CLOCK_RATE;
1649        else if (clock == PRCMU_PLLSOC0)
1650                return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1651        else if (clock == PRCMU_PLLSOC1)
1652                return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1653        else if (clock == PRCMU_ARMSS)
1654                return armss_rate();
1655        else if (clock == PRCMU_PLLDDR)
1656                return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1657        else if (clock == PRCMU_PLLDSI)
1658                return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1659                        PLL_RAW);
1660        else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1661                return dsiclk_rate(clock - PRCMU_DSI0CLK);
1662        else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1663                return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
1664        else
1665                return 0;
1666}
1667
1668static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
1669{
1670        if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
1671                return ROOT_CLOCK_RATE;
1672        clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
1673        if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1674                return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
1675        else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1676                return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
1677        else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
1678                return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
1679        else
1680                return 0;
1681}
1682
1683static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1684{
1685        u32 div;
1686
1687        div = (src_rate / rate);
1688        if (div == 0)
1689                return 1;
1690        if (rate < (src_rate / div))
1691                div++;
1692        return div;
1693}
1694
1695static long round_clock_rate(u8 clock, unsigned long rate)
1696{
1697        u32 val;
1698        u32 div;
1699        unsigned long src_rate;
1700        long rounded_rate;
1701
1702        val = readl(prcmu_base + clk_mgt[clock].offset);
1703        src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1704                clk_mgt[clock].branch);
1705        div = clock_divider(src_rate, rate);
1706        if (val & PRCM_CLK_MGT_CLK38) {
1707                if (clk_mgt[clock].clk38div) {
1708                        if (div > 2)
1709                                div = 2;
1710                } else {
1711                        div = 1;
1712                }
1713        } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1714                u64 r = (src_rate * 10);
1715
1716                (void)do_div(r, 25);
1717                if (r <= rate)
1718                        return (unsigned long)r;
1719        }
1720        rounded_rate = (src_rate / min(div, (u32)31));
1721
1722        return rounded_rate;
1723}
1724
1725/* CPU FREQ table, may be changed due to if MAX_OPP is supported. */
1726static struct cpufreq_frequency_table db8500_cpufreq_table[] = {
1727        { .frequency = 200000, .index = ARM_EXTCLK,},
1728        { .frequency = 400000, .index = ARM_50_OPP,},
1729        { .frequency = 800000, .index = ARM_100_OPP,},
1730        { .frequency = CPUFREQ_TABLE_END,}, /* To be used for MAX_OPP. */
1731        { .frequency = CPUFREQ_TABLE_END,},
1732};
1733
1734static long round_armss_rate(unsigned long rate)
1735{
1736        long freq = 0;
1737        int i = 0;
1738
1739        /* cpufreq table frequencies is in KHz. */
1740        rate = rate / 1000;
1741
1742        /* Find the corresponding arm opp from the cpufreq table. */
1743        while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) {
1744                freq = db8500_cpufreq_table[i].frequency;
1745                if (freq == rate)
1746                        break;
1747                i++;
1748        }
1749
1750        /* Return the last valid value, even if a match was not found. */
1751        return freq * 1000;
1752}
1753
1754#define MIN_PLL_VCO_RATE 600000000ULL
1755#define MAX_PLL_VCO_RATE 1680640000ULL
1756
1757static long round_plldsi_rate(unsigned long rate)
1758{
1759        long rounded_rate = 0;
1760        unsigned long src_rate;
1761        unsigned long rem;
1762        u32 r;
1763
1764        src_rate = clock_rate(PRCMU_HDMICLK);
1765        rem = rate;
1766
1767        for (r = 7; (rem > 0) && (r > 0); r--) {
1768                u64 d;
1769
1770                d = (r * rate);
1771                (void)do_div(d, src_rate);
1772                if (d < 6)
1773                        d = 6;
1774                else if (d > 255)
1775                        d = 255;
1776                d *= src_rate;
1777                if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
1778                        ((r * MAX_PLL_VCO_RATE) < (2 * d)))
1779                        continue;
1780                (void)do_div(d, r);
1781                if (rate < d) {
1782                        if (rounded_rate == 0)
1783                                rounded_rate = (long)d;
1784                        break;
1785                }
1786                if ((rate - d) < rem) {
1787                        rem = (rate - d);
1788                        rounded_rate = (long)d;
1789                }
1790        }
1791        return rounded_rate;
1792}
1793
1794static long round_dsiclk_rate(unsigned long rate)
1795{
1796        u32 div;
1797        unsigned long src_rate;
1798        long rounded_rate;
1799
1800        src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1801                PLL_RAW);
1802        div = clock_divider(src_rate, rate);
1803        rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1804
1805        return rounded_rate;
1806}
1807
1808static long round_dsiescclk_rate(unsigned long rate)
1809{
1810        u32 div;
1811        unsigned long src_rate;
1812        long rounded_rate;
1813
1814        src_rate = clock_rate(PRCMU_TVCLK);
1815        div = clock_divider(src_rate, rate);
1816        rounded_rate = (src_rate / min(div, (u32)255));
1817
1818        return rounded_rate;
1819}
1820
1821long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1822{
1823        if (clock < PRCMU_NUM_REG_CLOCKS)
1824                return round_clock_rate(clock, rate);
1825        else if (clock == PRCMU_ARMSS)
1826                return round_armss_rate(rate);
1827        else if (clock == PRCMU_PLLDSI)
1828                return round_plldsi_rate(rate);
1829        else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1830                return round_dsiclk_rate(rate);
1831        else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1832                return round_dsiescclk_rate(rate);
1833        else
1834                return (long)prcmu_clock_rate(clock);
1835}
1836
1837static void set_clock_rate(u8 clock, unsigned long rate)
1838{
1839        u32 val;
1840        u32 div;
1841        unsigned long src_rate;
1842        unsigned long flags;
1843
1844        spin_lock_irqsave(&clk_mgt_lock, flags);
1845
1846        /* Grab the HW semaphore. */
1847        while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1848                cpu_relax();
1849
1850        val = readl(prcmu_base + clk_mgt[clock].offset);
1851        src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1852                clk_mgt[clock].branch);
1853        div = clock_divider(src_rate, rate);
1854        if (val & PRCM_CLK_MGT_CLK38) {
1855                if (clk_mgt[clock].clk38div) {
1856                        if (div > 1)
1857                                val |= PRCM_CLK_MGT_CLK38DIV;
1858                        else
1859                                val &= ~PRCM_CLK_MGT_CLK38DIV;
1860                }
1861        } else if (clock == PRCMU_SGACLK) {
1862                val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
1863                        PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
1864                if (div == 3) {
1865                        u64 r = (src_rate * 10);
1866
1867                        (void)do_div(r, 25);
1868                        if (r <= rate) {
1869                                val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
1870                                div = 0;
1871                        }
1872                }
1873                val |= min(div, (u32)31);
1874        } else {
1875                val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1876                val |= min(div, (u32)31);
1877        }
1878        writel(val, prcmu_base + clk_mgt[clock].offset);
1879
1880        /* Release the HW semaphore. */
1881        writel(0, PRCM_SEM);
1882
1883        spin_unlock_irqrestore(&clk_mgt_lock, flags);
1884}
1885
1886static int set_armss_rate(unsigned long rate)
1887{
1888        int i = 0;
1889
1890        /* cpufreq table frequencies is in KHz. */
1891        rate = rate / 1000;
1892
1893        /* Find the corresponding arm opp from the cpufreq table. */
1894        while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) {
1895                if (db8500_cpufreq_table[i].frequency == rate)
1896                        break;
1897                i++;
1898        }
1899
1900        if (db8500_cpufreq_table[i].frequency != rate)
1901                return -EINVAL;
1902
1903        /* Set the new arm opp. */
1904        return db8500_prcmu_set_arm_opp(db8500_cpufreq_table[i].index);
1905}
1906
1907static int set_plldsi_rate(unsigned long rate)
1908{
1909        unsigned long src_rate;
1910        unsigned long rem;
1911        u32 pll_freq = 0;
1912        u32 r;
1913
1914        src_rate = clock_rate(PRCMU_HDMICLK);
1915        rem = rate;
1916
1917        for (r = 7; (rem > 0) && (r > 0); r--) {
1918                u64 d;
1919                u64 hwrate;
1920
1921                d = (r * rate);
1922                (void)do_div(d, src_rate);
1923                if (d < 6)
1924                        d = 6;
1925                else if (d > 255)
1926                        d = 255;
1927                hwrate = (d * src_rate);
1928                if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
1929                        ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
1930                        continue;
1931                (void)do_div(hwrate, r);
1932                if (rate < hwrate) {
1933                        if (pll_freq == 0)
1934                                pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1935                                        (r << PRCM_PLL_FREQ_R_SHIFT));
1936                        break;
1937                }
1938                if ((rate - hwrate) < rem) {
1939                        rem = (rate - hwrate);
1940                        pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1941                                (r << PRCM_PLL_FREQ_R_SHIFT));
1942                }
1943        }
1944        if (pll_freq == 0)
1945                return -EINVAL;
1946
1947        pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
1948        writel(pll_freq, PRCM_PLLDSI_FREQ);
1949
1950        return 0;
1951}
1952
1953static void set_dsiclk_rate(u8 n, unsigned long rate)
1954{
1955        u32 val;
1956        u32 div;
1957
1958        div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
1959                        clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
1960
1961        dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
1962                           (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
1963                           /* else */   PRCM_DSI_PLLOUT_SEL_PHI_4;
1964
1965        val = readl(PRCM_DSI_PLLOUT_SEL);
1966        val &= ~dsiclk[n].divsel_mask;
1967        val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
1968        writel(val, PRCM_DSI_PLLOUT_SEL);
1969}
1970
1971static void set_dsiescclk_rate(u8 n, unsigned long rate)
1972{
1973        u32 val;
1974        u32 div;
1975
1976        div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
1977        val = readl(PRCM_DSITVCLK_DIV);
1978        val &= ~dsiescclk[n].div_mask;
1979        val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
1980        writel(val, PRCM_DSITVCLK_DIV);
1981}
1982
1983int prcmu_set_clock_rate(u8 clock, unsigned long rate)
1984{
1985        if (clock < PRCMU_NUM_REG_CLOCKS)
1986                set_clock_rate(clock, rate);
1987        else if (clock == PRCMU_ARMSS)
1988                return set_armss_rate(rate);
1989        else if (clock == PRCMU_PLLDSI)
1990                return set_plldsi_rate(rate);
1991        else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1992                set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
1993        else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1994                set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
1995        return 0;
1996}
1997
1998int db8500_prcmu_config_esram0_deep_sleep(u8 state)
1999{
2000        if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
2001            (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
2002                return -EINVAL;
2003
2004        mutex_lock(&mb4_transfer.lock);
2005
2006        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2007                cpu_relax();
2008
2009        writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2010        writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
2011               (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
2012        writeb(DDR_PWR_STATE_ON,
2013               (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
2014        writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
2015
2016        writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2017        wait_for_completion(&mb4_transfer.work);
2018
2019        mutex_unlock(&mb4_transfer.lock);
2020
2021        return 0;
2022}
2023
2024int db8500_prcmu_config_hotdog(u8 threshold)
2025{
2026        mutex_lock(&mb4_transfer.lock);
2027
2028        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2029                cpu_relax();
2030
2031        writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
2032        writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2033
2034        writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2035        wait_for_completion(&mb4_transfer.work);
2036
2037        mutex_unlock(&mb4_transfer.lock);
2038
2039        return 0;
2040}
2041
2042int db8500_prcmu_config_hotmon(u8 low, u8 high)
2043{
2044        mutex_lock(&mb4_transfer.lock);
2045
2046        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2047                cpu_relax();
2048
2049        writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
2050        writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
2051        writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
2052                (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
2053        writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2054
2055        writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2056        wait_for_completion(&mb4_transfer.work);
2057
2058        mutex_unlock(&mb4_transfer.lock);
2059
2060        return 0;
2061}
2062
2063static int config_hot_period(u16 val)
2064{
2065        mutex_lock(&mb4_transfer.lock);
2066
2067        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2068                cpu_relax();
2069
2070        writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
2071        writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2072
2073        writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2074        wait_for_completion(&mb4_transfer.work);
2075
2076        mutex_unlock(&mb4_transfer.lock);
2077
2078        return 0;
2079}
2080
2081int db8500_prcmu_start_temp_sense(u16 cycles32k)
2082{
2083        if (cycles32k == 0xFFFF)
2084                return -EINVAL;
2085
2086        return config_hot_period(cycles32k);
2087}
2088
2089int db8500_prcmu_stop_temp_sense(void)
2090{
2091        return config_hot_period(0xFFFF);
2092}
2093
2094static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
2095{
2096
2097        mutex_lock(&mb4_transfer.lock);
2098
2099        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2100                cpu_relax();
2101
2102        writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2103        writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2104        writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2105        writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2106
2107        writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2108
2109        writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2110        wait_for_completion(&mb4_transfer.work);
2111
2112        mutex_unlock(&mb4_transfer.lock);
2113
2114        return 0;
2115
2116}
2117
2118int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
2119{
2120        BUG_ON(num == 0 || num > 0xf);
2121        return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
2122                            sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
2123                            A9WDOG_AUTO_OFF_DIS);
2124}
2125EXPORT_SYMBOL(db8500_prcmu_config_a9wdog);
2126
2127int db8500_prcmu_enable_a9wdog(u8 id)
2128{
2129        return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
2130}
2131EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog);
2132
2133int db8500_prcmu_disable_a9wdog(u8 id)
2134{
2135        return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
2136}
2137EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog);
2138
2139int db8500_prcmu_kick_a9wdog(u8 id)
2140{
2141        return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
2142}
2143EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog);
2144
2145/*
2146 * timeout is 28 bit, in ms.
2147 */
2148int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
2149{
2150        return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
2151                            (id & A9WDOG_ID_MASK) |
2152                            /*
2153                             * Put the lowest 28 bits of timeout at
2154                             * offset 4. Four first bits are used for id.
2155                             */
2156                            (u8)((timeout << 4) & 0xf0),
2157                            (u8)((timeout >> 4) & 0xff),
2158                            (u8)((timeout >> 12) & 0xff),
2159                            (u8)((timeout >> 20) & 0xff));
2160}
2161EXPORT_SYMBOL(db8500_prcmu_load_a9wdog);
2162
2163/**
2164 * prcmu_abb_read() - Read register value(s) from the ABB.
2165 * @slave:      The I2C slave address.
2166 * @reg:        The (start) register address.
2167 * @value:      The read out value(s).
2168 * @size:       The number of registers to read.
2169 *
2170 * Reads register value(s) from the ABB.
2171 * @size has to be 1 for the current firmware version.
2172 */
2173int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2174{
2175        int r;
2176
2177        if (size != 1)
2178                return -EINVAL;
2179
2180        mutex_lock(&mb5_transfer.lock);
2181
2182        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2183                cpu_relax();
2184
2185        writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2186        writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2187        writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2188        writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2189        writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2190
2191        writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2192
2193        if (!wait_for_completion_timeout(&mb5_transfer.work,
2194                                msecs_to_jiffies(20000))) {
2195                pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2196                        __func__);
2197                r = -EIO;
2198        } else {
2199                r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
2200        }
2201
2202        if (!r)
2203                *value = mb5_transfer.ack.value;
2204
2205        mutex_unlock(&mb5_transfer.lock);
2206
2207        return r;
2208}
2209
2210/**
2211 * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
2212 * @slave:      The I2C slave address.
2213 * @reg:        The (start) register address.
2214 * @value:      The value(s) to write.
2215 * @mask:       The mask(s) to use.
2216 * @size:       The number of registers to write.
2217 *
2218 * Writes masked register value(s) to the ABB.
2219 * For each @value, only the bits set to 1 in the corresponding @mask
2220 * will be written. The other bits are not changed.
2221 * @size has to be 1 for the current firmware version.
2222 */
2223int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
2224{
2225        int r;
2226
2227        if (size != 1)
2228                return -EINVAL;
2229
2230        mutex_lock(&mb5_transfer.lock);
2231
2232        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2233                cpu_relax();
2234
2235        writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2236        writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2237        writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2238        writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2239        writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2240
2241        writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2242
2243        if (!wait_for_completion_timeout(&mb5_transfer.work,
2244                                msecs_to_jiffies(20000))) {
2245                pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2246                        __func__);
2247                r = -EIO;
2248        } else {
2249                r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
2250        }
2251
2252        mutex_unlock(&mb5_transfer.lock);
2253
2254        return r;
2255}
2256
2257/**
2258 * prcmu_abb_write() - Write register value(s) to the ABB.
2259 * @slave:      The I2C slave address.
2260 * @reg:        The (start) register address.
2261 * @value:      The value(s) to write.
2262 * @size:       The number of registers to write.
2263 *
2264 * Writes register value(s) to the ABB.
2265 * @size has to be 1 for the current firmware version.
2266 */
2267int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2268{
2269        u8 mask = ~0;
2270
2271        return prcmu_abb_write_masked(slave, reg, value, &mask, size);
2272}
2273
2274/**
2275 * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2276 */
2277int prcmu_ac_wake_req(void)
2278{
2279        u32 val;
2280        int ret = 0;
2281
2282        mutex_lock(&mb0_transfer.ac_wake_lock);
2283
2284        val = readl(PRCM_HOSTACCESS_REQ);
2285        if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2286                goto unlock_and_return;
2287
2288        atomic_set(&ac_wake_req_state, 1);
2289
2290        /*
2291         * Force Modem Wake-up before hostaccess_req ping-pong.
2292         * It prevents Modem to enter in Sleep while acking the hostaccess
2293         * request. The 31us delay has been calculated by HWI.
2294         */
2295        val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
2296        writel(val, PRCM_HOSTACCESS_REQ);
2297
2298        udelay(31);
2299
2300        val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
2301        writel(val, PRCM_HOSTACCESS_REQ);
2302
2303        if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2304                        msecs_to_jiffies(5000))) {
2305#if defined(CONFIG_DBX500_PRCMU_DEBUG)
2306                db8500_prcmu_debug_dump(__func__, true, true);
2307#endif
2308                pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2309                        __func__);
2310                ret = -EFAULT;
2311        }
2312
2313unlock_and_return:
2314        mutex_unlock(&mb0_transfer.ac_wake_lock);
2315        return ret;
2316}
2317
2318/**
2319 * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2320 */
2321void prcmu_ac_sleep_req()
2322{
2323        u32 val;
2324
2325        mutex_lock(&mb0_transfer.ac_wake_lock);
2326
2327        val = readl(PRCM_HOSTACCESS_REQ);
2328        if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2329                goto unlock_and_return;
2330
2331        writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
2332                PRCM_HOSTACCESS_REQ);
2333
2334        if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2335                        msecs_to_jiffies(5000))) {
2336                pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2337                        __func__);
2338        }
2339
2340        atomic_set(&ac_wake_req_state, 0);
2341
2342unlock_and_return:
2343        mutex_unlock(&mb0_transfer.ac_wake_lock);
2344}
2345
2346bool db8500_prcmu_is_ac_wake_requested(void)
2347{
2348        return (atomic_read(&ac_wake_req_state) != 0);
2349}
2350
2351/**
2352 * db8500_prcmu_system_reset - System reset
2353 *
2354 * Saves the reset reason code and then sets the APE_SOFTRST register which
2355 * fires interrupt to fw
2356 */
2357void db8500_prcmu_system_reset(u16 reset_code)
2358{
2359        writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
2360        writel(1, PRCM_APE_SOFTRST);
2361}
2362
2363/**
2364 * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2365 *
2366 * Retrieves the reset reason code stored by prcmu_system_reset() before
2367 * last restart.
2368 */
2369u16 db8500_prcmu_get_reset_code(void)
2370{
2371        return readw(tcdm_base + PRCM_SW_RST_REASON);
2372}
2373
2374/**
2375 * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
2376 */
2377void db8500_prcmu_modem_reset(void)
2378{
2379        mutex_lock(&mb1_transfer.lock);
2380
2381        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
2382                cpu_relax();
2383
2384        writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
2385        writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
2386        wait_for_completion(&mb1_transfer.work);
2387
2388        /*
2389         * No need to check return from PRCMU as modem should go in reset state
2390         * This state is already managed by upper layer
2391         */
2392
2393        mutex_unlock(&mb1_transfer.lock);
2394}
2395
2396static void ack_dbb_wakeup(void)
2397{
2398        unsigned long flags;
2399
2400        spin_lock_irqsave(&mb0_transfer.lock, flags);
2401
2402        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
2403                cpu_relax();
2404
2405        writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
2406        writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
2407
2408        spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2409}
2410
2411static inline void print_unknown_header_warning(u8 n, u8 header)
2412{
2413        pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
2414                header, n);
2415}
2416
2417static bool read_mailbox_0(void)
2418{
2419        bool r;
2420        u32 ev;
2421        unsigned int n;
2422        u8 header;
2423
2424        header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2425        switch (header) {
2426        case MB0H_WAKEUP_EXE:
2427        case MB0H_WAKEUP_SLEEP:
2428                if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2429                        ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2430                else
2431                        ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2432
2433                if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
2434                        complete(&mb0_transfer.ac_wake_work);
2435                if (ev & WAKEUP_BIT_SYSCLK_OK)
2436                        complete(&mb3_transfer.sysclk_work);
2437
2438                ev &= mb0_transfer.req.dbb_irqs;
2439
2440                for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2441                        if (ev & prcmu_irq_bit[n])
2442                                generic_handle_irq(irq_find_mapping(db8500_irq_domain, n));
2443                }
2444                r = true;
2445                break;
2446        default:
2447                print_unknown_header_warning(0, header);
2448                r = false;
2449                break;
2450        }
2451        writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
2452        return r;
2453}
2454
2455static bool read_mailbox_1(void)
2456{
2457        mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2458        mb1_transfer.ack.arm_opp = readb(tcdm_base +
2459                PRCM_ACK_MB1_CURRENT_ARM_OPP);
2460        mb1_transfer.ack.ape_opp = readb(tcdm_base +
2461                PRCM_ACK_MB1_CURRENT_APE_OPP);
2462        mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2463                PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
2464        writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
2465        complete(&mb1_transfer.work);
2466        return false;
2467}
2468
2469static bool read_mailbox_2(void)
2470{
2471        mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
2472        writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
2473        complete(&mb2_transfer.work);
2474        return false;
2475}
2476
2477static bool read_mailbox_3(void)
2478{
2479        writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
2480        return false;
2481}
2482
2483static bool read_mailbox_4(void)
2484{
2485        u8 header;
2486        bool do_complete = true;
2487
2488        header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2489        switch (header) {
2490        case MB4H_MEM_ST:
2491        case MB4H_HOTDOG:
2492        case MB4H_HOTMON:
2493        case MB4H_HOT_PERIOD:
2494        case MB4H_A9WDOG_CONF:
2495        case MB4H_A9WDOG_EN:
2496        case MB4H_A9WDOG_DIS:
2497        case MB4H_A9WDOG_LOAD:
2498        case MB4H_A9WDOG_KICK:
2499                break;
2500        default:
2501                print_unknown_header_warning(4, header);
2502                do_complete = false;
2503                break;
2504        }
2505
2506        writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
2507
2508        if (do_complete)
2509                complete(&mb4_transfer.work);
2510
2511        return false;
2512}
2513
2514static bool read_mailbox_5(void)
2515{
2516        mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2517        mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
2518        writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
2519        complete(&mb5_transfer.work);
2520        return false;
2521}
2522
2523static bool read_mailbox_6(void)
2524{
2525        writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
2526        return false;
2527}
2528
2529static bool read_mailbox_7(void)
2530{
2531        writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
2532        return false;
2533}
2534
2535static bool (* const read_mailbox[NUM_MB])(void) = {
2536        read_mailbox_0,
2537        read_mailbox_1,
2538        read_mailbox_2,
2539        read_mailbox_3,
2540        read_mailbox_4,
2541        read_mailbox_5,
2542        read_mailbox_6,
2543        read_mailbox_7
2544};
2545
2546static irqreturn_t prcmu_irq_handler(int irq, void *data)
2547{
2548        u32 bits;
2549        u8 n;
2550        irqreturn_t r;
2551
2552        bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
2553        if (unlikely(!bits))
2554                return IRQ_NONE;
2555
2556        r = IRQ_HANDLED;
2557        for (n = 0; bits; n++) {
2558                if (bits & MBOX_BIT(n)) {
2559                        bits -= MBOX_BIT(n);
2560                        if (read_mailbox[n]())
2561                                r = IRQ_WAKE_THREAD;
2562                }
2563        }
2564        return r;
2565}
2566
2567static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
2568{
2569        ack_dbb_wakeup();
2570        return IRQ_HANDLED;
2571}
2572
2573static void prcmu_mask_work(struct work_struct *work)
2574{
2575        unsigned long flags;
2576
2577        spin_lock_irqsave(&mb0_transfer.lock, flags);
2578
2579        config_wakeups();
2580
2581        spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2582}
2583
2584static void prcmu_irq_mask(struct irq_data *d)
2585{
2586        unsigned long flags;
2587
2588        spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2589
2590        mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
2591
2592        spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2593
2594        if (d->irq != IRQ_PRCMU_CA_SLEEP)
2595                schedule_work(&mb0_transfer.mask_work);
2596}
2597
2598static void prcmu_irq_unmask(struct irq_data *d)
2599{
2600        unsigned long flags;
2601
2602        spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2603
2604        mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
2605
2606        spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2607
2608        if (d->irq != IRQ_PRCMU_CA_SLEEP)
2609                schedule_work(&mb0_transfer.mask_work);
2610}
2611
2612static void noop(struct irq_data *d)
2613{
2614}
2615
2616static struct irq_chip prcmu_irq_chip = {
2617        .name           = "prcmu",
2618        .irq_disable    = prcmu_irq_mask,
2619        .irq_ack        = noop,
2620        .irq_mask       = prcmu_irq_mask,
2621        .irq_unmask     = prcmu_irq_unmask,
2622};
2623
2624static __init char *fw_project_name(u32 project)
2625{
2626        switch (project) {
2627        case PRCMU_FW_PROJECT_U8500:
2628                return "U8500";
2629        case PRCMU_FW_PROJECT_U8400:
2630                return "U8400";
2631        case PRCMU_FW_PROJECT_U9500:
2632                return "U9500";
2633        case PRCMU_FW_PROJECT_U8500_MBB:
2634                return "U8500 MBB";
2635        case PRCMU_FW_PROJECT_U8500_C1:
2636                return "U8500 C1";
2637        case PRCMU_FW_PROJECT_U8500_C2:
2638                return "U8500 C2";
2639        case PRCMU_FW_PROJECT_U8500_C3:
2640                return "U8500 C3";
2641        case PRCMU_FW_PROJECT_U8500_C4:
2642                return "U8500 C4";
2643        case PRCMU_FW_PROJECT_U9500_MBL:
2644                return "U9500 MBL";
2645        case PRCMU_FW_PROJECT_U8500_MBL:
2646                return "U8500 MBL";
2647        case PRCMU_FW_PROJECT_U8500_MBL2:
2648                return "U8500 MBL2";
2649        case PRCMU_FW_PROJECT_U8520:
2650                return "U8520 MBL";
2651        case PRCMU_FW_PROJECT_U8420:
2652                return "U8420";
2653        case PRCMU_FW_PROJECT_U9540:
2654                return "U9540";
2655        case PRCMU_FW_PROJECT_A9420:
2656                return "A9420";
2657        case PRCMU_FW_PROJECT_L8540:
2658                return "L8540";
2659        case PRCMU_FW_PROJECT_L8580:
2660                return "L8580";
2661        default:
2662                return "Unknown";
2663        }
2664}
2665
2666static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
2667                                irq_hw_number_t hwirq)
2668{
2669        irq_set_chip_and_handler(virq, &prcmu_irq_chip,
2670                                handle_simple_irq);
2671        set_irq_flags(virq, IRQF_VALID);
2672
2673        return 0;
2674}
2675
2676static struct irq_domain_ops db8500_irq_ops = {
2677        .map    = db8500_irq_map,
2678        .xlate  = irq_domain_xlate_twocell,
2679};
2680
2681static int db8500_irq_init(struct device_node *np, int irq_base)
2682{
2683        int i;
2684
2685        /* In the device tree case, just take some IRQs */
2686        if (np)
2687                irq_base = 0;
2688
2689        db8500_irq_domain = irq_domain_add_simple(
2690                np, NUM_PRCMU_WAKEUPS, irq_base,
2691                &db8500_irq_ops, NULL);
2692
2693        if (!db8500_irq_domain) {
2694                pr_err("Failed to create irqdomain\n");
2695                return -ENOSYS;
2696        }
2697
2698        /* All wakeups will be used, so create mappings for all */
2699        for (i = 0; i < NUM_PRCMU_WAKEUPS; i++)
2700                irq_create_mapping(db8500_irq_domain, i);
2701
2702        return 0;
2703}
2704
2705static void dbx500_fw_version_init(struct platform_device *pdev,
2706                            u32 version_offset)
2707{
2708        struct resource *res;
2709        void __iomem *tcpm_base;
2710        u32 version;
2711
2712        res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2713                                           "prcmu-tcpm");
2714        if (!res) {
2715                dev_err(&pdev->dev,
2716                        "Error: no prcmu tcpm memory region provided\n");
2717                return;
2718        }
2719        tcpm_base = ioremap(res->start, resource_size(res));
2720        if (!tcpm_base) {
2721                dev_err(&pdev->dev, "no prcmu tcpm mem region provided\n");
2722                return;
2723        }
2724
2725        version = readl(tcpm_base + version_offset);
2726        fw_info.version.project = (version & 0xFF);
2727        fw_info.version.api_version = (version >> 8) & 0xFF;
2728        fw_info.version.func_version = (version >> 16) & 0xFF;
2729        fw_info.version.errata = (version >> 24) & 0xFF;
2730        strncpy(fw_info.version.project_name,
2731                fw_project_name(fw_info.version.project),
2732                PRCMU_FW_PROJECT_NAME_LEN);
2733        fw_info.valid = true;
2734        pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n",
2735                fw_info.version.project_name,
2736                fw_info.version.project,
2737                fw_info.version.api_version,
2738                fw_info.version.func_version,
2739                fw_info.version.errata);
2740        iounmap(tcpm_base);
2741}
2742
2743void __init db8500_prcmu_early_init(u32 phy_base, u32 size)
2744{
2745        /*
2746         * This is a temporary remap to bring up the clocks. It is
2747         * subsequently replaces with a real remap. After the merge of
2748         * the mailbox subsystem all of this early code goes away, and the
2749         * clock driver can probe independently. An early initcall will
2750         * still be needed, but it can be diverted into drivers/clk/ux500.
2751         */
2752        prcmu_base = ioremap(phy_base, size);
2753        if (!prcmu_base)
2754                pr_err("%s: ioremap() of prcmu registers failed!\n", __func__);
2755
2756        spin_lock_init(&mb0_transfer.lock);
2757        spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2758        mutex_init(&mb0_transfer.ac_wake_lock);
2759        init_completion(&mb0_transfer.ac_wake_work);
2760        mutex_init(&mb1_transfer.lock);
2761        init_completion(&mb1_transfer.work);
2762        mb1_transfer.ape_opp = APE_NO_CHANGE;
2763        mutex_init(&mb2_transfer.lock);
2764        init_completion(&mb2_transfer.work);
2765        spin_lock_init(&mb2_transfer.auto_pm_lock);
2766        spin_lock_init(&mb3_transfer.lock);
2767        mutex_init(&mb3_transfer.sysclk_lock);
2768        init_completion(&mb3_transfer.sysclk_work);
2769        mutex_init(&mb4_transfer.lock);
2770        init_completion(&mb4_transfer.work);
2771        mutex_init(&mb5_transfer.lock);
2772        init_completion(&mb5_transfer.work);
2773
2774        INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
2775}
2776
2777static void __init init_prcm_registers(void)
2778{
2779        u32 val;
2780
2781        val = readl(PRCM_A9PL_FORCE_CLKEN);
2782        val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2783                PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2784        writel(val, (PRCM_A9PL_FORCE_CLKEN));
2785}
2786
2787/*
2788 * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2789 */
2790static struct regulator_consumer_supply db8500_vape_consumers[] = {
2791        REGULATOR_SUPPLY("v-ape", NULL),
2792        REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2793        REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2794        REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2795        REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2796        REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
2797        /* "v-mmc" changed to "vcore" in the mainline kernel */
2798        REGULATOR_SUPPLY("vcore", "sdi0"),
2799        REGULATOR_SUPPLY("vcore", "sdi1"),
2800        REGULATOR_SUPPLY("vcore", "sdi2"),
2801        REGULATOR_SUPPLY("vcore", "sdi3"),
2802        REGULATOR_SUPPLY("vcore", "sdi4"),
2803        REGULATOR_SUPPLY("v-dma", "dma40.0"),
2804        REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2805        /* "v-uart" changed to "vcore" in the mainline kernel */
2806        REGULATOR_SUPPLY("vcore", "uart0"),
2807        REGULATOR_SUPPLY("vcore", "uart1"),
2808        REGULATOR_SUPPLY("vcore", "uart2"),
2809        REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
2810        REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
2811        REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
2812};
2813
2814static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
2815        REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2816        /* AV8100 regulator */
2817        REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2818};
2819
2820static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
2821        REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
2822        REGULATOR_SUPPLY("vsupply", "mcde"),
2823};
2824
2825/* SVA MMDSP regulator switch */
2826static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2827        REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2828};
2829
2830/* SVA pipe regulator switch */
2831static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2832        REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2833};
2834
2835/* SIA MMDSP regulator switch */
2836static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2837        REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2838};
2839
2840/* SIA pipe regulator switch */
2841static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2842        REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2843};
2844
2845static struct regulator_consumer_supply db8500_sga_consumers[] = {
2846        REGULATOR_SUPPLY("v-mali", NULL),
2847};
2848
2849/* ESRAM1 and 2 regulator switch */
2850static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2851        REGULATOR_SUPPLY("esram12", "cm_control"),
2852};
2853
2854/* ESRAM3 and 4 regulator switch */
2855static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2856        REGULATOR_SUPPLY("v-esram34", "mcde"),
2857        REGULATOR_SUPPLY("esram34", "cm_control"),
2858        REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
2859};
2860
2861static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2862        [DB8500_REGULATOR_VAPE] = {
2863                .constraints = {
2864                        .name = "db8500-vape",
2865                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2866                        .always_on = true,
2867                },
2868                .consumer_supplies = db8500_vape_consumers,
2869                .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
2870        },
2871        [DB8500_REGULATOR_VARM] = {
2872                .constraints = {
2873                        .name = "db8500-varm",
2874                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2875                },
2876        },
2877        [DB8500_REGULATOR_VMODEM] = {
2878                .constraints = {
2879                        .name = "db8500-vmodem",
2880                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2881                },
2882        },
2883        [DB8500_REGULATOR_VPLL] = {
2884                .constraints = {
2885                        .name = "db8500-vpll",
2886                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2887                },
2888        },
2889        [DB8500_REGULATOR_VSMPS1] = {
2890                .constraints = {
2891                        .name = "db8500-vsmps1",
2892                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2893                },
2894        },
2895        [DB8500_REGULATOR_VSMPS2] = {
2896                .constraints = {
2897                        .name = "db8500-vsmps2",
2898                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2899                },
2900                .consumer_supplies = db8500_vsmps2_consumers,
2901                .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2902        },
2903        [DB8500_REGULATOR_VSMPS3] = {
2904                .constraints = {
2905                        .name = "db8500-vsmps3",
2906                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2907                },
2908        },
2909        [DB8500_REGULATOR_VRF1] = {
2910                .constraints = {
2911                        .name = "db8500-vrf1",
2912                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2913                },
2914        },
2915        [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
2916                /* dependency to u8500-vape is handled outside regulator framework */
2917                .constraints = {
2918                        .name = "db8500-sva-mmdsp",
2919                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2920                },
2921                .consumer_supplies = db8500_svammdsp_consumers,
2922                .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
2923        },
2924        [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
2925                .constraints = {
2926                        /* "ret" means "retention" */
2927                        .name = "db8500-sva-mmdsp-ret",
2928                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2929                },
2930        },
2931        [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
2932                /* dependency to u8500-vape is handled outside regulator framework */
2933                .constraints = {
2934                        .name = "db8500-sva-pipe",
2935                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2936                },
2937                .consumer_supplies = db8500_svapipe_consumers,
2938                .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
2939        },
2940        [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
2941                /* dependency to u8500-vape is handled outside regulator framework */
2942                .constraints = {
2943                        .name = "db8500-sia-mmdsp",
2944                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2945                },
2946                .consumer_supplies = db8500_siammdsp_consumers,
2947                .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
2948        },
2949        [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
2950                .constraints = {
2951                        .name = "db8500-sia-mmdsp-ret",
2952                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2953                },
2954        },
2955        [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
2956                /* dependency to u8500-vape is handled outside regulator framework */
2957                .constraints = {
2958                        .name = "db8500-sia-pipe",
2959                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2960                },
2961                .consumer_supplies = db8500_siapipe_consumers,
2962                .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
2963        },
2964        [DB8500_REGULATOR_SWITCH_SGA] = {
2965                .supply_regulator = "db8500-vape",
2966                .constraints = {
2967                        .name = "db8500-sga",
2968                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2969                },
2970                .consumer_supplies = db8500_sga_consumers,
2971                .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
2972
2973        },
2974        [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
2975                .supply_regulator = "db8500-vape",
2976                .constraints = {
2977                        .name = "db8500-b2r2-mcde",
2978                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2979                },
2980                .consumer_supplies = db8500_b2r2_mcde_consumers,
2981                .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
2982        },
2983        [DB8500_REGULATOR_SWITCH_ESRAM12] = {
2984                /*
2985                 * esram12 is set in retention and supplied by Vsafe when Vape is off,
2986                 * no need to hold Vape
2987                 */
2988                .constraints = {
2989                        .name = "db8500-esram12",
2990                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2991                },
2992                .consumer_supplies = db8500_esram12_consumers,
2993                .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
2994        },
2995        [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
2996                .constraints = {
2997                        .name = "db8500-esram12-ret",
2998                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2999                },
3000        },
3001        [DB8500_REGULATOR_SWITCH_ESRAM34] = {
3002                /*
3003                 * esram34 is set in retention and supplied by Vsafe when Vape is off,
3004                 * no need to hold Vape
3005                 */
3006                .constraints = {
3007                        .name = "db8500-esram34",
3008                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3009                },
3010                .consumer_supplies = db8500_esram34_consumers,
3011                .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
3012        },
3013        [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
3014                .constraints = {
3015                        .name = "db8500-esram34-ret",
3016                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3017                },
3018        },
3019};
3020
3021static struct ux500_wdt_data db8500_wdt_pdata = {
3022        .timeout = 600, /* 10 minutes */
3023        .has_28_bits_resolution = true,
3024};
3025/*
3026 * Thermal Sensor
3027 */
3028
3029static struct resource db8500_thsens_resources[] = {
3030        {
3031                .name = "IRQ_HOTMON_LOW",
3032                .start  = IRQ_PRCMU_HOTMON_LOW,
3033                .end    = IRQ_PRCMU_HOTMON_LOW,
3034                .flags  = IORESOURCE_IRQ,
3035        },
3036        {
3037                .name = "IRQ_HOTMON_HIGH",
3038                .start  = IRQ_PRCMU_HOTMON_HIGH,
3039                .end    = IRQ_PRCMU_HOTMON_HIGH,
3040                .flags  = IORESOURCE_IRQ,
3041        },
3042};
3043
3044static struct db8500_thsens_platform_data db8500_thsens_data = {
3045        .trip_points[0] = {
3046                .temp = 70000,
3047                .type = THERMAL_TRIP_ACTIVE,
3048                .cdev_name = {
3049                        [0] = "thermal-cpufreq-0",
3050                },
3051        },
3052        .trip_points[1] = {
3053                .temp = 75000,
3054                .type = THERMAL_TRIP_ACTIVE,
3055                .cdev_name = {
3056                        [0] = "thermal-cpufreq-0",
3057                },
3058        },
3059        .trip_points[2] = {
3060                .temp = 80000,
3061                .type = THERMAL_TRIP_ACTIVE,
3062                .cdev_name = {
3063                        [0] = "thermal-cpufreq-0",
3064                },
3065        },
3066        .trip_points[3] = {
3067                .temp = 85000,
3068                .type = THERMAL_TRIP_CRITICAL,
3069        },
3070        .num_trips = 4,
3071};
3072
3073static struct mfd_cell common_prcmu_devs[] = {
3074        {
3075                .name = "ux500_wdt",
3076                .platform_data = &db8500_wdt_pdata,
3077                .pdata_size = sizeof(db8500_wdt_pdata),
3078                .id = -1,
3079        },
3080};
3081
3082static struct mfd_cell db8500_prcmu_devs[] = {
3083        {
3084                .name = "db8500-prcmu-regulators",
3085                .of_compatible = "stericsson,db8500-prcmu-regulator",
3086                .platform_data = &db8500_regulators,
3087                .pdata_size = sizeof(db8500_regulators),
3088        },
3089        {
3090                .name = "cpufreq-ux500",
3091                .of_compatible = "stericsson,cpufreq-ux500",
3092                .platform_data = &db8500_cpufreq_table,
3093                .pdata_size = sizeof(db8500_cpufreq_table),
3094        },
3095        {
3096                .name = "db8500-thermal",
3097                .num_resources = ARRAY_SIZE(db8500_thsens_resources),
3098                .resources = db8500_thsens_resources,
3099                .platform_data = &db8500_thsens_data,
3100                .pdata_size = sizeof(db8500_thsens_data),
3101        },
3102};
3103
3104static void db8500_prcmu_update_cpufreq(void)
3105{
3106        if (prcmu_has_arm_maxopp()) {
3107                db8500_cpufreq_table[3].frequency = 1000000;
3108                db8500_cpufreq_table[3].index = ARM_MAX_OPP;
3109        }
3110}
3111
3112static int db8500_prcmu_register_ab8500(struct device *parent,
3113                                        struct ab8500_platform_data *pdata,
3114                                        int irq)
3115{
3116        struct resource ab8500_resource = DEFINE_RES_IRQ(irq);
3117        struct mfd_cell ab8500_cell = {
3118                .name = "ab8500-core",
3119                .of_compatible = "stericsson,ab8500",
3120                .id = AB8500_VERSION_AB8500,
3121                .platform_data = pdata,
3122                .pdata_size = sizeof(struct ab8500_platform_data),
3123                .resources = &ab8500_resource,
3124                .num_resources = 1,
3125        };
3126
3127        return mfd_add_devices(parent, 0, &ab8500_cell, 1, NULL, 0, NULL);
3128}
3129
3130/**
3131 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
3132 *
3133 */
3134static int db8500_prcmu_probe(struct platform_device *pdev)
3135{
3136        struct device_node *np = pdev->dev.of_node;
3137        struct prcmu_pdata *pdata = dev_get_platdata(&pdev->dev);
3138        int irq = 0, err = 0;
3139        struct resource *res;
3140
3141        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu");
3142        if (!res) {
3143                dev_err(&pdev->dev, "no prcmu memory region provided\n");
3144                return -ENOENT;
3145        }
3146        prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
3147        if (!prcmu_base) {
3148                dev_err(&pdev->dev,
3149                        "failed to ioremap prcmu register memory\n");
3150                return -ENOENT;
3151        }
3152        init_prcm_registers();
3153        dbx500_fw_version_init(pdev, pdata->version_offset);
3154        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm");
3155        if (!res) {
3156                dev_err(&pdev->dev, "no prcmu tcdm region provided\n");
3157                return -ENOENT;
3158        }
3159        tcdm_base = devm_ioremap(&pdev->dev, res->start,
3160                        resource_size(res));
3161
3162        /* Clean up the mailbox interrupts after pre-kernel code. */
3163        writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
3164
3165        irq = platform_get_irq(pdev, 0);
3166        if (irq <= 0) {
3167                dev_err(&pdev->dev, "no prcmu irq provided\n");
3168                return -ENOENT;
3169        }
3170
3171        err = request_threaded_irq(irq, prcmu_irq_handler,
3172                prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
3173        if (err < 0) {
3174                pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
3175                err = -EBUSY;
3176                goto no_irq_return;
3177        }
3178
3179        db8500_irq_init(np, pdata->irq_base);
3180
3181        prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3182
3183        db8500_prcmu_update_cpufreq();
3184
3185        err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs,
3186                              ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain);
3187        if (err) {
3188                pr_err("prcmu: Failed to add subdevices\n");
3189                return err;
3190        }
3191
3192        /* TODO: Remove restriction when clk definitions are available. */
3193        if (!of_machine_is_compatible("st-ericsson,u8540")) {
3194                err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
3195                                      ARRAY_SIZE(db8500_prcmu_devs), NULL, 0,
3196                                      db8500_irq_domain);
3197                if (err) {
3198                        mfd_remove_devices(&pdev->dev);
3199                        pr_err("prcmu: Failed to add subdevices\n");
3200                        goto no_irq_return;
3201                }
3202        }
3203
3204        err = db8500_prcmu_register_ab8500(&pdev->dev, pdata->ab_platdata,
3205                                           pdata->ab_irq);
3206        if (err) {
3207                mfd_remove_devices(&pdev->dev);
3208                pr_err("prcmu: Failed to add ab8500 subdevice\n");
3209                goto no_irq_return;
3210        }
3211
3212        pr_info("DB8500 PRCMU initialized\n");
3213
3214no_irq_return:
3215        return err;
3216}
3217static const struct of_device_id db8500_prcmu_match[] = {
3218        { .compatible = "stericsson,db8500-prcmu"},
3219        { },
3220};
3221
3222static struct platform_driver db8500_prcmu_driver = {
3223        .driver = {
3224                .name = "db8500-prcmu",
3225                .owner = THIS_MODULE,
3226                .of_match_table = db8500_prcmu_match,
3227        },
3228        .probe = db8500_prcmu_probe,
3229};
3230
3231static int __init db8500_prcmu_init(void)
3232{
3233        return platform_driver_register(&db8500_prcmu_driver);
3234}
3235
3236core_initcall(db8500_prcmu_init);
3237
3238MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>");
3239MODULE_DESCRIPTION("DB8500 PRCM Unit driver");
3240MODULE_LICENSE("GPL v2");
3241
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