linux/drivers/irqchip/irq-sirfsoc.c
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   1/*
   2 * interrupt controller support for CSR SiRFprimaII
   3 *
   4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5 *
   6 * Licensed under GPLv2 or later.
   7 */
   8
   9#include <linux/init.h>
  10#include <linux/io.h>
  11#include <linux/irq.h>
  12#include <linux/of.h>
  13#include <linux/of_address.h>
  14#include <linux/irqdomain.h>
  15#include <linux/syscore_ops.h>
  16#include <asm/mach/irq.h>
  17#include <asm/exception.h>
  18#include "irqchip.h"
  19
  20#define SIRFSOC_INT_RISC_MASK0          0x0018
  21#define SIRFSOC_INT_RISC_MASK1          0x001C
  22#define SIRFSOC_INT_RISC_LEVEL0         0x0020
  23#define SIRFSOC_INT_RISC_LEVEL1         0x0024
  24#define SIRFSOC_INIT_IRQ_ID             0x0038
  25
  26#define SIRFSOC_NUM_IRQS                128
  27
  28static struct irq_domain *sirfsoc_irqdomain;
  29
  30static __init void
  31sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
  32{
  33        struct irq_chip_generic *gc;
  34        struct irq_chip_type *ct;
  35
  36        gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
  37        ct = gc->chip_types;
  38
  39        ct->chip.irq_mask = irq_gc_mask_clr_bit;
  40        ct->chip.irq_unmask = irq_gc_mask_set_bit;
  41        ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
  42
  43        irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
  44}
  45
  46static asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
  47{
  48        void __iomem *base = sirfsoc_irqdomain->host_data;
  49        u32 irqstat, irqnr;
  50
  51        irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
  52        irqnr = irq_find_mapping(sirfsoc_irqdomain, irqstat & 0xff);
  53
  54        handle_IRQ(irqnr, regs);
  55}
  56
  57static int __init sirfsoc_irq_init(struct device_node *np, struct device_node *parent)
  58{
  59        void __iomem *base = of_iomap(np, 0);
  60        if (!base)
  61                panic("unable to map intc cpu registers\n");
  62
  63        /* using legacy because irqchip_generic does not work with linear */
  64        sirfsoc_irqdomain = irq_domain_add_legacy(np, SIRFSOC_NUM_IRQS, 0, 0,
  65                                 &irq_domain_simple_ops, base);
  66
  67        sirfsoc_alloc_gc(base, 0, 32);
  68        sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32);
  69
  70        writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);
  71        writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);
  72
  73        writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);
  74        writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);
  75
  76        set_handle_irq(sirfsoc_handle_irq);
  77
  78        return 0;
  79}
  80IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);
  81
  82struct sirfsoc_irq_status {
  83        u32 mask0;
  84        u32 mask1;
  85        u32 level0;
  86        u32 level1;
  87};
  88
  89static struct sirfsoc_irq_status sirfsoc_irq_st;
  90
  91static int sirfsoc_irq_suspend(void)
  92{
  93        void __iomem *base = sirfsoc_irqdomain->host_data;
  94
  95        sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
  96        sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
  97        sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);
  98        sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);
  99
 100        return 0;
 101}
 102
 103static void sirfsoc_irq_resume(void)
 104{
 105        void __iomem *base = sirfsoc_irqdomain->host_data;
 106
 107        writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
 108        writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
 109        writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);
 110        writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);
 111}
 112
 113static struct syscore_ops sirfsoc_irq_syscore_ops = {
 114        .suspend        = sirfsoc_irq_suspend,
 115        .resume         = sirfsoc_irq_resume,
 116};
 117
 118static int __init sirfsoc_irq_pm_init(void)
 119{
 120        if (!sirfsoc_irqdomain)
 121                return 0;
 122
 123        register_syscore_ops(&sirfsoc_irq_syscore_ops);
 124        return 0;
 125}
 126device_initcall(sirfsoc_irq_pm_init);
 127
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