linux/drivers/iommu/amd_iommu_init.c
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   1/*
   2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
   3 * Author: Joerg Roedel <joerg.roedel@amd.com>
   4 *         Leo Duran <leo.duran@amd.com>
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms of the GNU General Public License version 2 as published
   8 * by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18 */
  19
  20#include <linux/pci.h>
  21#include <linux/acpi.h>
  22#include <linux/list.h>
  23#include <linux/slab.h>
  24#include <linux/syscore_ops.h>
  25#include <linux/interrupt.h>
  26#include <linux/msi.h>
  27#include <linux/amd-iommu.h>
  28#include <linux/export.h>
  29#include <acpi/acpi.h>
  30#include <asm/pci-direct.h>
  31#include <asm/iommu.h>
  32#include <asm/gart.h>
  33#include <asm/x86_init.h>
  34#include <asm/iommu_table.h>
  35#include <asm/io_apic.h>
  36#include <asm/irq_remapping.h>
  37
  38#include "amd_iommu_proto.h"
  39#include "amd_iommu_types.h"
  40#include "irq_remapping.h"
  41
  42/*
  43 * definitions for the ACPI scanning code
  44 */
  45#define IVRS_HEADER_LENGTH 48
  46
  47#define ACPI_IVHD_TYPE                  0x10
  48#define ACPI_IVMD_TYPE_ALL              0x20
  49#define ACPI_IVMD_TYPE                  0x21
  50#define ACPI_IVMD_TYPE_RANGE            0x22
  51
  52#define IVHD_DEV_ALL                    0x01
  53#define IVHD_DEV_SELECT                 0x02
  54#define IVHD_DEV_SELECT_RANGE_START     0x03
  55#define IVHD_DEV_RANGE_END              0x04
  56#define IVHD_DEV_ALIAS                  0x42
  57#define IVHD_DEV_ALIAS_RANGE            0x43
  58#define IVHD_DEV_EXT_SELECT             0x46
  59#define IVHD_DEV_EXT_SELECT_RANGE       0x47
  60#define IVHD_DEV_SPECIAL                0x48
  61
  62#define IVHD_SPECIAL_IOAPIC             1
  63#define IVHD_SPECIAL_HPET               2
  64
  65#define IVHD_FLAG_HT_TUN_EN_MASK        0x01
  66#define IVHD_FLAG_PASSPW_EN_MASK        0x02
  67#define IVHD_FLAG_RESPASSPW_EN_MASK     0x04
  68#define IVHD_FLAG_ISOC_EN_MASK          0x08
  69
  70#define IVMD_FLAG_EXCL_RANGE            0x08
  71#define IVMD_FLAG_UNITY_MAP             0x01
  72
  73#define ACPI_DEVFLAG_INITPASS           0x01
  74#define ACPI_DEVFLAG_EXTINT             0x02
  75#define ACPI_DEVFLAG_NMI                0x04
  76#define ACPI_DEVFLAG_SYSMGT1            0x10
  77#define ACPI_DEVFLAG_SYSMGT2            0x20
  78#define ACPI_DEVFLAG_LINT0              0x40
  79#define ACPI_DEVFLAG_LINT1              0x80
  80#define ACPI_DEVFLAG_ATSDIS             0x10000000
  81
  82/*
  83 * ACPI table definitions
  84 *
  85 * These data structures are laid over the table to parse the important values
  86 * out of it.
  87 */
  88
  89/*
  90 * structure describing one IOMMU in the ACPI table. Typically followed by one
  91 * or more ivhd_entrys.
  92 */
  93struct ivhd_header {
  94        u8 type;
  95        u8 flags;
  96        u16 length;
  97        u16 devid;
  98        u16 cap_ptr;
  99        u64 mmio_phys;
 100        u16 pci_seg;
 101        u16 info;
 102        u32 reserved;
 103} __attribute__((packed));
 104
 105/*
 106 * A device entry describing which devices a specific IOMMU translates and
 107 * which requestor ids they use.
 108 */
 109struct ivhd_entry {
 110        u8 type;
 111        u16 devid;
 112        u8 flags;
 113        u32 ext;
 114} __attribute__((packed));
 115
 116/*
 117 * An AMD IOMMU memory definition structure. It defines things like exclusion
 118 * ranges for devices and regions that should be unity mapped.
 119 */
 120struct ivmd_header {
 121        u8 type;
 122        u8 flags;
 123        u16 length;
 124        u16 devid;
 125        u16 aux;
 126        u64 resv;
 127        u64 range_start;
 128        u64 range_length;
 129} __attribute__((packed));
 130
 131bool amd_iommu_dump;
 132bool amd_iommu_irq_remap __read_mostly;
 133
 134static bool amd_iommu_detected;
 135static bool __initdata amd_iommu_disabled;
 136
 137u16 amd_iommu_last_bdf;                 /* largest PCI device id we have
 138                                           to handle */
 139LIST_HEAD(amd_iommu_unity_map);         /* a list of required unity mappings
 140                                           we find in ACPI */
 141u32 amd_iommu_unmap_flush;              /* if true, flush on every unmap */
 142
 143LIST_HEAD(amd_iommu_list);              /* list of all AMD IOMMUs in the
 144                                           system */
 145
 146/* Array to assign indices to IOMMUs*/
 147struct amd_iommu *amd_iommus[MAX_IOMMUS];
 148int amd_iommus_present;
 149
 150/* IOMMUs have a non-present cache? */
 151bool amd_iommu_np_cache __read_mostly;
 152bool amd_iommu_iotlb_sup __read_mostly = true;
 153
 154u32 amd_iommu_max_pasids __read_mostly = ~0;
 155
 156bool amd_iommu_v2_present __read_mostly;
 157
 158bool amd_iommu_force_isolation __read_mostly;
 159
 160/*
 161 * List of protection domains - used during resume
 162 */
 163LIST_HEAD(amd_iommu_pd_list);
 164spinlock_t amd_iommu_pd_lock;
 165
 166/*
 167 * Pointer to the device table which is shared by all AMD IOMMUs
 168 * it is indexed by the PCI device id or the HT unit id and contains
 169 * information about the domain the device belongs to as well as the
 170 * page table root pointer.
 171 */
 172struct dev_table_entry *amd_iommu_dev_table;
 173
 174/*
 175 * The alias table is a driver specific data structure which contains the
 176 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
 177 * More than one device can share the same requestor id.
 178 */
 179u16 *amd_iommu_alias_table;
 180
 181/*
 182 * The rlookup table is used to find the IOMMU which is responsible
 183 * for a specific device. It is also indexed by the PCI device id.
 184 */
 185struct amd_iommu **amd_iommu_rlookup_table;
 186
 187/*
 188 * This table is used to find the irq remapping table for a given device id
 189 * quickly.
 190 */
 191struct irq_remap_table **irq_lookup_table;
 192
 193/*
 194 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
 195 * to know which ones are already in use.
 196 */
 197unsigned long *amd_iommu_pd_alloc_bitmap;
 198
 199static u32 dev_table_size;      /* size of the device table */
 200static u32 alias_table_size;    /* size of the alias table */
 201static u32 rlookup_table_size;  /* size if the rlookup table */
 202
 203enum iommu_init_state {
 204        IOMMU_START_STATE,
 205        IOMMU_IVRS_DETECTED,
 206        IOMMU_ACPI_FINISHED,
 207        IOMMU_ENABLED,
 208        IOMMU_PCI_INIT,
 209        IOMMU_INTERRUPTS_EN,
 210        IOMMU_DMA_OPS,
 211        IOMMU_INITIALIZED,
 212        IOMMU_NOT_FOUND,
 213        IOMMU_INIT_ERROR,
 214};
 215
 216/* Early ioapic and hpet maps from kernel command line */
 217#define EARLY_MAP_SIZE          4
 218static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
 219static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
 220static int __initdata early_ioapic_map_size;
 221static int __initdata early_hpet_map_size;
 222static bool __initdata cmdline_maps;
 223
 224static enum iommu_init_state init_state = IOMMU_START_STATE;
 225
 226static int amd_iommu_enable_interrupts(void);
 227static int __init iommu_go_to_state(enum iommu_init_state state);
 228
 229static inline void update_last_devid(u16 devid)
 230{
 231        if (devid > amd_iommu_last_bdf)
 232                amd_iommu_last_bdf = devid;
 233}
 234
 235static inline unsigned long tbl_size(int entry_size)
 236{
 237        unsigned shift = PAGE_SHIFT +
 238                         get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
 239
 240        return 1UL << shift;
 241}
 242
 243/* Access to l1 and l2 indexed register spaces */
 244
 245static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
 246{
 247        u32 val;
 248
 249        pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
 250        pci_read_config_dword(iommu->dev, 0xfc, &val);
 251        return val;
 252}
 253
 254static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
 255{
 256        pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
 257        pci_write_config_dword(iommu->dev, 0xfc, val);
 258        pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
 259}
 260
 261static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
 262{
 263        u32 val;
 264
 265        pci_write_config_dword(iommu->dev, 0xf0, address);
 266        pci_read_config_dword(iommu->dev, 0xf4, &val);
 267        return val;
 268}
 269
 270static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
 271{
 272        pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
 273        pci_write_config_dword(iommu->dev, 0xf4, val);
 274}
 275
 276/****************************************************************************
 277 *
 278 * AMD IOMMU MMIO register space handling functions
 279 *
 280 * These functions are used to program the IOMMU device registers in
 281 * MMIO space required for that driver.
 282 *
 283 ****************************************************************************/
 284
 285/*
 286 * This function set the exclusion range in the IOMMU. DMA accesses to the
 287 * exclusion range are passed through untranslated
 288 */
 289static void iommu_set_exclusion_range(struct amd_iommu *iommu)
 290{
 291        u64 start = iommu->exclusion_start & PAGE_MASK;
 292        u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
 293        u64 entry;
 294
 295        if (!iommu->exclusion_start)
 296                return;
 297
 298        entry = start | MMIO_EXCL_ENABLE_MASK;
 299        memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
 300                        &entry, sizeof(entry));
 301
 302        entry = limit;
 303        memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
 304                        &entry, sizeof(entry));
 305}
 306
 307/* Programs the physical address of the device table into the IOMMU hardware */
 308static void iommu_set_device_table(struct amd_iommu *iommu)
 309{
 310        u64 entry;
 311
 312        BUG_ON(iommu->mmio_base == NULL);
 313
 314        entry = virt_to_phys(amd_iommu_dev_table);
 315        entry |= (dev_table_size >> 12) - 1;
 316        memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
 317                        &entry, sizeof(entry));
 318}
 319
 320/* Generic functions to enable/disable certain features of the IOMMU. */
 321static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
 322{
 323        u32 ctrl;
 324
 325        ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
 326        ctrl |= (1 << bit);
 327        writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
 328}
 329
 330static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
 331{
 332        u32 ctrl;
 333
 334        ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
 335        ctrl &= ~(1 << bit);
 336        writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
 337}
 338
 339static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
 340{
 341        u32 ctrl;
 342
 343        ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
 344        ctrl &= ~CTRL_INV_TO_MASK;
 345        ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
 346        writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
 347}
 348
 349/* Function to enable the hardware */
 350static void iommu_enable(struct amd_iommu *iommu)
 351{
 352        iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
 353}
 354
 355static void iommu_disable(struct amd_iommu *iommu)
 356{
 357        /* Disable command buffer */
 358        iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
 359
 360        /* Disable event logging and event interrupts */
 361        iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
 362        iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
 363
 364        /* Disable IOMMU hardware itself */
 365        iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
 366}
 367
 368/*
 369 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
 370 * the system has one.
 371 */
 372static u8 __iomem * __init iommu_map_mmio_space(u64 address)
 373{
 374        if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) {
 375                pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n",
 376                        address);
 377                pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
 378                return NULL;
 379        }
 380
 381        return (u8 __iomem *)ioremap_nocache(address, MMIO_REGION_LENGTH);
 382}
 383
 384static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
 385{
 386        if (iommu->mmio_base)
 387                iounmap(iommu->mmio_base);
 388        release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
 389}
 390
 391/****************************************************************************
 392 *
 393 * The functions below belong to the first pass of AMD IOMMU ACPI table
 394 * parsing. In this pass we try to find out the highest device id this
 395 * code has to handle. Upon this information the size of the shared data
 396 * structures is determined later.
 397 *
 398 ****************************************************************************/
 399
 400/*
 401 * This function calculates the length of a given IVHD entry
 402 */
 403static inline int ivhd_entry_length(u8 *ivhd)
 404{
 405        return 0x04 << (*ivhd >> 6);
 406}
 407
 408/*
 409 * This function reads the last device id the IOMMU has to handle from the PCI
 410 * capability header for this IOMMU
 411 */
 412static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
 413{
 414        u32 cap;
 415
 416        cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
 417        update_last_devid(PCI_DEVID(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
 418
 419        return 0;
 420}
 421
 422/*
 423 * After reading the highest device id from the IOMMU PCI capability header
 424 * this function looks if there is a higher device id defined in the ACPI table
 425 */
 426static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
 427{
 428        u8 *p = (void *)h, *end = (void *)h;
 429        struct ivhd_entry *dev;
 430
 431        p += sizeof(*h);
 432        end += h->length;
 433
 434        find_last_devid_on_pci(PCI_BUS_NUM(h->devid),
 435                        PCI_SLOT(h->devid),
 436                        PCI_FUNC(h->devid),
 437                        h->cap_ptr);
 438
 439        while (p < end) {
 440                dev = (struct ivhd_entry *)p;
 441                switch (dev->type) {
 442                case IVHD_DEV_SELECT:
 443                case IVHD_DEV_RANGE_END:
 444                case IVHD_DEV_ALIAS:
 445                case IVHD_DEV_EXT_SELECT:
 446                        /* all the above subfield types refer to device ids */
 447                        update_last_devid(dev->devid);
 448                        break;
 449                default:
 450                        break;
 451                }
 452                p += ivhd_entry_length(p);
 453        }
 454
 455        WARN_ON(p != end);
 456
 457        return 0;
 458}
 459
 460/*
 461 * Iterate over all IVHD entries in the ACPI table and find the highest device
 462 * id which we need to handle. This is the first of three functions which parse
 463 * the ACPI table. So we check the checksum here.
 464 */
 465static int __init find_last_devid_acpi(struct acpi_table_header *table)
 466{
 467        int i;
 468        u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
 469        struct ivhd_header *h;
 470
 471        /*
 472         * Validate checksum here so we don't need to do it when
 473         * we actually parse the table
 474         */
 475        for (i = 0; i < table->length; ++i)
 476                checksum += p[i];
 477        if (checksum != 0)
 478                /* ACPI table corrupt */
 479                return -ENODEV;
 480
 481        p += IVRS_HEADER_LENGTH;
 482
 483        end += table->length;
 484        while (p < end) {
 485                h = (struct ivhd_header *)p;
 486                switch (h->type) {
 487                case ACPI_IVHD_TYPE:
 488                        find_last_devid_from_ivhd(h);
 489                        break;
 490                default:
 491                        break;
 492                }
 493                p += h->length;
 494        }
 495        WARN_ON(p != end);
 496
 497        return 0;
 498}
 499
 500/****************************************************************************
 501 *
 502 * The following functions belong to the code path which parses the ACPI table
 503 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
 504 * data structures, initialize the device/alias/rlookup table and also
 505 * basically initialize the hardware.
 506 *
 507 ****************************************************************************/
 508
 509/*
 510 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
 511 * write commands to that buffer later and the IOMMU will execute them
 512 * asynchronously
 513 */
 514static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
 515{
 516        u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
 517                        get_order(CMD_BUFFER_SIZE));
 518
 519        if (cmd_buf == NULL)
 520                return NULL;
 521
 522        iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED;
 523
 524        return cmd_buf;
 525}
 526
 527/*
 528 * This function resets the command buffer if the IOMMU stopped fetching
 529 * commands from it.
 530 */
 531void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
 532{
 533        iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
 534
 535        writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
 536        writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
 537
 538        iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
 539}
 540
 541/*
 542 * This function writes the command buffer address to the hardware and
 543 * enables it.
 544 */
 545static void iommu_enable_command_buffer(struct amd_iommu *iommu)
 546{
 547        u64 entry;
 548
 549        BUG_ON(iommu->cmd_buf == NULL);
 550
 551        entry = (u64)virt_to_phys(iommu->cmd_buf);
 552        entry |= MMIO_CMD_SIZE_512;
 553
 554        memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
 555                    &entry, sizeof(entry));
 556
 557        amd_iommu_reset_cmd_buffer(iommu);
 558        iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED);
 559}
 560
 561static void __init free_command_buffer(struct amd_iommu *iommu)
 562{
 563        free_pages((unsigned long)iommu->cmd_buf,
 564                   get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED)));
 565}
 566
 567/* allocates the memory where the IOMMU will log its events to */
 568static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
 569{
 570        iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
 571                                                get_order(EVT_BUFFER_SIZE));
 572
 573        if (iommu->evt_buf == NULL)
 574                return NULL;
 575
 576        iommu->evt_buf_size = EVT_BUFFER_SIZE;
 577
 578        return iommu->evt_buf;
 579}
 580
 581static void iommu_enable_event_buffer(struct amd_iommu *iommu)
 582{
 583        u64 entry;
 584
 585        BUG_ON(iommu->evt_buf == NULL);
 586
 587        entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
 588
 589        memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
 590                    &entry, sizeof(entry));
 591
 592        /* set head and tail to zero manually */
 593        writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
 594        writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
 595
 596        iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
 597}
 598
 599static void __init free_event_buffer(struct amd_iommu *iommu)
 600{
 601        free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
 602}
 603
 604/* allocates the memory where the IOMMU will log its events to */
 605static u8 * __init alloc_ppr_log(struct amd_iommu *iommu)
 606{
 607        iommu->ppr_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
 608                                                get_order(PPR_LOG_SIZE));
 609
 610        if (iommu->ppr_log == NULL)
 611                return NULL;
 612
 613        return iommu->ppr_log;
 614}
 615
 616static void iommu_enable_ppr_log(struct amd_iommu *iommu)
 617{
 618        u64 entry;
 619
 620        if (iommu->ppr_log == NULL)
 621                return;
 622
 623        entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
 624
 625        memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
 626                    &entry, sizeof(entry));
 627
 628        /* set head and tail to zero manually */
 629        writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
 630        writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
 631
 632        iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
 633        iommu_feature_enable(iommu, CONTROL_PPR_EN);
 634}
 635
 636static void __init free_ppr_log(struct amd_iommu *iommu)
 637{
 638        if (iommu->ppr_log == NULL)
 639                return;
 640
 641        free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
 642}
 643
 644static void iommu_enable_gt(struct amd_iommu *iommu)
 645{
 646        if (!iommu_feature(iommu, FEATURE_GT))
 647                return;
 648
 649        iommu_feature_enable(iommu, CONTROL_GT_EN);
 650}
 651
 652/* sets a specific bit in the device table entry. */
 653static void set_dev_entry_bit(u16 devid, u8 bit)
 654{
 655        int i = (bit >> 6) & 0x03;
 656        int _bit = bit & 0x3f;
 657
 658        amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
 659}
 660
 661static int get_dev_entry_bit(u16 devid, u8 bit)
 662{
 663        int i = (bit >> 6) & 0x03;
 664        int _bit = bit & 0x3f;
 665
 666        return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
 667}
 668
 669
 670void amd_iommu_apply_erratum_63(u16 devid)
 671{
 672        int sysmgt;
 673
 674        sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
 675                 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
 676
 677        if (sysmgt == 0x01)
 678                set_dev_entry_bit(devid, DEV_ENTRY_IW);
 679}
 680
 681/* Writes the specific IOMMU for a device into the rlookup table */
 682static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
 683{
 684        amd_iommu_rlookup_table[devid] = iommu;
 685}
 686
 687/*
 688 * This function takes the device specific flags read from the ACPI
 689 * table and sets up the device table entry with that information
 690 */
 691static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
 692                                           u16 devid, u32 flags, u32 ext_flags)
 693{
 694        if (flags & ACPI_DEVFLAG_INITPASS)
 695                set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
 696        if (flags & ACPI_DEVFLAG_EXTINT)
 697                set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
 698        if (flags & ACPI_DEVFLAG_NMI)
 699                set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
 700        if (flags & ACPI_DEVFLAG_SYSMGT1)
 701                set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
 702        if (flags & ACPI_DEVFLAG_SYSMGT2)
 703                set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
 704        if (flags & ACPI_DEVFLAG_LINT0)
 705                set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
 706        if (flags & ACPI_DEVFLAG_LINT1)
 707                set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
 708
 709        amd_iommu_apply_erratum_63(devid);
 710
 711        set_iommu_for_device(iommu, devid);
 712}
 713
 714static int __init add_special_device(u8 type, u8 id, u16 devid, bool cmd_line)
 715{
 716        struct devid_map *entry;
 717        struct list_head *list;
 718
 719        if (type == IVHD_SPECIAL_IOAPIC)
 720                list = &ioapic_map;
 721        else if (type == IVHD_SPECIAL_HPET)
 722                list = &hpet_map;
 723        else
 724                return -EINVAL;
 725
 726        list_for_each_entry(entry, list, list) {
 727                if (!(entry->id == id && entry->cmd_line))
 728                        continue;
 729
 730                pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
 731                        type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
 732
 733                return 0;
 734        }
 735
 736        entry = kzalloc(sizeof(*entry), GFP_KERNEL);
 737        if (!entry)
 738                return -ENOMEM;
 739
 740        entry->id       = id;
 741        entry->devid    = devid;
 742        entry->cmd_line = cmd_line;
 743
 744        list_add_tail(&entry->list, list);
 745
 746        return 0;
 747}
 748
 749static int __init add_early_maps(void)
 750{
 751        int i, ret;
 752
 753        for (i = 0; i < early_ioapic_map_size; ++i) {
 754                ret = add_special_device(IVHD_SPECIAL_IOAPIC,
 755                                         early_ioapic_map[i].id,
 756                                         early_ioapic_map[i].devid,
 757                                         early_ioapic_map[i].cmd_line);
 758                if (ret)
 759                        return ret;
 760        }
 761
 762        for (i = 0; i < early_hpet_map_size; ++i) {
 763                ret = add_special_device(IVHD_SPECIAL_HPET,
 764                                         early_hpet_map[i].id,
 765                                         early_hpet_map[i].devid,
 766                                         early_hpet_map[i].cmd_line);
 767                if (ret)
 768                        return ret;
 769        }
 770
 771        return 0;
 772}
 773
 774/*
 775 * Reads the device exclusion range from ACPI and initializes the IOMMU with
 776 * it
 777 */
 778static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
 779{
 780        struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
 781
 782        if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
 783                return;
 784
 785        if (iommu) {
 786                /*
 787                 * We only can configure exclusion ranges per IOMMU, not
 788                 * per device. But we can enable the exclusion range per
 789                 * device. This is done here
 790                 */
 791                set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
 792                iommu->exclusion_start = m->range_start;
 793                iommu->exclusion_length = m->range_length;
 794        }
 795}
 796
 797/*
 798 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
 799 * initializes the hardware and our data structures with it.
 800 */
 801static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
 802                                        struct ivhd_header *h)
 803{
 804        u8 *p = (u8 *)h;
 805        u8 *end = p, flags = 0;
 806        u16 devid = 0, devid_start = 0, devid_to = 0;
 807        u32 dev_i, ext_flags = 0;
 808        bool alias = false;
 809        struct ivhd_entry *e;
 810        int ret;
 811
 812
 813        ret = add_early_maps();
 814        if (ret)
 815                return ret;
 816
 817        /*
 818         * First save the recommended feature enable bits from ACPI
 819         */
 820        iommu->acpi_flags = h->flags;
 821
 822        /*
 823         * Done. Now parse the device entries
 824         */
 825        p += sizeof(struct ivhd_header);
 826        end += h->length;
 827
 828
 829        while (p < end) {
 830                e = (struct ivhd_entry *)p;
 831                switch (e->type) {
 832                case IVHD_DEV_ALL:
 833
 834                        DUMP_printk("  DEV_ALL\t\t\t first devid: %02x:%02x.%x"
 835                                    " last device %02x:%02x.%x flags: %02x\n",
 836                                    PCI_BUS_NUM(iommu->first_device),
 837                                    PCI_SLOT(iommu->first_device),
 838                                    PCI_FUNC(iommu->first_device),
 839                                    PCI_BUS_NUM(iommu->last_device),
 840                                    PCI_SLOT(iommu->last_device),
 841                                    PCI_FUNC(iommu->last_device),
 842                                    e->flags);
 843
 844                        for (dev_i = iommu->first_device;
 845                                        dev_i <= iommu->last_device; ++dev_i)
 846                                set_dev_entry_from_acpi(iommu, dev_i,
 847                                                        e->flags, 0);
 848                        break;
 849                case IVHD_DEV_SELECT:
 850
 851                        DUMP_printk("  DEV_SELECT\t\t\t devid: %02x:%02x.%x "
 852                                    "flags: %02x\n",
 853                                    PCI_BUS_NUM(e->devid),
 854                                    PCI_SLOT(e->devid),
 855                                    PCI_FUNC(e->devid),
 856                                    e->flags);
 857
 858                        devid = e->devid;
 859                        set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
 860                        break;
 861                case IVHD_DEV_SELECT_RANGE_START:
 862
 863                        DUMP_printk("  DEV_SELECT_RANGE_START\t "
 864                                    "devid: %02x:%02x.%x flags: %02x\n",
 865                                    PCI_BUS_NUM(e->devid),
 866                                    PCI_SLOT(e->devid),
 867                                    PCI_FUNC(e->devid),
 868                                    e->flags);
 869
 870                        devid_start = e->devid;
 871                        flags = e->flags;
 872                        ext_flags = 0;
 873                        alias = false;
 874                        break;
 875                case IVHD_DEV_ALIAS:
 876
 877                        DUMP_printk("  DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
 878                                    "flags: %02x devid_to: %02x:%02x.%x\n",
 879                                    PCI_BUS_NUM(e->devid),
 880                                    PCI_SLOT(e->devid),
 881                                    PCI_FUNC(e->devid),
 882                                    e->flags,
 883                                    PCI_BUS_NUM(e->ext >> 8),
 884                                    PCI_SLOT(e->ext >> 8),
 885                                    PCI_FUNC(e->ext >> 8));
 886
 887                        devid = e->devid;
 888                        devid_to = e->ext >> 8;
 889                        set_dev_entry_from_acpi(iommu, devid   , e->flags, 0);
 890                        set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
 891                        amd_iommu_alias_table[devid] = devid_to;
 892                        break;
 893                case IVHD_DEV_ALIAS_RANGE:
 894
 895                        DUMP_printk("  DEV_ALIAS_RANGE\t\t "
 896                                    "devid: %02x:%02x.%x flags: %02x "
 897                                    "devid_to: %02x:%02x.%x\n",
 898                                    PCI_BUS_NUM(e->devid),
 899                                    PCI_SLOT(e->devid),
 900                                    PCI_FUNC(e->devid),
 901                                    e->flags,
 902                                    PCI_BUS_NUM(e->ext >> 8),
 903                                    PCI_SLOT(e->ext >> 8),
 904                                    PCI_FUNC(e->ext >> 8));
 905
 906                        devid_start = e->devid;
 907                        flags = e->flags;
 908                        devid_to = e->ext >> 8;
 909                        ext_flags = 0;
 910                        alias = true;
 911                        break;
 912                case IVHD_DEV_EXT_SELECT:
 913
 914                        DUMP_printk("  DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
 915                                    "flags: %02x ext: %08x\n",
 916                                    PCI_BUS_NUM(e->devid),
 917                                    PCI_SLOT(e->devid),
 918                                    PCI_FUNC(e->devid),
 919                                    e->flags, e->ext);
 920
 921                        devid = e->devid;
 922                        set_dev_entry_from_acpi(iommu, devid, e->flags,
 923                                                e->ext);
 924                        break;
 925                case IVHD_DEV_EXT_SELECT_RANGE:
 926
 927                        DUMP_printk("  DEV_EXT_SELECT_RANGE\t devid: "
 928                                    "%02x:%02x.%x flags: %02x ext: %08x\n",
 929                                    PCI_BUS_NUM(e->devid),
 930                                    PCI_SLOT(e->devid),
 931                                    PCI_FUNC(e->devid),
 932                                    e->flags, e->ext);
 933
 934                        devid_start = e->devid;
 935                        flags = e->flags;
 936                        ext_flags = e->ext;
 937                        alias = false;
 938                        break;
 939                case IVHD_DEV_RANGE_END:
 940
 941                        DUMP_printk("  DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
 942                                    PCI_BUS_NUM(e->devid),
 943                                    PCI_SLOT(e->devid),
 944                                    PCI_FUNC(e->devid));
 945
 946                        devid = e->devid;
 947                        for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
 948                                if (alias) {
 949                                        amd_iommu_alias_table[dev_i] = devid_to;
 950                                        set_dev_entry_from_acpi(iommu,
 951                                                devid_to, flags, ext_flags);
 952                                }
 953                                set_dev_entry_from_acpi(iommu, dev_i,
 954                                                        flags, ext_flags);
 955                        }
 956                        break;
 957                case IVHD_DEV_SPECIAL: {
 958                        u8 handle, type;
 959                        const char *var;
 960                        u16 devid;
 961                        int ret;
 962
 963                        handle = e->ext & 0xff;
 964                        devid  = (e->ext >>  8) & 0xffff;
 965                        type   = (e->ext >> 24) & 0xff;
 966
 967                        if (type == IVHD_SPECIAL_IOAPIC)
 968                                var = "IOAPIC";
 969                        else if (type == IVHD_SPECIAL_HPET)
 970                                var = "HPET";
 971                        else
 972                                var = "UNKNOWN";
 973
 974                        DUMP_printk("  DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
 975                                    var, (int)handle,
 976                                    PCI_BUS_NUM(devid),
 977                                    PCI_SLOT(devid),
 978                                    PCI_FUNC(devid));
 979
 980                        set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
 981                        ret = add_special_device(type, handle, devid, false);
 982                        if (ret)
 983                                return ret;
 984                        break;
 985                }
 986                default:
 987                        break;
 988                }
 989
 990                p += ivhd_entry_length(p);
 991        }
 992
 993        return 0;
 994}
 995
 996/* Initializes the device->iommu mapping for the driver */
 997static int __init init_iommu_devices(struct amd_iommu *iommu)
 998{
 999        u32 i;
1000
1001        for (i = iommu->first_device; i <= iommu->last_device; ++i)
1002                set_iommu_for_device(iommu, i);
1003
1004        return 0;
1005}
1006
1007static void __init free_iommu_one(struct amd_iommu *iommu)
1008{
1009        free_command_buffer(iommu);
1010        free_event_buffer(iommu);
1011        free_ppr_log(iommu);
1012        iommu_unmap_mmio_space(iommu);
1013}
1014
1015static void __init free_iommu_all(void)
1016{
1017        struct amd_iommu *iommu, *next;
1018
1019        for_each_iommu_safe(iommu, next) {
1020                list_del(&iommu->list);
1021                free_iommu_one(iommu);
1022                kfree(iommu);
1023        }
1024}
1025
1026/*
1027 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1028 * Workaround:
1029 *     BIOS should disable L2B micellaneous clock gating by setting
1030 *     L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1031 */
1032static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1033{
1034        u32 value;
1035
1036        if ((boot_cpu_data.x86 != 0x15) ||
1037            (boot_cpu_data.x86_model < 0x10) ||
1038            (boot_cpu_data.x86_model > 0x1f))
1039                return;
1040
1041        pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1042        pci_read_config_dword(iommu->dev, 0xf4, &value);
1043
1044        if (value & BIT(2))
1045                return;
1046
1047        /* Select NB indirect register 0x90 and enable writing */
1048        pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1049
1050        pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1051        pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1052                dev_name(&iommu->dev->dev));
1053
1054        /* Clear the enable writing bit */
1055        pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1056}
1057
1058/*
1059 * This function clues the initialization function for one IOMMU
1060 * together and also allocates the command buffer and programs the
1061 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1062 */
1063static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1064{
1065        int ret;
1066
1067        spin_lock_init(&iommu->lock);
1068
1069        /* Add IOMMU to internal data structures */
1070        list_add_tail(&iommu->list, &amd_iommu_list);
1071        iommu->index             = amd_iommus_present++;
1072
1073        if (unlikely(iommu->index >= MAX_IOMMUS)) {
1074                WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1075                return -ENOSYS;
1076        }
1077
1078        /* Index is fine - add IOMMU to the array */
1079        amd_iommus[iommu->index] = iommu;
1080
1081        /*
1082         * Copy data from ACPI table entry to the iommu struct
1083         */
1084        iommu->devid   = h->devid;
1085        iommu->cap_ptr = h->cap_ptr;
1086        iommu->pci_seg = h->pci_seg;
1087        iommu->mmio_phys = h->mmio_phys;
1088        iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
1089        if (!iommu->mmio_base)
1090                return -ENOMEM;
1091
1092        iommu->cmd_buf = alloc_command_buffer(iommu);
1093        if (!iommu->cmd_buf)
1094                return -ENOMEM;
1095
1096        iommu->evt_buf = alloc_event_buffer(iommu);
1097        if (!iommu->evt_buf)
1098                return -ENOMEM;
1099
1100        iommu->int_enabled = false;
1101
1102        ret = init_iommu_from_acpi(iommu, h);
1103        if (ret)
1104                return ret;
1105
1106        /*
1107         * Make sure IOMMU is not considered to translate itself. The IVRS
1108         * table tells us so, but this is a lie!
1109         */
1110        amd_iommu_rlookup_table[iommu->devid] = NULL;
1111
1112        init_iommu_devices(iommu);
1113
1114        return 0;
1115}
1116
1117/*
1118 * Iterates over all IOMMU entries in the ACPI table, allocates the
1119 * IOMMU structure and initializes it with init_iommu_one()
1120 */
1121static int __init init_iommu_all(struct acpi_table_header *table)
1122{
1123        u8 *p = (u8 *)table, *end = (u8 *)table;
1124        struct ivhd_header *h;
1125        struct amd_iommu *iommu;
1126        int ret;
1127
1128        end += table->length;
1129        p += IVRS_HEADER_LENGTH;
1130
1131        while (p < end) {
1132                h = (struct ivhd_header *)p;
1133                switch (*p) {
1134                case ACPI_IVHD_TYPE:
1135
1136                        DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1137                                    "seg: %d flags: %01x info %04x\n",
1138                                    PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
1139                                    PCI_FUNC(h->devid), h->cap_ptr,
1140                                    h->pci_seg, h->flags, h->info);
1141                        DUMP_printk("       mmio-addr: %016llx\n",
1142                                    h->mmio_phys);
1143
1144                        iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1145                        if (iommu == NULL)
1146                                return -ENOMEM;
1147
1148                        ret = init_iommu_one(iommu, h);
1149                        if (ret)
1150                                return ret;
1151                        break;
1152                default:
1153                        break;
1154                }
1155                p += h->length;
1156
1157        }
1158        WARN_ON(p != end);
1159
1160        return 0;
1161}
1162
1163static int iommu_init_pci(struct amd_iommu *iommu)
1164{
1165        int cap_ptr = iommu->cap_ptr;
1166        u32 range, misc, low, high;
1167
1168        iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
1169                                          iommu->devid & 0xff);
1170        if (!iommu->dev)
1171                return -ENODEV;
1172
1173        pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1174                              &iommu->cap);
1175        pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1176                              &range);
1177        pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1178                              &misc);
1179
1180        iommu->first_device = PCI_DEVID(MMIO_GET_BUS(range),
1181                                         MMIO_GET_FD(range));
1182        iommu->last_device = PCI_DEVID(MMIO_GET_BUS(range),
1183                                        MMIO_GET_LD(range));
1184
1185        if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1186                amd_iommu_iotlb_sup = false;
1187
1188        /* read extended feature bits */
1189        low  = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1190        high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1191
1192        iommu->features = ((u64)high << 32) | low;
1193
1194        if (iommu_feature(iommu, FEATURE_GT)) {
1195                int glxval;
1196                u32 pasids;
1197                u64 shift;
1198
1199                shift   = iommu->features & FEATURE_PASID_MASK;
1200                shift >>= FEATURE_PASID_SHIFT;
1201                pasids  = (1 << shift);
1202
1203                amd_iommu_max_pasids = min(amd_iommu_max_pasids, pasids);
1204
1205                glxval   = iommu->features & FEATURE_GLXVAL_MASK;
1206                glxval >>= FEATURE_GLXVAL_SHIFT;
1207
1208                if (amd_iommu_max_glx_val == -1)
1209                        amd_iommu_max_glx_val = glxval;
1210                else
1211                        amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1212        }
1213
1214        if (iommu_feature(iommu, FEATURE_GT) &&
1215            iommu_feature(iommu, FEATURE_PPR)) {
1216                iommu->is_iommu_v2   = true;
1217                amd_iommu_v2_present = true;
1218        }
1219
1220        if (iommu_feature(iommu, FEATURE_PPR)) {
1221                iommu->ppr_log = alloc_ppr_log(iommu);
1222                if (!iommu->ppr_log)
1223                        return -ENOMEM;
1224        }
1225
1226        if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1227                amd_iommu_np_cache = true;
1228
1229        if (is_rd890_iommu(iommu->dev)) {
1230                int i, j;
1231
1232                iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1233                                PCI_DEVFN(0, 0));
1234
1235                /*
1236                 * Some rd890 systems may not be fully reconfigured by the
1237                 * BIOS, so it's necessary for us to store this information so
1238                 * it can be reprogrammed on resume
1239                 */
1240                pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1241                                &iommu->stored_addr_lo);
1242                pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1243                                &iommu->stored_addr_hi);
1244
1245                /* Low bit locks writes to configuration space */
1246                iommu->stored_addr_lo &= ~1;
1247
1248                for (i = 0; i < 6; i++)
1249                        for (j = 0; j < 0x12; j++)
1250                                iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1251
1252                for (i = 0; i < 0x83; i++)
1253                        iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1254        }
1255
1256        amd_iommu_erratum_746_workaround(iommu);
1257
1258        return pci_enable_device(iommu->dev);
1259}
1260
1261static void print_iommu_info(void)
1262{
1263        static const char * const feat_str[] = {
1264                "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1265                "IA", "GA", "HE", "PC"
1266        };
1267        struct amd_iommu *iommu;
1268
1269        for_each_iommu(iommu) {
1270                int i;
1271
1272                pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1273                        dev_name(&iommu->dev->dev), iommu->cap_ptr);
1274
1275                if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1276                        pr_info("AMD-Vi:  Extended features: ");
1277                        for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1278                                if (iommu_feature(iommu, (1ULL << i)))
1279                                        pr_cont(" %s", feat_str[i]);
1280                        }
1281                pr_cont("\n");
1282                }
1283        }
1284        if (irq_remapping_enabled)
1285                pr_info("AMD-Vi: Interrupt remapping enabled\n");
1286}
1287
1288static int __init amd_iommu_init_pci(void)
1289{
1290        struct amd_iommu *iommu;
1291        int ret = 0;
1292
1293        for_each_iommu(iommu) {
1294                ret = iommu_init_pci(iommu);
1295                if (ret)
1296                        break;
1297        }
1298
1299        ret = amd_iommu_init_devices();
1300
1301        print_iommu_info();
1302
1303        return ret;
1304}
1305
1306/****************************************************************************
1307 *
1308 * The following functions initialize the MSI interrupts for all IOMMUs
1309 * in the system. It's a bit challenging because there could be multiple
1310 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1311 * pci_dev.
1312 *
1313 ****************************************************************************/
1314
1315static int iommu_setup_msi(struct amd_iommu *iommu)
1316{
1317        int r;
1318
1319        r = pci_enable_msi(iommu->dev);
1320        if (r)
1321                return r;
1322
1323        r = request_threaded_irq(iommu->dev->irq,
1324                                 amd_iommu_int_handler,
1325                                 amd_iommu_int_thread,
1326                                 0, "AMD-Vi",
1327                                 iommu);
1328
1329        if (r) {
1330                pci_disable_msi(iommu->dev);
1331                return r;
1332        }
1333
1334        iommu->int_enabled = true;
1335
1336        return 0;
1337}
1338
1339static int iommu_init_msi(struct amd_iommu *iommu)
1340{
1341        int ret;
1342
1343        if (iommu->int_enabled)
1344                goto enable_faults;
1345
1346        if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
1347                ret = iommu_setup_msi(iommu);
1348        else
1349                ret = -ENODEV;
1350
1351        if (ret)
1352                return ret;
1353
1354enable_faults:
1355        iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1356
1357        if (iommu->ppr_log != NULL)
1358                iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1359
1360        return 0;
1361}
1362
1363/****************************************************************************
1364 *
1365 * The next functions belong to the third pass of parsing the ACPI
1366 * table. In this last pass the memory mapping requirements are
1367 * gathered (like exclusion and unity mapping ranges).
1368 *
1369 ****************************************************************************/
1370
1371static void __init free_unity_maps(void)
1372{
1373        struct unity_map_entry *entry, *next;
1374
1375        list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1376                list_del(&entry->list);
1377                kfree(entry);
1378        }
1379}
1380
1381/* called when we find an exclusion range definition in ACPI */
1382static int __init init_exclusion_range(struct ivmd_header *m)
1383{
1384        int i;
1385
1386        switch (m->type) {
1387        case ACPI_IVMD_TYPE:
1388                set_device_exclusion_range(m->devid, m);
1389                break;
1390        case ACPI_IVMD_TYPE_ALL:
1391                for (i = 0; i <= amd_iommu_last_bdf; ++i)
1392                        set_device_exclusion_range(i, m);
1393                break;
1394        case ACPI_IVMD_TYPE_RANGE:
1395                for (i = m->devid; i <= m->aux; ++i)
1396                        set_device_exclusion_range(i, m);
1397                break;
1398        default:
1399                break;
1400        }
1401
1402        return 0;
1403}
1404
1405/* called for unity map ACPI definition */
1406static int __init init_unity_map_range(struct ivmd_header *m)
1407{
1408        struct unity_map_entry *e = NULL;
1409        char *s;
1410
1411        e = kzalloc(sizeof(*e), GFP_KERNEL);
1412        if (e == NULL)
1413                return -ENOMEM;
1414
1415        switch (m->type) {
1416        default:
1417                kfree(e);
1418                return 0;
1419        case ACPI_IVMD_TYPE:
1420                s = "IVMD_TYPEi\t\t\t";
1421                e->devid_start = e->devid_end = m->devid;
1422                break;
1423        case ACPI_IVMD_TYPE_ALL:
1424                s = "IVMD_TYPE_ALL\t\t";
1425                e->devid_start = 0;
1426                e->devid_end = amd_iommu_last_bdf;
1427                break;
1428        case ACPI_IVMD_TYPE_RANGE:
1429                s = "IVMD_TYPE_RANGE\t\t";
1430                e->devid_start = m->devid;
1431                e->devid_end = m->aux;
1432                break;
1433        }
1434        e->address_start = PAGE_ALIGN(m->range_start);
1435        e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1436        e->prot = m->flags >> 1;
1437
1438        DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1439                    " range_start: %016llx range_end: %016llx flags: %x\n", s,
1440                    PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
1441                    PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
1442                    PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1443                    e->address_start, e->address_end, m->flags);
1444
1445        list_add_tail(&e->list, &amd_iommu_unity_map);
1446
1447        return 0;
1448}
1449
1450/* iterates over all memory definitions we find in the ACPI table */
1451static int __init init_memory_definitions(struct acpi_table_header *table)
1452{
1453        u8 *p = (u8 *)table, *end = (u8 *)table;
1454        struct ivmd_header *m;
1455
1456        end += table->length;
1457        p += IVRS_HEADER_LENGTH;
1458
1459        while (p < end) {
1460                m = (struct ivmd_header *)p;
1461                if (m->flags & IVMD_FLAG_EXCL_RANGE)
1462                        init_exclusion_range(m);
1463                else if (m->flags & IVMD_FLAG_UNITY_MAP)
1464                        init_unity_map_range(m);
1465
1466                p += m->length;
1467        }
1468
1469        return 0;
1470}
1471
1472/*
1473 * Init the device table to not allow DMA access for devices and
1474 * suppress all page faults
1475 */
1476static void init_device_table_dma(void)
1477{
1478        u32 devid;
1479
1480        for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1481                set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1482                set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1483        }
1484}
1485
1486static void __init uninit_device_table_dma(void)
1487{
1488        u32 devid;
1489
1490        for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1491                amd_iommu_dev_table[devid].data[0] = 0ULL;
1492                amd_iommu_dev_table[devid].data[1] = 0ULL;
1493        }
1494}
1495
1496static void init_device_table(void)
1497{
1498        u32 devid;
1499
1500        if (!amd_iommu_irq_remap)
1501                return;
1502
1503        for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1504                set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
1505}
1506
1507static void iommu_init_flags(struct amd_iommu *iommu)
1508{
1509        iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1510                iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1511                iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1512
1513        iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1514                iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1515                iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1516
1517        iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1518                iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1519                iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1520
1521        iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1522                iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1523                iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1524
1525        /*
1526         * make IOMMU memory accesses cache coherent
1527         */
1528        iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1529
1530        /* Set IOTLB invalidation timeout to 1s */
1531        iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
1532}
1533
1534static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1535{
1536        int i, j;
1537        u32 ioc_feature_control;
1538        struct pci_dev *pdev = iommu->root_pdev;
1539
1540        /* RD890 BIOSes may not have completely reconfigured the iommu */
1541        if (!is_rd890_iommu(iommu->dev) || !pdev)
1542                return;
1543
1544        /*
1545         * First, we need to ensure that the iommu is enabled. This is
1546         * controlled by a register in the northbridge
1547         */
1548
1549        /* Select Northbridge indirect register 0x75 and enable writing */
1550        pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1551        pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1552
1553        /* Enable the iommu */
1554        if (!(ioc_feature_control & 0x1))
1555                pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1556
1557        /* Restore the iommu BAR */
1558        pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1559                               iommu->stored_addr_lo);
1560        pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1561                               iommu->stored_addr_hi);
1562
1563        /* Restore the l1 indirect regs for each of the 6 l1s */
1564        for (i = 0; i < 6; i++)
1565                for (j = 0; j < 0x12; j++)
1566                        iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1567
1568        /* Restore the l2 indirect regs */
1569        for (i = 0; i < 0x83; i++)
1570                iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1571
1572        /* Lock PCI setup registers */
1573        pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1574                               iommu->stored_addr_lo | 1);
1575}
1576
1577/*
1578 * This function finally enables all IOMMUs found in the system after
1579 * they have been initialized
1580 */
1581static void early_enable_iommus(void)
1582{
1583        struct amd_iommu *iommu;
1584
1585        for_each_iommu(iommu) {
1586                iommu_disable(iommu);
1587                iommu_init_flags(iommu);
1588                iommu_set_device_table(iommu);
1589                iommu_enable_command_buffer(iommu);
1590                iommu_enable_event_buffer(iommu);
1591                iommu_set_exclusion_range(iommu);
1592                iommu_enable(iommu);
1593                iommu_flush_all_caches(iommu);
1594        }
1595}
1596
1597static void enable_iommus_v2(void)
1598{
1599        struct amd_iommu *iommu;
1600
1601        for_each_iommu(iommu) {
1602                iommu_enable_ppr_log(iommu);
1603                iommu_enable_gt(iommu);
1604        }
1605}
1606
1607static void enable_iommus(void)
1608{
1609        early_enable_iommus();
1610
1611        enable_iommus_v2();
1612}
1613
1614static void disable_iommus(void)
1615{
1616        struct amd_iommu *iommu;
1617
1618        for_each_iommu(iommu)
1619                iommu_disable(iommu);
1620}
1621
1622/*
1623 * Suspend/Resume support
1624 * disable suspend until real resume implemented
1625 */
1626
1627static void amd_iommu_resume(void)
1628{
1629        struct amd_iommu *iommu;
1630
1631        for_each_iommu(iommu)
1632                iommu_apply_resume_quirks(iommu);
1633
1634        /* re-load the hardware */
1635        enable_iommus();
1636
1637        amd_iommu_enable_interrupts();
1638}
1639
1640static int amd_iommu_suspend(void)
1641{
1642        /* disable IOMMUs to go out of the way for BIOS */
1643        disable_iommus();
1644
1645        return 0;
1646}
1647
1648static struct syscore_ops amd_iommu_syscore_ops = {
1649        .suspend = amd_iommu_suspend,
1650        .resume = amd_iommu_resume,
1651};
1652
1653static void __init free_on_init_error(void)
1654{
1655        free_pages((unsigned long)irq_lookup_table,
1656                   get_order(rlookup_table_size));
1657
1658        if (amd_iommu_irq_cache) {
1659                kmem_cache_destroy(amd_iommu_irq_cache);
1660                amd_iommu_irq_cache = NULL;
1661
1662        }
1663
1664        free_pages((unsigned long)amd_iommu_rlookup_table,
1665                   get_order(rlookup_table_size));
1666
1667        free_pages((unsigned long)amd_iommu_alias_table,
1668                   get_order(alias_table_size));
1669
1670        free_pages((unsigned long)amd_iommu_dev_table,
1671                   get_order(dev_table_size));
1672
1673        free_iommu_all();
1674
1675#ifdef CONFIG_GART_IOMMU
1676        /*
1677         * We failed to initialize the AMD IOMMU - try fallback to GART
1678         * if possible.
1679         */
1680        gart_iommu_init();
1681
1682#endif
1683}
1684
1685/* SB IOAPIC is always on this device in AMD systems */
1686#define IOAPIC_SB_DEVID         ((0x00 << 8) | PCI_DEVFN(0x14, 0))
1687
1688static bool __init check_ioapic_information(void)
1689{
1690        const char *fw_bug = FW_BUG;
1691        bool ret, has_sb_ioapic;
1692        int idx;
1693
1694        has_sb_ioapic = false;
1695        ret           = false;
1696
1697        /*
1698         * If we have map overrides on the kernel command line the
1699         * messages in this function might not describe firmware bugs
1700         * anymore - so be careful
1701         */
1702        if (cmdline_maps)
1703                fw_bug = "";
1704
1705        for (idx = 0; idx < nr_ioapics; idx++) {
1706                int devid, id = mpc_ioapic_id(idx);
1707
1708                devid = get_ioapic_devid(id);
1709                if (devid < 0) {
1710                        pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
1711                                fw_bug, id);
1712                        ret = false;
1713                } else if (devid == IOAPIC_SB_DEVID) {
1714                        has_sb_ioapic = true;
1715                        ret           = true;
1716                }
1717        }
1718
1719        if (!has_sb_ioapic) {
1720                /*
1721                 * We expect the SB IOAPIC to be listed in the IVRS
1722                 * table. The system timer is connected to the SB IOAPIC
1723                 * and if we don't have it in the list the system will
1724                 * panic at boot time.  This situation usually happens
1725                 * when the BIOS is buggy and provides us the wrong
1726                 * device id for the IOAPIC in the system.
1727                 */
1728                pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
1729        }
1730
1731        if (!ret)
1732                pr_err("AMD-Vi: Disabling interrupt remapping\n");
1733
1734        return ret;
1735}
1736
1737static void __init free_dma_resources(void)
1738{
1739        amd_iommu_uninit_devices();
1740
1741        free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1742                   get_order(MAX_DOMAIN_ID/8));
1743
1744        free_unity_maps();
1745}
1746
1747/*
1748 * This is the hardware init function for AMD IOMMU in the system.
1749 * This function is called either from amd_iommu_init or from the interrupt
1750 * remapping setup code.
1751 *
1752 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1753 * three times:
1754 *
1755 *      1 pass) Find the highest PCI device id the driver has to handle.
1756 *              Upon this information the size of the data structures is
1757 *              determined that needs to be allocated.
1758 *
1759 *      2 pass) Initialize the data structures just allocated with the
1760 *              information in the ACPI table about available AMD IOMMUs
1761 *              in the system. It also maps the PCI devices in the
1762 *              system to specific IOMMUs
1763 *
1764 *      3 pass) After the basic data structures are allocated and
1765 *              initialized we update them with information about memory
1766 *              remapping requirements parsed out of the ACPI table in
1767 *              this last pass.
1768 *
1769 * After everything is set up the IOMMUs are enabled and the necessary
1770 * hotplug and suspend notifiers are registered.
1771 */
1772static int __init early_amd_iommu_init(void)
1773{
1774        struct acpi_table_header *ivrs_base;
1775        acpi_size ivrs_size;
1776        acpi_status status;
1777        int i, ret = 0;
1778
1779        if (!amd_iommu_detected)
1780                return -ENODEV;
1781
1782        status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1783        if (status == AE_NOT_FOUND)
1784                return -ENODEV;
1785        else if (ACPI_FAILURE(status)) {
1786                const char *err = acpi_format_exception(status);
1787                pr_err("AMD-Vi: IVRS table error: %s\n", err);
1788                return -EINVAL;
1789        }
1790
1791        /*
1792         * First parse ACPI tables to find the largest Bus/Dev/Func
1793         * we need to handle. Upon this information the shared data
1794         * structures for the IOMMUs in the system will be allocated
1795         */
1796        ret = find_last_devid_acpi(ivrs_base);
1797        if (ret)
1798                goto out;
1799
1800        dev_table_size     = tbl_size(DEV_TABLE_ENTRY_SIZE);
1801        alias_table_size   = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1802        rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1803
1804        /* Device table - directly used by all IOMMUs */
1805        ret = -ENOMEM;
1806        amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1807                                      get_order(dev_table_size));
1808        if (amd_iommu_dev_table == NULL)
1809                goto out;
1810
1811        /*
1812         * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1813         * IOMMU see for that device
1814         */
1815        amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1816                        get_order(alias_table_size));
1817        if (amd_iommu_alias_table == NULL)
1818                goto out;
1819
1820        /* IOMMU rlookup table - find the IOMMU for a specific device */
1821        amd_iommu_rlookup_table = (void *)__get_free_pages(
1822                        GFP_KERNEL | __GFP_ZERO,
1823                        get_order(rlookup_table_size));
1824        if (amd_iommu_rlookup_table == NULL)
1825                goto out;
1826
1827        amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1828                                            GFP_KERNEL | __GFP_ZERO,
1829                                            get_order(MAX_DOMAIN_ID/8));
1830        if (amd_iommu_pd_alloc_bitmap == NULL)
1831                goto out;
1832
1833        /*
1834         * let all alias entries point to itself
1835         */
1836        for (i = 0; i <= amd_iommu_last_bdf; ++i)
1837                amd_iommu_alias_table[i] = i;
1838
1839        /*
1840         * never allocate domain 0 because its used as the non-allocated and
1841         * error value placeholder
1842         */
1843        amd_iommu_pd_alloc_bitmap[0] = 1;
1844
1845        spin_lock_init(&amd_iommu_pd_lock);
1846
1847        /*
1848         * now the data structures are allocated and basically initialized
1849         * start the real acpi table scan
1850         */
1851        ret = init_iommu_all(ivrs_base);
1852        if (ret)
1853                goto out;
1854
1855        if (amd_iommu_irq_remap)
1856                amd_iommu_irq_remap = check_ioapic_information();
1857
1858        if (amd_iommu_irq_remap) {
1859                /*
1860                 * Interrupt remapping enabled, create kmem_cache for the
1861                 * remapping tables.
1862                 */
1863                ret = -ENOMEM;
1864                amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
1865                                MAX_IRQS_PER_TABLE * sizeof(u32),
1866                                IRQ_TABLE_ALIGNMENT,
1867                                0, NULL);
1868                if (!amd_iommu_irq_cache)
1869                        goto out;
1870
1871                irq_lookup_table = (void *)__get_free_pages(
1872                                GFP_KERNEL | __GFP_ZERO,
1873                                get_order(rlookup_table_size));
1874                if (!irq_lookup_table)
1875                        goto out;
1876        }
1877
1878        ret = init_memory_definitions(ivrs_base);
1879        if (ret)
1880                goto out;
1881
1882        /* init the device table */
1883        init_device_table();
1884
1885out:
1886        /* Don't leak any ACPI memory */
1887        early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1888        ivrs_base = NULL;
1889
1890        return ret;
1891}
1892
1893static int amd_iommu_enable_interrupts(void)
1894{
1895        struct amd_iommu *iommu;
1896        int ret = 0;
1897
1898        for_each_iommu(iommu) {
1899                ret = iommu_init_msi(iommu);
1900                if (ret)
1901                        goto out;
1902        }
1903
1904out:
1905        return ret;
1906}
1907
1908static bool detect_ivrs(void)
1909{
1910        struct acpi_table_header *ivrs_base;
1911        acpi_size ivrs_size;
1912        acpi_status status;
1913
1914        status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1915        if (status == AE_NOT_FOUND)
1916                return false;
1917        else if (ACPI_FAILURE(status)) {
1918                const char *err = acpi_format_exception(status);
1919                pr_err("AMD-Vi: IVRS table error: %s\n", err);
1920                return false;
1921        }
1922
1923        early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1924
1925        /* Make sure ACS will be enabled during PCI probe */
1926        pci_request_acs();
1927
1928        if (!disable_irq_remap)
1929                amd_iommu_irq_remap = true;
1930
1931        return true;
1932}
1933
1934static int amd_iommu_init_dma(void)
1935{
1936        struct amd_iommu *iommu;
1937        int ret;
1938
1939        if (iommu_pass_through)
1940                ret = amd_iommu_init_passthrough();
1941        else
1942                ret = amd_iommu_init_dma_ops();
1943
1944        if (ret)
1945                return ret;
1946
1947        init_device_table_dma();
1948
1949        for_each_iommu(iommu)
1950                iommu_flush_all_caches(iommu);
1951
1952        amd_iommu_init_api();
1953
1954        amd_iommu_init_notifier();
1955
1956        return 0;
1957}
1958
1959/****************************************************************************
1960 *
1961 * AMD IOMMU Initialization State Machine
1962 *
1963 ****************************************************************************/
1964
1965static int __init state_next(void)
1966{
1967        int ret = 0;
1968
1969        switch (init_state) {
1970        case IOMMU_START_STATE:
1971                if (!detect_ivrs()) {
1972                        init_state      = IOMMU_NOT_FOUND;
1973                        ret             = -ENODEV;
1974                } else {
1975                        init_state      = IOMMU_IVRS_DETECTED;
1976                }
1977                break;
1978        case IOMMU_IVRS_DETECTED:
1979                ret = early_amd_iommu_init();
1980                init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
1981                break;
1982        case IOMMU_ACPI_FINISHED:
1983                early_enable_iommus();
1984                register_syscore_ops(&amd_iommu_syscore_ops);
1985                x86_platform.iommu_shutdown = disable_iommus;
1986                init_state = IOMMU_ENABLED;
1987                break;
1988        case IOMMU_ENABLED:
1989                ret = amd_iommu_init_pci();
1990                init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
1991                enable_iommus_v2();
1992                break;
1993        case IOMMU_PCI_INIT:
1994                ret = amd_iommu_enable_interrupts();
1995                init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
1996                break;
1997        case IOMMU_INTERRUPTS_EN:
1998                ret = amd_iommu_init_dma();
1999                init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2000                break;
2001        case IOMMU_DMA_OPS:
2002                init_state = IOMMU_INITIALIZED;
2003                break;
2004        case IOMMU_INITIALIZED:
2005                /* Nothing to do */
2006                break;
2007        case IOMMU_NOT_FOUND:
2008        case IOMMU_INIT_ERROR:
2009                /* Error states => do nothing */
2010                ret = -EINVAL;
2011                break;
2012        default:
2013                /* Unknown state */
2014                BUG();
2015        }
2016
2017        return ret;
2018}
2019
2020static int __init iommu_go_to_state(enum iommu_init_state state)
2021{
2022        int ret = 0;
2023
2024        while (init_state != state) {
2025                ret = state_next();
2026                if (init_state == IOMMU_NOT_FOUND ||
2027                    init_state == IOMMU_INIT_ERROR)
2028                        break;
2029        }
2030
2031        return ret;
2032}
2033
2034#ifdef CONFIG_IRQ_REMAP
2035int __init amd_iommu_prepare(void)
2036{
2037        return iommu_go_to_state(IOMMU_ACPI_FINISHED);
2038}
2039
2040int __init amd_iommu_supported(void)
2041{
2042        return amd_iommu_irq_remap ? 1 : 0;
2043}
2044
2045int __init amd_iommu_enable(void)
2046{
2047        int ret;
2048
2049        ret = iommu_go_to_state(IOMMU_ENABLED);
2050        if (ret)
2051                return ret;
2052
2053        irq_remapping_enabled = 1;
2054
2055        return 0;
2056}
2057
2058void amd_iommu_disable(void)
2059{
2060        amd_iommu_suspend();
2061}
2062
2063int amd_iommu_reenable(int mode)
2064{
2065        amd_iommu_resume();
2066
2067        return 0;
2068}
2069
2070int __init amd_iommu_enable_faulting(void)
2071{
2072        /* We enable MSI later when PCI is initialized */
2073        return 0;
2074}
2075#endif
2076
2077/*
2078 * This is the core init function for AMD IOMMU hardware in the system.
2079 * This function is called from the generic x86 DMA layer initialization
2080 * code.
2081 */
2082static int __init amd_iommu_init(void)
2083{
2084        int ret;
2085
2086        ret = iommu_go_to_state(IOMMU_INITIALIZED);
2087        if (ret) {
2088                free_dma_resources();
2089                if (!irq_remapping_enabled) {
2090                        disable_iommus();
2091                        free_on_init_error();
2092                } else {
2093                        struct amd_iommu *iommu;
2094
2095                        uninit_device_table_dma();
2096                        for_each_iommu(iommu)
2097                                iommu_flush_all_caches(iommu);
2098                }
2099        }
2100
2101        return ret;
2102}
2103
2104/****************************************************************************
2105 *
2106 * Early detect code. This code runs at IOMMU detection time in the DMA
2107 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2108 * IOMMUs
2109 *
2110 ****************************************************************************/
2111int __init amd_iommu_detect(void)
2112{
2113        int ret;
2114
2115        if (no_iommu || (iommu_detected && !gart_iommu_aperture))
2116                return -ENODEV;
2117
2118        if (amd_iommu_disabled)
2119                return -ENODEV;
2120
2121        ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2122        if (ret)
2123                return ret;
2124
2125        amd_iommu_detected = true;
2126        iommu_detected = 1;
2127        x86_init.iommu.iommu_init = amd_iommu_init;
2128
2129        return 0;
2130}
2131
2132/****************************************************************************
2133 *
2134 * Parsing functions for the AMD IOMMU specific kernel command line
2135 * options.
2136 *
2137 ****************************************************************************/
2138
2139static int __init parse_amd_iommu_dump(char *str)
2140{
2141        amd_iommu_dump = true;
2142
2143        return 1;
2144}
2145
2146static int __init parse_amd_iommu_options(char *str)
2147{
2148        for (; *str; ++str) {
2149                if (strncmp(str, "fullflush", 9) == 0)
2150                        amd_iommu_unmap_flush = true;
2151                if (strncmp(str, "off", 3) == 0)
2152                        amd_iommu_disabled = true;
2153                if (strncmp(str, "force_isolation", 15) == 0)
2154                        amd_iommu_force_isolation = true;
2155        }
2156
2157        return 1;
2158}
2159
2160static int __init parse_ivrs_ioapic(char *str)
2161{
2162        unsigned int bus, dev, fn;
2163        int ret, id, i;
2164        u16 devid;
2165
2166        ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2167
2168        if (ret != 4) {
2169                pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2170                return 1;
2171        }
2172
2173        if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2174                pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2175                        str);
2176                return 1;
2177        }
2178
2179        devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2180
2181        cmdline_maps                    = true;
2182        i                               = early_ioapic_map_size++;
2183        early_ioapic_map[i].id          = id;
2184        early_ioapic_map[i].devid       = devid;
2185        early_ioapic_map[i].cmd_line    = true;
2186
2187        return 1;
2188}
2189
2190static int __init parse_ivrs_hpet(char *str)
2191{
2192        unsigned int bus, dev, fn;
2193        int ret, id, i;
2194        u16 devid;
2195
2196        ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2197
2198        if (ret != 4) {
2199                pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2200                return 1;
2201        }
2202
2203        if (early_hpet_map_size == EARLY_MAP_SIZE) {
2204                pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2205                        str);
2206                return 1;
2207        }
2208
2209        devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2210
2211        cmdline_maps                    = true;
2212        i                               = early_hpet_map_size++;
2213        early_hpet_map[i].id            = id;
2214        early_hpet_map[i].devid         = devid;
2215        early_hpet_map[i].cmd_line      = true;
2216
2217        return 1;
2218}
2219
2220__setup("amd_iommu_dump",       parse_amd_iommu_dump);
2221__setup("amd_iommu=",           parse_amd_iommu_options);
2222__setup("ivrs_ioapic",          parse_ivrs_ioapic);
2223__setup("ivrs_hpet",            parse_ivrs_hpet);
2224
2225IOMMU_INIT_FINISH(amd_iommu_detect,
2226                  gart_iommu_hole_init,
2227                  NULL,
2228                  NULL);
2229
2230bool amd_iommu_v2_supported(void)
2231{
2232        return amd_iommu_v2_present;
2233}
2234EXPORT_SYMBOL(amd_iommu_v2_supported);
2235
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