linux/drivers/gpio/gpio-ich.c
<<
>>
Prefs
   1/*
   2 * Intel ICH6-10, Series 5 and 6 GPIO driver
   3 *
   4 * Copyright (C) 2010 Extreme Engineering Solutions.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19 */
  20
  21#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22
  23#include <linux/module.h>
  24#include <linux/pci.h>
  25#include <linux/gpio.h>
  26#include <linux/platform_device.h>
  27#include <linux/mfd/lpc_ich.h>
  28
  29#define DRV_NAME "gpio_ich"
  30
  31/*
  32 * GPIO register offsets in GPIO I/O space.
  33 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
  34 * LVLx registers.  Logic in the read/write functions takes a register and
  35 * an absolute bit number and determines the proper register offset and bit
  36 * number in that register.  For example, to read the value of GPIO bit 50
  37 * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
  38 * bit 18 (50%32).
  39 */
  40enum GPIO_REG {
  41        GPIO_USE_SEL = 0,
  42        GPIO_IO_SEL,
  43        GPIO_LVL,
  44};
  45
  46static const u8 ichx_regs[3][3] = {
  47        {0x00, 0x30, 0x40},     /* USE_SEL[1-3] offsets */
  48        {0x04, 0x34, 0x44},     /* IO_SEL[1-3] offsets */
  49        {0x0c, 0x38, 0x48},     /* LVL[1-3] offsets */
  50};
  51
  52static const u8 ichx_reglen[3] = {
  53        0x30, 0x10, 0x10,
  54};
  55
  56#define ICHX_WRITE(val, reg, base_res)  outl(val, (reg) + (base_res)->start)
  57#define ICHX_READ(reg, base_res)        inl((reg) + (base_res)->start)
  58
  59struct ichx_desc {
  60        /* Max GPIO pins the chipset can have */
  61        uint ngpio;
  62
  63        /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
  64        bool uses_gpe0;
  65
  66        /* USE_SEL is bogus on some chipsets, eg 3100 */
  67        u32 use_sel_ignore[3];
  68
  69        /* Some chipsets have quirks, let these use their own request/get */
  70        int (*request)(struct gpio_chip *chip, unsigned offset);
  71        int (*get)(struct gpio_chip *chip, unsigned offset);
  72};
  73
  74static struct {
  75        spinlock_t lock;
  76        struct platform_device *dev;
  77        struct gpio_chip chip;
  78        struct resource *gpio_base;     /* GPIO IO base */
  79        struct resource *pm_base;       /* Power Mangagment IO base */
  80        struct ichx_desc *desc; /* Pointer to chipset-specific description */
  81        u32 orig_gpio_ctrl;     /* Orig CTRL value, used to restore on exit */
  82        u8 use_gpio;            /* Which GPIO groups are usable */
  83} ichx_priv;
  84
  85static int modparam_gpiobase = -1;      /* dynamic */
  86module_param_named(gpiobase, modparam_gpiobase, int, 0444);
  87MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
  88                           "which is the default.");
  89
  90static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
  91{
  92        unsigned long flags;
  93        u32 data, tmp;
  94        int reg_nr = nr / 32;
  95        int bit = nr & 0x1f;
  96        int ret = 0;
  97
  98        spin_lock_irqsave(&ichx_priv.lock, flags);
  99
 100        data = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
 101        if (val)
 102                data |= 1 << bit;
 103        else
 104                data &= ~(1 << bit);
 105        ICHX_WRITE(data, ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
 106        tmp = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
 107        if (verify && data != tmp)
 108                ret = -EPERM;
 109
 110        spin_unlock_irqrestore(&ichx_priv.lock, flags);
 111
 112        return ret;
 113}
 114
 115static int ichx_read_bit(int reg, unsigned nr)
 116{
 117        unsigned long flags;
 118        u32 data;
 119        int reg_nr = nr / 32;
 120        int bit = nr & 0x1f;
 121
 122        spin_lock_irqsave(&ichx_priv.lock, flags);
 123
 124        data = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
 125
 126        spin_unlock_irqrestore(&ichx_priv.lock, flags);
 127
 128        return data & (1 << bit) ? 1 : 0;
 129}
 130
 131static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
 132{
 133        return !!(ichx_priv.use_gpio & (1 << (nr / 32)));
 134}
 135
 136static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
 137{
 138        /*
 139         * Try setting pin as an input and verify it worked since many pins
 140         * are output-only.
 141         */
 142        if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
 143                return -EINVAL;
 144
 145        return 0;
 146}
 147
 148static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
 149                                        int val)
 150{
 151        /* Set GPIO output value. */
 152        ichx_write_bit(GPIO_LVL, nr, val, 0);
 153
 154        /*
 155         * Try setting pin as an output and verify it worked since many pins
 156         * are input-only.
 157         */
 158        if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
 159                return -EINVAL;
 160
 161        return 0;
 162}
 163
 164static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
 165{
 166        return ichx_read_bit(GPIO_LVL, nr);
 167}
 168
 169static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
 170{
 171        unsigned long flags;
 172        u32 data;
 173
 174        /*
 175         * GPI 0 - 15 need to be read from the power management registers on
 176         * a ICH6/3100 bridge.
 177         */
 178        if (nr < 16) {
 179                if (!ichx_priv.pm_base)
 180                        return -ENXIO;
 181
 182                spin_lock_irqsave(&ichx_priv.lock, flags);
 183
 184                /* GPI 0 - 15 are latched, write 1 to clear*/
 185                ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base);
 186                data = ICHX_READ(0, ichx_priv.pm_base);
 187
 188                spin_unlock_irqrestore(&ichx_priv.lock, flags);
 189
 190                return (data >> 16) & (1 << nr) ? 1 : 0;
 191        } else {
 192                return ichx_gpio_get(chip, nr);
 193        }
 194}
 195
 196static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
 197{
 198        if (!ichx_gpio_check_available(chip, nr))
 199                return -ENXIO;
 200
 201        /*
 202         * Note we assume the BIOS properly set a bridge's USE value.  Some
 203         * chips (eg Intel 3100) have bogus USE values though, so first see if
 204         * the chipset's USE value can be trusted for this specific bit.
 205         * If it can't be trusted, assume that the pin can be used as a GPIO.
 206         */
 207        if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))
 208                return 0;
 209
 210        return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
 211}
 212
 213static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
 214{
 215        /*
 216         * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
 217         * bridge as they are controlled by USE register bits 0 and 1.  See
 218         * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
 219         * additional info.
 220         */
 221        if (nr == 16 || nr == 17)
 222                nr -= 16;
 223
 224        return ichx_gpio_request(chip, nr);
 225}
 226
 227static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
 228{
 229        ichx_write_bit(GPIO_LVL, nr, val, 0);
 230}
 231
 232static void ichx_gpiolib_setup(struct gpio_chip *chip)
 233{
 234        chip->owner = THIS_MODULE;
 235        chip->label = DRV_NAME;
 236        chip->dev = &ichx_priv.dev->dev;
 237
 238        /* Allow chip-specific overrides of request()/get() */
 239        chip->request = ichx_priv.desc->request ?
 240                ichx_priv.desc->request : ichx_gpio_request;
 241        chip->get = ichx_priv.desc->get ?
 242                ichx_priv.desc->get : ichx_gpio_get;
 243
 244        chip->set = ichx_gpio_set;
 245        chip->direction_input = ichx_gpio_direction_input;
 246        chip->direction_output = ichx_gpio_direction_output;
 247        chip->base = modparam_gpiobase;
 248        chip->ngpio = ichx_priv.desc->ngpio;
 249        chip->can_sleep = 0;
 250        chip->dbg_show = NULL;
 251}
 252
 253/* ICH6-based, 631xesb-based */
 254static struct ichx_desc ich6_desc = {
 255        /* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
 256        .request = ich6_gpio_request,
 257        .get = ich6_gpio_get,
 258
 259        /* GPIO 0-15 are read in the GPE0_STS PM register */
 260        .uses_gpe0 = true,
 261
 262        .ngpio = 50,
 263};
 264
 265/* Intel 3100 */
 266static struct ichx_desc i3100_desc = {
 267        /*
 268         * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
 269         * the Intel 3100.  See "Table 712. GPIO Summary Table" of 3100
 270         * Datasheet for more info.
 271         */
 272        .use_sel_ignore = {0x00130000, 0x00010000, 0x0},
 273
 274        /* The 3100 needs fixups for GPIO 0 - 17 */
 275        .request = ich6_gpio_request,
 276        .get = ich6_gpio_get,
 277
 278        /* GPIO 0-15 are read in the GPE0_STS PM register */
 279        .uses_gpe0 = true,
 280
 281        .ngpio = 50,
 282};
 283
 284/* ICH7 and ICH8-based */
 285static struct ichx_desc ich7_desc = {
 286        .ngpio = 50,
 287};
 288
 289/* ICH9-based */
 290static struct ichx_desc ich9_desc = {
 291        .ngpio = 61,
 292};
 293
 294/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
 295static struct ichx_desc ich10_cons_desc = {
 296        .ngpio = 61,
 297};
 298static struct ichx_desc ich10_corp_desc = {
 299        .ngpio = 72,
 300};
 301
 302/* Intel 5 series, 6 series, 3400 series, and C200 series */
 303static struct ichx_desc intel5_desc = {
 304        .ngpio = 76,
 305};
 306
 307static int ichx_gpio_request_regions(struct resource *res_base,
 308                                                const char *name, u8 use_gpio)
 309{
 310        int i;
 311
 312        if (!res_base || !res_base->start || !res_base->end)
 313                return -ENODEV;
 314
 315        for (i = 0; i < ARRAY_SIZE(ichx_regs[0]); i++) {
 316                if (!(use_gpio & (1 << i)))
 317                        continue;
 318                if (!request_region(res_base->start + ichx_regs[0][i],
 319                                    ichx_reglen[i], name))
 320                        goto request_err;
 321        }
 322        return 0;
 323
 324request_err:
 325        /* Clean up: release already requested regions, if any */
 326        for (i--; i >= 0; i--) {
 327                if (!(use_gpio & (1 << i)))
 328                        continue;
 329                release_region(res_base->start + ichx_regs[0][i],
 330                               ichx_reglen[i]);
 331        }
 332        return -EBUSY;
 333}
 334
 335static void ichx_gpio_release_regions(struct resource *res_base, u8 use_gpio)
 336{
 337        int i;
 338
 339        for (i = 0; i < ARRAY_SIZE(ichx_regs[0]); i++) {
 340                if (!(use_gpio & (1 << i)))
 341                        continue;
 342                release_region(res_base->start + ichx_regs[0][i],
 343                               ichx_reglen[i]);
 344        }
 345}
 346
 347static int ichx_gpio_probe(struct platform_device *pdev)
 348{
 349        struct resource *res_base, *res_pm;
 350        int err;
 351        struct lpc_ich_info *ich_info = pdev->dev.platform_data;
 352
 353        if (!ich_info)
 354                return -ENODEV;
 355
 356        ichx_priv.dev = pdev;
 357
 358        switch (ich_info->gpio_version) {
 359        case ICH_I3100_GPIO:
 360                ichx_priv.desc = &i3100_desc;
 361                break;
 362        case ICH_V5_GPIO:
 363                ichx_priv.desc = &intel5_desc;
 364                break;
 365        case ICH_V6_GPIO:
 366                ichx_priv.desc = &ich6_desc;
 367                break;
 368        case ICH_V7_GPIO:
 369                ichx_priv.desc = &ich7_desc;
 370                break;
 371        case ICH_V9_GPIO:
 372                ichx_priv.desc = &ich9_desc;
 373                break;
 374        case ICH_V10CORP_GPIO:
 375                ichx_priv.desc = &ich10_corp_desc;
 376                break;
 377        case ICH_V10CONS_GPIO:
 378                ichx_priv.desc = &ich10_cons_desc;
 379                break;
 380        default:
 381                return -ENODEV;
 382        }
 383
 384        spin_lock_init(&ichx_priv.lock);
 385        res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
 386        ichx_priv.use_gpio = ich_info->use_gpio;
 387        err = ichx_gpio_request_regions(res_base, pdev->name,
 388                                        ichx_priv.use_gpio);
 389        if (err)
 390                return err;
 391
 392        ichx_priv.gpio_base = res_base;
 393
 394        /*
 395         * If necessary, determine the I/O address of ACPI/power management
 396         * registers which are needed to read the the GPE0 register for GPI pins
 397         * 0 - 15 on some chipsets.
 398         */
 399        if (!ichx_priv.desc->uses_gpe0)
 400                goto init;
 401
 402        res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
 403        if (!res_pm) {
 404                pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
 405                goto init;
 406        }
 407
 408        if (!request_region(res_pm->start, resource_size(res_pm),
 409                        pdev->name)) {
 410                pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
 411                goto init;
 412        }
 413
 414        ichx_priv.pm_base = res_pm;
 415
 416init:
 417        ichx_gpiolib_setup(&ichx_priv.chip);
 418        err = gpiochip_add(&ichx_priv.chip);
 419        if (err) {
 420                pr_err("Failed to register GPIOs\n");
 421                goto add_err;
 422        }
 423
 424        pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
 425               ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);
 426
 427        return 0;
 428
 429add_err:
 430        ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
 431        if (ichx_priv.pm_base)
 432                release_region(ichx_priv.pm_base->start,
 433                                resource_size(ichx_priv.pm_base));
 434        return err;
 435}
 436
 437static int ichx_gpio_remove(struct platform_device *pdev)
 438{
 439        int err;
 440
 441        err = gpiochip_remove(&ichx_priv.chip);
 442        if (err) {
 443                dev_err(&pdev->dev, "%s failed, %d\n",
 444                                "gpiochip_remove()", err);
 445                return err;
 446        }
 447
 448        ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
 449        if (ichx_priv.pm_base)
 450                release_region(ichx_priv.pm_base->start,
 451                                resource_size(ichx_priv.pm_base));
 452
 453        return 0;
 454}
 455
 456static struct platform_driver ichx_gpio_driver = {
 457        .driver         = {
 458                .owner  = THIS_MODULE,
 459                .name   = DRV_NAME,
 460        },
 461        .probe          = ichx_gpio_probe,
 462        .remove         = ichx_gpio_remove,
 463};
 464
 465module_platform_driver(ichx_gpio_driver);
 466
 467MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
 468MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
 469MODULE_LICENSE("GPL");
 470MODULE_ALIAS("platform:"DRV_NAME);
 471
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.