linux/drivers/gpio/gpio-em.c
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   1/*
   2 * Emma Mobile GPIO Support - GIO
   3 *
   4 *  Copyright (C) 2012 Magnus Damm
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18 */
  19
  20#include <linux/init.h>
  21#include <linux/platform_device.h>
  22#include <linux/spinlock.h>
  23#include <linux/interrupt.h>
  24#include <linux/ioport.h>
  25#include <linux/io.h>
  26#include <linux/irq.h>
  27#include <linux/irqdomain.h>
  28#include <linux/bitops.h>
  29#include <linux/err.h>
  30#include <linux/gpio.h>
  31#include <linux/slab.h>
  32#include <linux/module.h>
  33#include <linux/platform_data/gpio-em.h>
  34
  35struct em_gio_priv {
  36        void __iomem *base0;
  37        void __iomem *base1;
  38        spinlock_t sense_lock;
  39        struct platform_device *pdev;
  40        struct gpio_chip gpio_chip;
  41        struct irq_chip irq_chip;
  42        struct irq_domain *irq_domain;
  43};
  44
  45#define GIO_E1 0x00
  46#define GIO_E0 0x04
  47#define GIO_EM 0x04
  48#define GIO_OL 0x08
  49#define GIO_OH 0x0c
  50#define GIO_I 0x10
  51#define GIO_IIA 0x14
  52#define GIO_IEN 0x18
  53#define GIO_IDS 0x1c
  54#define GIO_IIM 0x1c
  55#define GIO_RAW 0x20
  56#define GIO_MST 0x24
  57#define GIO_IIR 0x28
  58
  59#define GIO_IDT0 0x40
  60#define GIO_IDT1 0x44
  61#define GIO_IDT2 0x48
  62#define GIO_IDT3 0x4c
  63#define GIO_RAWBL 0x50
  64#define GIO_RAWBH 0x54
  65#define GIO_IRBL 0x58
  66#define GIO_IRBH 0x5c
  67
  68#define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))
  69
  70static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
  71{
  72        if (offs < GIO_IDT0)
  73                return ioread32(p->base0 + offs);
  74        else
  75                return ioread32(p->base1 + (offs - GIO_IDT0));
  76}
  77
  78static inline void em_gio_write(struct em_gio_priv *p, int offs,
  79                                unsigned long value)
  80{
  81        if (offs < GIO_IDT0)
  82                iowrite32(value, p->base0 + offs);
  83        else
  84                iowrite32(value, p->base1 + (offs - GIO_IDT0));
  85}
  86
  87static void em_gio_irq_disable(struct irq_data *d)
  88{
  89        struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
  90
  91        em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
  92}
  93
  94static void em_gio_irq_enable(struct irq_data *d)
  95{
  96        struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
  97
  98        em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
  99}
 100
 101#define GIO_ASYNC(x) (x + 8)
 102
 103static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
 104        [IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
 105        [IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
 106        [IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
 107        [IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
 108        [IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
 109};
 110
 111static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
 112{
 113        unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
 114        struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
 115        unsigned int reg, offset, shift;
 116        unsigned long flags;
 117        unsigned long tmp;
 118
 119        if (!value)
 120                return -EINVAL;
 121
 122        offset = irqd_to_hwirq(d);
 123
 124        pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);
 125
 126        /* 8 x 4 bit fields in 4 IDT registers */
 127        reg = GIO_IDT(offset >> 3);
 128        shift = (offset & 0x07) << 4;
 129
 130        spin_lock_irqsave(&p->sense_lock, flags);
 131
 132        /* disable the interrupt in IIA */
 133        tmp = em_gio_read(p, GIO_IIA);
 134        tmp &= ~BIT(offset);
 135        em_gio_write(p, GIO_IIA, tmp);
 136
 137        /* change the sense setting in IDT */
 138        tmp = em_gio_read(p, reg);
 139        tmp &= ~(0xf << shift);
 140        tmp |= value << shift;
 141        em_gio_write(p, reg, tmp);
 142
 143        /* clear pending interrupts */
 144        em_gio_write(p, GIO_IIR, BIT(offset));
 145
 146        /* enable the interrupt in IIA */
 147        tmp = em_gio_read(p, GIO_IIA);
 148        tmp |= BIT(offset);
 149        em_gio_write(p, GIO_IIA, tmp);
 150
 151        spin_unlock_irqrestore(&p->sense_lock, flags);
 152
 153        return 0;
 154}
 155
 156static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
 157{
 158        struct em_gio_priv *p = dev_id;
 159        unsigned long pending;
 160        unsigned int offset, irqs_handled = 0;
 161
 162        while ((pending = em_gio_read(p, GIO_MST))) {
 163                offset = __ffs(pending);
 164                em_gio_write(p, GIO_IIR, BIT(offset));
 165                generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
 166                irqs_handled++;
 167        }
 168
 169        return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
 170}
 171
 172static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip)
 173{
 174        return container_of(chip, struct em_gio_priv, gpio_chip);
 175}
 176
 177static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
 178{
 179        em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
 180        return 0;
 181}
 182
 183static int em_gio_get(struct gpio_chip *chip, unsigned offset)
 184{
 185        return (int)(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
 186}
 187
 188static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
 189                         unsigned shift, int value)
 190{
 191        /* upper 16 bits contains mask and lower 16 actual value */
 192        em_gio_write(gpio_to_priv(chip), reg,
 193                     (1 << (shift + 16)) | (value << shift));
 194}
 195
 196static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
 197{
 198        /* output is split into two registers */
 199        if (offset < 16)
 200                __em_gio_set(chip, GIO_OL, offset, value);
 201        else
 202                __em_gio_set(chip, GIO_OH, offset - 16, value);
 203}
 204
 205static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
 206                                   int value)
 207{
 208        /* write GPIO value to output before selecting output mode of pin */
 209        em_gio_set(chip, offset, value);
 210        em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
 211        return 0;
 212}
 213
 214static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
 215{
 216        return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
 217}
 218
 219static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int virq,
 220                                 irq_hw_number_t hw)
 221{
 222        struct em_gio_priv *p = h->host_data;
 223
 224        pr_debug("gio: map hw irq = %d, virq = %d\n", (int)hw, virq);
 225
 226        irq_set_chip_data(virq, h->host_data);
 227        irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
 228        set_irq_flags(virq, IRQF_VALID); /* kill me now */
 229        return 0;
 230}
 231
 232static struct irq_domain_ops em_gio_irq_domain_ops = {
 233        .map    = em_gio_irq_domain_map,
 234        .xlate  = irq_domain_xlate_twocell,
 235};
 236
 237static int em_gio_probe(struct platform_device *pdev)
 238{
 239        struct gpio_em_config pdata_dt;
 240        struct gpio_em_config *pdata = pdev->dev.platform_data;
 241        struct em_gio_priv *p;
 242        struct resource *io[2], *irq[2];
 243        struct gpio_chip *gpio_chip;
 244        struct irq_chip *irq_chip;
 245        const char *name = dev_name(&pdev->dev);
 246        int ret;
 247
 248        p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
 249        if (!p) {
 250                dev_err(&pdev->dev, "failed to allocate driver data\n");
 251                ret = -ENOMEM;
 252                goto err0;
 253        }
 254
 255        p->pdev = pdev;
 256        platform_set_drvdata(pdev, p);
 257        spin_lock_init(&p->sense_lock);
 258
 259        io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 260        io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 261        irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 262        irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
 263
 264        if (!io[0] || !io[1] || !irq[0] || !irq[1]) {
 265                dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
 266                ret = -EINVAL;
 267                goto err0;
 268        }
 269
 270        p->base0 = devm_ioremap_nocache(&pdev->dev, io[0]->start,
 271                                        resource_size(io[0]));
 272        if (!p->base0) {
 273                dev_err(&pdev->dev, "failed to remap low I/O memory\n");
 274                ret = -ENXIO;
 275                goto err0;
 276        }
 277
 278        p->base1 = devm_ioremap_nocache(&pdev->dev, io[1]->start,
 279                                   resource_size(io[1]));
 280        if (!p->base1) {
 281                dev_err(&pdev->dev, "failed to remap high I/O memory\n");
 282                ret = -ENXIO;
 283                goto err0;
 284        }
 285
 286        if (!pdata) {
 287                memset(&pdata_dt, 0, sizeof(pdata_dt));
 288                pdata = &pdata_dt;
 289
 290                if (of_property_read_u32(pdev->dev.of_node, "ngpios",
 291                                         &pdata->number_of_pins)) {
 292                        dev_err(&pdev->dev, "Missing ngpios OF property\n");
 293                        ret = -EINVAL;
 294                        goto err0;
 295                }
 296
 297                ret = of_alias_get_id(pdev->dev.of_node, "gpio");
 298                if (ret < 0) {
 299                        dev_err(&pdev->dev, "Couldn't get OF id\n");
 300                        goto err0;
 301                }
 302                pdata->gpio_base = ret * 32; /* 32 GPIOs per instance */
 303        }
 304
 305        gpio_chip = &p->gpio_chip;
 306        gpio_chip->direction_input = em_gio_direction_input;
 307        gpio_chip->get = em_gio_get;
 308        gpio_chip->direction_output = em_gio_direction_output;
 309        gpio_chip->set = em_gio_set;
 310        gpio_chip->to_irq = em_gio_to_irq;
 311        gpio_chip->label = name;
 312        gpio_chip->owner = THIS_MODULE;
 313        gpio_chip->base = pdata->gpio_base;
 314        gpio_chip->ngpio = pdata->number_of_pins;
 315
 316        irq_chip = &p->irq_chip;
 317        irq_chip->name = name;
 318        irq_chip->irq_mask = em_gio_irq_disable;
 319        irq_chip->irq_unmask = em_gio_irq_enable;
 320        irq_chip->irq_enable = em_gio_irq_enable;
 321        irq_chip->irq_disable = em_gio_irq_disable;
 322        irq_chip->irq_set_type = em_gio_irq_set_type;
 323        irq_chip->flags = IRQCHIP_SKIP_SET_WAKE;
 324
 325        p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
 326                                              pdata->number_of_pins,
 327                                              pdata->irq_base,
 328                                              &em_gio_irq_domain_ops, p);
 329        if (!p->irq_domain) {
 330                ret = -ENXIO;
 331                dev_err(&pdev->dev, "cannot initialize irq domain\n");
 332                goto err0;
 333        }
 334
 335        if (devm_request_irq(&pdev->dev, irq[0]->start,
 336                             em_gio_irq_handler, 0, name, p)) {
 337                dev_err(&pdev->dev, "failed to request low IRQ\n");
 338                ret = -ENOENT;
 339                goto err1;
 340        }
 341
 342        if (devm_request_irq(&pdev->dev, irq[1]->start,
 343                             em_gio_irq_handler, 0, name, p)) {
 344                dev_err(&pdev->dev, "failed to request high IRQ\n");
 345                ret = -ENOENT;
 346                goto err1;
 347        }
 348
 349        ret = gpiochip_add(gpio_chip);
 350        if (ret) {
 351                dev_err(&pdev->dev, "failed to add GPIO controller\n");
 352                goto err1;
 353        }
 354        return 0;
 355
 356err1:
 357        irq_domain_remove(p->irq_domain);
 358err0:
 359        return ret;
 360}
 361
 362static int em_gio_remove(struct platform_device *pdev)
 363{
 364        struct em_gio_priv *p = platform_get_drvdata(pdev);
 365        int ret;
 366
 367        ret = gpiochip_remove(&p->gpio_chip);
 368        if (ret)
 369                return ret;
 370
 371        irq_domain_remove(p->irq_domain);
 372        return 0;
 373}
 374
 375static const struct of_device_id em_gio_dt_ids[] = {
 376        { .compatible = "renesas,em-gio", },
 377        {},
 378};
 379MODULE_DEVICE_TABLE(of, em_gio_dt_ids);
 380
 381static struct platform_driver em_gio_device_driver = {
 382        .probe          = em_gio_probe,
 383        .remove         = em_gio_remove,
 384        .driver         = {
 385                .name   = "em_gio",
 386                .of_match_table = em_gio_dt_ids,
 387                .owner          = THIS_MODULE,
 388        }
 389};
 390
 391static int __init em_gio_init(void)
 392{
 393        return platform_driver_register(&em_gio_device_driver);
 394}
 395postcore_initcall(em_gio_init);
 396
 397static void __exit em_gio_exit(void)
 398{
 399        platform_driver_unregister(&em_gio_device_driver);
 400}
 401module_exit(em_gio_exit);
 402
 403MODULE_AUTHOR("Magnus Damm");
 404MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
 405MODULE_LICENSE("GPL v2");
 406
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