linux/drivers/edac/i5100_edac.c
<<
>>
Prefs
   1/*
   2 * Intel 5100 Memory Controllers kernel module
   3 *
   4 * This file may be distributed under the terms of the
   5 * GNU General Public License.
   6 *
   7 * This module is based on the following document:
   8 *
   9 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet
  10 *      http://download.intel.com/design/chipsets/datashts/318378.pdf
  11 *
  12 * The intel 5100 has two independent channels. EDAC core currently
  13 * can not reflect this configuration so instead the chip-select
  14 * rows for each respective channel are laid out one after another,
  15 * the first half belonging to channel 0, the second half belonging
  16 * to channel 1.
  17 *
  18 * This driver is for DDR2 DIMMs, and it uses chip select to select among the
  19 * several ranks. However, instead of showing memories as ranks, it outputs
  20 * them as DIMM's. An internal table creates the association between ranks
  21 * and DIMM's.
  22 */
  23#include <linux/module.h>
  24#include <linux/init.h>
  25#include <linux/pci.h>
  26#include <linux/pci_ids.h>
  27#include <linux/edac.h>
  28#include <linux/delay.h>
  29#include <linux/mmzone.h>
  30#include <linux/debugfs.h>
  31
  32#include "edac_core.h"
  33
  34/* register addresses */
  35
  36/* device 16, func 1 */
  37#define I5100_MC                0x40    /* Memory Control Register */
  38#define         I5100_MC_SCRBEN_MASK    (1 << 7)
  39#define         I5100_MC_SCRBDONE_MASK  (1 << 4)
  40#define I5100_MS                0x44    /* Memory Status Register */
  41#define I5100_SPDDATA           0x48    /* Serial Presence Detect Status Reg */
  42#define I5100_SPDCMD            0x4c    /* Serial Presence Detect Command Reg */
  43#define I5100_TOLM              0x6c    /* Top of Low Memory */
  44#define I5100_MIR0              0x80    /* Memory Interleave Range 0 */
  45#define I5100_MIR1              0x84    /* Memory Interleave Range 1 */
  46#define I5100_AMIR_0            0x8c    /* Adjusted Memory Interleave Range 0 */
  47#define I5100_AMIR_1            0x90    /* Adjusted Memory Interleave Range 1 */
  48#define I5100_FERR_NF_MEM       0xa0    /* MC First Non Fatal Errors */
  49#define         I5100_FERR_NF_MEM_M16ERR_MASK   (1 << 16)
  50#define         I5100_FERR_NF_MEM_M15ERR_MASK   (1 << 15)
  51#define         I5100_FERR_NF_MEM_M14ERR_MASK   (1 << 14)
  52#define         I5100_FERR_NF_MEM_M12ERR_MASK   (1 << 12)
  53#define         I5100_FERR_NF_MEM_M11ERR_MASK   (1 << 11)
  54#define         I5100_FERR_NF_MEM_M10ERR_MASK   (1 << 10)
  55#define         I5100_FERR_NF_MEM_M6ERR_MASK    (1 << 6)
  56#define         I5100_FERR_NF_MEM_M5ERR_MASK    (1 << 5)
  57#define         I5100_FERR_NF_MEM_M4ERR_MASK    (1 << 4)
  58#define         I5100_FERR_NF_MEM_M1ERR_MASK    (1 << 1)
  59#define         I5100_FERR_NF_MEM_ANY_MASK      \
  60                        (I5100_FERR_NF_MEM_M16ERR_MASK | \
  61                        I5100_FERR_NF_MEM_M15ERR_MASK | \
  62                        I5100_FERR_NF_MEM_M14ERR_MASK | \
  63                        I5100_FERR_NF_MEM_M12ERR_MASK | \
  64                        I5100_FERR_NF_MEM_M11ERR_MASK | \
  65                        I5100_FERR_NF_MEM_M10ERR_MASK | \
  66                        I5100_FERR_NF_MEM_M6ERR_MASK | \
  67                        I5100_FERR_NF_MEM_M5ERR_MASK | \
  68                        I5100_FERR_NF_MEM_M4ERR_MASK | \
  69                        I5100_FERR_NF_MEM_M1ERR_MASK)
  70#define I5100_NERR_NF_MEM       0xa4    /* MC Next Non-Fatal Errors */
  71#define I5100_EMASK_MEM         0xa8    /* MC Error Mask Register */
  72#define I5100_MEM0EINJMSK0      0x200   /* Injection Mask0 Register Channel 0 */
  73#define I5100_MEM1EINJMSK0      0x208   /* Injection Mask0 Register Channel 1 */
  74#define         I5100_MEMXEINJMSK0_EINJEN       (1 << 27)
  75#define I5100_MEM0EINJMSK1      0x204   /* Injection Mask1 Register Channel 0 */
  76#define I5100_MEM1EINJMSK1      0x206   /* Injection Mask1 Register Channel 1 */
  77
  78/* Device 19, Function 0 */
  79#define I5100_DINJ0 0x9a
  80
  81/* device 21 and 22, func 0 */
  82#define I5100_MTR_0     0x154   /* Memory Technology Registers 0-3 */
  83#define I5100_DMIR      0x15c   /* DIMM Interleave Range */
  84#define I5100_VALIDLOG  0x18c   /* Valid Log Markers */
  85#define I5100_NRECMEMA  0x190   /* Non-Recoverable Memory Error Log Reg A */
  86#define I5100_NRECMEMB  0x194   /* Non-Recoverable Memory Error Log Reg B */
  87#define I5100_REDMEMA   0x198   /* Recoverable Memory Data Error Log Reg A */
  88#define I5100_REDMEMB   0x19c   /* Recoverable Memory Data Error Log Reg B */
  89#define I5100_RECMEMA   0x1a0   /* Recoverable Memory Error Log Reg A */
  90#define I5100_RECMEMB   0x1a4   /* Recoverable Memory Error Log Reg B */
  91#define I5100_MTR_4     0x1b0   /* Memory Technology Registers 4,5 */
  92
  93/* bit field accessors */
  94
  95static inline u32 i5100_mc_scrben(u32 mc)
  96{
  97        return mc >> 7 & 1;
  98}
  99
 100static inline u32 i5100_mc_errdeten(u32 mc)
 101{
 102        return mc >> 5 & 1;
 103}
 104
 105static inline u32 i5100_mc_scrbdone(u32 mc)
 106{
 107        return mc >> 4 & 1;
 108}
 109
 110static inline u16 i5100_spddata_rdo(u16 a)
 111{
 112        return a >> 15 & 1;
 113}
 114
 115static inline u16 i5100_spddata_sbe(u16 a)
 116{
 117        return a >> 13 & 1;
 118}
 119
 120static inline u16 i5100_spddata_busy(u16 a)
 121{
 122        return a >> 12 & 1;
 123}
 124
 125static inline u16 i5100_spddata_data(u16 a)
 126{
 127        return a & ((1 << 8) - 1);
 128}
 129
 130static inline u32 i5100_spdcmd_create(u32 dti, u32 ckovrd, u32 sa, u32 ba,
 131                                      u32 data, u32 cmd)
 132{
 133        return  ((dti & ((1 << 4) - 1))  << 28) |
 134                ((ckovrd & 1)            << 27) |
 135                ((sa & ((1 << 3) - 1))   << 24) |
 136                ((ba & ((1 << 8) - 1))   << 16) |
 137                ((data & ((1 << 8) - 1)) <<  8) |
 138                (cmd & 1);
 139}
 140
 141static inline u16 i5100_tolm_tolm(u16 a)
 142{
 143        return a >> 12 & ((1 << 4) - 1);
 144}
 145
 146static inline u16 i5100_mir_limit(u16 a)
 147{
 148        return a >> 4 & ((1 << 12) - 1);
 149}
 150
 151static inline u16 i5100_mir_way1(u16 a)
 152{
 153        return a >> 1 & 1;
 154}
 155
 156static inline u16 i5100_mir_way0(u16 a)
 157{
 158        return a & 1;
 159}
 160
 161static inline u32 i5100_ferr_nf_mem_chan_indx(u32 a)
 162{
 163        return a >> 28 & 1;
 164}
 165
 166static inline u32 i5100_ferr_nf_mem_any(u32 a)
 167{
 168        return a & I5100_FERR_NF_MEM_ANY_MASK;
 169}
 170
 171static inline u32 i5100_nerr_nf_mem_any(u32 a)
 172{
 173        return i5100_ferr_nf_mem_any(a);
 174}
 175
 176static inline u32 i5100_dmir_limit(u32 a)
 177{
 178        return a >> 16 & ((1 << 11) - 1);
 179}
 180
 181static inline u32 i5100_dmir_rank(u32 a, u32 i)
 182{
 183        return a >> (4 * i) & ((1 << 2) - 1);
 184}
 185
 186static inline u16 i5100_mtr_present(u16 a)
 187{
 188        return a >> 10 & 1;
 189}
 190
 191static inline u16 i5100_mtr_ethrottle(u16 a)
 192{
 193        return a >> 9 & 1;
 194}
 195
 196static inline u16 i5100_mtr_width(u16 a)
 197{
 198        return a >> 8 & 1;
 199}
 200
 201static inline u16 i5100_mtr_numbank(u16 a)
 202{
 203        return a >> 6 & 1;
 204}
 205
 206static inline u16 i5100_mtr_numrow(u16 a)
 207{
 208        return a >> 2 & ((1 << 2) - 1);
 209}
 210
 211static inline u16 i5100_mtr_numcol(u16 a)
 212{
 213        return a & ((1 << 2) - 1);
 214}
 215
 216
 217static inline u32 i5100_validlog_redmemvalid(u32 a)
 218{
 219        return a >> 2 & 1;
 220}
 221
 222static inline u32 i5100_validlog_recmemvalid(u32 a)
 223{
 224        return a >> 1 & 1;
 225}
 226
 227static inline u32 i5100_validlog_nrecmemvalid(u32 a)
 228{
 229        return a & 1;
 230}
 231
 232static inline u32 i5100_nrecmema_merr(u32 a)
 233{
 234        return a >> 15 & ((1 << 5) - 1);
 235}
 236
 237static inline u32 i5100_nrecmema_bank(u32 a)
 238{
 239        return a >> 12 & ((1 << 3) - 1);
 240}
 241
 242static inline u32 i5100_nrecmema_rank(u32 a)
 243{
 244        return a >>  8 & ((1 << 3) - 1);
 245}
 246
 247static inline u32 i5100_nrecmema_dm_buf_id(u32 a)
 248{
 249        return a & ((1 << 8) - 1);
 250}
 251
 252static inline u32 i5100_nrecmemb_cas(u32 a)
 253{
 254        return a >> 16 & ((1 << 13) - 1);
 255}
 256
 257static inline u32 i5100_nrecmemb_ras(u32 a)
 258{
 259        return a & ((1 << 16) - 1);
 260}
 261
 262static inline u32 i5100_redmemb_ecc_locator(u32 a)
 263{
 264        return a & ((1 << 18) - 1);
 265}
 266
 267static inline u32 i5100_recmema_merr(u32 a)
 268{
 269        return i5100_nrecmema_merr(a);
 270}
 271
 272static inline u32 i5100_recmema_bank(u32 a)
 273{
 274        return i5100_nrecmema_bank(a);
 275}
 276
 277static inline u32 i5100_recmema_rank(u32 a)
 278{
 279        return i5100_nrecmema_rank(a);
 280}
 281
 282static inline u32 i5100_recmema_dm_buf_id(u32 a)
 283{
 284        return i5100_nrecmema_dm_buf_id(a);
 285}
 286
 287static inline u32 i5100_recmemb_cas(u32 a)
 288{
 289        return i5100_nrecmemb_cas(a);
 290}
 291
 292static inline u32 i5100_recmemb_ras(u32 a)
 293{
 294        return i5100_nrecmemb_ras(a);
 295}
 296
 297/* some generic limits */
 298#define I5100_MAX_RANKS_PER_CHAN        6
 299#define I5100_CHANNELS                      2
 300#define I5100_MAX_RANKS_PER_DIMM        4
 301#define I5100_DIMM_ADDR_LINES           (6 - 3) /* 64 bits / 8 bits per byte */
 302#define I5100_MAX_DIMM_SLOTS_PER_CHAN   4
 303#define I5100_MAX_RANK_INTERLEAVE       4
 304#define I5100_MAX_DMIRS                 5
 305#define I5100_SCRUB_REFRESH_RATE        (5 * 60 * HZ)
 306
 307struct i5100_priv {
 308        /* ranks on each dimm -- 0 maps to not present -- obtained via SPD */
 309        int dimm_numrank[I5100_CHANNELS][I5100_MAX_DIMM_SLOTS_PER_CHAN];
 310
 311        /*
 312         * mainboard chip select map -- maps i5100 chip selects to
 313         * DIMM slot chip selects.  In the case of only 4 ranks per
 314         * channel, the mapping is fairly obvious but not unique.
 315         * we map -1 -> NC and assume both channels use the same
 316         * map...
 317         *
 318         */
 319        int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CHAN][I5100_MAX_RANKS_PER_DIMM];
 320
 321        /* memory interleave range */
 322        struct {
 323                u64      limit;
 324                unsigned way[2];
 325        } mir[I5100_CHANNELS];
 326
 327        /* adjusted memory interleave range register */
 328        unsigned amir[I5100_CHANNELS];
 329
 330        /* dimm interleave range */
 331        struct {
 332                unsigned rank[I5100_MAX_RANK_INTERLEAVE];
 333                u64      limit;
 334        } dmir[I5100_CHANNELS][I5100_MAX_DMIRS];
 335
 336        /* memory technology registers... */
 337        struct {
 338                unsigned present;       /* 0 or 1 */
 339                unsigned ethrottle;     /* 0 or 1 */
 340                unsigned width;         /* 4 or 8 bits  */
 341                unsigned numbank;       /* 2 or 3 lines */
 342                unsigned numrow;        /* 13 .. 16 lines */
 343                unsigned numcol;        /* 11 .. 12 lines */
 344        } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN];
 345
 346        u64 tolm;               /* top of low memory in bytes */
 347        unsigned ranksperchan;  /* number of ranks per channel */
 348
 349        struct pci_dev *mc;     /* device 16 func 1 */
 350        struct pci_dev *einj;   /* device 19 func 0 */
 351        struct pci_dev *ch0mm;  /* device 21 func 0 */
 352        struct pci_dev *ch1mm;  /* device 22 func 0 */
 353
 354        struct delayed_work i5100_scrubbing;
 355        int scrub_enable;
 356
 357        /* Error injection */
 358        u8 inject_channel;
 359        u8 inject_hlinesel;
 360        u8 inject_deviceptr1;
 361        u8 inject_deviceptr2;
 362        u16 inject_eccmask1;
 363        u16 inject_eccmask2;
 364
 365        struct dentry *debugfs;
 366};
 367
 368static struct dentry *i5100_debugfs;
 369
 370/* map a rank/chan to a slot number on the mainboard */
 371static int i5100_rank_to_slot(const struct mem_ctl_info *mci,
 372                              int chan, int rank)
 373{
 374        const struct i5100_priv *priv = mci->pvt_info;
 375        int i;
 376
 377        for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
 378                int j;
 379                const int numrank = priv->dimm_numrank[chan][i];
 380
 381                for (j = 0; j < numrank; j++)
 382                        if (priv->dimm_csmap[i][j] == rank)
 383                                return i * 2 + chan;
 384        }
 385
 386        return -1;
 387}
 388
 389static const char *i5100_err_msg(unsigned err)
 390{
 391        static const char *merrs[] = {
 392                "unknown", /* 0 */
 393                "uncorrectable data ECC on replay", /* 1 */
 394                "unknown", /* 2 */
 395                "unknown", /* 3 */
 396                "aliased uncorrectable demand data ECC", /* 4 */
 397                "aliased uncorrectable spare-copy data ECC", /* 5 */
 398                "aliased uncorrectable patrol data ECC", /* 6 */
 399                "unknown", /* 7 */
 400                "unknown", /* 8 */
 401                "unknown", /* 9 */
 402                "non-aliased uncorrectable demand data ECC", /* 10 */
 403                "non-aliased uncorrectable spare-copy data ECC", /* 11 */
 404                "non-aliased uncorrectable patrol data ECC", /* 12 */
 405                "unknown", /* 13 */
 406                "correctable demand data ECC", /* 14 */
 407                "correctable spare-copy data ECC", /* 15 */
 408                "correctable patrol data ECC", /* 16 */
 409                "unknown", /* 17 */
 410                "SPD protocol error", /* 18 */
 411                "unknown", /* 19 */
 412                "spare copy initiated", /* 20 */
 413                "spare copy completed", /* 21 */
 414        };
 415        unsigned i;
 416
 417        for (i = 0; i < ARRAY_SIZE(merrs); i++)
 418                if (1 << i & err)
 419                        return merrs[i];
 420
 421        return "none";
 422}
 423
 424/* convert csrow index into a rank (per channel -- 0..5) */
 425static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow)
 426{
 427        const struct i5100_priv *priv = mci->pvt_info;
 428
 429        return csrow % priv->ranksperchan;
 430}
 431
 432/* convert csrow index into a channel (0..1) */
 433static int i5100_csrow_to_chan(const struct mem_ctl_info *mci, int csrow)
 434{
 435        const struct i5100_priv *priv = mci->pvt_info;
 436
 437        return csrow / priv->ranksperchan;
 438}
 439
 440static void i5100_handle_ce(struct mem_ctl_info *mci,
 441                            int chan,
 442                            unsigned bank,
 443                            unsigned rank,
 444                            unsigned long syndrome,
 445                            unsigned cas,
 446                            unsigned ras,
 447                            const char *msg)
 448{
 449        char detail[80];
 450
 451        /* Form out message */
 452        snprintf(detail, sizeof(detail),
 453                 "bank %u, cas %u, ras %u\n",
 454                 bank, cas, ras);
 455
 456        edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
 457                             0, 0, syndrome,
 458                             chan, rank, -1,
 459                             msg, detail);
 460}
 461
 462static void i5100_handle_ue(struct mem_ctl_info *mci,
 463                            int chan,
 464                            unsigned bank,
 465                            unsigned rank,
 466                            unsigned long syndrome,
 467                            unsigned cas,
 468                            unsigned ras,
 469                            const char *msg)
 470{
 471        char detail[80];
 472
 473        /* Form out message */
 474        snprintf(detail, sizeof(detail),
 475                 "bank %u, cas %u, ras %u\n",
 476                 bank, cas, ras);
 477
 478        edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
 479                             0, 0, syndrome,
 480                             chan, rank, -1,
 481                             msg, detail);
 482}
 483
 484static void i5100_read_log(struct mem_ctl_info *mci, int chan,
 485                           u32 ferr, u32 nerr)
 486{
 487        struct i5100_priv *priv = mci->pvt_info;
 488        struct pci_dev *pdev = (chan) ? priv->ch1mm : priv->ch0mm;
 489        u32 dw;
 490        u32 dw2;
 491        unsigned syndrome = 0;
 492        unsigned ecc_loc = 0;
 493        unsigned merr;
 494        unsigned bank;
 495        unsigned rank;
 496        unsigned cas;
 497        unsigned ras;
 498
 499        pci_read_config_dword(pdev, I5100_VALIDLOG, &dw);
 500
 501        if (i5100_validlog_redmemvalid(dw)) {
 502                pci_read_config_dword(pdev, I5100_REDMEMA, &dw2);
 503                syndrome = dw2;
 504                pci_read_config_dword(pdev, I5100_REDMEMB, &dw2);
 505                ecc_loc = i5100_redmemb_ecc_locator(dw2);
 506        }
 507
 508        if (i5100_validlog_recmemvalid(dw)) {
 509                const char *msg;
 510
 511                pci_read_config_dword(pdev, I5100_RECMEMA, &dw2);
 512                merr = i5100_recmema_merr(dw2);
 513                bank = i5100_recmema_bank(dw2);
 514                rank = i5100_recmema_rank(dw2);
 515
 516                pci_read_config_dword(pdev, I5100_RECMEMB, &dw2);
 517                cas = i5100_recmemb_cas(dw2);
 518                ras = i5100_recmemb_ras(dw2);
 519
 520                /* FIXME:  not really sure if this is what merr is...
 521                 */
 522                if (!merr)
 523                        msg = i5100_err_msg(ferr);
 524                else
 525                        msg = i5100_err_msg(nerr);
 526
 527                i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg);
 528        }
 529
 530        if (i5100_validlog_nrecmemvalid(dw)) {
 531                const char *msg;
 532
 533                pci_read_config_dword(pdev, I5100_NRECMEMA, &dw2);
 534                merr = i5100_nrecmema_merr(dw2);
 535                bank = i5100_nrecmema_bank(dw2);
 536                rank = i5100_nrecmema_rank(dw2);
 537
 538                pci_read_config_dword(pdev, I5100_NRECMEMB, &dw2);
 539                cas = i5100_nrecmemb_cas(dw2);
 540                ras = i5100_nrecmemb_ras(dw2);
 541
 542                /* FIXME:  not really sure if this is what merr is...
 543                 */
 544                if (!merr)
 545                        msg = i5100_err_msg(ferr);
 546                else
 547                        msg = i5100_err_msg(nerr);
 548
 549                i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg);
 550        }
 551
 552        pci_write_config_dword(pdev, I5100_VALIDLOG, dw);
 553}
 554
 555static void i5100_check_error(struct mem_ctl_info *mci)
 556{
 557        struct i5100_priv *priv = mci->pvt_info;
 558        u32 dw, dw2;
 559
 560        pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw);
 561        if (i5100_ferr_nf_mem_any(dw)) {
 562
 563                pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2);
 564
 565                i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw),
 566                               i5100_ferr_nf_mem_any(dw),
 567                               i5100_nerr_nf_mem_any(dw2));
 568
 569                pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, dw2);
 570        }
 571        pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw);
 572}
 573
 574/* The i5100 chipset will scrub the entire memory once, then
 575 * set a done bit. Continuous scrubbing is achieved by enqueing
 576 * delayed work to a workqueue, checking every few minutes if
 577 * the scrubbing has completed and if so reinitiating it.
 578 */
 579
 580static void i5100_refresh_scrubbing(struct work_struct *work)
 581{
 582        struct delayed_work *i5100_scrubbing = container_of(work,
 583                                                            struct delayed_work,
 584                                                            work);
 585        struct i5100_priv *priv = container_of(i5100_scrubbing,
 586                                               struct i5100_priv,
 587                                               i5100_scrubbing);
 588        u32 dw;
 589
 590        pci_read_config_dword(priv->mc, I5100_MC, &dw);
 591
 592        if (priv->scrub_enable) {
 593
 594                pci_read_config_dword(priv->mc, I5100_MC, &dw);
 595
 596                if (i5100_mc_scrbdone(dw)) {
 597                        dw |= I5100_MC_SCRBEN_MASK;
 598                        pci_write_config_dword(priv->mc, I5100_MC, dw);
 599                        pci_read_config_dword(priv->mc, I5100_MC, &dw);
 600                }
 601
 602                schedule_delayed_work(&(priv->i5100_scrubbing),
 603                                      I5100_SCRUB_REFRESH_RATE);
 604        }
 605}
 606/*
 607 * The bandwidth is based on experimentation, feel free to refine it.
 608 */
 609static int i5100_set_scrub_rate(struct mem_ctl_info *mci, u32 bandwidth)
 610{
 611        struct i5100_priv *priv = mci->pvt_info;
 612        u32 dw;
 613
 614        pci_read_config_dword(priv->mc, I5100_MC, &dw);
 615        if (bandwidth) {
 616                priv->scrub_enable = 1;
 617                dw |= I5100_MC_SCRBEN_MASK;
 618                schedule_delayed_work(&(priv->i5100_scrubbing),
 619                                      I5100_SCRUB_REFRESH_RATE);
 620        } else {
 621                priv->scrub_enable = 0;
 622                dw &= ~I5100_MC_SCRBEN_MASK;
 623                cancel_delayed_work(&(priv->i5100_scrubbing));
 624        }
 625        pci_write_config_dword(priv->mc, I5100_MC, dw);
 626
 627        pci_read_config_dword(priv->mc, I5100_MC, &dw);
 628
 629        bandwidth = 5900000 * i5100_mc_scrben(dw);
 630
 631        return bandwidth;
 632}
 633
 634static int i5100_get_scrub_rate(struct mem_ctl_info *mci)
 635{
 636        struct i5100_priv *priv = mci->pvt_info;
 637        u32 dw;
 638
 639        pci_read_config_dword(priv->mc, I5100_MC, &dw);
 640
 641        return 5900000 * i5100_mc_scrben(dw);
 642}
 643
 644static struct pci_dev *pci_get_device_func(unsigned vendor,
 645                                           unsigned device,
 646                                           unsigned func)
 647{
 648        struct pci_dev *ret = NULL;
 649
 650        while (1) {
 651                ret = pci_get_device(vendor, device, ret);
 652
 653                if (!ret)
 654                        break;
 655
 656                if (PCI_FUNC(ret->devfn) == func)
 657                        break;
 658        }
 659
 660        return ret;
 661}
 662
 663static unsigned long i5100_npages(struct mem_ctl_info *mci, int csrow)
 664{
 665        struct i5100_priv *priv = mci->pvt_info;
 666        const unsigned chan_rank = i5100_csrow_to_rank(mci, csrow);
 667        const unsigned chan = i5100_csrow_to_chan(mci, csrow);
 668        unsigned addr_lines;
 669
 670        /* dimm present? */
 671        if (!priv->mtr[chan][chan_rank].present)
 672                return 0ULL;
 673
 674        addr_lines =
 675                I5100_DIMM_ADDR_LINES +
 676                priv->mtr[chan][chan_rank].numcol +
 677                priv->mtr[chan][chan_rank].numrow +
 678                priv->mtr[chan][chan_rank].numbank;
 679
 680        return (unsigned long)
 681                ((unsigned long long) (1ULL << addr_lines) / PAGE_SIZE);
 682}
 683
 684static void i5100_init_mtr(struct mem_ctl_info *mci)
 685{
 686        struct i5100_priv *priv = mci->pvt_info;
 687        struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
 688        int i;
 689
 690        for (i = 0; i < I5100_CHANNELS; i++) {
 691                int j;
 692                struct pci_dev *pdev = mms[i];
 693
 694                for (j = 0; j < I5100_MAX_RANKS_PER_CHAN; j++) {
 695                        const unsigned addr =
 696                                (j < 4) ? I5100_MTR_0 + j * 2 :
 697                                          I5100_MTR_4 + (j - 4) * 2;
 698                        u16 w;
 699
 700                        pci_read_config_word(pdev, addr, &w);
 701
 702                        priv->mtr[i][j].present = i5100_mtr_present(w);
 703                        priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w);
 704                        priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w);
 705                        priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w);
 706                        priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w);
 707                        priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w);
 708                }
 709        }
 710}
 711
 712/*
 713 * FIXME: make this into a real i2c adapter (so that dimm-decode
 714 * will work)?
 715 */
 716static int i5100_read_spd_byte(const struct mem_ctl_info *mci,
 717                               u8 ch, u8 slot, u8 addr, u8 *byte)
 718{
 719        struct i5100_priv *priv = mci->pvt_info;
 720        u16 w;
 721        unsigned long et;
 722
 723        pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
 724        if (i5100_spddata_busy(w))
 725                return -1;
 726
 727        pci_write_config_dword(priv->mc, I5100_SPDCMD,
 728                               i5100_spdcmd_create(0xa, 1, ch * 4 + slot, addr,
 729                                                   0, 0));
 730
 731        /* wait up to 100ms */
 732        et = jiffies + HZ / 10;
 733        udelay(100);
 734        while (1) {
 735                pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
 736                if (!i5100_spddata_busy(w))
 737                        break;
 738                udelay(100);
 739        }
 740
 741        if (!i5100_spddata_rdo(w) || i5100_spddata_sbe(w))
 742                return -1;
 743
 744        *byte = i5100_spddata_data(w);
 745
 746        return 0;
 747}
 748
 749/*
 750 * fill dimm chip select map
 751 *
 752 * FIXME:
 753 *   o not the only way to may chip selects to dimm slots
 754 *   o investigate if there is some way to obtain this map from the bios
 755 */
 756static void i5100_init_dimm_csmap(struct mem_ctl_info *mci)
 757{
 758        struct i5100_priv *priv = mci->pvt_info;
 759        int i;
 760
 761        for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
 762                int j;
 763
 764                for (j = 0; j < I5100_MAX_RANKS_PER_DIMM; j++)
 765                        priv->dimm_csmap[i][j] = -1; /* default NC */
 766        }
 767
 768        /* only 2 chip selects per slot... */
 769        if (priv->ranksperchan == 4) {
 770                priv->dimm_csmap[0][0] = 0;
 771                priv->dimm_csmap[0][1] = 3;
 772                priv->dimm_csmap[1][0] = 1;
 773                priv->dimm_csmap[1][1] = 2;
 774                priv->dimm_csmap[2][0] = 2;
 775                priv->dimm_csmap[3][0] = 3;
 776        } else {
 777                priv->dimm_csmap[0][0] = 0;
 778                priv->dimm_csmap[0][1] = 1;
 779                priv->dimm_csmap[1][0] = 2;
 780                priv->dimm_csmap[1][1] = 3;
 781                priv->dimm_csmap[2][0] = 4;
 782                priv->dimm_csmap[2][1] = 5;
 783        }
 784}
 785
 786static void i5100_init_dimm_layout(struct pci_dev *pdev,
 787                                   struct mem_ctl_info *mci)
 788{
 789        struct i5100_priv *priv = mci->pvt_info;
 790        int i;
 791
 792        for (i = 0; i < I5100_CHANNELS; i++) {
 793                int j;
 794
 795                for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CHAN; j++) {
 796                        u8 rank;
 797
 798                        if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0)
 799                                priv->dimm_numrank[i][j] = 0;
 800                        else
 801                                priv->dimm_numrank[i][j] = (rank & 3) + 1;
 802                }
 803        }
 804
 805        i5100_init_dimm_csmap(mci);
 806}
 807
 808static void i5100_init_interleaving(struct pci_dev *pdev,
 809                                    struct mem_ctl_info *mci)
 810{
 811        u16 w;
 812        u32 dw;
 813        struct i5100_priv *priv = mci->pvt_info;
 814        struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
 815        int i;
 816
 817        pci_read_config_word(pdev, I5100_TOLM, &w);
 818        priv->tolm = (u64) i5100_tolm_tolm(w) * 256 * 1024 * 1024;
 819
 820        pci_read_config_word(pdev, I5100_MIR0, &w);
 821        priv->mir[0].limit = (u64) i5100_mir_limit(w) << 28;
 822        priv->mir[0].way[1] = i5100_mir_way1(w);
 823        priv->mir[0].way[0] = i5100_mir_way0(w);
 824
 825        pci_read_config_word(pdev, I5100_MIR1, &w);
 826        priv->mir[1].limit = (u64) i5100_mir_limit(w) << 28;
 827        priv->mir[1].way[1] = i5100_mir_way1(w);
 828        priv->mir[1].way[0] = i5100_mir_way0(w);
 829
 830        pci_read_config_word(pdev, I5100_AMIR_0, &w);
 831        priv->amir[0] = w;
 832        pci_read_config_word(pdev, I5100_AMIR_1, &w);
 833        priv->amir[1] = w;
 834
 835        for (i = 0; i < I5100_CHANNELS; i++) {
 836                int j;
 837
 838                for (j = 0; j < 5; j++) {
 839                        int k;
 840
 841                        pci_read_config_dword(mms[i], I5100_DMIR + j * 4, &dw);
 842
 843                        priv->dmir[i][j].limit =
 844                                (u64) i5100_dmir_limit(dw) << 28;
 845                        for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++)
 846                                priv->dmir[i][j].rank[k] =
 847                                        i5100_dmir_rank(dw, k);
 848                }
 849        }
 850
 851        i5100_init_mtr(mci);
 852}
 853
 854static void i5100_init_csrows(struct mem_ctl_info *mci)
 855{
 856        int i;
 857        struct i5100_priv *priv = mci->pvt_info;
 858
 859        for (i = 0; i < mci->tot_dimms; i++) {
 860                struct dimm_info *dimm;
 861                const unsigned long npages = i5100_npages(mci, i);
 862                const unsigned chan = i5100_csrow_to_chan(mci, i);
 863                const unsigned rank = i5100_csrow_to_rank(mci, i);
 864
 865                if (!npages)
 866                        continue;
 867
 868                dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
 869                               chan, rank, 0);
 870
 871                dimm->nr_pages = npages;
 872                if (npages) {
 873                        dimm->grain = 32;
 874                        dimm->dtype = (priv->mtr[chan][rank].width == 4) ?
 875                                        DEV_X4 : DEV_X8;
 876                        dimm->mtype = MEM_RDDR2;
 877                        dimm->edac_mode = EDAC_SECDED;
 878                        snprintf(dimm->label, sizeof(dimm->label),
 879                                "DIMM%u",
 880                                i5100_rank_to_slot(mci, chan, rank));
 881                }
 882
 883                edac_dbg(2, "dimm channel %d, rank %d, size %ld\n",
 884                         chan, rank, (long)PAGES_TO_MiB(npages));
 885        }
 886}
 887
 888/****************************************************************************
 889 *                       Error injection routines
 890 ****************************************************************************/
 891
 892static void i5100_do_inject(struct mem_ctl_info *mci)
 893{
 894        struct i5100_priv *priv = mci->pvt_info;
 895        u32 mask0;
 896        u16 mask1;
 897
 898        /* MEM[1:0]EINJMSK0
 899         * 31    - ADDRMATCHEN
 900         * 29:28 - HLINESEL
 901         *         00 Reserved
 902         *         01 Lower half of cache line
 903         *         10 Upper half of cache line
 904         *         11 Both upper and lower parts of cache line
 905         * 27    - EINJEN
 906         * 25:19 - XORMASK1 for deviceptr1
 907         * 9:5   - SEC2RAM for deviceptr2
 908         * 4:0   - FIR2RAM for deviceptr1
 909         */
 910        mask0 = ((priv->inject_hlinesel & 0x3) << 28) |
 911                I5100_MEMXEINJMSK0_EINJEN |
 912                ((priv->inject_eccmask1 & 0xffff) << 10) |
 913                ((priv->inject_deviceptr2 & 0x1f) << 5) |
 914                (priv->inject_deviceptr1 & 0x1f);
 915
 916        /* MEM[1:0]EINJMSK1
 917         * 15:0  - XORMASK2 for deviceptr2
 918         */
 919        mask1 = priv->inject_eccmask2;
 920
 921        if (priv->inject_channel == 0) {
 922                pci_write_config_dword(priv->mc, I5100_MEM0EINJMSK0, mask0);
 923                pci_write_config_word(priv->mc, I5100_MEM0EINJMSK1, mask1);
 924        } else {
 925                pci_write_config_dword(priv->mc, I5100_MEM1EINJMSK0, mask0);
 926                pci_write_config_word(priv->mc, I5100_MEM1EINJMSK1, mask1);
 927        }
 928
 929        /* Error Injection Response Function
 930         * Intel 5100 Memory Controller Hub Chipset (318378) datasheet
 931         * hints about this register but carry no data about them. All
 932         * data regarding device 19 is based on experimentation and the
 933         * Intel 7300 Chipset Memory Controller Hub (318082) datasheet
 934         * which appears to be accurate for the i5100 in this area.
 935         *
 936         * The injection code don't work without setting this register.
 937         * The register needs to be flipped off then on else the hardware
 938         * will only preform the first injection.
 939         *
 940         * Stop condition bits 7:4
 941         * 1010 - Stop after one injection
 942         * 1011 - Never stop injecting faults
 943         *
 944         * Start condition bits 3:0
 945         * 1010 - Never start
 946         * 1011 - Start immediately
 947         */
 948        pci_write_config_byte(priv->einj, I5100_DINJ0, 0xaa);
 949        pci_write_config_byte(priv->einj, I5100_DINJ0, 0xab);
 950}
 951
 952#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
 953static ssize_t inject_enable_write(struct file *file, const char __user *data,
 954                size_t count, loff_t *ppos)
 955{
 956        struct device *dev = file->private_data;
 957        struct mem_ctl_info *mci = to_mci(dev);
 958
 959        i5100_do_inject(mci);
 960
 961        return count;
 962}
 963
 964static const struct file_operations i5100_inject_enable_fops = {
 965        .open = simple_open,
 966        .write = inject_enable_write,
 967        .llseek = generic_file_llseek,
 968};
 969
 970static int i5100_setup_debugfs(struct mem_ctl_info *mci)
 971{
 972        struct i5100_priv *priv = mci->pvt_info;
 973
 974        if (!i5100_debugfs)
 975                return -ENODEV;
 976
 977        priv->debugfs = debugfs_create_dir(mci->bus.name, i5100_debugfs);
 978
 979        if (!priv->debugfs)
 980                return -ENOMEM;
 981
 982        debugfs_create_x8("inject_channel", S_IRUGO | S_IWUSR, priv->debugfs,
 983                        &priv->inject_channel);
 984        debugfs_create_x8("inject_hlinesel", S_IRUGO | S_IWUSR, priv->debugfs,
 985                        &priv->inject_hlinesel);
 986        debugfs_create_x8("inject_deviceptr1", S_IRUGO | S_IWUSR, priv->debugfs,
 987                        &priv->inject_deviceptr1);
 988        debugfs_create_x8("inject_deviceptr2", S_IRUGO | S_IWUSR, priv->debugfs,
 989                        &priv->inject_deviceptr2);
 990        debugfs_create_x16("inject_eccmask1", S_IRUGO | S_IWUSR, priv->debugfs,
 991                        &priv->inject_eccmask1);
 992        debugfs_create_x16("inject_eccmask2", S_IRUGO | S_IWUSR, priv->debugfs,
 993                        &priv->inject_eccmask2);
 994        debugfs_create_file("inject_enable", S_IWUSR, priv->debugfs,
 995                        &mci->dev, &i5100_inject_enable_fops);
 996
 997        return 0;
 998
 999}
1000
1001static int i5100_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1002{
1003        int rc;
1004        struct mem_ctl_info *mci;
1005        struct edac_mc_layer layers[2];
1006        struct i5100_priv *priv;
1007        struct pci_dev *ch0mm, *ch1mm, *einj;
1008        int ret = 0;
1009        u32 dw;
1010        int ranksperch;
1011
1012        if (PCI_FUNC(pdev->devfn) != 1)
1013                return -ENODEV;
1014
1015        rc = pci_enable_device(pdev);
1016        if (rc < 0) {
1017                ret = rc;
1018                goto bail;
1019        }
1020
1021        /* ECC enabled? */
1022        pci_read_config_dword(pdev, I5100_MC, &dw);
1023        if (!i5100_mc_errdeten(dw)) {
1024                printk(KERN_INFO "i5100_edac: ECC not enabled.\n");
1025                ret = -ENODEV;
1026                goto bail_pdev;
1027        }
1028
1029        /* figure out how many ranks, from strapped state of 48GB_Mode input */
1030        pci_read_config_dword(pdev, I5100_MS, &dw);
1031        ranksperch = !!(dw & (1 << 8)) * 2 + 4;
1032
1033        /* enable error reporting... */
1034        pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw);
1035        dw &= ~I5100_FERR_NF_MEM_ANY_MASK;
1036        pci_write_config_dword(pdev, I5100_EMASK_MEM, dw);
1037
1038        /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */
1039        ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
1040                                    PCI_DEVICE_ID_INTEL_5100_21, 0);
1041        if (!ch0mm) {
1042                ret = -ENODEV;
1043                goto bail_pdev;
1044        }
1045
1046        rc = pci_enable_device(ch0mm);
1047        if (rc < 0) {
1048                ret = rc;
1049                goto bail_ch0;
1050        }
1051
1052        /* device 22, func 0, Channel 1 Memory Map, Error Flag/Mask, etc... */
1053        ch1mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
1054                                    PCI_DEVICE_ID_INTEL_5100_22, 0);
1055        if (!ch1mm) {
1056                ret = -ENODEV;
1057                goto bail_disable_ch0;
1058        }
1059
1060        rc = pci_enable_device(ch1mm);
1061        if (rc < 0) {
1062                ret = rc;
1063                goto bail_ch1;
1064        }
1065
1066        layers[0].type = EDAC_MC_LAYER_CHANNEL;
1067        layers[0].size = 2;
1068        layers[0].is_virt_csrow = false;
1069        layers[1].type = EDAC_MC_LAYER_SLOT;
1070        layers[1].size = ranksperch;
1071        layers[1].is_virt_csrow = true;
1072        mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
1073                            sizeof(*priv));
1074        if (!mci) {
1075                ret = -ENOMEM;
1076                goto bail_disable_ch1;
1077        }
1078
1079
1080        /* device 19, func 0, Error injection */
1081        einj = pci_get_device_func(PCI_VENDOR_ID_INTEL,
1082                                    PCI_DEVICE_ID_INTEL_5100_19, 0);
1083        if (!einj) {
1084                ret = -ENODEV;
1085                goto bail_einj;
1086        }
1087
1088        rc = pci_enable_device(einj);
1089        if (rc < 0) {
1090                ret = rc;
1091                goto bail_disable_einj;
1092        }
1093
1094
1095        mci->pdev = &pdev->dev;
1096
1097        priv = mci->pvt_info;
1098        priv->ranksperchan = ranksperch;
1099        priv->mc = pdev;
1100        priv->ch0mm = ch0mm;
1101        priv->ch1mm = ch1mm;
1102        priv->einj = einj;
1103
1104        INIT_DELAYED_WORK(&(priv->i5100_scrubbing), i5100_refresh_scrubbing);
1105
1106        /* If scrubbing was already enabled by the bios, start maintaining it */
1107        pci_read_config_dword(pdev, I5100_MC, &dw);
1108        if (i5100_mc_scrben(dw)) {
1109                priv->scrub_enable = 1;
1110                schedule_delayed_work(&(priv->i5100_scrubbing),
1111                                      I5100_SCRUB_REFRESH_RATE);
1112        }
1113
1114        i5100_init_dimm_layout(pdev, mci);
1115        i5100_init_interleaving(pdev, mci);
1116
1117        mci->mtype_cap = MEM_FLAG_FB_DDR2;
1118        mci->edac_ctl_cap = EDAC_FLAG_SECDED;
1119        mci->edac_cap = EDAC_FLAG_SECDED;
1120        mci->mod_name = "i5100_edac.c";
1121        mci->mod_ver = "not versioned";
1122        mci->ctl_name = "i5100";
1123        mci->dev_name = pci_name(pdev);
1124        mci->ctl_page_to_phys = NULL;
1125
1126        mci->edac_check = i5100_check_error;
1127        mci->set_sdram_scrub_rate = i5100_set_scrub_rate;
1128        mci->get_sdram_scrub_rate = i5100_get_scrub_rate;
1129
1130        priv->inject_channel = 0;
1131        priv->inject_hlinesel = 0;
1132        priv->inject_deviceptr1 = 0;
1133        priv->inject_deviceptr2 = 0;
1134        priv->inject_eccmask1 = 0;
1135        priv->inject_eccmask2 = 0;
1136
1137        i5100_init_csrows(mci);
1138
1139        /* this strange construction seems to be in every driver, dunno why */
1140        switch (edac_op_state) {
1141        case EDAC_OPSTATE_POLL:
1142        case EDAC_OPSTATE_NMI:
1143                break;
1144        default:
1145                edac_op_state = EDAC_OPSTATE_POLL;
1146                break;
1147        }
1148
1149        if (edac_mc_add_mc(mci)) {
1150                ret = -ENODEV;
1151                goto bail_scrub;
1152        }
1153
1154        i5100_setup_debugfs(mci);
1155
1156        return ret;
1157
1158bail_scrub:
1159        priv->scrub_enable = 0;
1160        cancel_delayed_work_sync(&(priv->i5100_scrubbing));
1161        edac_mc_free(mci);
1162
1163bail_disable_einj:
1164        pci_disable_device(einj);
1165
1166bail_einj:
1167        pci_dev_put(einj);
1168
1169bail_disable_ch1:
1170        pci_disable_device(ch1mm);
1171
1172bail_ch1:
1173        pci_dev_put(ch1mm);
1174
1175bail_disable_ch0:
1176        pci_disable_device(ch0mm);
1177
1178bail_ch0:
1179        pci_dev_put(ch0mm);
1180
1181bail_pdev:
1182        pci_disable_device(pdev);
1183
1184bail:
1185        return ret;
1186}
1187
1188static void i5100_remove_one(struct pci_dev *pdev)
1189{
1190        struct mem_ctl_info *mci;
1191        struct i5100_priv *priv;
1192
1193        mci = edac_mc_del_mc(&pdev->dev);
1194
1195        if (!mci)
1196                return;
1197
1198        priv = mci->pvt_info;
1199
1200        debugfs_remove_recursive(priv->debugfs);
1201
1202        priv->scrub_enable = 0;
1203        cancel_delayed_work_sync(&(priv->i5100_scrubbing));
1204
1205        pci_disable_device(pdev);
1206        pci_disable_device(priv->ch0mm);
1207        pci_disable_device(priv->ch1mm);
1208        pci_disable_device(priv->einj);
1209        pci_dev_put(priv->ch0mm);
1210        pci_dev_put(priv->ch1mm);
1211        pci_dev_put(priv->einj);
1212
1213        edac_mc_free(mci);
1214}
1215
1216static DEFINE_PCI_DEVICE_TABLE(i5100_pci_tbl) = {
1217        /* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */
1218        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) },
1219        { 0, }
1220};
1221MODULE_DEVICE_TABLE(pci, i5100_pci_tbl);
1222
1223static struct pci_driver i5100_driver = {
1224        .name = KBUILD_BASENAME,
1225        .probe = i5100_init_one,
1226        .remove = i5100_remove_one,
1227        .id_table = i5100_pci_tbl,
1228};
1229
1230static int __init i5100_init(void)
1231{
1232        int pci_rc;
1233
1234        i5100_debugfs = debugfs_create_dir("i5100_edac", NULL);
1235
1236        pci_rc = pci_register_driver(&i5100_driver);
1237        return (pci_rc < 0) ? pci_rc : 0;
1238}
1239
1240static void __exit i5100_exit(void)
1241{
1242        debugfs_remove(i5100_debugfs);
1243
1244        pci_unregister_driver(&i5100_driver);
1245}
1246
1247module_init(i5100_init);
1248module_exit(i5100_exit);
1249
1250MODULE_LICENSE("GPL");
1251MODULE_AUTHOR
1252    ("Arthur Jones <ajones@riverbed.com>");
1253MODULE_DESCRIPTION("MC Driver for Intel I5100 memory controllers");
1254
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.