linux/drivers/edac/amd64_edac.h
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   1/*
   2 * AMD64 class Memory Controller kernel module
   3 *
   4 * Copyright (c) 2009 SoftwareBitMaker.
   5 * Copyright (c) 2009 Advanced Micro Devices, Inc.
   6 *
   7 * This file may be distributed under the terms of the
   8 * GNU General Public License.
   9 *
  10 *      Originally Written by Thayne Harbaugh
  11 *
  12 *      Changes by Douglas "norsk" Thompson  <dougthompson@xmission.com>:
  13 *              - K8 CPU Revision D and greater support
  14 *
  15 *      Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>:
  16 *              - Module largely rewritten, with new (and hopefully correct)
  17 *              code for dealing with node and chip select interleaving,
  18 *              various code cleanup, and bug fixes
  19 *              - Added support for memory hoisting using DRAM hole address
  20 *              register
  21 *
  22 *      Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
  23 *              -K8 Rev (1207) revision support added, required Revision
  24 *              specific mini-driver code to support Rev F as well as
  25 *              prior revisions
  26 *
  27 *      Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
  28 *              -Family 10h revision support added. New PCI Device IDs,
  29 *              indicating new changes. Actual registers modified
  30 *              were slight, less than the Rev E to Rev F transition
  31 *              but changing the PCI Device ID was the proper thing to
  32 *              do, as it provides for almost automactic family
  33 *              detection. The mods to Rev F required more family
  34 *              information detection.
  35 *
  36 *      Changes/Fixes by Borislav Petkov <bp@alien8.de>:
  37 *              - misc fixes and code cleanups
  38 *
  39 * This module is based on the following documents
  40 * (available from http://www.amd.com/):
  41 *
  42 *      Title:  BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD
  43 *              Opteron Processors
  44 *      AMD publication #: 26094
  45 *`     Revision: 3.26
  46 *
  47 *      Title:  BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh
  48 *              Processors
  49 *      AMD publication #: 32559
  50 *      Revision: 3.00
  51 *      Issue Date: May 2006
  52 *
  53 *      Title:  BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h
  54 *              Processors
  55 *      AMD publication #: 31116
  56 *      Revision: 3.00
  57 *      Issue Date: September 07, 2007
  58 *
  59 * Sections in the first 2 documents are no longer in sync with each other.
  60 * The Family 10h BKDG was totally re-written from scratch with a new
  61 * presentation model.
  62 * Therefore, comments that refer to a Document section might be off.
  63 */
  64
  65#include <linux/module.h>
  66#include <linux/ctype.h>
  67#include <linux/init.h>
  68#include <linux/pci.h>
  69#include <linux/pci_ids.h>
  70#include <linux/slab.h>
  71#include <linux/mmzone.h>
  72#include <linux/edac.h>
  73#include <asm/msr.h>
  74#include "edac_core.h"
  75#include "mce_amd.h"
  76
  77#define amd64_debug(fmt, arg...) \
  78        edac_printk(KERN_DEBUG, "amd64", fmt, ##arg)
  79
  80#define amd64_info(fmt, arg...) \
  81        edac_printk(KERN_INFO, "amd64", fmt, ##arg)
  82
  83#define amd64_notice(fmt, arg...) \
  84        edac_printk(KERN_NOTICE, "amd64", fmt, ##arg)
  85
  86#define amd64_warn(fmt, arg...) \
  87        edac_printk(KERN_WARNING, "amd64", fmt, ##arg)
  88
  89#define amd64_err(fmt, arg...) \
  90        edac_printk(KERN_ERR, "amd64", fmt, ##arg)
  91
  92#define amd64_mc_warn(mci, fmt, arg...) \
  93        edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
  94
  95#define amd64_mc_err(mci, fmt, arg...) \
  96        edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
  97
  98/*
  99 * Throughout the comments in this code, the following terms are used:
 100 *
 101 *      SysAddr, DramAddr, and InputAddr
 102 *
 103 *  These terms come directly from the amd64 documentation
 104 * (AMD publication #26094).  They are defined as follows:
 105 *
 106 *     SysAddr:
 107 *         This is a physical address generated by a CPU core or a device
 108 *         doing DMA.  If generated by a CPU core, a SysAddr is the result of
 109 *         a virtual to physical address translation by the CPU core's address
 110 *         translation mechanism (MMU).
 111 *
 112 *     DramAddr:
 113 *         A DramAddr is derived from a SysAddr by subtracting an offset that
 114 *         depends on which node the SysAddr maps to and whether the SysAddr
 115 *         is within a range affected by memory hoisting.  The DRAM Base
 116 *         (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
 117 *         determine which node a SysAddr maps to.
 118 *
 119 *         If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
 120 *         is within the range of addresses specified by this register, then
 121 *         a value x from the DHAR is subtracted from the SysAddr to produce a
 122 *         DramAddr.  Here, x represents the base address for the node that
 123 *         the SysAddr maps to plus an offset due to memory hoisting.  See
 124 *         section 3.4.8 and the comments in amd64_get_dram_hole_info() and
 125 *         sys_addr_to_dram_addr() below for more information.
 126 *
 127 *         If the SysAddr is not affected by the DHAR then a value y is
 128 *         subtracted from the SysAddr to produce a DramAddr.  Here, y is the
 129 *         base address for the node that the SysAddr maps to.  See section
 130 *         3.4.4 and the comments in sys_addr_to_dram_addr() below for more
 131 *         information.
 132 *
 133 *     InputAddr:
 134 *         A DramAddr is translated to an InputAddr before being passed to the
 135 *         memory controller for the node that the DramAddr is associated
 136 *         with.  The memory controller then maps the InputAddr to a csrow.
 137 *         If node interleaving is not in use, then the InputAddr has the same
 138 *         value as the DramAddr.  Otherwise, the InputAddr is produced by
 139 *         discarding the bits used for node interleaving from the DramAddr.
 140 *         See section 3.4.4 for more information.
 141 *
 142 *         The memory controller for a given node uses its DRAM CS Base and
 143 *         DRAM CS Mask registers to map an InputAddr to a csrow.  See
 144 *         sections 3.5.4 and 3.5.5 for more information.
 145 */
 146
 147#define EDAC_AMD64_VERSION              "3.4.0"
 148#define EDAC_MOD_STR                    "amd64_edac"
 149
 150/* Extended Model from CPUID, for CPU Revision numbers */
 151#define K8_REV_D                        1
 152#define K8_REV_E                        2
 153#define K8_REV_F                        4
 154
 155/* Hardware limit on ChipSelect rows per MC and processors per system */
 156#define NUM_CHIPSELECTS                 8
 157#define DRAM_RANGES                     8
 158
 159#define ON true
 160#define OFF false
 161
 162/*
 163 * Create a contiguous bitmask starting at bit position @lo and ending at
 164 * position @hi. For example
 165 *
 166 * GENMASK(21, 39) gives us the 64bit vector 0x000000ffffe00000.
 167 */
 168#define GENMASK(lo, hi)                 (((1ULL << ((hi) - (lo) + 1)) - 1) << (lo))
 169
 170/*
 171 * PCI-defined configuration space registers
 172 */
 173#define PCI_DEVICE_ID_AMD_15H_NB_F1     0x1601
 174#define PCI_DEVICE_ID_AMD_15H_NB_F2     0x1602
 175#define PCI_DEVICE_ID_AMD_16H_NB_F1     0x1531
 176#define PCI_DEVICE_ID_AMD_16H_NB_F2     0x1532
 177
 178/*
 179 * Function 1 - Address Map
 180 */
 181#define DRAM_BASE_LO                    0x40
 182#define DRAM_LIMIT_LO                   0x44
 183
 184#define dram_intlv_en(pvt, i)           ((u8)((pvt->ranges[i].base.lo >> 8) & 0x7))
 185#define dram_rw(pvt, i)                 ((u8)(pvt->ranges[i].base.lo & 0x3))
 186#define dram_intlv_sel(pvt, i)          ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
 187#define dram_dst_node(pvt, i)           ((u8)(pvt->ranges[i].lim.lo & 0x7))
 188
 189#define DHAR                            0xf0
 190#define dhar_valid(pvt)                 ((pvt)->dhar & BIT(0))
 191#define dhar_mem_hoist_valid(pvt)       ((pvt)->dhar & BIT(1))
 192#define dhar_base(pvt)                  ((pvt)->dhar & 0xff000000)
 193#define k8_dhar_offset(pvt)             (((pvt)->dhar & 0x0000ff00) << 16)
 194
 195                                        /* NOTE: Extra mask bit vs K8 */
 196#define f10_dhar_offset(pvt)            (((pvt)->dhar & 0x0000ff80) << 16)
 197
 198#define DCT_CFG_SEL                     0x10C
 199
 200#define DRAM_LOCAL_NODE_BASE            0x120
 201#define DRAM_LOCAL_NODE_LIM             0x124
 202
 203#define DRAM_BASE_HI                    0x140
 204#define DRAM_LIMIT_HI                   0x144
 205
 206
 207/*
 208 * Function 2 - DRAM controller
 209 */
 210#define DCSB0                           0x40
 211#define DCSB1                           0x140
 212#define DCSB_CS_ENABLE                  BIT(0)
 213
 214#define DCSM0                           0x60
 215#define DCSM1                           0x160
 216
 217#define csrow_enabled(i, dct, pvt)      ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
 218
 219#define DBAM0                           0x80
 220#define DBAM1                           0x180
 221
 222/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
 223#define DBAM_DIMM(i, reg)               ((((reg) >> (4*(i)))) & 0xF)
 224
 225#define DBAM_MAX_VALUE                  11
 226
 227#define DCLR0                           0x90
 228#define DCLR1                           0x190
 229#define REVE_WIDTH_128                  BIT(16)
 230#define WIDTH_128                       BIT(11)
 231
 232#define DCHR0                           0x94
 233#define DCHR1                           0x194
 234#define DDR3_MODE                       BIT(8)
 235
 236#define DCT_SEL_LO                      0x110
 237#define dct_sel_baseaddr(pvt)           ((pvt)->dct_sel_lo & 0xFFFFF800)
 238#define dct_sel_interleave_addr(pvt)    (((pvt)->dct_sel_lo >> 6) & 0x3)
 239#define dct_high_range_enabled(pvt)     ((pvt)->dct_sel_lo & BIT(0))
 240#define dct_interleave_enabled(pvt)     ((pvt)->dct_sel_lo & BIT(2))
 241
 242#define dct_ganging_enabled(pvt)        ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
 243
 244#define dct_data_intlv_enabled(pvt)     ((pvt)->dct_sel_lo & BIT(5))
 245#define dct_memory_cleared(pvt)         ((pvt)->dct_sel_lo & BIT(10))
 246
 247#define SWAP_INTLV_REG                  0x10c
 248
 249#define DCT_SEL_HI                      0x114
 250
 251/*
 252 * Function 3 - Misc Control
 253 */
 254#define NBCTL                           0x40
 255
 256#define NBCFG                           0x44
 257#define NBCFG_CHIPKILL                  BIT(23)
 258#define NBCFG_ECC_ENABLE                BIT(22)
 259
 260/* F3x48: NBSL */
 261#define F10_NBSL_EXT_ERR_ECC            0x8
 262#define NBSL_PP_OBS                     0x2
 263
 264#define SCRCTRL                         0x58
 265
 266#define F10_ONLINE_SPARE                0xB0
 267#define online_spare_swap_done(pvt, c)  (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
 268#define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
 269
 270#define F10_NB_ARRAY_ADDR               0xB8
 271#define F10_NB_ARRAY_DRAM               BIT(31)
 272
 273/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline  */
 274#define SET_NB_ARRAY_ADDR(section)      (((section) & 0x3) << 1)
 275
 276#define F10_NB_ARRAY_DATA               0xBC
 277#define F10_NB_ARR_ECC_WR_REQ           BIT(17)
 278#define SET_NB_DRAM_INJECTION_WRITE(inj)  \
 279                                        (BIT(((inj.word) & 0xF) + 20) | \
 280                                        F10_NB_ARR_ECC_WR_REQ | inj.bit_map)
 281#define SET_NB_DRAM_INJECTION_READ(inj)  \
 282                                        (BIT(((inj.word) & 0xF) + 20) | \
 283                                        BIT(16) |  inj.bit_map)
 284
 285
 286#define NBCAP                           0xE8
 287#define NBCAP_CHIPKILL                  BIT(4)
 288#define NBCAP_SECDED                    BIT(3)
 289#define NBCAP_DCT_DUAL                  BIT(0)
 290
 291#define EXT_NB_MCA_CFG                  0x180
 292
 293/* MSRs */
 294#define MSR_MCGCTL_NBE                  BIT(4)
 295
 296enum amd_families {
 297        K8_CPUS = 0,
 298        F10_CPUS,
 299        F15_CPUS,
 300        F16_CPUS,
 301        NUM_FAMILIES,
 302};
 303
 304/* Error injection control structure */
 305struct error_injection {
 306        u32      section;
 307        u32      word;
 308        u32      bit_map;
 309};
 310
 311/* low and high part of PCI config space regs */
 312struct reg_pair {
 313        u32 lo, hi;
 314};
 315
 316/*
 317 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
 318 */
 319struct dram_range {
 320        struct reg_pair base;
 321        struct reg_pair lim;
 322};
 323
 324/* A DCT chip selects collection */
 325struct chip_select {
 326        u32 csbases[NUM_CHIPSELECTS];
 327        u8 b_cnt;
 328
 329        u32 csmasks[NUM_CHIPSELECTS];
 330        u8 m_cnt;
 331};
 332
 333struct amd64_pvt {
 334        struct low_ops *ops;
 335
 336        /* pci_device handles which we utilize */
 337        struct pci_dev *F1, *F2, *F3;
 338
 339        u16 mc_node_id;         /* MC index of this MC node */
 340        int ext_model;          /* extended model value of this node */
 341        int channel_count;
 342
 343        /* Raw registers */
 344        u32 dclr0;              /* DRAM Configuration Low DCT0 reg */
 345        u32 dclr1;              /* DRAM Configuration Low DCT1 reg */
 346        u32 dchr0;              /* DRAM Configuration High DCT0 reg */
 347        u32 dchr1;              /* DRAM Configuration High DCT1 reg */
 348        u32 nbcap;              /* North Bridge Capabilities */
 349        u32 nbcfg;              /* F10 North Bridge Configuration */
 350        u32 ext_nbcfg;          /* Extended F10 North Bridge Configuration */
 351        u32 dhar;               /* DRAM Hoist reg */
 352        u32 dbam0;              /* DRAM Base Address Mapping reg for DCT0 */
 353        u32 dbam1;              /* DRAM Base Address Mapping reg for DCT1 */
 354
 355        /* one for each DCT */
 356        struct chip_select csels[2];
 357
 358        /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
 359        struct dram_range ranges[DRAM_RANGES];
 360
 361        u64 top_mem;            /* top of memory below 4GB */
 362        u64 top_mem2;           /* top of memory above 4GB */
 363
 364        u32 dct_sel_lo;         /* DRAM Controller Select Low */
 365        u32 dct_sel_hi;         /* DRAM Controller Select High */
 366        u32 online_spare;       /* On-Line spare Reg */
 367
 368        /* x4 or x8 syndromes in use */
 369        u8 ecc_sym_sz;
 370
 371        /* place to store error injection parameters prior to issue */
 372        struct error_injection injection;
 373};
 374
 375enum err_codes {
 376        DECODE_OK       =  0,
 377        ERR_NODE        = -1,
 378        ERR_CSROW       = -2,
 379        ERR_CHANNEL     = -3,
 380};
 381
 382struct err_info {
 383        int err_code;
 384        struct mem_ctl_info *src_mci;
 385        int csrow;
 386        int channel;
 387        u16 syndrome;
 388        u32 page;
 389        u32 offset;
 390};
 391
 392static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
 393{
 394        u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
 395
 396        if (boot_cpu_data.x86 == 0xf)
 397                return addr;
 398
 399        return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
 400}
 401
 402static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
 403{
 404        u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
 405
 406        if (boot_cpu_data.x86 == 0xf)
 407                return lim;
 408
 409        return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
 410}
 411
 412static inline u16 extract_syndrome(u64 status)
 413{
 414        return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
 415}
 416
 417/*
 418 * per-node ECC settings descriptor
 419 */
 420struct ecc_settings {
 421        u32 old_nbctl;
 422        bool nbctl_valid;
 423
 424        struct flags {
 425                unsigned long nb_mce_enable:1;
 426                unsigned long nb_ecc_prev:1;
 427        } flags;
 428};
 429
 430#ifdef CONFIG_EDAC_DEBUG
 431int amd64_create_sysfs_dbg_files(struct mem_ctl_info *mci);
 432void amd64_remove_sysfs_dbg_files(struct mem_ctl_info *mci);
 433
 434#else
 435static inline int amd64_create_sysfs_dbg_files(struct mem_ctl_info *mci)
 436{
 437        return 0;
 438}
 439static void inline amd64_remove_sysfs_dbg_files(struct mem_ctl_info *mci)
 440{
 441}
 442#endif
 443
 444#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
 445int amd64_create_sysfs_inject_files(struct mem_ctl_info *mci);
 446void amd64_remove_sysfs_inject_files(struct mem_ctl_info *mci);
 447
 448#else
 449static inline int amd64_create_sysfs_inject_files(struct mem_ctl_info *mci)
 450{
 451        return 0;
 452}
 453static inline void amd64_remove_sysfs_inject_files(struct mem_ctl_info *mci)
 454{
 455}
 456#endif
 457
 458/*
 459 * Each of the PCI Device IDs types have their own set of hardware accessor
 460 * functions and per device encoding/decoding logic.
 461 */
 462struct low_ops {
 463        int (*early_channel_count)      (struct amd64_pvt *pvt);
 464        void (*map_sysaddr_to_csrow)    (struct mem_ctl_info *mci, u64 sys_addr,
 465                                         struct err_info *);
 466        int (*dbam_to_cs)               (struct amd64_pvt *pvt, u8 dct, unsigned cs_mode);
 467        int (*read_dct_pci_cfg)         (struct amd64_pvt *pvt, int offset,
 468                                         u32 *val, const char *func);
 469};
 470
 471struct amd64_family_type {
 472        const char *ctl_name;
 473        u16 f1_id, f3_id;
 474        struct low_ops ops;
 475};
 476
 477int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
 478                               u32 *val, const char *func);
 479int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
 480                                u32 val, const char *func);
 481
 482#define amd64_read_pci_cfg(pdev, offset, val)   \
 483        __amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
 484
 485#define amd64_write_pci_cfg(pdev, offset, val)  \
 486        __amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
 487
 488#define amd64_read_dct_pci_cfg(pvt, offset, val) \
 489        pvt->ops->read_dct_pci_cfg(pvt, offset, val, __func__)
 490
 491int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
 492                             u64 *hole_offset, u64 *hole_size);
 493
 494#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
 495
 496/* Injection helpers */
 497static inline void disable_caches(void *dummy)
 498{
 499        write_cr0(read_cr0() | X86_CR0_CD);
 500        wbinvd();
 501}
 502
 503static inline void enable_caches(void *dummy)
 504{
 505        write_cr0(read_cr0() & ~X86_CR0_CD);
 506}
 507
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