linux/drivers/dma/omap-dma.c
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   1/*
   2 * OMAP DMAengine support
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License version 2 as
   6 * published by the Free Software Foundation.
   7 */
   8#include <linux/dmaengine.h>
   9#include <linux/dma-mapping.h>
  10#include <linux/err.h>
  11#include <linux/init.h>
  12#include <linux/interrupt.h>
  13#include <linux/list.h>
  14#include <linux/module.h>
  15#include <linux/omap-dma.h>
  16#include <linux/platform_device.h>
  17#include <linux/slab.h>
  18#include <linux/spinlock.h>
  19#include <linux/of_dma.h>
  20#include <linux/of_device.h>
  21
  22#include "virt-dma.h"
  23
  24struct omap_dmadev {
  25        struct dma_device ddev;
  26        spinlock_t lock;
  27        struct tasklet_struct task;
  28        struct list_head pending;
  29};
  30
  31struct omap_chan {
  32        struct virt_dma_chan vc;
  33        struct list_head node;
  34
  35        struct dma_slave_config cfg;
  36        unsigned dma_sig;
  37        bool cyclic;
  38        bool paused;
  39
  40        int dma_ch;
  41        struct omap_desc *desc;
  42        unsigned sgidx;
  43};
  44
  45struct omap_sg {
  46        dma_addr_t addr;
  47        uint32_t en;            /* number of elements (24-bit) */
  48        uint32_t fn;            /* number of frames (16-bit) */
  49};
  50
  51struct omap_desc {
  52        struct virt_dma_desc vd;
  53        enum dma_transfer_direction dir;
  54        dma_addr_t dev_addr;
  55
  56        int16_t fi;             /* for OMAP_DMA_SYNC_PACKET */
  57        uint8_t es;             /* OMAP_DMA_DATA_TYPE_xxx */
  58        uint8_t sync_mode;      /* OMAP_DMA_SYNC_xxx */
  59        uint8_t sync_type;      /* OMAP_DMA_xxx_SYNC* */
  60        uint8_t periph_port;    /* Peripheral port */
  61
  62        unsigned sglen;
  63        struct omap_sg sg[0];
  64};
  65
  66static const unsigned es_bytes[] = {
  67        [OMAP_DMA_DATA_TYPE_S8] = 1,
  68        [OMAP_DMA_DATA_TYPE_S16] = 2,
  69        [OMAP_DMA_DATA_TYPE_S32] = 4,
  70};
  71
  72static struct of_dma_filter_info omap_dma_info = {
  73        .filter_fn = omap_dma_filter_fn,
  74};
  75
  76static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d)
  77{
  78        return container_of(d, struct omap_dmadev, ddev);
  79}
  80
  81static inline struct omap_chan *to_omap_dma_chan(struct dma_chan *c)
  82{
  83        return container_of(c, struct omap_chan, vc.chan);
  84}
  85
  86static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor *t)
  87{
  88        return container_of(t, struct omap_desc, vd.tx);
  89}
  90
  91static void omap_dma_desc_free(struct virt_dma_desc *vd)
  92{
  93        kfree(container_of(vd, struct omap_desc, vd));
  94}
  95
  96static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
  97        unsigned idx)
  98{
  99        struct omap_sg *sg = d->sg + idx;
 100
 101        if (d->dir == DMA_DEV_TO_MEM)
 102                omap_set_dma_dest_params(c->dma_ch, OMAP_DMA_PORT_EMIFF,
 103                        OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0);
 104        else
 105                omap_set_dma_src_params(c->dma_ch, OMAP_DMA_PORT_EMIFF,
 106                        OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0);
 107
 108        omap_set_dma_transfer_params(c->dma_ch, d->es, sg->en, sg->fn,
 109                d->sync_mode, c->dma_sig, d->sync_type);
 110
 111        omap_start_dma(c->dma_ch);
 112}
 113
 114static void omap_dma_start_desc(struct omap_chan *c)
 115{
 116        struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
 117        struct omap_desc *d;
 118
 119        if (!vd) {
 120                c->desc = NULL;
 121                return;
 122        }
 123
 124        list_del(&vd->node);
 125
 126        c->desc = d = to_omap_dma_desc(&vd->tx);
 127        c->sgidx = 0;
 128
 129        if (d->dir == DMA_DEV_TO_MEM)
 130                omap_set_dma_src_params(c->dma_ch, d->periph_port,
 131                        OMAP_DMA_AMODE_CONSTANT, d->dev_addr, 0, d->fi);
 132        else
 133                omap_set_dma_dest_params(c->dma_ch, d->periph_port,
 134                        OMAP_DMA_AMODE_CONSTANT, d->dev_addr, 0, d->fi);
 135
 136        omap_dma_start_sg(c, d, 0);
 137}
 138
 139static void omap_dma_callback(int ch, u16 status, void *data)
 140{
 141        struct omap_chan *c = data;
 142        struct omap_desc *d;
 143        unsigned long flags;
 144
 145        spin_lock_irqsave(&c->vc.lock, flags);
 146        d = c->desc;
 147        if (d) {
 148                if (!c->cyclic) {
 149                        if (++c->sgidx < d->sglen) {
 150                                omap_dma_start_sg(c, d, c->sgidx);
 151                        } else {
 152                                omap_dma_start_desc(c);
 153                                vchan_cookie_complete(&d->vd);
 154                        }
 155                } else {
 156                        vchan_cyclic_callback(&d->vd);
 157                }
 158        }
 159        spin_unlock_irqrestore(&c->vc.lock, flags);
 160}
 161
 162/*
 163 * This callback schedules all pending channels.  We could be more
 164 * clever here by postponing allocation of the real DMA channels to
 165 * this point, and freeing them when our virtual channel becomes idle.
 166 *
 167 * We would then need to deal with 'all channels in-use'
 168 */
 169static void omap_dma_sched(unsigned long data)
 170{
 171        struct omap_dmadev *d = (struct omap_dmadev *)data;
 172        LIST_HEAD(head);
 173
 174        spin_lock_irq(&d->lock);
 175        list_splice_tail_init(&d->pending, &head);
 176        spin_unlock_irq(&d->lock);
 177
 178        while (!list_empty(&head)) {
 179                struct omap_chan *c = list_first_entry(&head,
 180                        struct omap_chan, node);
 181
 182                spin_lock_irq(&c->vc.lock);
 183                list_del_init(&c->node);
 184                omap_dma_start_desc(c);
 185                spin_unlock_irq(&c->vc.lock);
 186        }
 187}
 188
 189static int omap_dma_alloc_chan_resources(struct dma_chan *chan)
 190{
 191        struct omap_chan *c = to_omap_dma_chan(chan);
 192
 193        dev_info(c->vc.chan.device->dev, "allocating channel for %u\n", c->dma_sig);
 194
 195        return omap_request_dma(c->dma_sig, "DMA engine",
 196                omap_dma_callback, c, &c->dma_ch);
 197}
 198
 199static void omap_dma_free_chan_resources(struct dma_chan *chan)
 200{
 201        struct omap_chan *c = to_omap_dma_chan(chan);
 202
 203        vchan_free_chan_resources(&c->vc);
 204        omap_free_dma(c->dma_ch);
 205
 206        dev_info(c->vc.chan.device->dev, "freeing channel for %u\n", c->dma_sig);
 207}
 208
 209static size_t omap_dma_sg_size(struct omap_sg *sg)
 210{
 211        return sg->en * sg->fn;
 212}
 213
 214static size_t omap_dma_desc_size(struct omap_desc *d)
 215{
 216        unsigned i;
 217        size_t size;
 218
 219        for (size = i = 0; i < d->sglen; i++)
 220                size += omap_dma_sg_size(&d->sg[i]);
 221
 222        return size * es_bytes[d->es];
 223}
 224
 225static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr)
 226{
 227        unsigned i;
 228        size_t size, es_size = es_bytes[d->es];
 229
 230        for (size = i = 0; i < d->sglen; i++) {
 231                size_t this_size = omap_dma_sg_size(&d->sg[i]) * es_size;
 232
 233                if (size)
 234                        size += this_size;
 235                else if (addr >= d->sg[i].addr &&
 236                         addr < d->sg[i].addr + this_size)
 237                        size += d->sg[i].addr + this_size - addr;
 238        }
 239        return size;
 240}
 241
 242static enum dma_status omap_dma_tx_status(struct dma_chan *chan,
 243        dma_cookie_t cookie, struct dma_tx_state *txstate)
 244{
 245        struct omap_chan *c = to_omap_dma_chan(chan);
 246        struct virt_dma_desc *vd;
 247        enum dma_status ret;
 248        unsigned long flags;
 249
 250        ret = dma_cookie_status(chan, cookie, txstate);
 251        if (ret == DMA_SUCCESS || !txstate)
 252                return ret;
 253
 254        spin_lock_irqsave(&c->vc.lock, flags);
 255        vd = vchan_find_desc(&c->vc, cookie);
 256        if (vd) {
 257                txstate->residue = omap_dma_desc_size(to_omap_dma_desc(&vd->tx));
 258        } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
 259                struct omap_desc *d = c->desc;
 260                dma_addr_t pos;
 261
 262                if (d->dir == DMA_MEM_TO_DEV)
 263                        pos = omap_get_dma_src_pos(c->dma_ch);
 264                else if (d->dir == DMA_DEV_TO_MEM)
 265                        pos = omap_get_dma_dst_pos(c->dma_ch);
 266                else
 267                        pos = 0;
 268
 269                txstate->residue = omap_dma_desc_size_pos(d, pos);
 270        } else {
 271                txstate->residue = 0;
 272        }
 273        spin_unlock_irqrestore(&c->vc.lock, flags);
 274
 275        return ret;
 276}
 277
 278static void omap_dma_issue_pending(struct dma_chan *chan)
 279{
 280        struct omap_chan *c = to_omap_dma_chan(chan);
 281        unsigned long flags;
 282
 283        spin_lock_irqsave(&c->vc.lock, flags);
 284        if (vchan_issue_pending(&c->vc) && !c->desc) {
 285                /*
 286                 * c->cyclic is used only by audio and in this case the DMA need
 287                 * to be started without delay.
 288                 */
 289                if (!c->cyclic) {
 290                        struct omap_dmadev *d = to_omap_dma_dev(chan->device);
 291                        spin_lock(&d->lock);
 292                        if (list_empty(&c->node))
 293                                list_add_tail(&c->node, &d->pending);
 294                        spin_unlock(&d->lock);
 295                        tasklet_schedule(&d->task);
 296                } else {
 297                        omap_dma_start_desc(c);
 298                }
 299        }
 300        spin_unlock_irqrestore(&c->vc.lock, flags);
 301}
 302
 303static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
 304        struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen,
 305        enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
 306{
 307        struct omap_chan *c = to_omap_dma_chan(chan);
 308        enum dma_slave_buswidth dev_width;
 309        struct scatterlist *sgent;
 310        struct omap_desc *d;
 311        dma_addr_t dev_addr;
 312        unsigned i, j = 0, es, en, frame_bytes, sync_type;
 313        u32 burst;
 314
 315        if (dir == DMA_DEV_TO_MEM) {
 316                dev_addr = c->cfg.src_addr;
 317                dev_width = c->cfg.src_addr_width;
 318                burst = c->cfg.src_maxburst;
 319                sync_type = OMAP_DMA_SRC_SYNC;
 320        } else if (dir == DMA_MEM_TO_DEV) {
 321                dev_addr = c->cfg.dst_addr;
 322                dev_width = c->cfg.dst_addr_width;
 323                burst = c->cfg.dst_maxburst;
 324                sync_type = OMAP_DMA_DST_SYNC;
 325        } else {
 326                dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
 327                return NULL;
 328        }
 329
 330        /* Bus width translates to the element size (ES) */
 331        switch (dev_width) {
 332        case DMA_SLAVE_BUSWIDTH_1_BYTE:
 333                es = OMAP_DMA_DATA_TYPE_S8;
 334                break;
 335        case DMA_SLAVE_BUSWIDTH_2_BYTES:
 336                es = OMAP_DMA_DATA_TYPE_S16;
 337                break;
 338        case DMA_SLAVE_BUSWIDTH_4_BYTES:
 339                es = OMAP_DMA_DATA_TYPE_S32;
 340                break;
 341        default: /* not reached */
 342                return NULL;
 343        }
 344
 345        /* Now allocate and setup the descriptor. */
 346        d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC);
 347        if (!d)
 348                return NULL;
 349
 350        d->dir = dir;
 351        d->dev_addr = dev_addr;
 352        d->es = es;
 353        d->sync_mode = OMAP_DMA_SYNC_FRAME;
 354        d->sync_type = sync_type;
 355        d->periph_port = OMAP_DMA_PORT_TIPB;
 356
 357        /*
 358         * Build our scatterlist entries: each contains the address,
 359         * the number of elements (EN) in each frame, and the number of
 360         * frames (FN).  Number of bytes for this entry = ES * EN * FN.
 361         *
 362         * Burst size translates to number of elements with frame sync.
 363         * Note: DMA engine defines burst to be the number of dev-width
 364         * transfers.
 365         */
 366        en = burst;
 367        frame_bytes = es_bytes[es] * en;
 368        for_each_sg(sgl, sgent, sglen, i) {
 369                d->sg[j].addr = sg_dma_address(sgent);
 370                d->sg[j].en = en;
 371                d->sg[j].fn = sg_dma_len(sgent) / frame_bytes;
 372                j++;
 373        }
 374
 375        d->sglen = j;
 376
 377        return vchan_tx_prep(&c->vc, &d->vd, tx_flags);
 378}
 379
 380static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
 381        struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
 382        size_t period_len, enum dma_transfer_direction dir, unsigned long flags,
 383        void *context)
 384{
 385        struct omap_chan *c = to_omap_dma_chan(chan);
 386        enum dma_slave_buswidth dev_width;
 387        struct omap_desc *d;
 388        dma_addr_t dev_addr;
 389        unsigned es, sync_type;
 390        u32 burst;
 391
 392        if (dir == DMA_DEV_TO_MEM) {
 393                dev_addr = c->cfg.src_addr;
 394                dev_width = c->cfg.src_addr_width;
 395                burst = c->cfg.src_maxburst;
 396                sync_type = OMAP_DMA_SRC_SYNC;
 397        } else if (dir == DMA_MEM_TO_DEV) {
 398                dev_addr = c->cfg.dst_addr;
 399                dev_width = c->cfg.dst_addr_width;
 400                burst = c->cfg.dst_maxburst;
 401                sync_type = OMAP_DMA_DST_SYNC;
 402        } else {
 403                dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
 404                return NULL;
 405        }
 406
 407        /* Bus width translates to the element size (ES) */
 408        switch (dev_width) {
 409        case DMA_SLAVE_BUSWIDTH_1_BYTE:
 410                es = OMAP_DMA_DATA_TYPE_S8;
 411                break;
 412        case DMA_SLAVE_BUSWIDTH_2_BYTES:
 413                es = OMAP_DMA_DATA_TYPE_S16;
 414                break;
 415        case DMA_SLAVE_BUSWIDTH_4_BYTES:
 416                es = OMAP_DMA_DATA_TYPE_S32;
 417                break;
 418        default: /* not reached */
 419                return NULL;
 420        }
 421
 422        /* Now allocate and setup the descriptor. */
 423        d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC);
 424        if (!d)
 425                return NULL;
 426
 427        d->dir = dir;
 428        d->dev_addr = dev_addr;
 429        d->fi = burst;
 430        d->es = es;
 431        if (burst)
 432                d->sync_mode = OMAP_DMA_SYNC_PACKET;
 433        else
 434                d->sync_mode = OMAP_DMA_SYNC_ELEMENT;
 435        d->sync_type = sync_type;
 436        d->periph_port = OMAP_DMA_PORT_MPUI;
 437        d->sg[0].addr = buf_addr;
 438        d->sg[0].en = period_len / es_bytes[es];
 439        d->sg[0].fn = buf_len / period_len;
 440        d->sglen = 1;
 441
 442        if (!c->cyclic) {
 443                c->cyclic = true;
 444                omap_dma_link_lch(c->dma_ch, c->dma_ch);
 445
 446                if (flags & DMA_PREP_INTERRUPT)
 447                        omap_enable_dma_irq(c->dma_ch, OMAP_DMA_FRAME_IRQ);
 448
 449                omap_disable_dma_irq(c->dma_ch, OMAP_DMA_BLOCK_IRQ);
 450        }
 451
 452        if (dma_omap2plus()) {
 453                omap_set_dma_src_burst_mode(c->dma_ch, OMAP_DMA_DATA_BURST_16);
 454                omap_set_dma_dest_burst_mode(c->dma_ch, OMAP_DMA_DATA_BURST_16);
 455        }
 456
 457        return vchan_tx_prep(&c->vc, &d->vd, flags);
 458}
 459
 460static int omap_dma_slave_config(struct omap_chan *c, struct dma_slave_config *cfg)
 461{
 462        if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
 463            cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
 464                return -EINVAL;
 465
 466        memcpy(&c->cfg, cfg, sizeof(c->cfg));
 467
 468        return 0;
 469}
 470
 471static int omap_dma_terminate_all(struct omap_chan *c)
 472{
 473        struct omap_dmadev *d = to_omap_dma_dev(c->vc.chan.device);
 474        unsigned long flags;
 475        LIST_HEAD(head);
 476
 477        spin_lock_irqsave(&c->vc.lock, flags);
 478
 479        /* Prevent this channel being scheduled */
 480        spin_lock(&d->lock);
 481        list_del_init(&c->node);
 482        spin_unlock(&d->lock);
 483
 484        /*
 485         * Stop DMA activity: we assume the callback will not be called
 486         * after omap_stop_dma() returns (even if it does, it will see
 487         * c->desc is NULL and exit.)
 488         */
 489        if (c->desc) {
 490                c->desc = NULL;
 491                /* Avoid stopping the dma twice */
 492                if (!c->paused)
 493                        omap_stop_dma(c->dma_ch);
 494        }
 495
 496        if (c->cyclic) {
 497                c->cyclic = false;
 498                c->paused = false;
 499                omap_dma_unlink_lch(c->dma_ch, c->dma_ch);
 500        }
 501
 502        vchan_get_all_descriptors(&c->vc, &head);
 503        spin_unlock_irqrestore(&c->vc.lock, flags);
 504        vchan_dma_desc_free_list(&c->vc, &head);
 505
 506        return 0;
 507}
 508
 509static int omap_dma_pause(struct omap_chan *c)
 510{
 511        /* Pause/Resume only allowed with cyclic mode */
 512        if (!c->cyclic)
 513                return -EINVAL;
 514
 515        if (!c->paused) {
 516                omap_stop_dma(c->dma_ch);
 517                c->paused = true;
 518        }
 519
 520        return 0;
 521}
 522
 523static int omap_dma_resume(struct omap_chan *c)
 524{
 525        /* Pause/Resume only allowed with cyclic mode */
 526        if (!c->cyclic)
 527                return -EINVAL;
 528
 529        if (c->paused) {
 530                omap_start_dma(c->dma_ch);
 531                c->paused = false;
 532        }
 533
 534        return 0;
 535}
 536
 537static int omap_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 538        unsigned long arg)
 539{
 540        struct omap_chan *c = to_omap_dma_chan(chan);
 541        int ret;
 542
 543        switch (cmd) {
 544        case DMA_SLAVE_CONFIG:
 545                ret = omap_dma_slave_config(c, (struct dma_slave_config *)arg);
 546                break;
 547
 548        case DMA_TERMINATE_ALL:
 549                ret = omap_dma_terminate_all(c);
 550                break;
 551
 552        case DMA_PAUSE:
 553                ret = omap_dma_pause(c);
 554                break;
 555
 556        case DMA_RESUME:
 557                ret = omap_dma_resume(c);
 558                break;
 559
 560        default:
 561                ret = -ENXIO;
 562                break;
 563        }
 564
 565        return ret;
 566}
 567
 568static int omap_dma_chan_init(struct omap_dmadev *od, int dma_sig)
 569{
 570        struct omap_chan *c;
 571
 572        c = kzalloc(sizeof(*c), GFP_KERNEL);
 573        if (!c)
 574                return -ENOMEM;
 575
 576        c->dma_sig = dma_sig;
 577        c->vc.desc_free = omap_dma_desc_free;
 578        vchan_init(&c->vc, &od->ddev);
 579        INIT_LIST_HEAD(&c->node);
 580
 581        od->ddev.chancnt++;
 582
 583        return 0;
 584}
 585
 586static void omap_dma_free(struct omap_dmadev *od)
 587{
 588        tasklet_kill(&od->task);
 589        while (!list_empty(&od->ddev.channels)) {
 590                struct omap_chan *c = list_first_entry(&od->ddev.channels,
 591                        struct omap_chan, vc.chan.device_node);
 592
 593                list_del(&c->vc.chan.device_node);
 594                tasklet_kill(&c->vc.task);
 595                kfree(c);
 596        }
 597        kfree(od);
 598}
 599
 600static int omap_dma_probe(struct platform_device *pdev)
 601{
 602        struct omap_dmadev *od;
 603        int rc, i;
 604
 605        od = kzalloc(sizeof(*od), GFP_KERNEL);
 606        if (!od)
 607                return -ENOMEM;
 608
 609        dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
 610        dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
 611        od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources;
 612        od->ddev.device_free_chan_resources = omap_dma_free_chan_resources;
 613        od->ddev.device_tx_status = omap_dma_tx_status;
 614        od->ddev.device_issue_pending = omap_dma_issue_pending;
 615        od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg;
 616        od->ddev.device_prep_dma_cyclic = omap_dma_prep_dma_cyclic;
 617        od->ddev.device_control = omap_dma_control;
 618        od->ddev.dev = &pdev->dev;
 619        INIT_LIST_HEAD(&od->ddev.channels);
 620        INIT_LIST_HEAD(&od->pending);
 621        spin_lock_init(&od->lock);
 622
 623        tasklet_init(&od->task, omap_dma_sched, (unsigned long)od);
 624
 625        for (i = 0; i < 127; i++) {
 626                rc = omap_dma_chan_init(od, i);
 627                if (rc) {
 628                        omap_dma_free(od);
 629                        return rc;
 630                }
 631        }
 632
 633        rc = dma_async_device_register(&od->ddev);
 634        if (rc) {
 635                pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n",
 636                        rc);
 637                omap_dma_free(od);
 638                return rc;
 639        }
 640
 641        platform_set_drvdata(pdev, od);
 642
 643        if (pdev->dev.of_node) {
 644                omap_dma_info.dma_cap = od->ddev.cap_mask;
 645
 646                /* Device-tree DMA controller registration */
 647                rc = of_dma_controller_register(pdev->dev.of_node,
 648                                of_dma_simple_xlate, &omap_dma_info);
 649                if (rc) {
 650                        pr_warn("OMAP-DMA: failed to register DMA controller\n");
 651                        dma_async_device_unregister(&od->ddev);
 652                        omap_dma_free(od);
 653                }
 654        }
 655
 656        dev_info(&pdev->dev, "OMAP DMA engine driver\n");
 657
 658        return rc;
 659}
 660
 661static int omap_dma_remove(struct platform_device *pdev)
 662{
 663        struct omap_dmadev *od = platform_get_drvdata(pdev);
 664
 665        if (pdev->dev.of_node)
 666                of_dma_controller_free(pdev->dev.of_node);
 667
 668        dma_async_device_unregister(&od->ddev);
 669        omap_dma_free(od);
 670
 671        return 0;
 672}
 673
 674static const struct of_device_id omap_dma_match[] = {
 675        { .compatible = "ti,omap2420-sdma", },
 676        { .compatible = "ti,omap2430-sdma", },
 677        { .compatible = "ti,omap3430-sdma", },
 678        { .compatible = "ti,omap3630-sdma", },
 679        { .compatible = "ti,omap4430-sdma", },
 680        {},
 681};
 682MODULE_DEVICE_TABLE(of, omap_dma_match);
 683
 684static struct platform_driver omap_dma_driver = {
 685        .probe  = omap_dma_probe,
 686        .remove = omap_dma_remove,
 687        .driver = {
 688                .name = "omap-dma-engine",
 689                .owner = THIS_MODULE,
 690                .of_match_table = of_match_ptr(omap_dma_match),
 691        },
 692};
 693
 694bool omap_dma_filter_fn(struct dma_chan *chan, void *param)
 695{
 696        if (chan->device->dev->driver == &omap_dma_driver.driver) {
 697                struct omap_chan *c = to_omap_dma_chan(chan);
 698                unsigned req = *(unsigned *)param;
 699
 700                return req == c->dma_sig;
 701        }
 702        return false;
 703}
 704EXPORT_SYMBOL_GPL(omap_dma_filter_fn);
 705
 706static int omap_dma_init(void)
 707{
 708        return platform_driver_register(&omap_dma_driver);
 709}
 710subsys_initcall(omap_dma_init);
 711
 712static void __exit omap_dma_exit(void)
 713{
 714        platform_driver_unregister(&omap_dma_driver);
 715}
 716module_exit(omap_dma_exit);
 717
 718MODULE_AUTHOR("Russell King");
 719MODULE_LICENSE("GPL");
 720
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