linux/drivers/dma/dw_dmac_regs.h
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   1/*
   2 * Driver for the Synopsys DesignWare AHB DMA Controller
   3 *
   4 * Copyright (C) 2005-2007 Atmel Corporation
   5 * Copyright (C) 2010-2011 ST Microelectronics
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10 */
  11
  12#include <linux/dmaengine.h>
  13#include <linux/dw_dmac.h>
  14
  15#define DW_DMA_MAX_NR_CHANNELS  8
  16#define DW_DMA_MAX_NR_REQUESTS  16
  17
  18/* flow controller */
  19enum dw_dma_fc {
  20        DW_DMA_FC_D_M2M,
  21        DW_DMA_FC_D_M2P,
  22        DW_DMA_FC_D_P2M,
  23        DW_DMA_FC_D_P2P,
  24        DW_DMA_FC_P_P2M,
  25        DW_DMA_FC_SP_P2P,
  26        DW_DMA_FC_P_M2P,
  27        DW_DMA_FC_DP_P2P,
  28};
  29
  30/*
  31 * Redefine this macro to handle differences between 32- and 64-bit
  32 * addressing, big vs. little endian, etc.
  33 */
  34#define DW_REG(name)            u32 name; u32 __pad_##name
  35
  36/* Hardware register definitions. */
  37struct dw_dma_chan_regs {
  38        DW_REG(SAR);            /* Source Address Register */
  39        DW_REG(DAR);            /* Destination Address Register */
  40        DW_REG(LLP);            /* Linked List Pointer */
  41        u32     CTL_LO;         /* Control Register Low */
  42        u32     CTL_HI;         /* Control Register High */
  43        DW_REG(SSTAT);
  44        DW_REG(DSTAT);
  45        DW_REG(SSTATAR);
  46        DW_REG(DSTATAR);
  47        u32     CFG_LO;         /* Configuration Register Low */
  48        u32     CFG_HI;         /* Configuration Register High */
  49        DW_REG(SGR);
  50        DW_REG(DSR);
  51};
  52
  53struct dw_dma_irq_regs {
  54        DW_REG(XFER);
  55        DW_REG(BLOCK);
  56        DW_REG(SRC_TRAN);
  57        DW_REG(DST_TRAN);
  58        DW_REG(ERROR);
  59};
  60
  61struct dw_dma_regs {
  62        /* per-channel registers */
  63        struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS];
  64
  65        /* irq handling */
  66        struct dw_dma_irq_regs  RAW;            /* r */
  67        struct dw_dma_irq_regs  STATUS;         /* r (raw & mask) */
  68        struct dw_dma_irq_regs  MASK;           /* rw (set = irq enabled) */
  69        struct dw_dma_irq_regs  CLEAR;          /* w (ack, affects "raw") */
  70
  71        DW_REG(STATUS_INT);                     /* r */
  72
  73        /* software handshaking */
  74        DW_REG(REQ_SRC);
  75        DW_REG(REQ_DST);
  76        DW_REG(SGL_REQ_SRC);
  77        DW_REG(SGL_REQ_DST);
  78        DW_REG(LAST_SRC);
  79        DW_REG(LAST_DST);
  80
  81        /* miscellaneous */
  82        DW_REG(CFG);
  83        DW_REG(CH_EN);
  84        DW_REG(ID);
  85        DW_REG(TEST);
  86
  87        /* reserved */
  88        DW_REG(__reserved0);
  89        DW_REG(__reserved1);
  90
  91        /* optional encoded params, 0x3c8..0x3f7 */
  92        u32     __reserved;
  93
  94        /* per-channel configuration registers */
  95        u32     DWC_PARAMS[DW_DMA_MAX_NR_CHANNELS];
  96        u32     MULTI_BLK_TYPE;
  97        u32     MAX_BLK_SIZE;
  98
  99        /* top-level parameters */
 100        u32     DW_PARAMS;
 101};
 102
 103#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
 104#define dma_readl_native ioread32be
 105#define dma_writel_native iowrite32be
 106#else
 107#define dma_readl_native readl
 108#define dma_writel_native writel
 109#endif
 110
 111/* To access the registers in early stage of probe */
 112#define dma_read_byaddr(addr, name) \
 113        dma_readl_native((addr) + offsetof(struct dw_dma_regs, name))
 114
 115/* Bitfields in DW_PARAMS */
 116#define DW_PARAMS_NR_CHAN       8               /* number of channels */
 117#define DW_PARAMS_NR_MASTER     11              /* number of AHB masters */
 118#define DW_PARAMS_DATA_WIDTH(n) (15 + 2 * (n))
 119#define DW_PARAMS_DATA_WIDTH1   15              /* master 1 data width */
 120#define DW_PARAMS_DATA_WIDTH2   17              /* master 2 data width */
 121#define DW_PARAMS_DATA_WIDTH3   19              /* master 3 data width */
 122#define DW_PARAMS_DATA_WIDTH4   21              /* master 4 data width */
 123#define DW_PARAMS_EN            28              /* encoded parameters */
 124
 125/* Bitfields in DWC_PARAMS */
 126#define DWC_PARAMS_MBLK_EN      11              /* multi block transfer */
 127
 128/* Bitfields in CTL_LO */
 129#define DWC_CTLL_INT_EN         (1 << 0)        /* irqs enabled? */
 130#define DWC_CTLL_DST_WIDTH(n)   ((n)<<1)        /* bytes per element */
 131#define DWC_CTLL_SRC_WIDTH(n)   ((n)<<4)
 132#define DWC_CTLL_DST_INC        (0<<7)          /* DAR update/not */
 133#define DWC_CTLL_DST_DEC        (1<<7)
 134#define DWC_CTLL_DST_FIX        (2<<7)
 135#define DWC_CTLL_SRC_INC        (0<<7)          /* SAR update/not */
 136#define DWC_CTLL_SRC_DEC        (1<<9)
 137#define DWC_CTLL_SRC_FIX        (2<<9)
 138#define DWC_CTLL_DST_MSIZE(n)   ((n)<<11)       /* burst, #elements */
 139#define DWC_CTLL_SRC_MSIZE(n)   ((n)<<14)
 140#define DWC_CTLL_S_GATH_EN      (1 << 17)       /* src gather, !FIX */
 141#define DWC_CTLL_D_SCAT_EN      (1 << 18)       /* dst scatter, !FIX */
 142#define DWC_CTLL_FC(n)          ((n) << 20)
 143#define DWC_CTLL_FC_M2M         (0 << 20)       /* mem-to-mem */
 144#define DWC_CTLL_FC_M2P         (1 << 20)       /* mem-to-periph */
 145#define DWC_CTLL_FC_P2M         (2 << 20)       /* periph-to-mem */
 146#define DWC_CTLL_FC_P2P         (3 << 20)       /* periph-to-periph */
 147/* plus 4 transfer types for peripheral-as-flow-controller */
 148#define DWC_CTLL_DMS(n)         ((n)<<23)       /* dst master select */
 149#define DWC_CTLL_SMS(n)         ((n)<<25)       /* src master select */
 150#define DWC_CTLL_LLP_D_EN       (1 << 27)       /* dest block chain */
 151#define DWC_CTLL_LLP_S_EN       (1 << 28)       /* src block chain */
 152
 153/* Bitfields in CTL_HI */
 154#define DWC_CTLH_DONE           0x00001000
 155#define DWC_CTLH_BLOCK_TS_MASK  0x00000fff
 156
 157/* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */
 158#define DWC_CFGL_CH_PRIOR_MASK  (0x7 << 5)      /* priority mask */
 159#define DWC_CFGL_CH_PRIOR(x)    ((x) << 5)      /* priority */
 160#define DWC_CFGL_CH_SUSP        (1 << 8)        /* pause xfer */
 161#define DWC_CFGL_FIFO_EMPTY     (1 << 9)        /* pause xfer */
 162#define DWC_CFGL_HS_DST         (1 << 10)       /* handshake w/dst */
 163#define DWC_CFGL_HS_SRC         (1 << 11)       /* handshake w/src */
 164#define DWC_CFGL_MAX_BURST(x)   ((x) << 20)
 165#define DWC_CFGL_RELOAD_SAR     (1 << 30)
 166#define DWC_CFGL_RELOAD_DAR     (1 << 31)
 167
 168/* Bitfields in CFG_HI. Platform-configurable bits are in <linux/dw_dmac.h> */
 169#define DWC_CFGH_DS_UPD_EN      (1 << 5)
 170#define DWC_CFGH_SS_UPD_EN      (1 << 6)
 171
 172/* Bitfields in SGR */
 173#define DWC_SGR_SGI(x)          ((x) << 0)
 174#define DWC_SGR_SGC(x)          ((x) << 20)
 175
 176/* Bitfields in DSR */
 177#define DWC_DSR_DSI(x)          ((x) << 0)
 178#define DWC_DSR_DSC(x)          ((x) << 20)
 179
 180/* Bitfields in CFG */
 181#define DW_CFG_DMA_EN           (1 << 0)
 182
 183enum dw_dmac_flags {
 184        DW_DMA_IS_CYCLIC = 0,
 185        DW_DMA_IS_SOFT_LLP = 1,
 186};
 187
 188struct dw_dma_chan {
 189        struct dma_chan                 chan;
 190        void __iomem                    *ch_regs;
 191        u8                              mask;
 192        u8                              priority;
 193        enum dma_transfer_direction     direction;
 194        bool                            paused;
 195        bool                            initialized;
 196
 197        /* software emulation of the LLP transfers */
 198        struct list_head        *tx_node_active;
 199
 200        spinlock_t              lock;
 201
 202        /* these other elements are all protected by lock */
 203        unsigned long           flags;
 204        struct list_head        active_list;
 205        struct list_head        queue;
 206        struct list_head        free_list;
 207        u32                     residue;
 208        struct dw_cyclic_desc   *cdesc;
 209
 210        unsigned int            descs_allocated;
 211
 212        /* hardware configuration */
 213        unsigned int            block_size;
 214        bool                    nollp;
 215
 216        /* custom slave configuration */
 217        unsigned int            request_line;
 218        unsigned char           src_master;
 219        unsigned char           dst_master;
 220
 221        /* configuration passed via DMA_SLAVE_CONFIG */
 222        struct dma_slave_config dma_sconfig;
 223};
 224
 225static inline struct dw_dma_chan_regs __iomem *
 226__dwc_regs(struct dw_dma_chan *dwc)
 227{
 228        return dwc->ch_regs;
 229}
 230
 231#define channel_readl(dwc, name) \
 232        dma_readl_native(&(__dwc_regs(dwc)->name))
 233#define channel_writel(dwc, name, val) \
 234        dma_writel_native((val), &(__dwc_regs(dwc)->name))
 235
 236static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
 237{
 238        return container_of(chan, struct dw_dma_chan, chan);
 239}
 240
 241struct dw_dma {
 242        struct dma_device       dma;
 243        void __iomem            *regs;
 244        struct dma_pool         *desc_pool;
 245        struct tasklet_struct   tasklet;
 246        struct clk              *clk;
 247
 248        u8                      all_chan_mask;
 249
 250        /* hardware configuration */
 251        unsigned char           nr_masters;
 252        unsigned char           data_width[4];
 253
 254        struct dw_dma_chan      chan[0];
 255};
 256
 257static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
 258{
 259        return dw->regs;
 260}
 261
 262#define dma_readl(dw, name) \
 263        dma_readl_native(&(__dw_regs(dw)->name))
 264#define dma_writel(dw, name, val) \
 265        dma_writel_native((val), &(__dw_regs(dw)->name))
 266
 267#define channel_set_bit(dw, reg, mask) \
 268        dma_writel(dw, reg, ((mask) << 8) | (mask))
 269#define channel_clear_bit(dw, reg, mask) \
 270        dma_writel(dw, reg, ((mask) << 8) | 0)
 271
 272static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
 273{
 274        return container_of(ddev, struct dw_dma, dma);
 275}
 276
 277/* LLI == Linked List Item; a.k.a. DMA block descriptor */
 278struct dw_lli {
 279        /* values that are not changed by hardware */
 280        u32             sar;
 281        u32             dar;
 282        u32             llp;            /* chain to next lli */
 283        u32             ctllo;
 284        /* values that may get written back: */
 285        u32             ctlhi;
 286        /* sstat and dstat can snapshot peripheral register state.
 287         * silicon config may discard either or both...
 288         */
 289        u32             sstat;
 290        u32             dstat;
 291};
 292
 293struct dw_desc {
 294        /* FIRST values the hardware uses */
 295        struct dw_lli                   lli;
 296
 297        /* THEN values for driver housekeeping */
 298        struct list_head                desc_node;
 299        struct list_head                tx_list;
 300        struct dma_async_tx_descriptor  txd;
 301        size_t                          len;
 302        size_t                          total_len;
 303};
 304
 305#define to_dw_desc(h)   list_entry(h, struct dw_desc, desc_node)
 306
 307static inline struct dw_desc *
 308txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
 309{
 310        return container_of(txd, struct dw_desc, txd);
 311}
 312
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