linux/drivers/cpufreq/s5pv210-cpufreq.c
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   1/*
   2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   3 *              http://www.samsung.com
   4 *
   5 * CPU frequency scaling for S5PC110/S5PV210
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10*/
  11
  12#include <linux/types.h>
  13#include <linux/kernel.h>
  14#include <linux/init.h>
  15#include <linux/err.h>
  16#include <linux/clk.h>
  17#include <linux/io.h>
  18#include <linux/cpufreq.h>
  19#include <linux/reboot.h>
  20#include <linux/regulator/consumer.h>
  21#include <linux/suspend.h>
  22
  23#include <mach/map.h>
  24#include <mach/regs-clock.h>
  25
  26static struct clk *cpu_clk;
  27static struct clk *dmc0_clk;
  28static struct clk *dmc1_clk;
  29static struct cpufreq_freqs freqs;
  30static DEFINE_MUTEX(set_freq_lock);
  31
  32/* APLL M,P,S values for 1G/800Mhz */
  33#define APLL_VAL_1000   ((1 << 31) | (125 << 16) | (3 << 8) | 1)
  34#define APLL_VAL_800    ((1 << 31) | (100 << 16) | (3 << 8) | 1)
  35
  36/* Use 800MHz when entering sleep mode */
  37#define SLEEP_FREQ      (800 * 1000)
  38
  39/*
  40 * relation has an additional symantics other than the standard of cpufreq
  41 * DISALBE_FURTHER_CPUFREQ: disable further access to target
  42 * ENABLE_FURTUER_CPUFREQ: enable access to target
  43 */
  44enum cpufreq_access {
  45        DISABLE_FURTHER_CPUFREQ = 0x10,
  46        ENABLE_FURTHER_CPUFREQ = 0x20,
  47};
  48
  49static bool no_cpufreq_access;
  50
  51/*
  52 * DRAM configurations to calculate refresh counter for changing
  53 * frequency of memory.
  54 */
  55struct dram_conf {
  56        unsigned long freq;     /* HZ */
  57        unsigned long refresh;  /* DRAM refresh counter * 1000 */
  58};
  59
  60/* DRAM configuration (DMC0 and DMC1) */
  61static struct dram_conf s5pv210_dram_conf[2];
  62
  63enum perf_level {
  64        L0, L1, L2, L3, L4,
  65};
  66
  67enum s5pv210_mem_type {
  68        LPDDR   = 0x1,
  69        LPDDR2  = 0x2,
  70        DDR2    = 0x4,
  71};
  72
  73enum s5pv210_dmc_port {
  74        DMC0 = 0,
  75        DMC1,
  76};
  77
  78static struct cpufreq_frequency_table s5pv210_freq_table[] = {
  79        {L0, 1000*1000},
  80        {L1, 800*1000},
  81        {L2, 400*1000},
  82        {L3, 200*1000},
  83        {L4, 100*1000},
  84        {0, CPUFREQ_TABLE_END},
  85};
  86
  87static struct regulator *arm_regulator;
  88static struct regulator *int_regulator;
  89
  90struct s5pv210_dvs_conf {
  91        int arm_volt;   /* uV */
  92        int int_volt;   /* uV */
  93};
  94
  95static const int arm_volt_max = 1350000;
  96static const int int_volt_max = 1250000;
  97
  98static struct s5pv210_dvs_conf dvs_conf[] = {
  99        [L0] = {
 100                .arm_volt       = 1250000,
 101                .int_volt       = 1100000,
 102        },
 103        [L1] = {
 104                .arm_volt       = 1200000,
 105                .int_volt       = 1100000,
 106        },
 107        [L2] = {
 108                .arm_volt       = 1050000,
 109                .int_volt       = 1100000,
 110        },
 111        [L3] = {
 112                .arm_volt       = 950000,
 113                .int_volt       = 1100000,
 114        },
 115        [L4] = {
 116                .arm_volt       = 950000,
 117                .int_volt       = 1000000,
 118        },
 119};
 120
 121static u32 clkdiv_val[5][11] = {
 122        /*
 123         * Clock divider value for following
 124         * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
 125         *   HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
 126         *   ONEDRAM, MFC, G3D }
 127         */
 128
 129        /* L0 : [1000/200/100][166/83][133/66][200/200] */
 130        {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
 131
 132        /* L1 : [800/200/100][166/83][133/66][200/200] */
 133        {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
 134
 135        /* L2 : [400/200/100][166/83][133/66][200/200] */
 136        {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
 137
 138        /* L3 : [200/200/100][166/83][133/66][200/200] */
 139        {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
 140
 141        /* L4 : [100/100/100][83/83][66/66][100/100] */
 142        {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
 143};
 144
 145/*
 146 * This function set DRAM refresh counter
 147 * accoriding to operating frequency of DRAM
 148 * ch: DMC port number 0 or 1
 149 * freq: Operating frequency of DRAM(KHz)
 150 */
 151static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
 152{
 153        unsigned long tmp, tmp1;
 154        void __iomem *reg = NULL;
 155
 156        if (ch == DMC0) {
 157                reg = (S5P_VA_DMC0 + 0x30);
 158        } else if (ch == DMC1) {
 159                reg = (S5P_VA_DMC1 + 0x30);
 160        } else {
 161                printk(KERN_ERR "Cannot find DMC port\n");
 162                return;
 163        }
 164
 165        /* Find current DRAM frequency */
 166        tmp = s5pv210_dram_conf[ch].freq;
 167
 168        do_div(tmp, freq);
 169
 170        tmp1 = s5pv210_dram_conf[ch].refresh;
 171
 172        do_div(tmp1, tmp);
 173
 174        __raw_writel(tmp1, reg);
 175}
 176
 177static int s5pv210_verify_speed(struct cpufreq_policy *policy)
 178{
 179        if (policy->cpu)
 180                return -EINVAL;
 181
 182        return cpufreq_frequency_table_verify(policy, s5pv210_freq_table);
 183}
 184
 185static unsigned int s5pv210_getspeed(unsigned int cpu)
 186{
 187        if (cpu)
 188                return 0;
 189
 190        return clk_get_rate(cpu_clk) / 1000;
 191}
 192
 193static int s5pv210_target(struct cpufreq_policy *policy,
 194                          unsigned int target_freq,
 195                          unsigned int relation)
 196{
 197        unsigned long reg;
 198        unsigned int index, priv_index;
 199        unsigned int pll_changing = 0;
 200        unsigned int bus_speed_changing = 0;
 201        int arm_volt, int_volt;
 202        int ret = 0;
 203
 204        mutex_lock(&set_freq_lock);
 205
 206        if (relation & ENABLE_FURTHER_CPUFREQ)
 207                no_cpufreq_access = false;
 208
 209        if (no_cpufreq_access) {
 210#ifdef CONFIG_PM_VERBOSE
 211                pr_err("%s:%d denied access to %s as it is disabled"
 212                                "temporarily\n", __FILE__, __LINE__, __func__);
 213#endif
 214                ret = -EINVAL;
 215                goto exit;
 216        }
 217
 218        if (relation & DISABLE_FURTHER_CPUFREQ)
 219                no_cpufreq_access = true;
 220
 221        relation &= ~(ENABLE_FURTHER_CPUFREQ | DISABLE_FURTHER_CPUFREQ);
 222
 223        freqs.old = s5pv210_getspeed(0);
 224
 225        if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
 226                                           target_freq, relation, &index)) {
 227                ret = -EINVAL;
 228                goto exit;
 229        }
 230
 231        freqs.new = s5pv210_freq_table[index].frequency;
 232
 233        if (freqs.new == freqs.old)
 234                goto exit;
 235
 236        /* Finding current running level index */
 237        if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
 238                                           freqs.old, relation, &priv_index)) {
 239                ret = -EINVAL;
 240                goto exit;
 241        }
 242
 243        arm_volt = dvs_conf[index].arm_volt;
 244        int_volt = dvs_conf[index].int_volt;
 245
 246        if (freqs.new > freqs.old) {
 247                ret = regulator_set_voltage(arm_regulator,
 248                                arm_volt, arm_volt_max);
 249                if (ret)
 250                        goto exit;
 251
 252                ret = regulator_set_voltage(int_regulator,
 253                                int_volt, int_volt_max);
 254                if (ret)
 255                        goto exit;
 256        }
 257
 258        cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
 259
 260        /* Check if there need to change PLL */
 261        if ((index == L0) || (priv_index == L0))
 262                pll_changing = 1;
 263
 264        /* Check if there need to change System bus clock */
 265        if ((index == L4) || (priv_index == L4))
 266                bus_speed_changing = 1;
 267
 268        if (bus_speed_changing) {
 269                /*
 270                 * Reconfigure DRAM refresh counter value for minimum
 271                 * temporary clock while changing divider.
 272                 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
 273                 */
 274                if (pll_changing)
 275                        s5pv210_set_refresh(DMC1, 83000);
 276                else
 277                        s5pv210_set_refresh(DMC1, 100000);
 278
 279                s5pv210_set_refresh(DMC0, 83000);
 280        }
 281
 282        /*
 283         * APLL should be changed in this level
 284         * APLL -> MPLL(for stable transition) -> APLL
 285         * Some clock source's clock API are not prepared.
 286         * Do not use clock API in below code.
 287         */
 288        if (pll_changing) {
 289                /*
 290                 * 1. Temporary Change divider for MFC and G3D
 291                 * SCLKA2M(200/1=200)->(200/4=50)Mhz
 292                 */
 293                reg = __raw_readl(S5P_CLK_DIV2);
 294                reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
 295                reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
 296                        (3 << S5P_CLKDIV2_MFC_SHIFT);
 297                __raw_writel(reg, S5P_CLK_DIV2);
 298
 299                /* For MFC, G3D dividing */
 300                do {
 301                        reg = __raw_readl(S5P_CLKDIV_STAT0);
 302                } while (reg & ((1 << 16) | (1 << 17)));
 303
 304                /*
 305                 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
 306                 * (200/4=50)->(667/4=166)Mhz
 307                 */
 308                reg = __raw_readl(S5P_CLK_SRC2);
 309                reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
 310                reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
 311                        (1 << S5P_CLKSRC2_MFC_SHIFT);
 312                __raw_writel(reg, S5P_CLK_SRC2);
 313
 314                do {
 315                        reg = __raw_readl(S5P_CLKMUX_STAT1);
 316                } while (reg & ((1 << 7) | (1 << 3)));
 317
 318                /*
 319                 * 3. DMC1 refresh count for 133Mhz if (index == L4) is
 320                 * true refresh counter is already programed in upper
 321                 * code. 0x287@83Mhz
 322                 */
 323                if (!bus_speed_changing)
 324                        s5pv210_set_refresh(DMC1, 133000);
 325
 326                /* 4. SCLKAPLL -> SCLKMPLL */
 327                reg = __raw_readl(S5P_CLK_SRC0);
 328                reg &= ~(S5P_CLKSRC0_MUX200_MASK);
 329                reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
 330                __raw_writel(reg, S5P_CLK_SRC0);
 331
 332                do {
 333                        reg = __raw_readl(S5P_CLKMUX_STAT0);
 334                } while (reg & (0x1 << 18));
 335
 336        }
 337
 338        /* Change divider */
 339        reg = __raw_readl(S5P_CLK_DIV0);
 340
 341        reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
 342                S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
 343                S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK |
 344                S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK);
 345
 346        reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
 347                (clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) |
 348                (clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) |
 349                (clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) |
 350                (clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) |
 351                (clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) |
 352                (clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
 353                (clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
 354
 355        __raw_writel(reg, S5P_CLK_DIV0);
 356
 357        do {
 358                reg = __raw_readl(S5P_CLKDIV_STAT0);
 359        } while (reg & 0xff);
 360
 361        /* ARM MCS value changed */
 362        reg = __raw_readl(S5P_ARM_MCS_CON);
 363        reg &= ~0x3;
 364        if (index >= L3)
 365                reg |= 0x3;
 366        else
 367                reg |= 0x1;
 368
 369        __raw_writel(reg, S5P_ARM_MCS_CON);
 370
 371        if (pll_changing) {
 372                /* 5. Set Lock time = 30us*24Mhz = 0x2cf */
 373                __raw_writel(0x2cf, S5P_APLL_LOCK);
 374
 375                /*
 376                 * 6. Turn on APLL
 377                 * 6-1. Set PMS values
 378                 * 6-2. Wait untile the PLL is locked
 379                 */
 380                if (index == L0)
 381                        __raw_writel(APLL_VAL_1000, S5P_APLL_CON);
 382                else
 383                        __raw_writel(APLL_VAL_800, S5P_APLL_CON);
 384
 385                do {
 386                        reg = __raw_readl(S5P_APLL_CON);
 387                } while (!(reg & (0x1 << 29)));
 388
 389                /*
 390                 * 7. Change souce clock from SCLKMPLL(667Mhz)
 391                 * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
 392                 * (667/4=166)->(200/4=50)Mhz
 393                 */
 394                reg = __raw_readl(S5P_CLK_SRC2);
 395                reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
 396                reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
 397                        (0 << S5P_CLKSRC2_MFC_SHIFT);
 398                __raw_writel(reg, S5P_CLK_SRC2);
 399
 400                do {
 401                        reg = __raw_readl(S5P_CLKMUX_STAT1);
 402                } while (reg & ((1 << 7) | (1 << 3)));
 403
 404                /*
 405                 * 8. Change divider for MFC and G3D
 406                 * (200/4=50)->(200/1=200)Mhz
 407                 */
 408                reg = __raw_readl(S5P_CLK_DIV2);
 409                reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
 410                reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
 411                        (clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
 412                __raw_writel(reg, S5P_CLK_DIV2);
 413
 414                /* For MFC, G3D dividing */
 415                do {
 416                        reg = __raw_readl(S5P_CLKDIV_STAT0);
 417                } while (reg & ((1 << 16) | (1 << 17)));
 418
 419                /* 9. Change MPLL to APLL in MSYS_MUX */
 420                reg = __raw_readl(S5P_CLK_SRC0);
 421                reg &= ~(S5P_CLKSRC0_MUX200_MASK);
 422                reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
 423                __raw_writel(reg, S5P_CLK_SRC0);
 424
 425                do {
 426                        reg = __raw_readl(S5P_CLKMUX_STAT0);
 427                } while (reg & (0x1 << 18));
 428
 429                /*
 430                 * 10. DMC1 refresh counter
 431                 * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
 432                 * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
 433                 */
 434                if (!bus_speed_changing)
 435                        s5pv210_set_refresh(DMC1, 200000);
 436        }
 437
 438        /*
 439         * L4 level need to change memory bus speed, hence onedram clock divier
 440         * and memory refresh parameter should be changed
 441         */
 442        if (bus_speed_changing) {
 443                reg = __raw_readl(S5P_CLK_DIV6);
 444                reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
 445                reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
 446                __raw_writel(reg, S5P_CLK_DIV6);
 447
 448                do {
 449                        reg = __raw_readl(S5P_CLKDIV_STAT1);
 450                } while (reg & (1 << 15));
 451
 452                /* Reconfigure DRAM refresh counter value */
 453                if (index != L4) {
 454                        /*
 455                         * DMC0 : 166Mhz
 456                         * DMC1 : 200Mhz
 457                         */
 458                        s5pv210_set_refresh(DMC0, 166000);
 459                        s5pv210_set_refresh(DMC1, 200000);
 460                } else {
 461                        /*
 462                         * DMC0 : 83Mhz
 463                         * DMC1 : 100Mhz
 464                         */
 465                        s5pv210_set_refresh(DMC0, 83000);
 466                        s5pv210_set_refresh(DMC1, 100000);
 467                }
 468        }
 469
 470        cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
 471
 472        if (freqs.new < freqs.old) {
 473                regulator_set_voltage(int_regulator,
 474                                int_volt, int_volt_max);
 475
 476                regulator_set_voltage(arm_regulator,
 477                                arm_volt, arm_volt_max);
 478        }
 479
 480        printk(KERN_DEBUG "Perf changed[L%d]\n", index);
 481
 482exit:
 483        mutex_unlock(&set_freq_lock);
 484        return ret;
 485}
 486
 487#ifdef CONFIG_PM
 488static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy)
 489{
 490        return 0;
 491}
 492
 493static int s5pv210_cpufreq_resume(struct cpufreq_policy *policy)
 494{
 495        return 0;
 496}
 497#endif
 498
 499static int check_mem_type(void __iomem *dmc_reg)
 500{
 501        unsigned long val;
 502
 503        val = __raw_readl(dmc_reg + 0x4);
 504        val = (val & (0xf << 8));
 505
 506        return val >> 8;
 507}
 508
 509static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
 510{
 511        unsigned long mem_type;
 512        int ret;
 513
 514        cpu_clk = clk_get(NULL, "armclk");
 515        if (IS_ERR(cpu_clk))
 516                return PTR_ERR(cpu_clk);
 517
 518        dmc0_clk = clk_get(NULL, "sclk_dmc0");
 519        if (IS_ERR(dmc0_clk)) {
 520                ret = PTR_ERR(dmc0_clk);
 521                goto out_dmc0;
 522        }
 523
 524        dmc1_clk = clk_get(NULL, "hclk_msys");
 525        if (IS_ERR(dmc1_clk)) {
 526                ret = PTR_ERR(dmc1_clk);
 527                goto out_dmc1;
 528        }
 529
 530        if (policy->cpu != 0) {
 531                ret = -EINVAL;
 532                goto out_dmc1;
 533        }
 534
 535        /*
 536         * check_mem_type : This driver only support LPDDR & LPDDR2.
 537         * other memory type is not supported.
 538         */
 539        mem_type = check_mem_type(S5P_VA_DMC0);
 540
 541        if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
 542                printk(KERN_ERR "CPUFreq doesn't support this memory type\n");
 543                ret = -EINVAL;
 544                goto out_dmc1;
 545        }
 546
 547        /* Find current refresh counter and frequency each DMC */
 548        s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000);
 549        s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
 550
 551        s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000);
 552        s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
 553
 554        policy->cur = policy->min = policy->max = s5pv210_getspeed(0);
 555
 556        cpufreq_frequency_table_get_attr(s5pv210_freq_table, policy->cpu);
 557
 558        policy->cpuinfo.transition_latency = 40000;
 559
 560        return cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table);
 561
 562out_dmc1:
 563        clk_put(dmc0_clk);
 564out_dmc0:
 565        clk_put(cpu_clk);
 566        return ret;
 567}
 568
 569static int s5pv210_cpufreq_notifier_event(struct notifier_block *this,
 570                                          unsigned long event, void *ptr)
 571{
 572        int ret;
 573
 574        switch (event) {
 575        case PM_SUSPEND_PREPARE:
 576                ret = cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ,
 577                                            DISABLE_FURTHER_CPUFREQ);
 578                if (ret < 0)
 579                        return NOTIFY_BAD;
 580
 581                return NOTIFY_OK;
 582        case PM_POST_RESTORE:
 583        case PM_POST_SUSPEND:
 584                cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ,
 585                                      ENABLE_FURTHER_CPUFREQ);
 586
 587                return NOTIFY_OK;
 588        }
 589
 590        return NOTIFY_DONE;
 591}
 592
 593static int s5pv210_cpufreq_reboot_notifier_event(struct notifier_block *this,
 594                                                 unsigned long event, void *ptr)
 595{
 596        int ret;
 597
 598        ret = cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ,
 599                                    DISABLE_FURTHER_CPUFREQ);
 600        if (ret < 0)
 601                return NOTIFY_BAD;
 602
 603        return NOTIFY_DONE;
 604}
 605
 606static struct cpufreq_driver s5pv210_driver = {
 607        .flags          = CPUFREQ_STICKY,
 608        .verify         = s5pv210_verify_speed,
 609        .target         = s5pv210_target,
 610        .get            = s5pv210_getspeed,
 611        .init           = s5pv210_cpu_init,
 612        .name           = "s5pv210",
 613#ifdef CONFIG_PM
 614        .suspend        = s5pv210_cpufreq_suspend,
 615        .resume         = s5pv210_cpufreq_resume,
 616#endif
 617};
 618
 619static struct notifier_block s5pv210_cpufreq_notifier = {
 620        .notifier_call = s5pv210_cpufreq_notifier_event,
 621};
 622
 623static struct notifier_block s5pv210_cpufreq_reboot_notifier = {
 624        .notifier_call = s5pv210_cpufreq_reboot_notifier_event,
 625};
 626
 627static int __init s5pv210_cpufreq_init(void)
 628{
 629        arm_regulator = regulator_get(NULL, "vddarm");
 630        if (IS_ERR(arm_regulator)) {
 631                pr_err("failed to get regulator vddarm");
 632                return PTR_ERR(arm_regulator);
 633        }
 634
 635        int_regulator = regulator_get(NULL, "vddint");
 636        if (IS_ERR(int_regulator)) {
 637                pr_err("failed to get regulator vddint");
 638                regulator_put(arm_regulator);
 639                return PTR_ERR(int_regulator);
 640        }
 641
 642        register_pm_notifier(&s5pv210_cpufreq_notifier);
 643        register_reboot_notifier(&s5pv210_cpufreq_reboot_notifier);
 644
 645        return cpufreq_register_driver(&s5pv210_driver);
 646}
 647
 648late_initcall(s5pv210_cpufreq_init);
 649
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