linux/drivers/cpufreq/exynos4x12-cpufreq.c
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   1/*
   2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
   3 *              http://www.samsung.com
   4 *
   5 * EXYNOS4X12 - CPU frequency scaling support
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10*/
  11
  12#include <linux/module.h>
  13#include <linux/kernel.h>
  14#include <linux/err.h>
  15#include <linux/clk.h>
  16#include <linux/io.h>
  17#include <linux/slab.h>
  18#include <linux/cpufreq.h>
  19
  20#include <mach/regs-clock.h>
  21
  22#include "exynos-cpufreq.h"
  23
  24static struct clk *cpu_clk;
  25static struct clk *moutcore;
  26static struct clk *mout_mpll;
  27static struct clk *mout_apll;
  28
  29static unsigned int exynos4x12_volt_table[] = {
  30        1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
  31        1000000,  987500,  975000,  950000,  925000,  900000,  900000
  32};
  33
  34static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
  35        {L0, CPUFREQ_ENTRY_INVALID},
  36        {L1, 1400 * 1000},
  37        {L2, 1300 * 1000},
  38        {L3, 1200 * 1000},
  39        {L4, 1100 * 1000},
  40        {L5, 1000 * 1000},
  41        {L6,  900 * 1000},
  42        {L7,  800 * 1000},
  43        {L8,  700 * 1000},
  44        {L9,  600 * 1000},
  45        {L10, 500 * 1000},
  46        {L11, 400 * 1000},
  47        {L12, 300 * 1000},
  48        {L13, 200 * 1000},
  49        {0, CPUFREQ_TABLE_END},
  50};
  51
  52static struct apll_freq *apll_freq_4x12;
  53
  54static struct apll_freq apll_freq_4212[] = {
  55        /*
  56         * values:
  57         * freq
  58         * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
  59         * clock divider for COPY, HPM, RESERVED
  60         * PLL M, P, S
  61         */
  62        APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 250, 4, 0),
  63        APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 175, 3, 0),
  64        APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 325, 6, 0),
  65        APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 200, 4, 0),
  66        APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 2, 0, 275, 6, 0),
  67        APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 2, 0, 125, 3, 0),
  68        APLL_FREQ(900,  0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 150, 4, 0),
  69        APLL_FREQ(800,  0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 0),
  70        APLL_FREQ(700,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 175, 3, 1),
  71        APLL_FREQ(600,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 200, 4, 1),
  72        APLL_FREQ(500,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 125, 3, 1),
  73        APLL_FREQ(400,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 1),
  74        APLL_FREQ(300,  0, 2, 4, 0, 2, 1, 1, 0, 3, 2, 0, 200, 4, 2),
  75        APLL_FREQ(200,  0, 1, 3, 0, 1, 1, 1, 0, 3, 2, 0, 100, 3, 2),
  76};
  77
  78static struct apll_freq apll_freq_4412[] = {
  79        /*
  80         * values:
  81         * freq
  82         * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
  83         * clock divider for COPY, HPM, CORES
  84         * PLL M, P, S
  85         */
  86        APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 7, 250, 4, 0),
  87        APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 6, 175, 3, 0),
  88        APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 6, 325, 6, 0),
  89        APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 5, 200, 4, 0),
  90        APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 0, 5, 275, 6, 0),
  91        APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 0, 4, 125, 3, 0),
  92        APLL_FREQ(900,  0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 4, 150, 4, 0),
  93        APLL_FREQ(800,  0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 3, 100, 3, 0),
  94        APLL_FREQ(700,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 3, 175, 3, 1),
  95        APLL_FREQ(600,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 200, 4, 1),
  96        APLL_FREQ(500,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 125, 3, 1),
  97        APLL_FREQ(400,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 1, 100, 3, 1),
  98        APLL_FREQ(300,  0, 2, 4, 0, 2, 1, 1, 0, 3, 0, 1, 200, 4, 2),
  99        APLL_FREQ(200,  0, 1, 3, 0, 1, 1, 1, 0, 3, 0, 0, 100, 3, 2),
 100};
 101
 102static void exynos4x12_set_clkdiv(unsigned int div_index)
 103{
 104        unsigned int tmp;
 105        unsigned int stat_cpu1;
 106
 107        /* Change Divider - CPU0 */
 108
 109        tmp = apll_freq_4x12[div_index].clk_div_cpu0;
 110
 111        __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
 112
 113        while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
 114                cpu_relax();
 115
 116        /* Change Divider - CPU1 */
 117        tmp = apll_freq_4x12[div_index].clk_div_cpu1;
 118
 119        __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
 120        if (soc_is_exynos4212())
 121                stat_cpu1 = 0x11;
 122        else
 123                stat_cpu1 = 0x111;
 124
 125        while (__raw_readl(EXYNOS4_CLKDIV_STATCPU1) & stat_cpu1)
 126                cpu_relax();
 127}
 128
 129static void exynos4x12_set_apll(unsigned int index)
 130{
 131        unsigned int tmp, pdiv;
 132
 133        /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
 134        clk_set_parent(moutcore, mout_mpll);
 135
 136        do {
 137                cpu_relax();
 138                tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
 139                        >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
 140                tmp &= 0x7;
 141        } while (tmp != 0x2);
 142
 143        /* 2. Set APLL Lock time */
 144        pdiv = ((apll_freq_4x12[index].mps >> 8) & 0x3f);
 145
 146        __raw_writel((pdiv * 250), EXYNOS4_APLL_LOCK);
 147
 148        /* 3. Change PLL PMS values */
 149        tmp = __raw_readl(EXYNOS4_APLL_CON0);
 150        tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
 151        tmp |= apll_freq_4x12[index].mps;
 152        __raw_writel(tmp, EXYNOS4_APLL_CON0);
 153
 154        /* 4. wait_lock_time */
 155        do {
 156                cpu_relax();
 157                tmp = __raw_readl(EXYNOS4_APLL_CON0);
 158        } while (!(tmp & (0x1 << EXYNOS4_APLLCON0_LOCKED_SHIFT)));
 159
 160        /* 5. MUX_CORE_SEL = APLL */
 161        clk_set_parent(moutcore, mout_apll);
 162
 163        do {
 164                cpu_relax();
 165                tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
 166                tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
 167        } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
 168}
 169
 170static bool exynos4x12_pms_change(unsigned int old_index, unsigned int new_index)
 171{
 172        unsigned int old_pm = apll_freq_4x12[old_index].mps >> 8;
 173        unsigned int new_pm = apll_freq_4x12[new_index].mps >> 8;
 174
 175        return (old_pm == new_pm) ? 0 : 1;
 176}
 177
 178static void exynos4x12_set_frequency(unsigned int old_index,
 179                                  unsigned int new_index)
 180{
 181        unsigned int tmp;
 182
 183        if (old_index > new_index) {
 184                if (!exynos4x12_pms_change(old_index, new_index)) {
 185                        /* 1. Change the system clock divider values */
 186                        exynos4x12_set_clkdiv(new_index);
 187                        /* 2. Change just s value in apll m,p,s value */
 188                        tmp = __raw_readl(EXYNOS4_APLL_CON0);
 189                        tmp &= ~(0x7 << 0);
 190                        tmp |= apll_freq_4x12[new_index].mps & 0x7;
 191                        __raw_writel(tmp, EXYNOS4_APLL_CON0);
 192
 193                } else {
 194                        /* Clock Configuration Procedure */
 195                        /* 1. Change the system clock divider values */
 196                        exynos4x12_set_clkdiv(new_index);
 197                        /* 2. Change the apll m,p,s value */
 198                        exynos4x12_set_apll(new_index);
 199                }
 200        } else if (old_index < new_index) {
 201                if (!exynos4x12_pms_change(old_index, new_index)) {
 202                        /* 1. Change just s value in apll m,p,s value */
 203                        tmp = __raw_readl(EXYNOS4_APLL_CON0);
 204                        tmp &= ~(0x7 << 0);
 205                        tmp |= apll_freq_4x12[new_index].mps & 0x7;
 206                        __raw_writel(tmp, EXYNOS4_APLL_CON0);
 207                        /* 2. Change the system clock divider values */
 208                        exynos4x12_set_clkdiv(new_index);
 209                } else {
 210                        /* Clock Configuration Procedure */
 211                        /* 1. Change the apll m,p,s value */
 212                        exynos4x12_set_apll(new_index);
 213                        /* 2. Change the system clock divider values */
 214                        exynos4x12_set_clkdiv(new_index);
 215                }
 216        }
 217}
 218
 219int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
 220{
 221        unsigned long rate;
 222
 223        cpu_clk = clk_get(NULL, "armclk");
 224        if (IS_ERR(cpu_clk))
 225                return PTR_ERR(cpu_clk);
 226
 227        moutcore = clk_get(NULL, "moutcore");
 228        if (IS_ERR(moutcore))
 229                goto err_moutcore;
 230
 231        mout_mpll = clk_get(NULL, "mout_mpll");
 232        if (IS_ERR(mout_mpll))
 233                goto err_mout_mpll;
 234
 235        rate = clk_get_rate(mout_mpll) / 1000;
 236
 237        mout_apll = clk_get(NULL, "mout_apll");
 238        if (IS_ERR(mout_apll))
 239                goto err_mout_apll;
 240
 241        if (soc_is_exynos4212())
 242                apll_freq_4x12 = apll_freq_4212;
 243        else
 244                apll_freq_4x12 = apll_freq_4412;
 245
 246        info->mpll_freq_khz = rate;
 247        /* 800Mhz */
 248        info->pll_safe_idx = L7;
 249        info->cpu_clk = cpu_clk;
 250        info->volt_table = exynos4x12_volt_table;
 251        info->freq_table = exynos4x12_freq_table;
 252        info->set_freq = exynos4x12_set_frequency;
 253        info->need_apll_change = exynos4x12_pms_change;
 254
 255        return 0;
 256
 257err_mout_apll:
 258        clk_put(mout_mpll);
 259err_mout_mpll:
 260        clk_put(moutcore);
 261err_moutcore:
 262        clk_put(cpu_clk);
 263
 264        pr_debug("%s: failed initialization\n", __func__);
 265        return -EINVAL;
 266}
 267EXPORT_SYMBOL(exynos4x12_cpufreq_init);
 268
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