linux/drivers/clk/clk-mux.c
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   1/*
   2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   3 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
   4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 *
  10 * Simple multiplexer clock implementation
  11 */
  12
  13#include <linux/clk.h>
  14#include <linux/clk-provider.h>
  15#include <linux/module.h>
  16#include <linux/slab.h>
  17#include <linux/io.h>
  18#include <linux/err.h>
  19
  20/*
  21 * DOC: basic adjustable multiplexer clock that cannot gate
  22 *
  23 * Traits of this clock:
  24 * prepare - clk_prepare only ensures that parents are prepared
  25 * enable - clk_enable only ensures that parents are enabled
  26 * rate - rate is only affected by parent switching.  No clk_set_rate support
  27 * parent - parent is adjustable through clk_set_parent
  28 */
  29
  30#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
  31
  32static u8 clk_mux_get_parent(struct clk_hw *hw)
  33{
  34        struct clk_mux *mux = to_clk_mux(hw);
  35        int num_parents = __clk_get_num_parents(hw->clk);
  36        u32 val;
  37
  38        /*
  39         * FIXME need a mux-specific flag to determine if val is bitwise or numeric
  40         * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
  41         * to 0x7 (index starts at one)
  42         * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
  43         * val = 0x4 really means "bit 2, index starts at bit 0"
  44         */
  45        val = readl(mux->reg) >> mux->shift;
  46        val &= mux->mask;
  47
  48        if (mux->table) {
  49                int i;
  50
  51                for (i = 0; i < num_parents; i++)
  52                        if (mux->table[i] == val)
  53                                return i;
  54                return -EINVAL;
  55        }
  56
  57        if (val && (mux->flags & CLK_MUX_INDEX_BIT))
  58                val = ffs(val) - 1;
  59
  60        if (val && (mux->flags & CLK_MUX_INDEX_ONE))
  61                val--;
  62
  63        if (val >= num_parents)
  64                return -EINVAL;
  65
  66        return val;
  67}
  68
  69static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
  70{
  71        struct clk_mux *mux = to_clk_mux(hw);
  72        u32 val;
  73        unsigned long flags = 0;
  74
  75        if (mux->table)
  76                index = mux->table[index];
  77
  78        else {
  79                if (mux->flags & CLK_MUX_INDEX_BIT)
  80                        index = (1 << ffs(index));
  81
  82                if (mux->flags & CLK_MUX_INDEX_ONE)
  83                        index++;
  84        }
  85
  86        if (mux->lock)
  87                spin_lock_irqsave(mux->lock, flags);
  88
  89        val = readl(mux->reg);
  90        val &= ~(mux->mask << mux->shift);
  91        val |= index << mux->shift;
  92        writel(val, mux->reg);
  93
  94        if (mux->lock)
  95                spin_unlock_irqrestore(mux->lock, flags);
  96
  97        return 0;
  98}
  99
 100const struct clk_ops clk_mux_ops = {
 101        .get_parent = clk_mux_get_parent,
 102        .set_parent = clk_mux_set_parent,
 103};
 104EXPORT_SYMBOL_GPL(clk_mux_ops);
 105
 106struct clk *clk_register_mux_table(struct device *dev, const char *name,
 107                const char **parent_names, u8 num_parents, unsigned long flags,
 108                void __iomem *reg, u8 shift, u32 mask,
 109                u8 clk_mux_flags, u32 *table, spinlock_t *lock)
 110{
 111        struct clk_mux *mux;
 112        struct clk *clk;
 113        struct clk_init_data init;
 114
 115        /* allocate the mux */
 116        mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
 117        if (!mux) {
 118                pr_err("%s: could not allocate mux clk\n", __func__);
 119                return ERR_PTR(-ENOMEM);
 120        }
 121
 122        init.name = name;
 123        init.ops = &clk_mux_ops;
 124        init.flags = flags | CLK_IS_BASIC;
 125        init.parent_names = parent_names;
 126        init.num_parents = num_parents;
 127
 128        /* struct clk_mux assignments */
 129        mux->reg = reg;
 130        mux->shift = shift;
 131        mux->mask = mask;
 132        mux->flags = clk_mux_flags;
 133        mux->lock = lock;
 134        mux->table = table;
 135        mux->hw.init = &init;
 136
 137        clk = clk_register(dev, &mux->hw);
 138
 139        if (IS_ERR(clk))
 140                kfree(mux);
 141
 142        return clk;
 143}
 144
 145struct clk *clk_register_mux(struct device *dev, const char *name,
 146                const char **parent_names, u8 num_parents, unsigned long flags,
 147                void __iomem *reg, u8 shift, u8 width,
 148                u8 clk_mux_flags, spinlock_t *lock)
 149{
 150        u32 mask = BIT(width) - 1;
 151
 152        return clk_register_mux_table(dev, name, parent_names, num_parents,
 153                                      flags, reg, shift, mask, clk_mux_flags,
 154                                      NULL, lock);
 155}
 156
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