linux/drivers/bus/omap_l3_smx.h
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   1/*
   2 * OMAP3XXX L3 Interconnect Driver header
   3 *
   4 * Copyright (C) 2011 Texas Corporation
   5 *      Felipe Balbi <balbi@ti.com>
   6 *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   7 *      sricharan <r.sricharan@ti.com>
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License as published by
  11 * the Free Software Foundation; either version 2 of the License, or
  12 * (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  22 * USA
  23 */
  24#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
  25#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
  26
  27/* Register definitions. All 64-bit wide */
  28#define L3_COMPONENT                    0x000
  29#define L3_CORE                         0x018
  30#define L3_AGENT_CONTROL                0x020
  31#define L3_AGENT_STATUS                 0x028
  32#define L3_ERROR_LOG                    0x058
  33
  34#define L3_ERROR_LOG_MULTI              (1 << 31)
  35#define L3_ERROR_LOG_SECONDARY          (1 << 30)
  36
  37#define L3_ERROR_LOG_ADDR               0x060
  38
  39/* Register definitions for Sideband Interconnect */
  40#define L3_SI_CONTROL                   0x020
  41#define L3_SI_FLAG_STATUS_0             0x510
  42
  43static const u64 shift = 1;
  44
  45#define L3_STATUS_0_MPUIA_BRST          (shift << 0)
  46#define L3_STATUS_0_MPUIA_RSP           (shift << 1)
  47#define L3_STATUS_0_MPUIA_INBAND        (shift << 2)
  48#define L3_STATUS_0_IVAIA_BRST          (shift << 6)
  49#define L3_STATUS_0_IVAIA_RSP           (shift << 7)
  50#define L3_STATUS_0_IVAIA_INBAND        (shift << 8)
  51#define L3_STATUS_0_SGXIA_BRST          (shift << 9)
  52#define L3_STATUS_0_SGXIA_RSP           (shift << 10)
  53#define L3_STATUS_0_SGXIA_MERROR        (shift << 11)
  54#define L3_STATUS_0_CAMIA_BRST          (shift << 12)
  55#define L3_STATUS_0_CAMIA_RSP           (shift << 13)
  56#define L3_STATUS_0_CAMIA_INBAND        (shift << 14)
  57#define L3_STATUS_0_DISPIA_BRST         (shift << 15)
  58#define L3_STATUS_0_DISPIA_RSP          (shift << 16)
  59#define L3_STATUS_0_DMARDIA_BRST        (shift << 18)
  60#define L3_STATUS_0_DMARDIA_RSP         (shift << 19)
  61#define L3_STATUS_0_DMAWRIA_BRST        (shift << 21)
  62#define L3_STATUS_0_DMAWRIA_RSP         (shift << 22)
  63#define L3_STATUS_0_USBOTGIA_BRST       (shift << 24)
  64#define L3_STATUS_0_USBOTGIA_RSP        (shift << 25)
  65#define L3_STATUS_0_USBOTGIA_INBAND     (shift << 26)
  66#define L3_STATUS_0_USBHOSTIA_BRST      (shift << 27)
  67#define L3_STATUS_0_USBHOSTIA_INBAND    (shift << 28)
  68#define L3_STATUS_0_SMSTA_REQ           (shift << 48)
  69#define L3_STATUS_0_GPMCTA_REQ          (shift << 49)
  70#define L3_STATUS_0_OCMRAMTA_REQ        (shift << 50)
  71#define L3_STATUS_0_OCMROMTA_REQ        (shift << 51)
  72#define L3_STATUS_0_IVATA_REQ           (shift << 54)
  73#define L3_STATUS_0_SGXTA_REQ           (shift << 55)
  74#define L3_STATUS_0_SGXTA_SERROR        (shift << 56)
  75#define L3_STATUS_0_GPMCTA_SERROR       (shift << 57)
  76#define L3_STATUS_0_L4CORETA_REQ        (shift << 58)
  77#define L3_STATUS_0_L4PERTA_REQ         (shift << 59)
  78#define L3_STATUS_0_L4EMUTA_REQ         (shift << 60)
  79#define L3_STATUS_0_MAD2DTA_REQ         (shift << 61)
  80
  81#define L3_STATUS_0_TIMEOUT_MASK        (L3_STATUS_0_MPUIA_BRST         \
  82                                        | L3_STATUS_0_MPUIA_RSP         \
  83                                        | L3_STATUS_0_IVAIA_BRST        \
  84                                        | L3_STATUS_0_IVAIA_RSP         \
  85                                        | L3_STATUS_0_SGXIA_BRST        \
  86                                        | L3_STATUS_0_SGXIA_RSP         \
  87                                        | L3_STATUS_0_CAMIA_BRST        \
  88                                        | L3_STATUS_0_CAMIA_RSP         \
  89                                        | L3_STATUS_0_DISPIA_BRST       \
  90                                        | L3_STATUS_0_DISPIA_RSP        \
  91                                        | L3_STATUS_0_DMARDIA_BRST      \
  92                                        | L3_STATUS_0_DMARDIA_RSP       \
  93                                        | L3_STATUS_0_DMAWRIA_BRST      \
  94                                        | L3_STATUS_0_DMAWRIA_RSP       \
  95                                        | L3_STATUS_0_USBOTGIA_BRST     \
  96                                        | L3_STATUS_0_USBOTGIA_RSP      \
  97                                        | L3_STATUS_0_USBHOSTIA_BRST    \
  98                                        | L3_STATUS_0_SMSTA_REQ         \
  99                                        | L3_STATUS_0_GPMCTA_REQ        \
 100                                        | L3_STATUS_0_OCMRAMTA_REQ      \
 101                                        | L3_STATUS_0_OCMROMTA_REQ      \
 102                                        | L3_STATUS_0_IVATA_REQ         \
 103                                        | L3_STATUS_0_SGXTA_REQ         \
 104                                        | L3_STATUS_0_L4CORETA_REQ      \
 105                                        | L3_STATUS_0_L4PERTA_REQ       \
 106                                        | L3_STATUS_0_L4EMUTA_REQ       \
 107                                        | L3_STATUS_0_MAD2DTA_REQ)
 108
 109#define L3_SI_FLAG_STATUS_1             0x530
 110
 111#define L3_STATUS_1_MPU_DATAIA          (1 << 0)
 112#define L3_STATUS_1_DAPIA0              (1 << 3)
 113#define L3_STATUS_1_DAPIA1              (1 << 4)
 114#define L3_STATUS_1_IVAIA               (1 << 6)
 115
 116#define L3_PM_ERROR_LOG                 0x020
 117#define L3_PM_CONTROL                   0x028
 118#define L3_PM_ERROR_CLEAR_SINGLE        0x030
 119#define L3_PM_ERROR_CLEAR_MULTI         0x038
 120#define L3_PM_REQ_INFO_PERMISSION(n)    (0x048 + (0x020 * n))
 121#define L3_PM_READ_PERMISSION(n)        (0x050 + (0x020 * n))
 122#define L3_PM_WRITE_PERMISSION(n)       (0x058 + (0x020 * n))
 123#define L3_PM_ADDR_MATCH(n)             (0x060 + (0x020 * n))
 124
 125/* L3 error log bit fields. Common for IA and TA */
 126#define L3_ERROR_LOG_CODE               24
 127#define L3_ERROR_LOG_INITID             8
 128#define L3_ERROR_LOG_CMD                0
 129
 130/* L3 agent status bit fields. */
 131#define L3_AGENT_STATUS_CLEAR_IA        0x10000000
 132#define L3_AGENT_STATUS_CLEAR_TA        0x01000000
 133
 134#define OMAP34xx_IRQ_L3_APP             10
 135#define L3_APPLICATION_ERROR            0x0
 136#define L3_DEBUG_ERROR                  0x1
 137
 138enum omap3_l3_initiator_id {
 139        /* LCD has 1 ID */
 140        OMAP_L3_LCD = 29,
 141        /* SAD2D has 1 ID */
 142        OMAP_L3_SAD2D = 28,
 143        /* MPU has 5 IDs */
 144        OMAP_L3_IA_MPU_SS_1 = 27,
 145        OMAP_L3_IA_MPU_SS_2 = 26,
 146        OMAP_L3_IA_MPU_SS_3 = 25,
 147        OMAP_L3_IA_MPU_SS_4 = 24,
 148        OMAP_L3_IA_MPU_SS_5 = 23,
 149        /* IVA2.2 SS has 3 IDs*/
 150        OMAP_L3_IA_IVA_SS_1 = 22,
 151        OMAP_L3_IA_IVA_SS_2 = 21,
 152        OMAP_L3_IA_IVA_SS_3 = 20,
 153        /* IVA 2.2 SS DMA has 6 IDS */
 154        OMAP_L3_IA_IVA_SS_DMA_1 = 19,
 155        OMAP_L3_IA_IVA_SS_DMA_2 = 18,
 156        OMAP_L3_IA_IVA_SS_DMA_3 = 17,
 157        OMAP_L3_IA_IVA_SS_DMA_4 = 16,
 158        OMAP_L3_IA_IVA_SS_DMA_5 = 15,
 159        OMAP_L3_IA_IVA_SS_DMA_6 = 14,
 160        /* SGX has 1 ID */
 161        OMAP_L3_IA_SGX = 13,
 162        /* CAM has 3 ID */
 163        OMAP_L3_IA_CAM_1 = 12,
 164        OMAP_L3_IA_CAM_2 = 11,
 165        OMAP_L3_IA_CAM_3 = 10,
 166        /* DAP has 1 ID */
 167        OMAP_L3_IA_DAP = 9,
 168        /* SDMA WR has 2 IDs */
 169        OMAP_L3_SDMA_WR_1 = 8,
 170        OMAP_L3_SDMA_WR_2 = 7,
 171        /* SDMA RD has 4 IDs */
 172        OMAP_L3_SDMA_RD_1 = 6,
 173        OMAP_L3_SDMA_RD_2 = 5,
 174        OMAP_L3_SDMA_RD_3 = 4,
 175        OMAP_L3_SDMA_RD_4 = 3,
 176        /* HSUSB OTG has 1 ID */
 177        OMAP_L3_USBOTG = 2,
 178        /* HSUSB HOST has 1 ID */
 179        OMAP_L3_USBHOST = 1,
 180};
 181
 182enum omap3_l3_code {
 183        OMAP_L3_CODE_NOERROR = 0,
 184        OMAP_L3_CODE_UNSUP_CMD = 1,
 185        OMAP_L3_CODE_ADDR_HOLE = 2,
 186        OMAP_L3_CODE_PROTECT_VIOLATION = 3,
 187        OMAP_L3_CODE_IN_BAND_ERR = 4,
 188        /* codes 5 and 6 are reserved */
 189        OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7,
 190        OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8,
 191        /* codes 9 - 15 are also reserved */
 192};
 193
 194struct omap3_l3 {
 195        struct device *dev;
 196        struct clk *ick;
 197
 198        /* memory base*/
 199        void __iomem *rt;
 200
 201        int debug_irq;
 202        int app_irq;
 203
 204        /* true when and inband functional error occurs */
 205        unsigned inband:1;
 206};
 207
 208/* offsets for l3 agents in order with the Flag status register */
 209static unsigned int omap3_l3_app_bases[] = {
 210        /* MPU IA */
 211        0x1400,
 212        0x1400,
 213        0x1400,
 214        /* RESERVED */
 215        0,
 216        0,
 217        0,
 218        /* IVA 2.2 IA */
 219        0x1800,
 220        0x1800,
 221        0x1800,
 222        /* SGX IA */
 223        0x1c00,
 224        0x1c00,
 225        /* RESERVED */
 226        0,
 227        /* CAMERA IA */
 228        0x5800,
 229        0x5800,
 230        0x5800,
 231        /* DISPLAY IA */
 232        0x5400,
 233        0x5400,
 234        /* RESERVED */
 235        0,
 236        /*SDMA RD IA */
 237        0x4c00,
 238        0x4c00,
 239        /* RESERVED */
 240        0,
 241        /* SDMA WR IA */
 242        0x5000,
 243        0x5000,
 244        /* RESERVED */
 245        0,
 246        /* USB OTG IA */
 247        0x4400,
 248        0x4400,
 249        0x4400,
 250        /* USB HOST IA */
 251        0x4000,
 252        0x4000,
 253        /* RESERVED */
 254        0,
 255        0,
 256        0,
 257        0,
 258        /* SAD2D IA */
 259        0x3000,
 260        0x3000,
 261        0x3000,
 262        /* RESERVED */
 263        0,
 264        0,
 265        0,
 266        0,
 267        0,
 268        0,
 269        0,
 270        0,
 271        0,
 272        0,
 273        0,
 274        0,
 275        /* SMA TA */
 276        0x2000,
 277        /* GPMC TA */
 278        0x2400,
 279        /* OCM RAM TA */
 280        0x2800,
 281        /* OCM ROM TA */
 282        0x2C00,
 283        /* L4 CORE TA */
 284        0x6800,
 285        /* L4 PER TA */
 286        0x6c00,
 287        /* IVA 2.2 TA */
 288        0x6000,
 289        /* SGX TA */
 290        0x6400,
 291        /* L4 EMU TA */
 292        0x7000,
 293        /* GPMC TA */
 294        0x2400,
 295        /* L4 CORE TA */
 296        0x6800,
 297        /* L4 PER TA */
 298        0x6c00,
 299        /* L4 EMU TA */
 300        0x7000,
 301        /* MAD2D TA */
 302        0x3400,
 303        /* RESERVED */
 304        0,
 305        0,
 306};
 307
 308static unsigned int omap3_l3_debug_bases[] = {
 309        /* MPU DATA IA */
 310        0x1400,
 311        /* RESERVED */
 312        0,
 313        0,
 314        /* DAP IA */
 315        0x5c00,
 316        0x5c00,
 317        /* RESERVED */
 318        0,
 319        /* IVA 2.2 IA */
 320        0x1800,
 321        /* REST RESERVED */
 322};
 323
 324static u32 *omap3_l3_bases[] = {
 325        omap3_l3_app_bases,
 326        omap3_l3_debug_bases,
 327};
 328
 329/*
 330 * REVISIT define __raw_readll/__raw_writell here, but move them to
 331 * <asm/io.h> at some point
 332 */
 333#define __raw_writell(v, a)     (__chk_io_ptr(a), \
 334                                *(volatile u64 __force *)(a) = (v))
 335#define __raw_readll(a)         (__chk_io_ptr(a), \
 336                                *(volatile u64 __force *)(a))
 337
 338#endif
 339
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