linux/drivers/ata/sata_rcar.c
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   1/*
   2 * Renesas R-Car SATA driver
   3 *
   4 * Author: Vladimir Barinov <source@cogentembedded.com>
   5 * Copyright (C) 2013 Cogent Embedded, Inc.
   6 * Copyright (C) 2013 Renesas Solutions Corp.
   7 *
   8 * This program is free software; you can redistribute  it and/or modify it
   9 * under  the terms of  the GNU General  Public License as published by the
  10 * Free Software Foundation;  either version 2 of the  License, or (at your
  11 * option) any later version.
  12 */
  13
  14#include <linux/kernel.h>
  15#include <linux/module.h>
  16#include <linux/ata.h>
  17#include <linux/libata.h>
  18#include <linux/platform_device.h>
  19#include <linux/clk.h>
  20#include <linux/err.h>
  21
  22#define DRV_NAME "sata_rcar"
  23
  24/* SH-Navi2G/ATAPI-ATA compatible task registers */
  25#define DATA_REG                        0x100
  26#define SDEVCON_REG                     0x138
  27
  28/* SH-Navi2G/ATAPI module compatible control registers */
  29#define ATAPI_CONTROL1_REG              0x180
  30#define ATAPI_STATUS_REG                0x184
  31#define ATAPI_INT_ENABLE_REG            0x188
  32#define ATAPI_DTB_ADR_REG               0x198
  33#define ATAPI_DMA_START_ADR_REG         0x19C
  34#define ATAPI_DMA_TRANS_CNT_REG         0x1A0
  35#define ATAPI_CONTROL2_REG              0x1A4
  36#define ATAPI_SIG_ST_REG                0x1B0
  37#define ATAPI_BYTE_SWAP_REG             0x1BC
  38
  39/* ATAPI control 1 register (ATAPI_CONTROL1) bits */
  40#define ATAPI_CONTROL1_ISM              BIT(16)
  41#define ATAPI_CONTROL1_DTA32M           BIT(11)
  42#define ATAPI_CONTROL1_RESET            BIT(7)
  43#define ATAPI_CONTROL1_DESE             BIT(3)
  44#define ATAPI_CONTROL1_RW               BIT(2)
  45#define ATAPI_CONTROL1_STOP             BIT(1)
  46#define ATAPI_CONTROL1_START            BIT(0)
  47
  48/* ATAPI status register (ATAPI_STATUS) bits */
  49#define ATAPI_STATUS_SATAINT            BIT(11)
  50#define ATAPI_STATUS_DNEND              BIT(6)
  51#define ATAPI_STATUS_DEVTRM             BIT(5)
  52#define ATAPI_STATUS_DEVINT             BIT(4)
  53#define ATAPI_STATUS_ERR                BIT(2)
  54#define ATAPI_STATUS_NEND               BIT(1)
  55#define ATAPI_STATUS_ACT                BIT(0)
  56
  57/* Interrupt enable register (ATAPI_INT_ENABLE) bits */
  58#define ATAPI_INT_ENABLE_SATAINT        BIT(11)
  59#define ATAPI_INT_ENABLE_DNEND          BIT(6)
  60#define ATAPI_INT_ENABLE_DEVTRM         BIT(5)
  61#define ATAPI_INT_ENABLE_DEVINT         BIT(4)
  62#define ATAPI_INT_ENABLE_ERR            BIT(2)
  63#define ATAPI_INT_ENABLE_NEND           BIT(1)
  64#define ATAPI_INT_ENABLE_ACT            BIT(0)
  65
  66/* Access control registers for physical layer control register */
  67#define SATAPHYADDR_REG                 0x200
  68#define SATAPHYWDATA_REG                0x204
  69#define SATAPHYACCEN_REG                0x208
  70#define SATAPHYRESET_REG                0x20C
  71#define SATAPHYRDATA_REG                0x210
  72#define SATAPHYACK_REG                  0x214
  73
  74/* Physical layer control address command register (SATAPHYADDR) bits */
  75#define SATAPHYADDR_PHYRATEMODE         BIT(10)
  76#define SATAPHYADDR_PHYCMD_READ         BIT(9)
  77#define SATAPHYADDR_PHYCMD_WRITE        BIT(8)
  78
  79/* Physical layer control enable register (SATAPHYACCEN) bits */
  80#define SATAPHYACCEN_PHYLANE            BIT(0)
  81
  82/* Physical layer control reset register (SATAPHYRESET) bits */
  83#define SATAPHYRESET_PHYRST             BIT(1)
  84#define SATAPHYRESET_PHYSRES            BIT(0)
  85
  86/* Physical layer control acknowledge register (SATAPHYACK) bits */
  87#define SATAPHYACK_PHYACK               BIT(0)
  88
  89/* Serial-ATA HOST control registers */
  90#define BISTCONF_REG                    0x102C
  91#define SDATA_REG                       0x1100
  92#define SSDEVCON_REG                    0x1204
  93
  94#define SCRSSTS_REG                     0x1400
  95#define SCRSERR_REG                     0x1404
  96#define SCRSCON_REG                     0x1408
  97#define SCRSACT_REG                     0x140C
  98
  99#define SATAINTSTAT_REG                 0x1508
 100#define SATAINTMASK_REG                 0x150C
 101
 102/* SATA INT status register (SATAINTSTAT) bits */
 103#define SATAINTSTAT_SERR                BIT(3)
 104#define SATAINTSTAT_ATA                 BIT(0)
 105
 106/* SATA INT mask register (SATAINTSTAT) bits */
 107#define SATAINTMASK_SERRMSK             BIT(3)
 108#define SATAINTMASK_ERRMSK              BIT(2)
 109#define SATAINTMASK_ERRCRTMSK           BIT(1)
 110#define SATAINTMASK_ATAMSK              BIT(0)
 111
 112#define SATA_RCAR_INT_MASK              (SATAINTMASK_SERRMSK | \
 113                                         SATAINTMASK_ATAMSK)
 114
 115/* Physical Layer Control Registers */
 116#define SATAPCTLR1_REG                  0x43
 117#define SATAPCTLR2_REG                  0x52
 118#define SATAPCTLR3_REG                  0x5A
 119#define SATAPCTLR4_REG                  0x60
 120
 121/* Descriptor table word 0 bit (when DTA32M = 1) */
 122#define SATA_RCAR_DTEND                 BIT(0)
 123
 124struct sata_rcar_priv {
 125        void __iomem *base;
 126        struct clk *clk;
 127};
 128
 129static void sata_rcar_phy_initialize(struct sata_rcar_priv *priv)
 130{
 131        /* idle state */
 132        iowrite32(0, priv->base + SATAPHYADDR_REG);
 133        /* reset */
 134        iowrite32(SATAPHYRESET_PHYRST, priv->base + SATAPHYRESET_REG);
 135        udelay(10);
 136        /* deassert reset */
 137        iowrite32(0, priv->base + SATAPHYRESET_REG);
 138}
 139
 140static void sata_rcar_phy_write(struct sata_rcar_priv *priv, u16 reg, u32 val,
 141                                int group)
 142{
 143        int timeout;
 144
 145        /* deassert reset */
 146        iowrite32(0, priv->base + SATAPHYRESET_REG);
 147        /* lane 1 */
 148        iowrite32(SATAPHYACCEN_PHYLANE, priv->base + SATAPHYACCEN_REG);
 149        /* write phy register value */
 150        iowrite32(val, priv->base + SATAPHYWDATA_REG);
 151        /* set register group */
 152        if (group)
 153                reg |= SATAPHYADDR_PHYRATEMODE;
 154        /* write command */
 155        iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, priv->base + SATAPHYADDR_REG);
 156        /* wait for ack */
 157        for (timeout = 0; timeout < 100; timeout++) {
 158                val = ioread32(priv->base + SATAPHYACK_REG);
 159                if (val & SATAPHYACK_PHYACK)
 160                        break;
 161        }
 162        if (timeout >= 100)
 163                pr_err("%s timeout\n", __func__);
 164        /* idle state */
 165        iowrite32(0, priv->base + SATAPHYADDR_REG);
 166}
 167
 168static void sata_rcar_freeze(struct ata_port *ap)
 169{
 170        struct sata_rcar_priv *priv = ap->host->private_data;
 171
 172        /* mask */
 173        iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
 174
 175        ata_sff_freeze(ap);
 176}
 177
 178static void sata_rcar_thaw(struct ata_port *ap)
 179{
 180        struct sata_rcar_priv *priv = ap->host->private_data;
 181
 182        /* ack */
 183        iowrite32(~SATA_RCAR_INT_MASK, priv->base + SATAINTSTAT_REG);
 184
 185        ata_sff_thaw(ap);
 186
 187        /* unmask */
 188        iowrite32(0x7ff & ~SATA_RCAR_INT_MASK, priv->base + SATAINTMASK_REG);
 189}
 190
 191static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count)
 192{
 193        u16 *ptr = buffer;
 194
 195        while (count--) {
 196                u16 data = ioread32(reg);
 197
 198                *ptr++ = data;
 199        }
 200}
 201
 202static void sata_rcar_iowrite16_rep(void __iomem *reg, void *buffer, int count)
 203{
 204        const u16 *ptr = buffer;
 205
 206        while (count--)
 207                iowrite32(*ptr++, reg);
 208}
 209
 210static u8 sata_rcar_check_status(struct ata_port *ap)
 211{
 212        return ioread32(ap->ioaddr.status_addr);
 213}
 214
 215static u8 sata_rcar_check_altstatus(struct ata_port *ap)
 216{
 217        return ioread32(ap->ioaddr.altstatus_addr);
 218}
 219
 220static void sata_rcar_set_devctl(struct ata_port *ap, u8 ctl)
 221{
 222        iowrite32(ctl, ap->ioaddr.ctl_addr);
 223}
 224
 225static void sata_rcar_dev_select(struct ata_port *ap, unsigned int device)
 226{
 227        iowrite32(ATA_DEVICE_OBS, ap->ioaddr.device_addr);
 228        ata_sff_pause(ap);      /* needed; also flushes, for mmio */
 229}
 230
 231static unsigned int sata_rcar_ata_devchk(struct ata_port *ap,
 232                                         unsigned int device)
 233{
 234        struct ata_ioports *ioaddr = &ap->ioaddr;
 235        u8 nsect, lbal;
 236
 237        sata_rcar_dev_select(ap, device);
 238
 239        iowrite32(0x55, ioaddr->nsect_addr);
 240        iowrite32(0xaa, ioaddr->lbal_addr);
 241
 242        iowrite32(0xaa, ioaddr->nsect_addr);
 243        iowrite32(0x55, ioaddr->lbal_addr);
 244
 245        iowrite32(0x55, ioaddr->nsect_addr);
 246        iowrite32(0xaa, ioaddr->lbal_addr);
 247
 248        nsect = ioread32(ioaddr->nsect_addr);
 249        lbal  = ioread32(ioaddr->lbal_addr);
 250
 251        if (nsect == 0x55 && lbal == 0xaa)
 252                return 1;       /* found a device */
 253
 254        return 0;               /* nothing found */
 255}
 256
 257static int sata_rcar_wait_after_reset(struct ata_link *link,
 258                                      unsigned long deadline)
 259{
 260        struct ata_port *ap = link->ap;
 261
 262        ata_msleep(ap, ATA_WAIT_AFTER_RESET);
 263
 264        return ata_sff_wait_ready(link, deadline);
 265}
 266
 267static int sata_rcar_bus_softreset(struct ata_port *ap, unsigned long deadline)
 268{
 269        struct ata_ioports *ioaddr = &ap->ioaddr;
 270
 271        DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
 272
 273        /* software reset.  causes dev0 to be selected */
 274        iowrite32(ap->ctl, ioaddr->ctl_addr);
 275        udelay(20);
 276        iowrite32(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
 277        udelay(20);
 278        iowrite32(ap->ctl, ioaddr->ctl_addr);
 279        ap->last_ctl = ap->ctl;
 280
 281        /* wait the port to become ready */
 282        return sata_rcar_wait_after_reset(&ap->link, deadline);
 283}
 284
 285static int sata_rcar_softreset(struct ata_link *link, unsigned int *classes,
 286                               unsigned long deadline)
 287{
 288        struct ata_port *ap = link->ap;
 289        unsigned int devmask = 0;
 290        int rc;
 291        u8 err;
 292
 293        /* determine if device 0 is present */
 294        if (sata_rcar_ata_devchk(ap, 0))
 295                devmask |= 1 << 0;
 296
 297        /* issue bus reset */
 298        DPRINTK("about to softreset, devmask=%x\n", devmask);
 299        rc = sata_rcar_bus_softreset(ap, deadline);
 300        /* if link is occupied, -ENODEV too is an error */
 301        if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
 302                ata_link_err(link, "SRST failed (errno=%d)\n", rc);
 303                return rc;
 304        }
 305
 306        /* determine by signature whether we have ATA or ATAPI devices */
 307        classes[0] = ata_sff_dev_classify(&link->device[0], devmask, &err);
 308
 309        DPRINTK("classes[0]=%u\n", classes[0]);
 310        return 0;
 311}
 312
 313static void sata_rcar_tf_load(struct ata_port *ap,
 314                              const struct ata_taskfile *tf)
 315{
 316        struct ata_ioports *ioaddr = &ap->ioaddr;
 317        unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
 318
 319        if (tf->ctl != ap->last_ctl) {
 320                iowrite32(tf->ctl, ioaddr->ctl_addr);
 321                ap->last_ctl = tf->ctl;
 322                ata_wait_idle(ap);
 323        }
 324
 325        if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
 326                iowrite32(tf->hob_feature, ioaddr->feature_addr);
 327                iowrite32(tf->hob_nsect, ioaddr->nsect_addr);
 328                iowrite32(tf->hob_lbal, ioaddr->lbal_addr);
 329                iowrite32(tf->hob_lbam, ioaddr->lbam_addr);
 330                iowrite32(tf->hob_lbah, ioaddr->lbah_addr);
 331                VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
 332                        tf->hob_feature,
 333                        tf->hob_nsect,
 334                        tf->hob_lbal,
 335                        tf->hob_lbam,
 336                        tf->hob_lbah);
 337        }
 338
 339        if (is_addr) {
 340                iowrite32(tf->feature, ioaddr->feature_addr);
 341                iowrite32(tf->nsect, ioaddr->nsect_addr);
 342                iowrite32(tf->lbal, ioaddr->lbal_addr);
 343                iowrite32(tf->lbam, ioaddr->lbam_addr);
 344                iowrite32(tf->lbah, ioaddr->lbah_addr);
 345                VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
 346                        tf->feature,
 347                        tf->nsect,
 348                        tf->lbal,
 349                        tf->lbam,
 350                        tf->lbah);
 351        }
 352
 353        if (tf->flags & ATA_TFLAG_DEVICE) {
 354                iowrite32(tf->device, ioaddr->device_addr);
 355                VPRINTK("device 0x%X\n", tf->device);
 356        }
 357
 358        ata_wait_idle(ap);
 359}
 360
 361static void sata_rcar_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
 362{
 363        struct ata_ioports *ioaddr = &ap->ioaddr;
 364
 365        tf->command = sata_rcar_check_status(ap);
 366        tf->feature = ioread32(ioaddr->error_addr);
 367        tf->nsect = ioread32(ioaddr->nsect_addr);
 368        tf->lbal = ioread32(ioaddr->lbal_addr);
 369        tf->lbam = ioread32(ioaddr->lbam_addr);
 370        tf->lbah = ioread32(ioaddr->lbah_addr);
 371        tf->device = ioread32(ioaddr->device_addr);
 372
 373        if (tf->flags & ATA_TFLAG_LBA48) {
 374                iowrite32(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
 375                tf->hob_feature = ioread32(ioaddr->error_addr);
 376                tf->hob_nsect = ioread32(ioaddr->nsect_addr);
 377                tf->hob_lbal = ioread32(ioaddr->lbal_addr);
 378                tf->hob_lbam = ioread32(ioaddr->lbam_addr);
 379                tf->hob_lbah = ioread32(ioaddr->lbah_addr);
 380                iowrite32(tf->ctl, ioaddr->ctl_addr);
 381                ap->last_ctl = tf->ctl;
 382        }
 383}
 384
 385static void sata_rcar_exec_command(struct ata_port *ap,
 386                                   const struct ata_taskfile *tf)
 387{
 388        DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
 389
 390        iowrite32(tf->command, ap->ioaddr.command_addr);
 391        ata_sff_pause(ap);
 392}
 393
 394static unsigned int sata_rcar_data_xfer(struct ata_device *dev,
 395                                              unsigned char *buf,
 396                                              unsigned int buflen, int rw)
 397{
 398        struct ata_port *ap = dev->link->ap;
 399        void __iomem *data_addr = ap->ioaddr.data_addr;
 400        unsigned int words = buflen >> 1;
 401
 402        /* Transfer multiple of 2 bytes */
 403        if (rw == READ)
 404                sata_rcar_ioread16_rep(data_addr, buf, words);
 405        else
 406                sata_rcar_iowrite16_rep(data_addr, buf, words);
 407
 408        /* Transfer trailing byte, if any. */
 409        if (unlikely(buflen & 0x01)) {
 410                unsigned char pad[2] = { };
 411
 412                /* Point buf to the tail of buffer */
 413                buf += buflen - 1;
 414
 415                /*
 416                 * Use io*16_rep() accessors here as well to avoid pointlessly
 417                 * swapping bytes to and from on the big endian machines...
 418                 */
 419                if (rw == READ) {
 420                        sata_rcar_ioread16_rep(data_addr, pad, 1);
 421                        *buf = pad[0];
 422                } else {
 423                        pad[0] = *buf;
 424                        sata_rcar_iowrite16_rep(data_addr, pad, 1);
 425                }
 426                words++;
 427        }
 428
 429        return words << 1;
 430}
 431
 432static void sata_rcar_drain_fifo(struct ata_queued_cmd *qc)
 433{
 434        int count;
 435        struct ata_port *ap;
 436
 437        /* We only need to flush incoming data when a command was running */
 438        if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
 439                return;
 440
 441        ap = qc->ap;
 442        /* Drain up to 64K of data before we give up this recovery method */
 443        for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) &&
 444                        count < 65536; count += 2)
 445                ioread32(ap->ioaddr.data_addr);
 446
 447        /* Can become DEBUG later */
 448        if (count)
 449                ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
 450}
 451
 452static int sata_rcar_scr_read(struct ata_link *link, unsigned int sc_reg,
 453                              u32 *val)
 454{
 455        if (sc_reg > SCR_ACTIVE)
 456                return -EINVAL;
 457
 458        *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg << 2));
 459        return 0;
 460}
 461
 462static int sata_rcar_scr_write(struct ata_link *link, unsigned int sc_reg,
 463                               u32 val)
 464{
 465        if (sc_reg > SCR_ACTIVE)
 466                return -EINVAL;
 467
 468        iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg << 2));
 469        return 0;
 470}
 471
 472static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc)
 473{
 474        struct ata_port *ap = qc->ap;
 475        struct ata_bmdma_prd *prd = ap->bmdma_prd;
 476        struct scatterlist *sg;
 477        unsigned int si, pi;
 478
 479        pi = 0;
 480        for_each_sg(qc->sg, sg, qc->n_elem, si) {
 481                u32 addr, sg_len, len;
 482
 483                /*
 484                 * Note: h/w doesn't support 64-bit, so we unconditionally
 485                 * truncate dma_addr_t to u32.
 486                 */
 487                addr = (u32)sg_dma_address(sg);
 488                sg_len = sg_dma_len(sg);
 489
 490                /* H/w transfer count is only 29 bits long, let's be careful */
 491                while (sg_len) {
 492                        len = sg_len;
 493                        if (len > 0x1ffffffe)
 494                                len = 0x1ffffffe;
 495
 496                        prd[pi].addr = cpu_to_le32(addr);
 497                        prd[pi].flags_len = cpu_to_le32(len);
 498                        VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
 499
 500                        pi++;
 501                        sg_len -= len;
 502                        addr += len;
 503                }
 504        }
 505
 506        /* end-of-table flag */
 507        prd[pi - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND);
 508}
 509
 510static void sata_rcar_qc_prep(struct ata_queued_cmd *qc)
 511{
 512        if (!(qc->flags & ATA_QCFLAG_DMAMAP))
 513                return;
 514
 515        sata_rcar_bmdma_fill_sg(qc);
 516}
 517
 518static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc)
 519{
 520        struct ata_port *ap = qc->ap;
 521        unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE;
 522        u32 dmactl;
 523        struct sata_rcar_priv *priv = ap->host->private_data;
 524
 525        /* load PRD table addr. */
 526        mb();   /* make sure PRD table writes are visible to controller */
 527        iowrite32(ap->bmdma_prd_dma, priv->base + ATAPI_DTB_ADR_REG);
 528
 529        /* specify data direction, triple-check start bit is clear */
 530        dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG);
 531        dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP);
 532        if (dmactl & ATAPI_CONTROL1_START) {
 533                dmactl &= ~ATAPI_CONTROL1_START;
 534                dmactl |= ATAPI_CONTROL1_STOP;
 535        }
 536        if (!rw)
 537                dmactl |= ATAPI_CONTROL1_RW;
 538        iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG);
 539
 540        /* issue r/w command */
 541        ap->ops->sff_exec_command(ap, &qc->tf);
 542}
 543
 544static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc)
 545{
 546        struct ata_port *ap = qc->ap;
 547        u32 dmactl;
 548        struct sata_rcar_priv *priv = ap->host->private_data;
 549
 550        /* start host DMA transaction */
 551        dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG);
 552        dmactl &= ~ATAPI_CONTROL1_STOP;
 553        dmactl |= ATAPI_CONTROL1_START;
 554        iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG);
 555}
 556
 557static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc)
 558{
 559        struct ata_port *ap = qc->ap;
 560        struct sata_rcar_priv *priv = ap->host->private_data;
 561        u32 dmactl;
 562
 563        /* force termination of DMA transfer if active */
 564        dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG);
 565        if (dmactl & ATAPI_CONTROL1_START) {
 566                dmactl &= ~ATAPI_CONTROL1_START;
 567                dmactl |= ATAPI_CONTROL1_STOP;
 568                iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG);
 569        }
 570
 571        /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
 572        ata_sff_dma_pause(ap);
 573}
 574
 575static u8 sata_rcar_bmdma_status(struct ata_port *ap)
 576{
 577        struct sata_rcar_priv *priv = ap->host->private_data;
 578        u32 status;
 579        u8 host_stat = 0;
 580
 581        status = ioread32(priv->base + ATAPI_STATUS_REG);
 582        if (status & ATAPI_STATUS_DEVINT)
 583                host_stat |= ATA_DMA_INTR;
 584        if (status & ATAPI_STATUS_ACT)
 585                host_stat |= ATA_DMA_ACTIVE;
 586
 587        return host_stat;
 588}
 589
 590static struct scsi_host_template sata_rcar_sht = {
 591        ATA_BMDMA_SHT(DRV_NAME),
 592};
 593
 594static struct ata_port_operations sata_rcar_port_ops = {
 595        .inherits               = &ata_bmdma_port_ops,
 596
 597        .freeze                 = sata_rcar_freeze,
 598        .thaw                   = sata_rcar_thaw,
 599        .softreset              = sata_rcar_softreset,
 600
 601        .scr_read               = sata_rcar_scr_read,
 602        .scr_write              = sata_rcar_scr_write,
 603
 604        .sff_dev_select         = sata_rcar_dev_select,
 605        .sff_set_devctl         = sata_rcar_set_devctl,
 606        .sff_check_status       = sata_rcar_check_status,
 607        .sff_check_altstatus    = sata_rcar_check_altstatus,
 608        .sff_tf_load            = sata_rcar_tf_load,
 609        .sff_tf_read            = sata_rcar_tf_read,
 610        .sff_exec_command       = sata_rcar_exec_command,
 611        .sff_data_xfer          = sata_rcar_data_xfer,
 612        .sff_drain_fifo         = sata_rcar_drain_fifo,
 613
 614        .qc_prep                = sata_rcar_qc_prep,
 615
 616        .bmdma_setup            = sata_rcar_bmdma_setup,
 617        .bmdma_start            = sata_rcar_bmdma_start,
 618        .bmdma_stop             = sata_rcar_bmdma_stop,
 619        .bmdma_status           = sata_rcar_bmdma_status,
 620};
 621
 622static void sata_rcar_serr_interrupt(struct ata_port *ap)
 623{
 624        struct sata_rcar_priv *priv = ap->host->private_data;
 625        struct ata_eh_info *ehi = &ap->link.eh_info;
 626        int freeze = 0;
 627        u32 serror;
 628
 629        serror = ioread32(priv->base + SCRSERR_REG);
 630        if (!serror)
 631                return;
 632
 633        DPRINTK("SError @host_intr: 0x%x\n", serror);
 634
 635        /* first, analyze and record host port events */
 636        ata_ehi_clear_desc(ehi);
 637
 638        if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
 639                /* Setup a soft-reset EH action */
 640                ata_ehi_hotplugged(ehi);
 641                ata_ehi_push_desc(ehi, "%s", "hotplug");
 642
 643                freeze = serror & SERR_COMM_WAKE ? 0 : 1;
 644        }
 645
 646        /* freeze or abort */
 647        if (freeze)
 648                ata_port_freeze(ap);
 649        else
 650                ata_port_abort(ap);
 651}
 652
 653static void sata_rcar_ata_interrupt(struct ata_port *ap)
 654{
 655        struct ata_queued_cmd *qc;
 656        int handled = 0;
 657
 658        qc = ata_qc_from_tag(ap, ap->link.active_tag);
 659        if (qc)
 660                handled |= ata_bmdma_port_intr(ap, qc);
 661
 662        /* be sure to clear ATA interrupt */
 663        if (!handled)
 664                sata_rcar_check_status(ap);
 665}
 666
 667static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance)
 668{
 669        struct ata_host *host = dev_instance;
 670        struct sata_rcar_priv *priv = host->private_data;
 671        struct ata_port *ap;
 672        unsigned int handled = 0;
 673        u32 sataintstat;
 674        unsigned long flags;
 675
 676        spin_lock_irqsave(&host->lock, flags);
 677
 678        sataintstat = ioread32(priv->base + SATAINTSTAT_REG);
 679        sataintstat &= SATA_RCAR_INT_MASK;
 680        if (!sataintstat)
 681                goto done;
 682        /* ack */
 683        iowrite32(~sataintstat & 0x7ff, priv->base + SATAINTSTAT_REG);
 684
 685        ap = host->ports[0];
 686
 687        if (sataintstat & SATAINTSTAT_ATA)
 688                sata_rcar_ata_interrupt(ap);
 689
 690        if (sataintstat & SATAINTSTAT_SERR)
 691                sata_rcar_serr_interrupt(ap);
 692
 693        handled = 1;
 694done:
 695        spin_unlock_irqrestore(&host->lock, flags);
 696
 697        return IRQ_RETVAL(handled);
 698}
 699
 700static void sata_rcar_setup_port(struct ata_host *host)
 701{
 702        struct ata_port *ap = host->ports[0];
 703        struct ata_ioports *ioaddr = &ap->ioaddr;
 704        struct sata_rcar_priv *priv = host->private_data;
 705
 706        ap->ops         = &sata_rcar_port_ops;
 707        ap->pio_mask    = ATA_PIO4;
 708        ap->udma_mask   = ATA_UDMA6;
 709        ap->flags       |= ATA_FLAG_SATA;
 710
 711        ioaddr->cmd_addr = priv->base + SDATA_REG;
 712        ioaddr->ctl_addr = priv->base + SSDEVCON_REG;
 713        ioaddr->scr_addr = priv->base + SCRSSTS_REG;
 714        ioaddr->altstatus_addr = ioaddr->ctl_addr;
 715
 716        ioaddr->data_addr       = ioaddr->cmd_addr + (ATA_REG_DATA << 2);
 717        ioaddr->error_addr      = ioaddr->cmd_addr + (ATA_REG_ERR << 2);
 718        ioaddr->feature_addr    = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2);
 719        ioaddr->nsect_addr      = ioaddr->cmd_addr + (ATA_REG_NSECT << 2);
 720        ioaddr->lbal_addr       = ioaddr->cmd_addr + (ATA_REG_LBAL << 2);
 721        ioaddr->lbam_addr       = ioaddr->cmd_addr + (ATA_REG_LBAM << 2);
 722        ioaddr->lbah_addr       = ioaddr->cmd_addr + (ATA_REG_LBAH << 2);
 723        ioaddr->device_addr     = ioaddr->cmd_addr + (ATA_REG_DEVICE << 2);
 724        ioaddr->status_addr     = ioaddr->cmd_addr + (ATA_REG_STATUS << 2);
 725        ioaddr->command_addr    = ioaddr->cmd_addr + (ATA_REG_CMD << 2);
 726}
 727
 728static void sata_rcar_init_controller(struct ata_host *host)
 729{
 730        struct sata_rcar_priv *priv = host->private_data;
 731        u32 val;
 732
 733        /* reset and setup phy */
 734        sata_rcar_phy_initialize(priv);
 735        sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0);
 736        sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1);
 737        sata_rcar_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0);
 738        sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0);
 739        sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1);
 740        sata_rcar_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0);
 741
 742        /* SATA-IP reset state */
 743        val = ioread32(priv->base + ATAPI_CONTROL1_REG);
 744        val |= ATAPI_CONTROL1_RESET;
 745        iowrite32(val, priv->base + ATAPI_CONTROL1_REG);
 746
 747        /* ISM mode, PRD mode, DTEND flag at bit 0 */
 748        val = ioread32(priv->base + ATAPI_CONTROL1_REG);
 749        val |= ATAPI_CONTROL1_ISM;
 750        val |= ATAPI_CONTROL1_DESE;
 751        val |= ATAPI_CONTROL1_DTA32M;
 752        iowrite32(val, priv->base + ATAPI_CONTROL1_REG);
 753
 754        /* Release the SATA-IP from the reset state */
 755        val = ioread32(priv->base + ATAPI_CONTROL1_REG);
 756        val &= ~ATAPI_CONTROL1_RESET;
 757        iowrite32(val, priv->base + ATAPI_CONTROL1_REG);
 758
 759        /* ack and mask */
 760        iowrite32(0, priv->base + SATAINTSTAT_REG);
 761        iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
 762        /* enable interrupts */
 763        iowrite32(ATAPI_INT_ENABLE_SATAINT, priv->base + ATAPI_INT_ENABLE_REG);
 764}
 765
 766static int sata_rcar_probe(struct platform_device *pdev)
 767{
 768        struct ata_host *host;
 769        struct sata_rcar_priv *priv;
 770        struct resource *mem;
 771        int irq;
 772        int ret = 0;
 773
 774        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 775        if (mem == NULL)
 776                return -EINVAL;
 777
 778        irq = platform_get_irq(pdev, 0);
 779        if (irq <= 0)
 780                return -EINVAL;
 781
 782        priv = devm_kzalloc(&pdev->dev, sizeof(struct sata_rcar_priv),
 783                           GFP_KERNEL);
 784        if (!priv)
 785                return -ENOMEM;
 786
 787        priv->clk = devm_clk_get(&pdev->dev, NULL);
 788        if (IS_ERR(priv->clk)) {
 789                dev_err(&pdev->dev, "failed to get access to sata clock\n");
 790                return PTR_ERR(priv->clk);
 791        }
 792        clk_enable(priv->clk);
 793
 794        host = ata_host_alloc(&pdev->dev, 1);
 795        if (!host) {
 796                dev_err(&pdev->dev, "ata_host_alloc failed\n");
 797                ret = -ENOMEM;
 798                goto cleanup;
 799        }
 800
 801        host->private_data = priv;
 802
 803        priv->base = devm_ioremap_resource(&pdev->dev, mem);
 804        if (IS_ERR(priv->base)) {
 805                ret = PTR_ERR(priv->base);
 806                goto cleanup;
 807        }
 808
 809        /* setup port */
 810        sata_rcar_setup_port(host);
 811
 812        /* initialize host controller */
 813        sata_rcar_init_controller(host);
 814
 815        ret = ata_host_activate(host, irq, sata_rcar_interrupt, 0,
 816                                &sata_rcar_sht);
 817        if (!ret)
 818                return 0;
 819
 820cleanup:
 821        clk_disable(priv->clk);
 822
 823        return ret;
 824}
 825
 826static int sata_rcar_remove(struct platform_device *pdev)
 827{
 828        struct ata_host *host = dev_get_drvdata(&pdev->dev);
 829        struct sata_rcar_priv *priv = host->private_data;
 830
 831        ata_host_detach(host);
 832
 833        /* disable interrupts */
 834        iowrite32(0, priv->base + ATAPI_INT_ENABLE_REG);
 835        /* ack and mask */
 836        iowrite32(0, priv->base + SATAINTSTAT_REG);
 837        iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
 838
 839        clk_disable(priv->clk);
 840
 841        return 0;
 842}
 843
 844#ifdef CONFIG_PM
 845static int sata_rcar_suspend(struct device *dev)
 846{
 847        struct ata_host *host = dev_get_drvdata(dev);
 848        struct sata_rcar_priv *priv = host->private_data;
 849        int ret;
 850
 851        ret = ata_host_suspend(host, PMSG_SUSPEND);
 852        if (!ret) {
 853                /* disable interrupts */
 854                iowrite32(0, priv->base + ATAPI_INT_ENABLE_REG);
 855                /* mask */
 856                iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
 857
 858                clk_disable(priv->clk);
 859        }
 860
 861        return ret;
 862}
 863
 864static int sata_rcar_resume(struct device *dev)
 865{
 866        struct ata_host *host = dev_get_drvdata(dev);
 867        struct sata_rcar_priv *priv = host->private_data;
 868
 869        clk_enable(priv->clk);
 870
 871        /* ack and mask */
 872        iowrite32(0, priv->base + SATAINTSTAT_REG);
 873        iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
 874        /* enable interrupts */
 875        iowrite32(ATAPI_INT_ENABLE_SATAINT, priv->base + ATAPI_INT_ENABLE_REG);
 876
 877        ata_host_resume(host);
 878
 879        return 0;
 880}
 881
 882static const struct dev_pm_ops sata_rcar_pm_ops = {
 883        .suspend        = sata_rcar_suspend,
 884        .resume         = sata_rcar_resume,
 885};
 886#endif
 887
 888static struct of_device_id sata_rcar_match[] = {
 889        { .compatible = "renesas,rcar-sata", },
 890        {},
 891};
 892MODULE_DEVICE_TABLE(of, sata_rcar_match);
 893
 894static struct platform_driver sata_rcar_driver = {
 895        .probe          = sata_rcar_probe,
 896        .remove         = sata_rcar_remove,
 897        .driver = {
 898                .name           = DRV_NAME,
 899                .owner          = THIS_MODULE,
 900                .of_match_table = sata_rcar_match,
 901#ifdef CONFIG_PM
 902                .pm             = &sata_rcar_pm_ops,
 903#endif
 904        },
 905};
 906
 907module_platform_driver(sata_rcar_driver);
 908
 909MODULE_LICENSE("GPL");
 910MODULE_AUTHOR("Vladimir Barinov");
 911MODULE_DESCRIPTION("Renesas R-Car SATA controller low level driver");
 912
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