linux/drivers/ata/sata_inic162x.c
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   1/*
   2 * sata_inic162x.c - Driver for Initio 162x SATA controllers
   3 *
   4 * Copyright 2006  SUSE Linux Products GmbH
   5 * Copyright 2006  Tejun Heo <teheo@novell.com>
   6 *
   7 * This file is released under GPL v2.
   8 *
   9 * This controller is eccentric and easily locks up if something isn't
  10 * right.  Documentation is available at initio's website but it only
  11 * documents registers (not programming model).
  12 *
  13 * This driver has interesting history.  The first version was written
  14 * from the documentation and a 2.4 IDE driver posted on a Taiwan
  15 * company, which didn't use any IDMA features and couldn't handle
  16 * LBA48.  The resulting driver couldn't handle LBA48 devices either
  17 * making it pretty useless.
  18 *
  19 * After a while, initio picked the driver up, renamed it to
  20 * sata_initio162x, updated it to use IDMA for ATA DMA commands and
  21 * posted it on their website.  It only used ATA_PROT_DMA for IDMA and
  22 * attaching both devices and issuing IDMA and !IDMA commands
  23 * simultaneously broke it due to PIRQ masking interaction but it did
  24 * show how to use the IDMA (ADMA + some initio specific twists)
  25 * engine.
  26 *
  27 * Then, I picked up their changes again and here's the usable driver
  28 * which uses IDMA for everything.  Everything works now including
  29 * LBA48, CD/DVD burning, suspend/resume and hotplug.  There are some
  30 * issues tho.  Result Tf is not resported properly, NCQ isn't
  31 * supported yet and CD/DVD writing works with DMA assisted PIO
  32 * protocol (which, for native SATA devices, shouldn't cause any
  33 * noticeable difference).
  34 *
  35 * Anyways, so, here's finally a working driver for inic162x.  Enjoy!
  36 *
  37 * initio: If you guys wanna improve the driver regarding result TF
  38 * access and other stuff, please feel free to contact me.  I'll be
  39 * happy to assist.
  40 */
  41
  42#include <linux/gfp.h>
  43#include <linux/kernel.h>
  44#include <linux/module.h>
  45#include <linux/pci.h>
  46#include <scsi/scsi_host.h>
  47#include <linux/libata.h>
  48#include <linux/blkdev.h>
  49#include <scsi/scsi_device.h>
  50
  51#define DRV_NAME        "sata_inic162x"
  52#define DRV_VERSION     "0.4"
  53
  54enum {
  55        MMIO_BAR_PCI            = 5,
  56        MMIO_BAR_CARDBUS        = 1,
  57
  58        NR_PORTS                = 2,
  59
  60        IDMA_CPB_TBL_SIZE       = 4 * 32,
  61
  62        INIC_DMA_BOUNDARY       = 0xffffff,
  63
  64        HOST_ACTRL              = 0x08,
  65        HOST_CTL                = 0x7c,
  66        HOST_STAT               = 0x7e,
  67        HOST_IRQ_STAT           = 0xbc,
  68        HOST_IRQ_MASK           = 0xbe,
  69
  70        PORT_SIZE               = 0x40,
  71
  72        /* registers for ATA TF operation */
  73        PORT_TF_DATA            = 0x00,
  74        PORT_TF_FEATURE         = 0x01,
  75        PORT_TF_NSECT           = 0x02,
  76        PORT_TF_LBAL            = 0x03,
  77        PORT_TF_LBAM            = 0x04,
  78        PORT_TF_LBAH            = 0x05,
  79        PORT_TF_DEVICE          = 0x06,
  80        PORT_TF_COMMAND         = 0x07,
  81        PORT_TF_ALT_STAT        = 0x08,
  82        PORT_IRQ_STAT           = 0x09,
  83        PORT_IRQ_MASK           = 0x0a,
  84        PORT_PRD_CTL            = 0x0b,
  85        PORT_PRD_ADDR           = 0x0c,
  86        PORT_PRD_XFERLEN        = 0x10,
  87        PORT_CPB_CPBLAR         = 0x18,
  88        PORT_CPB_PTQFIFO        = 0x1c,
  89
  90        /* IDMA register */
  91        PORT_IDMA_CTL           = 0x14,
  92        PORT_IDMA_STAT          = 0x16,
  93
  94        PORT_RPQ_FIFO           = 0x1e,
  95        PORT_RPQ_CNT            = 0x1f,
  96
  97        PORT_SCR                = 0x20,
  98
  99        /* HOST_CTL bits */
 100        HCTL_LEDEN              = (1 << 3),  /* enable LED operation */
 101        HCTL_IRQOFF             = (1 << 8),  /* global IRQ off */
 102        HCTL_FTHD0              = (1 << 10), /* fifo threshold 0 */
 103        HCTL_FTHD1              = (1 << 11), /* fifo threshold 1*/
 104        HCTL_PWRDWN             = (1 << 12), /* power down PHYs */
 105        HCTL_SOFTRST            = (1 << 13), /* global reset (no phy reset) */
 106        HCTL_RPGSEL             = (1 << 15), /* register page select */
 107
 108        HCTL_KNOWN_BITS         = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST |
 109                                  HCTL_RPGSEL,
 110
 111        /* HOST_IRQ_(STAT|MASK) bits */
 112        HIRQ_PORT0              = (1 << 0),
 113        HIRQ_PORT1              = (1 << 1),
 114        HIRQ_SOFT               = (1 << 14),
 115        HIRQ_GLOBAL             = (1 << 15), /* STAT only */
 116
 117        /* PORT_IRQ_(STAT|MASK) bits */
 118        PIRQ_OFFLINE            = (1 << 0),  /* device unplugged */
 119        PIRQ_ONLINE             = (1 << 1),  /* device plugged */
 120        PIRQ_COMPLETE           = (1 << 2),  /* completion interrupt */
 121        PIRQ_FATAL              = (1 << 3),  /* fatal error */
 122        PIRQ_ATA                = (1 << 4),  /* ATA interrupt */
 123        PIRQ_REPLY              = (1 << 5),  /* reply FIFO not empty */
 124        PIRQ_PENDING            = (1 << 7),  /* port IRQ pending (STAT only) */
 125
 126        PIRQ_ERR                = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL,
 127        PIRQ_MASK_DEFAULT       = PIRQ_REPLY | PIRQ_ATA,
 128        PIRQ_MASK_FREEZE        = 0xff,
 129
 130        /* PORT_PRD_CTL bits */
 131        PRD_CTL_START           = (1 << 0),
 132        PRD_CTL_WR              = (1 << 3),
 133        PRD_CTL_DMAEN           = (1 << 7),  /* DMA enable */
 134
 135        /* PORT_IDMA_CTL bits */
 136        IDMA_CTL_RST_ATA        = (1 << 2),  /* hardreset ATA bus */
 137        IDMA_CTL_RST_IDMA       = (1 << 5),  /* reset IDMA machinary */
 138        IDMA_CTL_GO             = (1 << 7),  /* IDMA mode go */
 139        IDMA_CTL_ATA_NIEN       = (1 << 8),  /* ATA IRQ disable */
 140
 141        /* PORT_IDMA_STAT bits */
 142        IDMA_STAT_PERR          = (1 << 0),  /* PCI ERROR MODE */
 143        IDMA_STAT_CPBERR        = (1 << 1),  /* ADMA CPB error */
 144        IDMA_STAT_LGCY          = (1 << 3),  /* ADMA legacy */
 145        IDMA_STAT_UIRQ          = (1 << 4),  /* ADMA unsolicited irq */
 146        IDMA_STAT_STPD          = (1 << 5),  /* ADMA stopped */
 147        IDMA_STAT_PSD           = (1 << 6),  /* ADMA pause */
 148        IDMA_STAT_DONE          = (1 << 7),  /* ADMA done */
 149
 150        IDMA_STAT_ERR           = IDMA_STAT_PERR | IDMA_STAT_CPBERR,
 151
 152        /* CPB Control Flags*/
 153        CPB_CTL_VALID           = (1 << 0),  /* CPB valid */
 154        CPB_CTL_QUEUED          = (1 << 1),  /* queued command */
 155        CPB_CTL_DATA            = (1 << 2),  /* data, rsvd in datasheet */
 156        CPB_CTL_IEN             = (1 << 3),  /* PCI interrupt enable */
 157        CPB_CTL_DEVDIR          = (1 << 4),  /* device direction control */
 158
 159        /* CPB Response Flags */
 160        CPB_RESP_DONE           = (1 << 0),  /* ATA command complete */
 161        CPB_RESP_REL            = (1 << 1),  /* ATA release */
 162        CPB_RESP_IGNORED        = (1 << 2),  /* CPB ignored */
 163        CPB_RESP_ATA_ERR        = (1 << 3),  /* ATA command error */
 164        CPB_RESP_SPURIOUS       = (1 << 4),  /* ATA spurious interrupt error */
 165        CPB_RESP_UNDERFLOW      = (1 << 5),  /* APRD deficiency length error */
 166        CPB_RESP_OVERFLOW       = (1 << 6),  /* APRD exccess length error */
 167        CPB_RESP_CPB_ERR        = (1 << 7),  /* CPB error flag */
 168
 169        /* PRD Control Flags */
 170        PRD_DRAIN               = (1 << 1),  /* ignore data excess */
 171        PRD_CDB                 = (1 << 2),  /* atapi packet command pointer */
 172        PRD_DIRECT_INTR         = (1 << 3),  /* direct interrupt */
 173        PRD_DMA                 = (1 << 4),  /* data transfer method */
 174        PRD_WRITE               = (1 << 5),  /* data dir, rsvd in datasheet */
 175        PRD_IOM                 = (1 << 6),  /* io/memory transfer */
 176        PRD_END                 = (1 << 7),  /* APRD chain end */
 177};
 178
 179/* Comman Parameter Block */
 180struct inic_cpb {
 181        u8              resp_flags;     /* Response Flags */
 182        u8              error;          /* ATA Error */
 183        u8              status;         /* ATA Status */
 184        u8              ctl_flags;      /* Control Flags */
 185        __le32          len;            /* Total Transfer Length */
 186        __le32          prd;            /* First PRD pointer */
 187        u8              rsvd[4];
 188        /* 16 bytes */
 189        u8              feature;        /* ATA Feature */
 190        u8              hob_feature;    /* ATA Ex. Feature */
 191        u8              device;         /* ATA Device/Head */
 192        u8              mirctl;         /* Mirror Control */
 193        u8              nsect;          /* ATA Sector Count */
 194        u8              hob_nsect;      /* ATA Ex. Sector Count */
 195        u8              lbal;           /* ATA Sector Number */
 196        u8              hob_lbal;       /* ATA Ex. Sector Number */
 197        u8              lbam;           /* ATA Cylinder Low */
 198        u8              hob_lbam;       /* ATA Ex. Cylinder Low */
 199        u8              lbah;           /* ATA Cylinder High */
 200        u8              hob_lbah;       /* ATA Ex. Cylinder High */
 201        u8              command;        /* ATA Command */
 202        u8              ctl;            /* ATA Control */
 203        u8              slave_error;    /* Slave ATA Error */
 204        u8              slave_status;   /* Slave ATA Status */
 205        /* 32 bytes */
 206} __packed;
 207
 208/* Physical Region Descriptor */
 209struct inic_prd {
 210        __le32          mad;            /* Physical Memory Address */
 211        __le16          len;            /* Transfer Length */
 212        u8              rsvd;
 213        u8              flags;          /* Control Flags */
 214} __packed;
 215
 216struct inic_pkt {
 217        struct inic_cpb cpb;
 218        struct inic_prd prd[LIBATA_MAX_PRD + 1];        /* + 1 for cdb */
 219        u8              cdb[ATAPI_CDB_LEN];
 220} __packed;
 221
 222struct inic_host_priv {
 223        void __iomem    *mmio_base;
 224        u16             cached_hctl;
 225};
 226
 227struct inic_port_priv {
 228        struct inic_pkt *pkt;
 229        dma_addr_t      pkt_dma;
 230        u32             *cpb_tbl;
 231        dma_addr_t      cpb_tbl_dma;
 232};
 233
 234static struct scsi_host_template inic_sht = {
 235        ATA_BASE_SHT(DRV_NAME),
 236        .sg_tablesize   = LIBATA_MAX_PRD,       /* maybe it can be larger? */
 237        .dma_boundary   = INIC_DMA_BOUNDARY,
 238};
 239
 240static const int scr_map[] = {
 241        [SCR_STATUS]    = 0,
 242        [SCR_ERROR]     = 1,
 243        [SCR_CONTROL]   = 2,
 244};
 245
 246static void __iomem *inic_port_base(struct ata_port *ap)
 247{
 248        struct inic_host_priv *hpriv = ap->host->private_data;
 249
 250        return hpriv->mmio_base + ap->port_no * PORT_SIZE;
 251}
 252
 253static void inic_reset_port(void __iomem *port_base)
 254{
 255        void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
 256
 257        /* stop IDMA engine */
 258        readw(idma_ctl); /* flush */
 259        msleep(1);
 260
 261        /* mask IRQ and assert reset */
 262        writew(IDMA_CTL_RST_IDMA, idma_ctl);
 263        readw(idma_ctl); /* flush */
 264        msleep(1);
 265
 266        /* release reset */
 267        writew(0, idma_ctl);
 268
 269        /* clear irq */
 270        writeb(0xff, port_base + PORT_IRQ_STAT);
 271}
 272
 273static int inic_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val)
 274{
 275        void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR;
 276
 277        if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
 278                return -EINVAL;
 279
 280        *val = readl(scr_addr + scr_map[sc_reg] * 4);
 281
 282        /* this controller has stuck DIAG.N, ignore it */
 283        if (sc_reg == SCR_ERROR)
 284                *val &= ~SERR_PHYRDY_CHG;
 285        return 0;
 286}
 287
 288static int inic_scr_write(struct ata_link *link, unsigned sc_reg, u32 val)
 289{
 290        void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR;
 291
 292        if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
 293                return -EINVAL;
 294
 295        writel(val, scr_addr + scr_map[sc_reg] * 4);
 296        return 0;
 297}
 298
 299static void inic_stop_idma(struct ata_port *ap)
 300{
 301        void __iomem *port_base = inic_port_base(ap);
 302
 303        readb(port_base + PORT_RPQ_FIFO);
 304        readb(port_base + PORT_RPQ_CNT);
 305        writew(0, port_base + PORT_IDMA_CTL);
 306}
 307
 308static void inic_host_err_intr(struct ata_port *ap, u8 irq_stat, u16 idma_stat)
 309{
 310        struct ata_eh_info *ehi = &ap->link.eh_info;
 311        struct inic_port_priv *pp = ap->private_data;
 312        struct inic_cpb *cpb = &pp->pkt->cpb;
 313        bool freeze = false;
 314
 315        ata_ehi_clear_desc(ehi);
 316        ata_ehi_push_desc(ehi, "irq_stat=0x%x idma_stat=0x%x",
 317                          irq_stat, idma_stat);
 318
 319        inic_stop_idma(ap);
 320
 321        if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) {
 322                ata_ehi_push_desc(ehi, "hotplug");
 323                ata_ehi_hotplugged(ehi);
 324                freeze = true;
 325        }
 326
 327        if (idma_stat & IDMA_STAT_PERR) {
 328                ata_ehi_push_desc(ehi, "PCI error");
 329                freeze = true;
 330        }
 331
 332        if (idma_stat & IDMA_STAT_CPBERR) {
 333                ata_ehi_push_desc(ehi, "CPB error");
 334
 335                if (cpb->resp_flags & CPB_RESP_IGNORED) {
 336                        __ata_ehi_push_desc(ehi, " ignored");
 337                        ehi->err_mask |= AC_ERR_INVALID;
 338                        freeze = true;
 339                }
 340
 341                if (cpb->resp_flags & CPB_RESP_ATA_ERR)
 342                        ehi->err_mask |= AC_ERR_DEV;
 343
 344                if (cpb->resp_flags & CPB_RESP_SPURIOUS) {
 345                        __ata_ehi_push_desc(ehi, " spurious-intr");
 346                        ehi->err_mask |= AC_ERR_HSM;
 347                        freeze = true;
 348                }
 349
 350                if (cpb->resp_flags &
 351                    (CPB_RESP_UNDERFLOW | CPB_RESP_OVERFLOW)) {
 352                        __ata_ehi_push_desc(ehi, " data-over/underflow");
 353                        ehi->err_mask |= AC_ERR_HSM;
 354                        freeze = true;
 355                }
 356        }
 357
 358        if (freeze)
 359                ata_port_freeze(ap);
 360        else
 361                ata_port_abort(ap);
 362}
 363
 364static void inic_host_intr(struct ata_port *ap)
 365{
 366        void __iomem *port_base = inic_port_base(ap);
 367        struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
 368        u8 irq_stat;
 369        u16 idma_stat;
 370
 371        /* read and clear IRQ status */
 372        irq_stat = readb(port_base + PORT_IRQ_STAT);
 373        writeb(irq_stat, port_base + PORT_IRQ_STAT);
 374        idma_stat = readw(port_base + PORT_IDMA_STAT);
 375
 376        if (unlikely((irq_stat & PIRQ_ERR) || (idma_stat & IDMA_STAT_ERR)))
 377                inic_host_err_intr(ap, irq_stat, idma_stat);
 378
 379        if (unlikely(!qc))
 380                goto spurious;
 381
 382        if (likely(idma_stat & IDMA_STAT_DONE)) {
 383                inic_stop_idma(ap);
 384
 385                /* Depending on circumstances, device error
 386                 * isn't reported by IDMA, check it explicitly.
 387                 */
 388                if (unlikely(readb(port_base + PORT_TF_COMMAND) &
 389                             (ATA_DF | ATA_ERR)))
 390                        qc->err_mask |= AC_ERR_DEV;
 391
 392                ata_qc_complete(qc);
 393                return;
 394        }
 395
 396 spurious:
 397        ata_port_warn(ap, "unhandled interrupt: cmd=0x%x irq_stat=0x%x idma_stat=0x%x\n",
 398                      qc ? qc->tf.command : 0xff, irq_stat, idma_stat);
 399}
 400
 401static irqreturn_t inic_interrupt(int irq, void *dev_instance)
 402{
 403        struct ata_host *host = dev_instance;
 404        struct inic_host_priv *hpriv = host->private_data;
 405        u16 host_irq_stat;
 406        int i, handled = 0;
 407
 408        host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT);
 409
 410        if (unlikely(!(host_irq_stat & HIRQ_GLOBAL)))
 411                goto out;
 412
 413        spin_lock(&host->lock);
 414
 415        for (i = 0; i < NR_PORTS; i++)
 416                if (host_irq_stat & (HIRQ_PORT0 << i)) {
 417                        inic_host_intr(host->ports[i]);
 418                        handled++;
 419                }
 420
 421        spin_unlock(&host->lock);
 422
 423 out:
 424        return IRQ_RETVAL(handled);
 425}
 426
 427static int inic_check_atapi_dma(struct ata_queued_cmd *qc)
 428{
 429        /* For some reason ATAPI_PROT_DMA doesn't work for some
 430         * commands including writes and other misc ops.  Use PIO
 431         * protocol instead, which BTW is driven by the DMA engine
 432         * anyway, so it shouldn't make much difference for native
 433         * SATA devices.
 434         */
 435        if (atapi_cmd_type(qc->cdb[0]) == READ)
 436                return 0;
 437        return 1;
 438}
 439
 440static void inic_fill_sg(struct inic_prd *prd, struct ata_queued_cmd *qc)
 441{
 442        struct scatterlist *sg;
 443        unsigned int si;
 444        u8 flags = 0;
 445
 446        if (qc->tf.flags & ATA_TFLAG_WRITE)
 447                flags |= PRD_WRITE;
 448
 449        if (ata_is_dma(qc->tf.protocol))
 450                flags |= PRD_DMA;
 451
 452        for_each_sg(qc->sg, sg, qc->n_elem, si) {
 453                prd->mad = cpu_to_le32(sg_dma_address(sg));
 454                prd->len = cpu_to_le16(sg_dma_len(sg));
 455                prd->flags = flags;
 456                prd++;
 457        }
 458
 459        WARN_ON(!si);
 460        prd[-1].flags |= PRD_END;
 461}
 462
 463static void inic_qc_prep(struct ata_queued_cmd *qc)
 464{
 465        struct inic_port_priv *pp = qc->ap->private_data;
 466        struct inic_pkt *pkt = pp->pkt;
 467        struct inic_cpb *cpb = &pkt->cpb;
 468        struct inic_prd *prd = pkt->prd;
 469        bool is_atapi = ata_is_atapi(qc->tf.protocol);
 470        bool is_data = ata_is_data(qc->tf.protocol);
 471        unsigned int cdb_len = 0;
 472
 473        VPRINTK("ENTER\n");
 474
 475        if (is_atapi)
 476                cdb_len = qc->dev->cdb_len;
 477
 478        /* prepare packet, based on initio driver */
 479        memset(pkt, 0, sizeof(struct inic_pkt));
 480
 481        cpb->ctl_flags = CPB_CTL_VALID | CPB_CTL_IEN;
 482        if (is_atapi || is_data)
 483                cpb->ctl_flags |= CPB_CTL_DATA;
 484
 485        cpb->len = cpu_to_le32(qc->nbytes + cdb_len);
 486        cpb->prd = cpu_to_le32(pp->pkt_dma + offsetof(struct inic_pkt, prd));
 487
 488        cpb->device = qc->tf.device;
 489        cpb->feature = qc->tf.feature;
 490        cpb->nsect = qc->tf.nsect;
 491        cpb->lbal = qc->tf.lbal;
 492        cpb->lbam = qc->tf.lbam;
 493        cpb->lbah = qc->tf.lbah;
 494
 495        if (qc->tf.flags & ATA_TFLAG_LBA48) {
 496                cpb->hob_feature = qc->tf.hob_feature;
cpb->ef">flags & lbal;
 44"u/a>->lbah 3914olass="sref">qccpb->ef">flags & ;
 = f">command : 0xff, <4 href49358" class="line" name="L358"> 358 3914olass="sref">qccpb->ef">flags &  3914olass="sref">qccpb->ef">flags & qc->ef="+code=flags" class="sref">flags 5s="sref">5nic_interrupt(int  471        unsigned int 5"+code=de5_instance" class="sref">5ev_in50ef">qc->tf. 398               sata_inic162x.c#L487" id="lass="sref">cpb->ef">flags &  398              lbal;
 477
hpriv = <5 href50>        u8<5s="line" 5ame="L405"> 405     5   477
qc5>    50;qc->lbah
for_each_sg(cpu_to_le32(h5riv-> 358n_elem, si) {
 453<6"> 486        cpb->cpu_to_le32(H5ST_IR51href="+code=ATA_DF" class="srlass="line" name="L358"> 358prd = cpu_to_le32(pp-&5" id="L435" class="line"" class="sref">pkt_dma + host_ire="L358"> 358n_elem, sg));
 454len = cpu_to_le32(sg_dma_len(sg));
sg));
CPB_CAG_WRITE)
;
spin_5ocksg_dma_len(sg));
 460        -><5 href="+code=lock" class5"sref51(sg_dma_len(flags;
i < flags 5ss="sref"5host_irq_stat & 5inic5ntr(<5 href="+code=host" class5"sref51b_len;
 477
;
handled++5
->sg_dma_len(cpu_to_le32( 419flags5=spin_unl5ck" class="sref">spin_un5ockqc-> 486        tf_tba href="+code=cp>tf_tbasref">cpb->cpu_to_le32(lockflags 5"> 422qc-> 424        return 5a hre5="+cod}
<="+code=tf" class="sref">tf<462" claissu>cpb->_to_le32" class="sref">cpu_aa href="drivers/ata/sata_inic162x.c#L463" id="L463" class="line" name="L463"> 463static void ha5dledqc->pkt =  465        struct cpu_to_le32((<5heck_atapi_dma(struc5 ;
;
 477
 4353">qc->CPB_Cc="L4LED"+code=cpb" classc="L4LED"+a hr  388       e=rea="Lcode=cpb" classc=rea="L/sata_inic162x.c#L383" id="L383" class="line"5 id="L4315 class="line" name="L4315> 43153ef">qc-> 388       stat" clas="Lcode=cpb" classstat" clas="L/sata_inic162x.c#L383" id="L383" class="line"5      got5ss="line" name="L432"> 45253ef">qc-> 388       stat"namePTQFIFO>
 422qc->cdb[0]) == qc<5a>->ef="+code=flags" class="sref">flags 5EAD" clas5="sref">READ)
inic5"> 436cpu_aa h"linrs/ata/sata_inic162"linid="L463" class="line>        struct  440static void flagtatic void  4375     5 returlass="sref">qc->prd, struc5 flags5ed_cmdqc->flaghref="+code=device" class="sref">device;
 407
 388               FEATUR)
 442       5struc54ef">qc->flaghref="+code=device" lass="sref">feature;
 407
 388               NSEC =  422 & nsect;
 407
 388               Lne" name="L410"> 4        Lne"/sata_inic162x.c#L383" id="L383" class="line"5eces.;
flaghref="+code=device"  cllass="sref">lbal;
 407
 388               LneM name="L410"> 4        LneM/sata_inic162x.c#L383" id="L383" class="line"5e/a>(fl54 href="+code=nbytes" class="/a> & lbam;
 407
 388               LneH name="L410"> 4        LneH/sata_inic162x.c#L383" id="L383" class="line"5eAD" clas5sref">tf. &  487
 407
 388               DEVIC)
 436 447            5   ));
flaghref="+code=device" ame="L398"> 398               """"e" name="L407"> 407
 388               COMMAic162x.c#L460" id=       COMMAic/sata_inic162x.c#L383" id="L383" class="line"5eclass="l5ode=PRD_WRITE" class="sr5f">PR54+code=irq_stat" class="sref">irq_stat, (qc<55pkt" class="sref">pkt, 0, sizeof(struct 5line" nam5="L450"> 450        5     55> 399}
tf. & cpu_aa href="drivers/ata/sata_inic162x.c#L463" id="L463" class="line" name="L463"> 463static void 55code=irq" class="sref">irq, void *, q5->static void  465 & cpu_to_le32(cpu_to_le325 & cpu_to_le32(cpu_to_5e16        u8<5   42/a>uMA doeerror, result TF acclass=="L477"> 477
         * anyway,"line" name="L42.  I tried#L42API_Pfrom BAR0/2, CPBA doeBAR5dn't make much difference for native5p5d5+;
         * anyway,None="L42s#L4gardllas ofwrites        tf" erface othuseddn't make much difference for native5    lass="comment">         * anyway,ic16now"cdb" cl40uMAindica_DMA/a>
5="L459" c5ass="line" name="L459"> 559        /* For Thothmeans that we" namrc#L4ne" PI_PboguMAa>;
c16"> 4RWn't make much difference for native5=ine" nam5e=prd" class="sref">prd<5a>[-156/a>         * cofailures.  Eeekk....n't make much difference for native5== P56a>         * prame="L477"> 477
qc-> 465        struct  & cpu_to_le32(inic_qc_prep(struc5 qc->qc)
 &  398              ="L495" class="line" name=ERR98"> 398   ame=ERRflagttatic void qc-&5t;flagscpu_to_le32(inic5/a> *cp56prd));
 398               sata_inic162x.c#L/a> &  398              lbal;
 5prd = device;
 489        cpb->featu5(qc<5a>-> 489 rugt;featu5qc<57flags 5sata_inic562x.c#L471" id="L471" cl5ss="l5ne" name="L471"> 471        unsigned int 5a href="+5ode=cdb_len" class="sref5>cdb_57> 461}
cpu_aa h"linrs/ata/sata_inic162"linid="L463" class="line>        struct  473 5     57f="+code=ata_queued_cmd" class="sref">ata_que5a>("ENTE5\n&qu5t;);
5c57" id="L396" class="line" namROT_D id="L435" classROT_D line" 388        ref=MASK_FREEZ)
 388            ref=MASK162x.c#L460" id=    ref=MASK/sata_inic162x.c#L383" id="L383" class="line"5ra> *57prd));
 388            ref=STA =  5478" id="L478" class="li5e" na57+code=irq_stat" class="sref">irq_stat, memset(pkt, 0, sizeof(struct 5a href="+5ode=inic_pkt" class="sre5">ini581 461}
cpu_aa h"linrs/ata/sata_inic162"linid="L463" class="line>        struct ctl_fl5gs = irq, void * 482        if5(cpb->ctl_flags |= ;
 388            ref=STA = qc        ref=MASK_DEFAUL =  388            ref=MASK162x.c#L460" id=    ref=MASK/sata_inic162x.c#L383" id="L383" class="line"5=offsetof5 class="sref">offsetof(str5ct irq_stat,  * =5qc}
tf<462" check_ers/ic162x.c#L409" i462" check_ers/i_to_le32" class="sref">cpu_aa hodekrs/ata/sata_inic162odekid="L463" class="lineodekrs/ata/sata_iniodekid="tatic void  = <5 href="+code=qc" class="5ref">5c-irq" class="sref">irq, void *5= qc->a href="drivers/ata/__iomf="+code=qc" clas__iomf=id="L463" class="line388" id="L388" class="line" name="L388_inic162x.c#L465"lass="lineid="L388" class="lilass="lineid="line"a_len" class="sodekrs/ata/sata_iniodekid=" name="L465"> 465        struct lbal =  471        unsigned int 5f">lbam = qc-&gd="L423" class="line"    ucheck_ers/ic162x.c#L409" i   ucheck_ers/iline"a_len" class="s07
 388               COMMAic162x.c#L460" id=       COMMAic/sataa_inic162x.c#L383" id="L383" class="line"5fass="sre5> = q=irq_stat" class="sref">irq_stat, tf.5a href="+code=lbah" clas5="sre59>        u8<5 class="s5ef">tf. 477
qc5/a>-&59456" lass="comment">        * SRSTA doeSControl har claetido BTW is g-&g477"thiss=="L477"> 477
 44"u/a>-><5 href59;
        * controller.  Only controller specif}
command : 0xff, <5 href59>    lass="comment">        rame="L477"> 477
tf<462" har claetL388" class="lilass=har claet_to_le32" class="sref">cpu_aa hodekrs/ata/sata_inic162odekid="L463" class="lineodekrs/ata/sata_iniodekid=",<="+code=tf" c463" class="line/ata/98"> 398    > 39id=",7"> 477
host_irrrrrrrrrrr="+code=tlonglass="sref">cpu_drs/+code="> 398   drs/+codid="tatic void 6nic_interrupt(int irq, void *6ev_in60/a>->static void  465        struct hpriv = <6 href60;);
tf. 388       stat" clas="Lcode=cpb" classstat" clas="L/sat_inic162x.c#L383" id="L383" class="line"6=6priv" c6af">tf. 489 imame"L388_inic162x.c#L465"383" ehc_deb_/imame=L489"> 489383" ehc_deb_/imameline"ata/sata_inic162x.c#odekrs/ata/sata_iniodekid=" name="L465"> 465qc6>    60;tf 44"u/a>-><6>hand60;
h6riv->s name="L477"> 477
H6ST_IR61->flags6drivers/a6a/sata_inic162x.c#L411" 6d="L461ef">qc->tf.qc->tf. 477
spin_6ock        struct ;
tf.i);
 & 6 489 imame"L38  398   drs/+codid="t_inic162x.c#L383" id="L383" class="line"6l8priv" c6 href="+code=host" class6"sref61b_len;
qc-> 358 = qc->handled++6
->faile=tto claum" odek aftar claeti(errno=%d)/a>
qc-> 419host_irrrrrrrrrrr6" class="line" namrid="L465" class=rc/satt_inic162x.c#L383" id="L383" class="line"6=spin_unl6ck" class="sref">spin_un6ock;
qc-&g=irq_stat" class="sref">irq_stat,  422qc-> 424        return 6a hre62_DATA;
 398    > 39id="8_inic162x.c#L465"ame=DEV_NON)
ha626_len;
 398   83" odek=on+codline"a_len" class="sodekrs/ata/sata_iniodekid=")sclass="sref">qc->static void  & cpu_to_le32((<6heck_atapi_dma(struc6  4odek to bes/ae#L42Ay name="L477"> 477
-> 398   drs/+codid="  4363 class="sref">host_irehref="drivers/ata/sata_iodek occupied, -ENODEV too othef=error name="L477"> 477
qc-> 46263f="+code=is_atapi" cl="+code=tf" class="sref83" odek=waren = qc->host_irehref="driver" name="L472">/a>

qc->host_ireass="line" namrid="L465" class=rc/satt_inic162x.c#L383" id="L383" class="line"6(qc<63 class="sref">flagsREAD)
irq_stat,  436 4376     63358" class="line" name="L358"> 358        struct  & cpu_to_le32( 398    > 39id="8_inic162x.c#L465"u_to/a>_ > 39ific162x.c#L409" i   u/a>_ > 39ifiline"ata/sata_inic162x.c#/a> & cpu_to_le32(prd, struc6 qc->ef="+code=flags" class="sref">flags 6ed_cmd 471        unsigned int 6e     got6e="L442"> 442       6struc64ef">qc-&gd="L423ass="sref">cdb[0]) == q=irq_stat" class="sref">irq_stat,         u8<6e/a>(fl64 href}
cpu_aa h"linrs/ata/sata_inic162"linid="L463" class="line>        struct tf.qc-> 447            6   ;
PR64return 1;
qc<65-> 450        6     65">qc->65code==irq_stat" class="sref">irq_stat, , q6-&irq_stat" class="sref">irq_stat,  422cpu_to_le326cpu_aa href="drivers/ata/sata_inic162x.c#L463" id="L463" class="line" name="L463"> 463static void cpu_to_6e16    lass="sref">qc-> 477
 465static void  436p6d65+code=4f3f">lbah 465        struct irq_stat,  659pkt, 0, sizeof(struct 6=ine" nam6e=prd" class="sref">prd<6a>[-1661 461}
cpu_aa h"linrs/ata/sata_inic162"linid="L463" class="line>        struct P66code=irq" class="sref">irq, void * 422inic_qc_prep(struc6 u8<6f="+code=6c" class="sref">qc-&6t; 477
.c#L466" id="L46" class=0, sizeofle32" class="sref">cpu_to_le32( *cp66prd));
tf_tba)
(qc<6a>-> 477
qc<67">qc->cpb-><>tf_tbasrefid="  388       stat"namenamLAR98"> 398   stat"namenamLAR/sata_inic162x.c#L383" id="L383" classirq_stat, irq_stat,  473 6     67="+co}
tf<462" ne" nclaum"L388" class="li462" ne" nclaum"ta/sae32" class="sref">cpu_aa h"linrs/ata/sata_inic162"linid="L463" class="line>        struct ("ENTE6\n&qu67>    lass="sref">qc->6c67" id="L396" cd="L423ass="sref">cdb[0]) == 67prdirq_stat, memset(->}
tf<462" ne" ncpu_aa h"linrs/ata/sata_inic162"linid="L463" class="line>        struct ini681 461lass="sref">qc->ctl_fl6gs = cpu_ne" name="L487"> 487
 487" cl8_inic162x.c#L465"u href="drivers/ata/satass="line" name="L46hosnrs/ata/sata_inihosn/satass="line" name="L46/a>me="L487"> 487" clss="sref">cdb[0]) ==  482        if6(->static void cdb[0]) == cpb->ctl_flags |= ;
 477
qcm_kzallocme="L487"> 487m_kzallocta/saa_len" class="s/a>me="L487"> 487" cl, sizeofl463" class="line3x.c#L466" id="L466" cl) offsetof(str68; *lbah 4ENOMEM" clss="sref">cdb[0]) == prd = cdb[0]) == 69pkt" class="sref">pkt, 0, sizeof(struct 6nsect6= qc-> href="drivers/ata/sata_iAlloc claources name="L477"> 477
lbal = qc-> 486        .c#L466" id="L46" clas8_inic162x.c#L465"/mam_alloc_cohera/sae="L487"> 487 487" cl, sizeofle32" class="sref">cpu_to_le32(qc->lbam = sref">cpb->.c#L466" id="L46" clas)inic162x.c#L383" id="L383" classtf.6a href="+code=lbah" clas6="sre69c162x.c#L434"a_addresd="L423-63" class="lineENOMEM name="L410"> 4ENOMEM" clss="sref">cdb[0]) == tf.qc6/a>-&69" id="L396" class="line" nam3x.c#L466" id="L466" class="line" name="L46>tf_tba href="+code=cp>tf_tba 487 487" cl, line" name="L46e="L3=PB_TBL_SIZ)
qc-> 44"u/a>-><6 href69+code=4f3f">lbahtf_tbasref">cpb-><>tf_tbasrefid=" command : 0xff, <6 href699tf_tba href="+code=cp>tf_tba 4ENOMEM" clss="sref">cdb[0]) == flags7s="sref">7nic_interrupt(int qc->7ev_in70/a>-&irq_stat" class="sref">irq_stat, cdb[0]) == hpriv = <7 href70;irq_stat, tf.qc7>    70;}
cpu_aa h"lin_opera>}on/sata_inic162x.caa h"lin_opera>}on/"+codstatic void qc-> 44"u/a>-><7>hand70+code=4f3f">l  qc->h7riv->H7ST_IR71-> &if="draheck_ta/pisref">cpb-><>heck_ta/pisref/a>->cpb->qc->-> &if="drqs="r62x.c#L462" id="Lqs="r62->qc->7a/sata_inic162x.c#L411" 7d="L471ef">qc-&gs &if="drqs=iss 489qs=iss 489lass=qs=issqc->qc-&gs &if="drqs=classr/a> &  & qc->spin_7ockctl_flags |= ;
qc->i;

qc-> & 7qc->l  qc->h72x.c#L418" id="L418" cla7s="li71358" class="l  qc->handled++7
pkt, 0, sizeof(struct 7aikely 419-> &if="drscr_ers/L388" class="liscr_ers/->qc->7ck" class="sref">spin_un7ockqc-&gs &if="drscr_ROT_DL388" class="liscr_ROT_D_to_ref="+code=e=es/nic162x.c#L465"lass=scr_ROT_DL388" class="lilass=scr_ROT_D_to_ ass="sref">qc->-&irq_stat" class="sref">irq_stat,  422qc-> 424        return 7a hre72_DATA;
qc->ha726_len}ss="sref">cdb[0]) == inic7"tr(<7heck_atapi_dma(struc7 }
cpu_aa h"lin_infosata_inic162x.caa h"lin_info"+codstatic void qc->qc->-> &if="drpio_maskrs/ata/sata_inipio_mask->qc-> 43731/a>-> &if="drmw+codmaskrs/ata/sata_inimw+codmaskta/sef="+code=e=es/nic162x.c#L465"ame=MWDM32" class="line" ame=MWDM32ta/s ass="sref">qc->7 class="line" name="L4317> 43173ef">qc-&gs &if="dru+codmaskrs/ata/sata_iniu+codmaskta/sef="+code=e=ees/nic162x.c#L465"ame=UDM36" class="line" ame=UDM36ta/s ass="sref">qc-> 47273ef">qc-&gs &if="dr"lin_op/sata_inic162x.c"lineop/qc->cdb[0]) ==         u8<7(qc<73 href}
tf<462t_controllerrs/ata/sata_inilastfcontrollerta/saa href="drivers/ata/__iomf="+code=qc" clas__iomf=id="L463" class="linemmio_id="L388" class="limmio_id="id=" tf.u8<7<#L425" i7="sref">READ)
qc-> 436;
tf<4rs/ata/sata_inil" clss="sref">cdb[0]) ==  4377     73>prd = tf.cdb[0]) == pkt, 0, sizeof(struct 7c id="L437ss="sref">prd, struc7 qc->tf.tf.cdb[0]) == 7 * 471        unsigned int 7e     got7e="L442"> 442       7struc74ef">qc-&g href="drivers/ata/sata_iSoft claetiwhole controller.  Spe
}on oth3me="L477"> 477
qlass="comment">                * PCI"coocks, be generous    tg7eces.    lass="comment">                *ame="L477"> 477
fl74 href="+code=nbytes" class="ROT_Da>
tf. 388       HOSTs="Lcode=cpb" classHOSTs="L/sata_inic162x.c#L383" id="L383" classtf.
 388       HOSTs="Lcode=cpb" classHOSTs="L/sata_l href="drivers/ata/sata_iflush name="L477"> 477
 447            7   PR74>prd =  4ata_inic162x.c#Llrs/ata/sata_inil" cles/05" class="line" nlrs/ata/sata_inil" cle< 105" class="line" nlrs/ata/sata_inil" cl++sclass="sref">qc->qc<75>-> 450        7     75 class="sref">host_iretf.
 388       HOSTs="Lcode=cpb" classHOSTs="L/sata_inic162x.c#L383" id="L383" class="line"7l="sref">7="+code=PRD_DMA" class="7ref">75R_DEV;
tf.u8<7g, q75f="+code=is_atapi" cl="+code=bersk_inic162x.c#L383" id="L383" class="line"7l> 422cpu_to_le327irq_stat, cpu_to_7e16        u8<7  ;
tf.u8<7 AD" clas7/ata/sata_inic162x.c#L457" id=75;cdb[0]) == p7d75;
 477
 759 =  4ata_inic162x.c#Llrs/ata/sata_inil" cles/05" class="line" nlrs/ata/sata_inil" cle<  class="line" nNR_statSsref">tf.qc->prd<7a>[-176 class="sref">host_ira href="drivers/ata/__iomf="+code=qc" clas__iomf=id="L463" class="line388" id="L388" class="line" name="L388_inic162x.c#L465"mmio_id="L388" class="limmio_id="id="8"> 388       lrs/ata/sata_inil" cle*> 388       stat"SIZ)
cdb[0]) == P76e" name="L471"> 471        unsigned int 7c#L461" i7="L461" class="line" nam7="L4676f="+code=is_atapi" clnbytes" class="ROT_D id="L435" classROT_D line"0xff,/ta_inic162x.c#L388" id="L388" class="line" name="L388"> 388            ref=MASK162x.c#L460" id=    ref=MASK/sata_inic162x.c#L383" id="L383" class="line"7c> 422inic_qc_prep(struc7 irq_stat, qc-&7t;);
 477
cp76prd));
tf. 388       HOSTs="Lcode=cpb" classHOSTs="L/sata_inic162x.c#L383" id="L383" classtf.
 388       HOSTsref=MASK162x.c#L460" idHOSTsref=MASK/sata_inic162x.c#L383" id="L383" class(qc<7a>->tf.qc<77">qc->tf. 388       HOSTsref=MASK162x.c#L460" idHOSTsref=MASK/sata_inic162x.c#L383" id="L383" class 471        unsigned int 7a href="+7ode=cdb_len" class="sref7>cdb_77ef">qc-&gd="L423ass="sref">cdb[0]) ==  473 7     77ef">q=irq_stat" class="sref">irq_stat, ("ENTE7\n&qu77>        u8<7rivers/at7/sata_inic162x.c#L475" i7="L4777 href#ifdef> 388       CONFIG_PM name="L410"> 4CONFIG_PM        u8<7rc_pkt7c77;}
tf<462" nci_/a>

cpu_nci_/a>L388" class="linci_/a>id="L463" class="line3/a>L388" class="lin/a>id=")    u8<7ra> *77prdqc->prd = cpu_aa hhosnrs/ata/sata_iniaa hhosnid="L463" class="linehosnrs/ata/sata_inihosn/sat8_inic162x.c#L465"/a>_getfdrvIEN;
L388" class="lin/a>id="ass="line" name="L46/a>me="L487"> 487" cla_inic162x.c#L383" id="L383" classmemset( = cpu_lass=host_pL38L388" class="lilass=host_pL38id="L463" class="linehpL38L388" class="lihpL38id="L_inic162x.c#L465"hosnrs/ata/sata_inihosn/satass="line" name="L466L38ate_IEN;
ini78">qc-> " class="sref">tfctl_fl7gs =  471        unsigned int 7ne" name=7L482"> 482        if7(->tf
L388" class="lin/a>id=")_inic162x.c#L383" id="L383" class="line"7flass="li7">cpb->tfu8<7="+code=C7B_CTL_DATA" class="sref"7CPB_C78c162x.c#L434"a_addresd="L423lass="sref">tfqc);
offsetof(str78; 487" cls &if="dr"lwerrs/ata/sata_ini"lwer" cls &if="dr"lwer_2/a>srs/ata/sata_ini"lwer_2/a>s" cls &if="dreva/sae="L487"> 487qc->lbahtftf.tfu8<7e = <7 href="+code=qc" class="7ref">79>->tf7= qc->ef="+code=flags" class="sref">flags 7f">lbal =  471        unsigned int 7f">lbam = tfctl_flags |= tf.7a href="+code=lbah" clas7="sre79c162x.c#L434"d="L423ass="sref">cdb[0]) == tf.flags 7foffsetof7code=qc" class="sref">qc7/a>-&79" id=#endiff="+code=flags" class="sref">flags 7fa> * 44"u/a>-><7 href79;
command : 0xff, <7 href799}
tf<462" lastfon"L388" class="li462" lastfon"line"e32" class="sref">cpu_nci_/a>L388" class="linci_/a>id="L463" class="line3/a>L388" class="lin/a>id=", constae32" class="sref">cpu_nci_/a>

 487qc->qc->constae32" class="sref">cpu_aa h"lin_infosata_inic162x.caa h"lin_info"+cod463" class="line3xlrs/ata/sata_ini3xl"+co[]8_il/ata/sata_inic162x.c#lass="lineinfosata_inic162x.class="lineinfocdb[0]) == 8nic_interrupt(int ;
cpu_aa hhosnrs/ata/sata_iniaa hhosnid="L463" class="linehosnrs/ata/sata_inihosn/satss="sref">cdb[0]) == 8n = ->static void cdb[0]) == 8n = cdb[0]) == 8n href="+code=lbah" clas8 href80c162x.c#L434"f" class="sref">tfcdb[0]) == 8nf">tf.tfqc8>    80t inic8=8priv" c8ae="L418"> 44"u/a>-><8>hand80prd));
 487L388" class="lin/a>id="ass="line" name="L46/a>me="L487"> 487" cl  487h8riv->H8ST_IR81-> 477
qc->L388" class="lin/a>id="ass="line" name="L46/a>me="L487"> 487" cl tf.8a/sata_inic162x.c#L411" 8d="L481ef">qc->m_kzallocme="L487"> 487m_kzallocta/saata/sata_inic162x.c#2/a>L388" class="lin/a>id="ass="line" name="L46/a>me="L487"> 487" cl qc-&g hre!63" class="linehosnrs/ata/sata_inihosn/sat8|| !63" class="linehpL38L388" class="lihpL38id=")inic162x.c#L383" id="L383" class8lock" class="sref">spin_8ock 4ENOMEM" clss="sref">cdb[0]) ==         u8<8l6priv" c8ref="+code=i" class="sre8">i;
cdb[0]) ==  & 8inic8l8priv" c8 href="+code=host" class8"sref81+code=4f3f">l href="drivers/ata/sata_iAcquire claources    tclas host.  Note that PCI"   tcardbusme="L477"> 477
h82x.c#L418" id="L418" cla8s="li81358" lass="comment">                * use differa/s BARs.n't make much difference for native8andled" c8ass="sref">handled++8
                *ame="L477"> 477
 419qc-> 487L388" class="lin/a>id=")_inic162x.c#L383" id="L383" class="line"8a="sref">8ck" class="sref">spin_un8ockqc-&g hrelass="sref">tfu8<8a+code=de8 href="+code=lock" class8"sref82f="+code=is_atapi" cld="L423lass="sref">tf 422ctl_flags |=  424        return 8a hre82_DATA;
L388" class="lin/a>id="  4IORESOURCE_MEM/sat)    u8<8a6priv" c8+code=handled" class="sr8f">ha826="+code=is_atapi" cllass="sref">tf(struc8 lbahtftf.h8 *->L388" class="lin/a>id=" <1e<<  class="line" nmmio_idrrs/ata/sata_inimmio_idrid="  43831/a>->tfu8<8i="sref">8 class="line" name="L4318> 43183R_DEV;
tf 48283/a>->tfL388" class="lin/a>id=")_inic162x.c#L383" id="L383" class="line"8i> 422->tf
tftf.
 388       HOSTs="Lcode=cpb" classHOSTs="L/sata_inic162x.c#L383" id="L383" class(qc<83led);
READ)
 4ata_inic162x.c#Llrs/ata/sata_inil" cles/05" class="line" nlrs/ata/sata_inil" cle<  class="line" nNR_statSsref">tf.qc-> 436lbahcpu_aa h"linrs/ata/sata_inic162"linid="L463" class="line>        struct h8ne" name="L437"> 4378     83return 1;
"mmio"me="L47a_inic162x.c#L383" id="L383" classprd, struc8 host_ire 388       stat"SIZ)
""lin"me="L47a_inic162x.c#L383" id="L383" class8 *flags 8e     got8e="L442"> 442       8struc84/a>-&irq_stat" class="sref">irq_stat,  422 477
->tfL388" class="lin/a>id=" (fl84 href="+code= hrelass="sref">tfqc->tf. 487=errline"ata/sata_inic162x.c#2/a>L388" class="lin/a>id="ass="line" name="L46/a>me="L487"> 487" cl "32-bit ="L enable failed\n"me="L47a_inic162x.c#L383" id="L383" class 436 447            8   lbahtfPR84>prd = flags 8(qc<85pkt" class="sref">pkt, 0, sizeof(struct 8line" nam8="L450"> 450        8     85">qc->L388" class="lin/a>id=" 8="+code=PRD_DMA" class="8ref">85ef">qc-&g hrelass="sref">tfqc->q85f="+code=is_atapi" clline" name="L46/a>=errme="L487"> 487=errline"ata/sata_inic162x.c#2/a>L388" class="lin/a>id="ass="line" name="L46/a>me="L487"> 487" cl "32-bit consista/s ="L enable failed\n"me="L47a_inic162x.c#L383" id="L383" class 422cpu_to_le328tfcpu_to_8e16irq_stat, );
 477
p8d85;
                * This controller othbraindamaged.  +codboundary oth0xffffme="L477"> 477
                * like oth hr but it wlas oock up th iwhole mach na HARDg hme="L477"> 477
 859                * 65536 byte PRDg   ry othfed. Reduce maximum seg    8=ine" nam8e=prd" class="sref">prd<8a>[-186 claslass="comment">                *ame="L477"> 477
P86ef">qc->L388" class="lin/a>id=" <65536 - 512a_inic162x.c#L383" id="L383" classqc-&g hrelass="sref">tfqc->inic_qc_prep(struc8  487=errline"ata/sata_inic162x.c#2/a>L388" class="lin/a>id="ass="line" name="L46/a>me="L487"> 487" cl "failed to aetith imaximum seg    tfqc-&8t;irq_stat, inic8=> 436cp86prd));
tf.tfqc->qc<87>-> 487=errline"ata/sata_inic162x.c#2/a>L388" class="lin/a>id="ass="line" name="L46/a>me="L487"> 487" cl "failed to lastialize controller\n"me="L47a_inic162x.c#L383" id="L383" classqc<87 class="sref">host_ird="L423lass="sref">tfflags 8a href="+8ode=cdb_len" class="sref8>cdb_87/a>-&irq_stat" class="sref">irq_stat,  473 8     874a>->tfL388" class="lin/a>id=")_inic162x.c#L383" id="L383" class="line"8a>("ENTE8\n&qu87c162x.c#L434"d="L423eL388" class="lin/a>id="ass="line" name="L46irqrs/ata/sata_inilrqid=" < class="line" nl62" la erruptrs/ata/sata_inilas" la erruptid=" < class="line" nIRQF_SHAREc162x.c#L460" idIRQF_SHAREcid=" inic162x.c#L383" id="L383" class="line"8a="+code=8/sata_inic162x.c#L475" i8="L47876="+code=is_atapi" cllllllllllllllllllata/sata_inic162x.c#lass=shtrs/ata/sata_inilas" shtid=")_inic162x.c#L383" id="L383" class="line"8ac_pkt8c87;flags 8a> 43687;
}
cpu_nci_/a>

tf.qc->memset( =  388       sCI_VDEVIC)
ini88">qc->{ } inic162x.c#L383" id="L383" class="line"8a=  = cdb[0]) ==  482        if8(-&irq_stat" class="sref">irq_stat, cpb->cpu_pci_/lass=rs/ata/sata_inipci_/lass=id="Lata_inic162x.c#lass=pci_/lass=rs/ata/sata_inilass=pci_/lass=/sat8_ilass="sref">qc-> &if="dr="srrs/ata/sata_ini="sr="+code=is_atap_inic162x.c#L465"DRV_NAM)
qc;
tf.offsetof(str88; 388       CONFIG_PM name="L410"> 4CONFIG_PM        u8<8=a> *l  l_inic162x.c#L465"u_tonci_/a>


 = <8 href="+code=qc" class="8ref">89>->#endiff="+code=flags" class="sref">flags 8nsect8=  = qc-&gs &if="drremov"L388" class="liclmov"ta/sf="+code=s/nic162x.c#L465"u_tonci_clmov"fon"L388" class="liu_tonci_clmov"fon"line inic162x.c#L383" id="L383" class="line"8ee" name=8> = cdb[0]) ==  = ctl_flags |= tf.8a href="+code=lbah" clas8="sre89c162xline" name="L46module=pci_/lass=rs/ata/sata_inimodule=pci_/lass=ta/sa63" class="linelass=pci_/lass=rs/ata/sata_inilass=pci_/lass=/sat)_inic162x.c#L383" id="L383" class="line"8 class="s8ef">tf.qc8/a>-&89" id=63" class="lineMODULE_AUTHORrs/ata/sata_iniMODULE_AUTHORta/sa6href="drivere32ing">"Tejun Heo"me="L47a_inic162x.c#L383" id="L383" class * 44"u/a>-><8 href89;
 487"low-level #L383"o"> 4Iastio scommand : 0xff, <8 href899"GPL v2"me="L47a_inic162x.c#L383" id="L383" classtf.qc<63" class="lineMODULE_VERSIONme="L487"> 487 4879nic_interrupt(int 


The original LXR software byith inic162x.chttp://aource"> ge.net/projects/lxrr>LXR "> uasty"+co lxr@pt lxr.ptRedpill Lt}ons ser" nas since 1995.