linux/drivers/ata/sata_fsl.c
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   1/*
   2 * drivers/ata/sata_fsl.c
   3 *
   4 * Freescale 3.0Gbps SATA device driver
   5 *
   6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
   7 * Li Yang <leoli@freescale.com>
   8 *
   9 * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc.
  10 *
  11 * This program is free software; you can redistribute  it and/or modify it
  12 * under  the terms of  the GNU General  Public License as published by the
  13 * Free Software Foundation;  either version 2 of the  License, or (at your
  14 * option) any later version.
  15 *
  16 */
  17
  18#include <linux/kernel.h>
  19#include <linux/module.h>
  20#include <linux/platform_device.h>
  21#include <linux/slab.h>
  22
  23#include <scsi/scsi_host.h>
  24#include <scsi/scsi_cmnd.h>
  25#include <linux/libata.h>
  26#include <asm/io.h>
  27#include <linux/of_platform.h>
  28
  29static unsigned int intr_coalescing_count;
  30module_param(intr_coalescing_count, int, S_IRUGO);
  31MODULE_PARM_DESC(intr_coalescing_count,
  32                                 "INT coalescing count threshold (1..31)");
  33
  34static unsigned int intr_coalescing_ticks;
  35module_param(intr_coalescing_ticks, int, S_IRUGO);
  36MODULE_PARM_DESC(intr_coalescing_ticks,
  37                                 "INT coalescing timer threshold in AHB ticks");
  38/* Controller information */
  39enum {
  40        SATA_FSL_QUEUE_DEPTH    = 16,
  41        SATA_FSL_MAX_PRD        = 63,
  42        SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
  43        SATA_FSL_MAX_PRD_DIRECT = 16,   /* Direct PRDT entries */
  44
  45        SATA_FSL_HOST_FLAGS     = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
  46                                ATA_FLAG_PMP | ATA_FLAG_NCQ | ATA_FLAG_AN),
  47
  48        SATA_FSL_MAX_CMDS       = SATA_FSL_QUEUE_DEPTH,
  49        SATA_FSL_CMD_HDR_SIZE   = 16,   /* 4 DWORDS */
  50        SATA_FSL_CMD_SLOT_SIZE  = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
  51
  52        /*
  53         * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
  54         * chained indirect PRDEs up to a max count of 63.
  55         * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will
  56         * be setup as an indirect descriptor, pointing to it's next
  57         * (contiguous) PRDE. Though chained indirect PRDE arrays are
  58         * supported,it will be more efficient to use a direct PRDT and
  59         * a single chain/link to indirect PRDE array/PRDT.
  60         */
  61
  62        SATA_FSL_CMD_DESC_CFIS_SZ       = 32,
  63        SATA_FSL_CMD_DESC_SFIS_SZ       = 32,
  64        SATA_FSL_CMD_DESC_ACMD_SZ       = 16,
  65        SATA_FSL_CMD_DESC_RSRVD         = 16,
  66
  67        SATA_FSL_CMD_DESC_SIZE  = (SATA_FSL_CMD_DESC_CFIS_SZ +
  68                                 SATA_FSL_CMD_DESC_SFIS_SZ +
  69                                 SATA_FSL_CMD_DESC_ACMD_SZ +
  70                                 SATA_FSL_CMD_DESC_RSRVD +
  71                                 SATA_FSL_MAX_PRD * 16),
  72
  73        SATA_FSL_CMD_DESC_OFFSET_TO_PRDT        =
  74                                (SATA_FSL_CMD_DESC_CFIS_SZ +
  75                                 SATA_FSL_CMD_DESC_SFIS_SZ +
  76                                 SATA_FSL_CMD_DESC_ACMD_SZ +
  77                                 SATA_FSL_CMD_DESC_RSRVD),
  78
  79        SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
  80        SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
  81                                        SATA_FSL_CMD_DESC_AR_SZ),
  82
  83        /*
  84         * MPC8315 has two SATA controllers, SATA1 & SATA2
  85         * (one port per controller)
  86         * MPC837x has 2/4 controllers, one port per controller
  87         */
  88
  89        SATA_FSL_MAX_PORTS      = 1,
  90
  91        SATA_FSL_IRQ_FLAG       = IRQF_SHARED,
  92};
  93
  94/*
  95 * Interrupt Coalescing Control Register bitdefs  */
  96enum {
  97        ICC_MIN_INT_COUNT_THRESHOLD     = 1,
  98        ICC_MAX_INT_COUNT_THRESHOLD     = ((1 << 5) - 1),
  99        ICC_MIN_INT_TICKS_THRESHOLD     = 0,
 100        ICC_MAX_INT_TICKS_THRESHOLD     = ((1 << 19) - 1),
 101        ICC_SAFE_INT_TICKS              = 1,
 102};
 103
 104/*
 105* Host Controller command register set - per port
 106*/
 107enum {
 108        CQ = 0,
 109        CA = 8,
 110        CC = 0x10,
 111        CE = 0x18,
 112        DE = 0x20,
 113        CHBA = 0x24,
 114        HSTATUS = 0x28,
 115        HCONTROL = 0x2C,
 116        CQPMP = 0x30,
 117        SIGNATURE = 0x34,
 118        ICC = 0x38,
 119
 120        /*
 121         * Host Status Register (HStatus) bitdefs
 122         */
 123        ONLINE = (1 << 31),
 124        GOING_OFFLINE = (1 << 30),
 125        BIST_ERR = (1 << 29),
 126        CLEAR_ERROR = (1 << 27),
 127
 128        FATAL_ERR_HC_MASTER_ERR = (1 << 18),
 129        FATAL_ERR_PARITY_ERR_TX = (1 << 17),
 130        FATAL_ERR_PARITY_ERR_RX = (1 << 16),
 131        FATAL_ERR_DATA_UNDERRUN = (1 << 13),
 132        FATAL_ERR_DATA_OVERRUN = (1 << 12),
 133        FATAL_ERR_CRC_ERR_TX = (1 << 11),
 134        FATAL_ERR_CRC_ERR_RX = (1 << 10),
 135        FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
 136        FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
 137
 138        FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
 139            FATAL_ERR_PARITY_ERR_TX |
 140            FATAL_ERR_PARITY_ERR_RX |
 141            FATAL_ERR_DATA_UNDERRUN |
 142            FATAL_ERR_DATA_OVERRUN |
 143            FATAL_ERR_CRC_ERR_TX |
 144            FATAL_ERR_CRC_ERR_RX |
 145            FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
 146
 147        INT_ON_DATA_LENGTH_MISMATCH = (1 << 12),
 148        INT_ON_FATAL_ERR = (1 << 5),
 149        INT_ON_PHYRDY_CHG = (1 << 4),
 150
 151        INT_ON_SIGNATURE_UPDATE = (1 << 3),
 152        INT_ON_SNOTIFY_UPDATE = (1 << 2),
 153        INT_ON_SINGL_DEVICE_ERR = (1 << 1),
 154        INT_ON_CMD_COMPLETE = 1,
 155
 156        INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE |
 157            INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
 158
 159        /*
 160         * Host Control Register (HControl) bitdefs
 161         */
 162        HCONTROL_ONLINE_PHY_RST = (1 << 31),
 163        HCONTROL_FORCE_OFFLINE = (1 << 30),
 164        HCONTROL_LEGACY = (1 << 28),
 165        HCONTROL_PARITY_PROT_MOD = (1 << 14),
 166        HCONTROL_DPATH_PARITY = (1 << 12),
 167        HCONTROL_SNOOP_ENABLE = (1 << 10),
 168        HCONTROL_PMP_ATTACHED = (1 << 9),
 169        HCONTROL_COPYOUT_STATFIS = (1 << 8),
 170        IE_ON_FATAL_ERR = (1 << 5),
 171        IE_ON_PHYRDY_CHG = (1 << 4),
 172        IE_ON_SIGNATURE_UPDATE = (1 << 3),
 173        IE_ON_SNOTIFY_UPDATE = (1 << 2),
 174        IE_ON_SINGL_DEVICE_ERR = (1 << 1),
 175        IE_ON_CMD_COMPLETE = 1,
 176
 177        DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
 178            IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE |
 179            IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
 180
 181        EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
 182        DATA_SNOOP_ENABLE_V1 = (1 << 22),
 183        DATA_SNOOP_ENABLE_V2 = (1 << 28),
 184};
 185
 186/*
 187 * SATA Superset Registers
 188 */
 189enum {
 190        SSTATUS = 0,
 191        SERROR = 4,
 192        SCONTROL = 8,
 193        SNOTIFY = 0xC,
 194};
 195
 196/*
 197 * Control Status Register Set
 198 */
 199enum {
 200        TRANSCFG = 0,
 201        TRANSSTATUS = 4,
 202        LINKCFG = 8,
 203        LINKCFG1 = 0xC,
 204        LINKCFG2 = 0x10,
 205        LINKSTATUS = 0x14,
 206        LINKSTATUS1 = 0x18,
 207        PHYCTRLCFG = 0x1C,
 208        COMMANDSTAT = 0x20,
 209};
 210
 211/* TRANSCFG (transport-layer) configuration control */
 212enum {
 213        TRANSCFG_RX_WATER_MARK = (1 << 4),
 214};
 215
 216/* PHY (link-layer) configuration control */
 217enum {
 218        PHY_BIST_ENABLE = 0x01,
 219};
 220
 221/*
 222 * Command Header Table entry, i.e, command slot
 223 * 4 Dwords per command slot, command header size ==  64 Dwords.
 224 */
 225struct cmdhdr_tbl_entry {
 226        u32 cda;
 227        u32 prde_fis_len;
 228        u32 ttl;
 229        u32 desc_info;
 230};
 231
 232/*
 233 * Description information bitdefs
 234 */
 235enum {
 236        CMD_DESC_RES = (1 << 11),
 237        VENDOR_SPECIFIC_BIST = (1 << 10),
 238        CMD_DESC_SNOOP_ENABLE = (1 << 9),
 239        FPDMA_QUEUED_CMD = (1 << 8),
 240        SRST_CMD = (1 << 7),
 241        BIST = (1 << 6),
 242        ATAPI_CMD = (1 << 5),
 243};
 244
 245/*
 246 * Command Descriptor
 247 */
 248struct command_desc {
 249        u8 cfis[8 * 4];
 250        u8 sfis[8 * 4];
 251        u8 acmd[4 * 4];
 252        u8 fill[4 * 4];
 253        u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
 254        u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
 255};
 256
 257/*
 258 * Physical region table descriptor(PRD)
 259 */
 260
 261struct prde {
 262        u32 dba;
 263        u8 fill[2 * 4];
 264        u32 ddc_and_ext;
 265};
 266
 267/*
 268 * ata_port private data
 269 * This is our per-port instance data.
 270 */
 271struct sata_fsl_port_priv {
 272        struct cmdhdr_tbl_entry *cmdslot;
 273        dma_addr_t cmdslot_paddr;
 274        struct command_desc *cmdentry;
 275        dma_addr_t cmdentry_paddr;
 276};
 277
 278/*
 279 * ata_port->host_set private data
 280 */
 281struct sata_fsl_host_priv {
 282        void __iomem *hcr_base;
 283        void __iomem *ssr_base;
 284        void __iomem *csr_base;
 285        int irq;
 286        int data_snoop;
 287        struct device_attribute intr_coalescing;
 288        struct device_attribute rx_watermark;
 289};
 290
 291static void fsl_sata_set_irq_coalescing(struct ata_host *host,
 292                unsigned int count, unsigned int ticks)
 293{
 294        struct sata_fsl_host_priv *host_priv = host->private_data;
 295        void __iomem *hcr_base = host_priv->hcr_base;
 296
 297        if (count > ICC_MAX_INT_COUNT_THRESHOLD)
 298                count = ICC_MAX_INT_COUNT_THRESHOLD;
 299        else if (count < ICC_MIN_INT_COUNT_THRESHOLD)
 300                count = ICC_MIN_INT_COUNT_THRESHOLD;
 301
 302        if (ticks > ICC_MAX_INT_TICKS_THRESHOLD)
 303                ticks = ICC_MAX_INT_TICKS_THRESHOLD;
 304        else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) &&
 305                        (count > ICC_MIN_INT_COUNT_THRESHOLD))
 306                ticks = ICC_SAFE_INT_TICKS;
 307
 308        spin_lock(&host->lock);
 309        iowrite32((count << 24 | ticks), hcr_base + ICC);
 310
 311        intr_coalescing_count = count;
 312        intr_coalescing_ticks = ticks;
 313        spin_unlock(&host->lock);
 314
 315        DPRINTK("interrupt coalescing, count = 0x%x, ticks = %x\n",
 316                        intr_coalescing_count, intr_coalescing_ticks);
 317        DPRINTK("ICC register status: (hcr base: 0x%x) = 0x%x\n",
 318                        hcr_base, ioread32(hcr_base + ICC));
 319}
 320
 321static ssize_t fsl_sata_intr_coalescing_show(struct device *dev,
 322                struct device_attribute *attr, char *buf)
 323{
 324        return sprintf(buf, "%d %d\n",
 325                        intr_coalescing_count, intr_coalescing_ticks);
 326}
 327
 328static ssize_t fsl_sata_intr_coalescing_store(struct device *dev,
 329                struct device_attribute *attr,
 330                const char *buf, size_t count)
 331{
 332        unsigned int coalescing_count,  coalescing_ticks;
 333
 334        if (sscanf(buf, "%d%d",
 335                                &coalescing_count,
 336                                &coalescing_ticks) != 2) {
 337                printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
 338                return -EINVAL;
 339        }
 340
 341        fsl_sata_set_irq_coalescing(dev_get_drvdata(dev),
 342                        coalescing_count, coalescing_ticks);
 343
 344        return strlen(buf);
 345}
 346
 347static ssize_t fsl_sata_rx_watermark_show(struct device *dev,
 348                struct device_attribute *attr, char *buf)
 349{
 350        unsigned int rx_watermark;
 351        unsigned long flags;
 352        struct ata_host *host = dev_get_drvdata(dev);
 353        struct sata_fsl_host_priv *host_priv = host->private_data;
 354        void __iomem *csr_base = host_priv->csr_base;
 355
 356        spin_lock_irqsave(&host->lock, flags);
 357        rx_watermark = ioread32(csr_base + TRANSCFG);
 358        rx_watermark &= 0x1f;
 359
 360        spin_unlock_irqrestore(&host->lock, flags);
 361        return sprintf(buf, "%d\n", rx_watermark);
 362}
 363
 364static ssize_t fsl_sata_rx_watermark_store(struct device *dev,
 365                struct device_attribute *attr,
 366                const char *buf, size_t count)
 367{
 368        unsigned int rx_watermark;
 369        unsigned long flags;
 370        struct ata_host *host = dev_get_drvdata(dev);
 371        struct sata_fsl_host_priv *host_priv = host->private_data;
 372        void __iomem *csr_base = host_priv->csr_base;
 373        u32 temp;
 374
 375        if (sscanf(buf, "%d", &rx_watermark) != 1) {
 376                printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
 377                return -EINVAL;
 378        }
 379
 380        spin_lock_irqsave(&host->lock, flags);
 381        temp = ioread32(csr_base + TRANSCFG);
 382        temp &= 0xffffffe0;
 383        iowrite32(temp | rx_watermark, csr_base + TRANSCFG);
 384
 385        spin_unlock_irqrestore(&host->lock, flags);
 386        return strlen(buf);
 387}
 388
 389static inline unsigned int sata_fsl_tag(unsigned int tag,
 390                                        void __iomem *hcr_base)
 391{
 392        /* We let libATA core do actual (queue) tag allocation */
 393
 394        /* all non NCQ/queued commands should have tag#0 */
 395        if (ata_tag_internal(tag)) {
 396                DPRINTK("mapping internal cmds to tag#0\n");
 397                return 0;
 398        }
 399
 400        if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
 401                DPRINTK("tag %d invalid : out of range\n", tag);
 402                return 0;
 403        }
 404
 405        if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
 406                DPRINTK("tag %d invalid : in use!!\n", tag);
 407                return 0;
 408        }
 409
 410        return tag;
 411}
 412
 413static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
 414                                         unsigned int tag, u32 desc_info,
 415                                         u32 data_xfer_len, u8 num_prde,
 416                                         u8 fis_len)
 417{
 418        dma_addr_t cmd_descriptor_address;
 419
 420        cmd_descriptor_address = pp->cmdentry_paddr +
 421            tag * SATA_FSL_CMD_DESC_SIZE;
 422
 423        /* NOTE: both data_xfer_len & fis_len are Dword counts */
 424
 425        pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
 426        pp->cmdslot[tag].prde_fis_len =
 427            cpu_to_le32((num_prde << 16) | (fis_len << 2));
 428        pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
 429        pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
 430
 431        VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
 432                pp->cmdslot[tag].cda,
 433                pp->cmdslot[tag].prde_fis_len,
 434                pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
 435
 436}
 437
 438static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
 439                                     u32 *ttl, dma_addr_t cmd_desc_paddr,
 440                                     int data_snoop)
 441{
 442        struct scatterlist *sg;
 443        unsigned int num_prde = 0;
 444        u32 ttl_dwords = 0;
 445
 446        /*
 447         * NOTE : direct & indirect prdt's are contiguously allocated
 448         */
 449        struct prde *prd = (struct prde *)&((struct command_desc *)
 450                                            cmd_desc)->prdt;
 451
 452        struct prde *prd_ptr_to_indirect_ext = NULL;
 453        unsigned indirect_ext_segment_sz = 0;
 454        dma_addr_t indirect_ext_segment_paddr;
 455        unsigned int si;
 456
 457        VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd);
 458
 459        indirect_ext_segment_paddr = cmd_desc_paddr +
 460            SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
 461
 462        for_each_sg(qc->sg, sg, qc->n_elem, si) {
 463                dma_addr_t sg_addr = sg_dma_address(sg);
 464                u32 sg_len = sg_dma_len(sg);
 465
 466                VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n",
 467                        (unsigned long long)sg_addr, sg_len);
 468
 469                /* warn if each s/g element is not dword aligned */
 470                if (unlikely(sg_addr & 0x03))
 471                        ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n",
 472                                     (unsigned long long)sg_addr);
 473                if (unlikely(sg_len & 0x03))
 474                        ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n",
 475                                     sg_len);
 476
 477                if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
 478                    sg_next(sg) != NULL) {
 479                        VPRINTK("setting indirect prde\n");
 480                        prd_ptr_to_indirect_ext = prd;
 481                        prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
 482                        indirect_ext_segment_sz = 0;
 483                        ++prd;
 484                        ++num_prde;
 485                }
 486
 487                ttl_dwords += sg_len;
 488                prd->dba = cpu_to_le32(sg_addr);
 489                prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03));
 490
 491                VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
 492                        ttl_dwords, prd->dba, prd->ddc_and_ext);
 493
 494                ++num_prde;
 495                ++prd;
 496                if (prd_ptr_to_indirect_ext)
 497                        indirect_ext_segment_sz += sg_len;
 498        }
 499
 500        if (prd_ptr_to_indirect_ext) {
 501                /* set indirect extension flag along with indirect ext. size */
 502                prd_ptr_to_indirect_ext->ddc_and_ext =
 503                    cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
 504                                 data_snoop |
 505                                 (indirect_ext_segment_sz & ~0x03)));
 506        }
 507
 508        *ttl = ttl_dwords;
 509        return num_prde;
 510}
 511
 512static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
 513{
 514        struct ata_port *ap = qc->ap;
 515        struct sata_fsl_port_priv *pp = ap->private_data;
 516        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 517        void __iomem *hcr_base = host_priv->hcr_base;
 518        unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
 519        struct command_desc *cd;
 520        u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
 521        u32 num_prde = 0;
 522        u32 ttl_dwords = 0;
 523        dma_addr_t cd_paddr;
 524
 525        cd = (struct command_desc *)pp->cmdentry + tag;
 526        cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
 527
 528        ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
 529
 530        VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
 531                cd->cfis[0], cd->cfis[1], cd->cfis[2]);
 532
 533        if (qc->tf.protocol == ATA_PROT_NCQ) {
 534                VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
 535                        cd->cfis[3], cd->cfis[11]);
 536        }
 537
 538        /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
 539        if (ata_is_atapi(qc->tf.protocol)) {
 540                desc_info |= ATAPI_CMD;
 541                memset((void *)&cd->acmd, 0, 32);
 542                memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
 543        }
 544
 545        if (qc->flags & ATA_QCFLAG_DMAMAP)
 546                num_prde = sata_fsl_fill_sg(qc, (void *)cd,
 547                                            &ttl_dwords, cd_paddr,
 548                                            host_priv->data_snoop);
 549
 550        if (qc->tf.protocol == ATA_PROT_NCQ)
 551                desc_info |= FPDMA_QUEUED_CMD;
 552
 553        sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
 554                                     num_prde, 5);
 555
 556        VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
 557                desc_info, ttl_dwords, num_prde);
 558}
 559
 560static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
 561{
 562        struct ata_port *ap = qc->ap;
 563        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 564        void __iomem *hcr_base = host_priv->hcr_base;
 565        unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
 566
 567        VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
 568                ioread32(CQ + hcr_base),
 569                ioread32(CA + hcr_base),
 570                ioread32(CE + hcr_base), ioread32(CC + hcr_base));
 571
 572        iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
 573
 574        /* Simply queue command to the controller/device */
 575        iowrite32(1 << tag, CQ + hcr_base);
 576
 577        VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
 578                tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
 579
 580        VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
 581                ioread32(CE + hcr_base),
 582                ioread32(DE + hcr_base),
 583                ioread32(CC + hcr_base),
 584                ioread32(COMMANDSTAT + host_priv->csr_base));
 585
 586        return 0;
 587}
 588
 589static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
 590{
 591        struct sata_fsl_port_priv *pp = qc->ap->private_data;
 592        struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
 593        void __iomem *hcr_base = host_priv->hcr_base;
 594        unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
 595        struct command_desc *cd;
 596
 597        cd = pp->cmdentry + tag;
 598
 599        ata_tf_from_fis(cd->sfis, &qc->result_tf);
 600        return true;
 601}
 602
 603static int sata_fsl_scr_write(struct ata_link *link,
 604                              unsigned int sc_reg_in, u32 val)
 605{
 606        struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
 607        void __iomem *ssr_base = host_priv->ssr_base;
 608        unsigned int sc_reg;
 609
 610        switch (sc_reg_in) {
 611        case SCR_STATUS:
 612        case SCR_ERROR:
 613        case SCR_CONTROL:
 614        case SCR_ACTIVE:
 615                sc_reg = sc_reg_in;
 616                break;
 617        default:
 618                return -EINVAL;
 619        }
 620
 621        VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
 622
 623        iowrite32(val, ssr_base + (sc_reg * 4));
 624        return 0;
 625}
 626
 627static int sata_fsl_scr_read(struct ata_link *link,
 628                             unsigned int sc_reg_in, u32 *val)
 629{
 630        struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
 631        void __iomem *ssr_base = host_priv->ssr_base;
 632        unsigned int sc_reg;
 633
 634        switch (sc_reg_in) {
 635        case SCR_STATUS:
 636        case SCR_ERROR:
 637        case SCR_CONTROL:
 638        case SCR_ACTIVE:
 639                sc_reg = sc_reg_in;
 640                break;
 641        default:
 642                return -EINVAL;
 643        }
 644
 645        VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
 646
 647        *val = ioread32(ssr_base + (sc_reg * 4));
 648        return 0;
 649}
 650
 651static void sata_fsl_freeze(struct ata_port *ap)
 652{
 653        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 654        void __iomem *hcr_base = host_priv->hcr_base;
 655        u32 temp;
 656
 657        VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
 658                ioread32(CQ + hcr_base),
 659                ioread32(CA + hcr_base),
 660                ioread32(CE + hcr_base), ioread32(DE + hcr_base));
 661        VPRINTK("CmdStat = 0x%x\n",
 662                ioread32(host_priv->csr_base + COMMANDSTAT));
 663
 664        /* disable interrupts on the controller/port */
 665        temp = ioread32(hcr_base + HCONTROL);
 666        iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
 667
 668        VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
 669                ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
 670}
 671
 672static void sata_fsl_thaw(struct ata_port *ap)
 673{
 674        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 675        void __iomem *hcr_base = host_priv->hcr_base;
 676        u32 temp;
 677
 678        /* ack. any pending IRQs for this controller/port */
 679        temp = ioread32(hcr_base + HSTATUS);
 680
 681        VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
 682
 683        if (temp & 0x3F)
 684                iowrite32((temp & 0x3F), hcr_base + HSTATUS);
 685
 686        /* enable interrupts on the controller/port */
 687        temp = ioread32(hcr_base + HCONTROL);
 688        iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
 689
 690        VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
 691                ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
 692}
 693
 694static void sata_fsl_pmp_attach(struct ata_port *ap)
 695{
 696        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 697        void __iomem *hcr_base = host_priv->hcr_base;
 698        u32 temp;
 699
 700        temp = ioread32(hcr_base + HCONTROL);
 701        iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
 702}
 703
 704static void sata_fsl_pmp_detach(struct ata_port *ap)
 705{
 706        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 707        void __iomem *hcr_base = host_priv->hcr_base;
 708        u32 temp;
 709
 710        temp = ioread32(hcr_base + HCONTROL);
 711        temp &= ~HCONTROL_PMP_ATTACHED;
 712        iowrite32(temp, hcr_base + HCONTROL);
 713
 714        /* enable interrupts on the controller/port */
 715        temp = ioread32(hcr_base + HCONTROL);
 716        iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
 717
 718}
 719
 720static int sata_fsl_port_start(struct ata_port *ap)
 721{
 722        struct device *dev = ap->host->dev;
 723        struct sata_fsl_port_priv *pp;
 724        void *mem;
 725        dma_addr_t mem_dma;
 726        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 727        void __iomem *hcr_base = host_priv->hcr_base;
 728        u32 temp;
 729
 730        pp = kzalloc(sizeof(*pp), GFP_KERNEL);
 731        if (!pp)
 732                return -ENOMEM;
 733
 734        mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
 735                                 GFP_KERNEL);
 736        if (!mem) {
 737                kfree(pp);
 738                return -ENOMEM;
 739        }
 740        memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ);
 741
 742        pp->cmdslot = mem;
 743        pp->cmdslot_paddr = mem_dma;
 744
 745        mem += SATA_FSL_CMD_SLOT_SIZE;
 746        mem_dma += SATA_FSL_CMD_SLOT_SIZE;
 747
 748        pp->cmdentry = mem;
 749        pp->cmdentry_paddr = mem_dma;
 750
 751        ap->private_data = pp;
 752
 753        VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
 754                pp->cmdslot_paddr, pp->cmdentry_paddr);
 755
 756        /* Now, update the CHBA register in host controller cmd register set */
 757        iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
 758
 759        /*
 760         * Now, we can bring the controller on-line & also initiate
 761         * the COMINIT sequence, we simply return here and the boot-probing
 762         * & device discovery process is re-initiated by libATA using a
 763         * Softreset EH (dummy) session. Hence, boot probing and device
 764         * discovey will be part of sata_fsl_softreset() callback.
 765         */
 766
 767        temp = ioread32(hcr_base + HCONTROL);
 768        iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
 769
 770        VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
 771        VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
 772        VPRINTK("CHBA  = 0x%x\n", ioread32(hcr_base + CHBA));
 773
 774#ifdef CONFIG_MPC8315_DS
 775        /*
 776         * Workaround for 8315DS board 3gbps link-up issue,
 777         * currently limit SATA port to GEN1 speed
 778         */
 779        sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
 780        temp &= ~(0xF << 4);
 781        temp |= (0x1 << 4);
 782        sata_fsl_scr_write(&ap->link, SCR_CONTROL, temp);
 783
 784        sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
 785        dev_warn(dev, "scr_control, speed limited to %x\n", temp);
 786#endif
 787
 788        return 0;
 789}
 790
 791static void sata_fsl_port_stop(struct ata_port *ap)
 792{
 793        struct device *dev = ap->host->dev;
 794        struct sata_fsl_port_priv *pp = ap->private_data;
 795        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 796        void __iomem *hcr_base = host_priv->hcr_base;
 797        u32 temp;
 798
 799        /*
 800         * Force host controller to go off-line, aborting current operations
 801         */
 802        temp = ioread32(hcr_base + HCONTROL);
 803        temp &= ~HCONTROL_ONLINE_PHY_RST;
 804        temp |= HCONTROL_FORCE_OFFLINE;
 805        iowrite32(temp, hcr_base + HCONTROL);
 806
 807        /* Poll for controller to go offline - should happen immediately */
 808        ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
 809
 810        ap->private_data = NULL;
 811        dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
 812                          pp->cmdslot, pp->cmdslot_paddr);
 813
 814        kfree(pp);
 815}
 816
 817static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
 818{
 819        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 820        void __iomem *hcr_base = host_priv->hcr_base;
 821        struct ata_taskfile tf;
 822        u32 temp;
 823
 824        temp = ioread32(hcr_base + SIGNATURE);
 825
 826        VPRINTK("raw sig = 0x%x\n", temp);
 827        VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
 828        VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
 829
 830        tf.lbah = (temp >> 24) & 0xff;
 831        tf.lbam = (temp >> 16) & 0xff;
 832        tf.lbal = (temp >> 8) & 0xff;
 833        tf.nsect = temp & 0xff;
 834
 835        return ata_dev_classify(&tf);
 836}
 837
 838static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
 839                                        unsigned long deadline)
 840{
 841        struct ata_port *ap = link->ap;
 842        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 843        void __iomem *hcr_base = host_priv->hcr_base;
 844        u32 temp;
 845        int i = 0;
 846        unsigned long start_jiffies;
 847
 848        DPRINTK("in xx_hardreset\n");
 849
 850try_offline_again:
 851        /*
 852         * Force host controller to go off-line, aborting current operations
 853         */
 854        temp = ioread32(hcr_base + HCONTROL);
 855        temp &= ~HCONTROL_ONLINE_PHY_RST;
 856        iowrite32(temp, hcr_base + HCONTROL);
 857
 858        /* Poll for controller to go offline */
 859        temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
 860                                 1, 500);
 861
 862        if (temp & ONLINE) {
 863                ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i);
 864
 865                /*
 866                 * Try to offline controller atleast twice
 867                 */
 868                i++;
 869                if (i == 2)
 870                        goto err;
 871                else
 872                        goto try_offline_again;
 873        }
 874
 875        DPRINTK("hardreset, controller off-lined\n");
 876        VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
 877        VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
 878
 879        /*
 880         * PHY reset should remain asserted for atleast 1ms
 881         */
 882        ata_msleep(ap, 1);
 883
 884        /*
 885         * Now, bring the host controller online again, this can take time
 886         * as PHY reset and communication establishment, 1st D2H FIS and
 887         * device signature update is done, on safe side assume 500ms
 888         * NOTE : Host online status may be indicated immediately!!
 889         */
 890
 891        temp = ioread32(hcr_base + HCONTROL);
 892        temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
 893        temp |= HCONTROL_PMP_ATTACHED;
 894        iowrite32(temp, hcr_base + HCONTROL);
 895
 896        temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
 897
 898        if (!(temp & ONLINE)) {
 899                ata_port_err(ap, "Hardreset failed, not on-lined\n");
 900                goto err;
 901        }
 902
 903        DPRINTK("hardreset, controller off-lined & on-lined\n");
 904        VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
 905        VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
 906
 907        /*
 908         * First, wait for the PHYRDY change to occur before waiting for
 909         * the signature, and also verify if SStatus indicates device
 910         * presence
 911         */
 912
 913        temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
 914        if ((!(temp & 0x10)) || ata_link_offline(link)) {
 915                ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n",
 916                              ioread32(hcr_base + HSTATUS));
 917                *class = ATA_DEV_NONE;
 918                return 0;
 919        }
 920
 921        /*
 922         * Wait for the first D2H from device,i.e,signature update notification
 923         */
 924        start_jiffies = jiffies;
 925        temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
 926                        500, jiffies_to_msecs(deadline - start_jiffies));
 927
 928        if ((temp & 0xFF) != 0x18) {
 929                ata_port_warn(ap, "No Signature Update\n");
 930                *class = ATA_DEV_NONE;
 931                goto do_followup_srst;
 932        } else {
 933                ata_port_info(ap, "Signature Update detected @ %d msecs\n",
 934                              jiffies_to_msecs(jiffies - start_jiffies));
 935                *class = sata_fsl_dev_classify(ap);
 936                return 0;
 937        }
 938
 939do_followup_srst:
 940        /*
 941         * request libATA to perform follow-up softreset
 942         */
 943        return -EAGAIN;
 944
 945err:
 946        return -EIO;
 947}
 948
 949static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
 950                                        unsigned long deadline)
 951{
 952        struct ata_port *ap = link->ap;
 953        struct sata_fsl_port_priv *pp = ap->private_data;
 954        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
 955        void __iomem *hcr_base = host_priv->hcr_base;
 956        int pmp = sata_srst_pmp(link);
 957        u32 temp;
 958        struct ata_taskfile tf;
 959        u8 *cfis;
 960        u32 Serror;
 961
 962        DPRINTK("in xx_softreset\n");
 963
 964        if (ata_link_offline(link)) {
 965                DPRINTK("PHY reports no device\n");
 966                *class = ATA_DEV_NONE;
 967                return 0;
 968        }
 969
 970        /*
 971         * Send a device reset (SRST) explicitly on command slot #0
 972         * Check : will the command queue (reg) be cleared during offlining ??
 973         * Also we will be online only if Phy commn. has been established
 974         * and device presence has been detected, therefore if we have
 975         * reached here, we can send a command to the target device
 976         */
 977
 978        DPRINTK("Sending SRST/device reset\n");
 979
 980        ata_tf_init(link->device, &tf);
 981        cfis = (u8 *) &pp->cmdentry->cfis;
 982
 983        /* device reset/SRST is a control register update FIS, uses tag0 */
 984        sata_fsl_setup_cmd_hdr_entry(pp, 0,
 985                SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
 986
 987        tf.ctl |= ATA_SRST;     /* setup SRST bit in taskfile control reg */
 988        ata_tf_to_fis(&tf, pmp, 0, cfis);
 989
 990        DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
 991                cfis[0], cfis[1], cfis[2], cfis[3]);
 992
 993        /*
 994         * Queue SRST command to the controller/device, ensure that no
 995         * other commands are active on the controller/device
 996         */
 997
 998        DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
 999                ioread32(CQ + hcr_base),
1000                ioread32(CA + hcr_base), ioread32(CC + hcr_base));
1001
1002        iowrite32(0xFFFF, CC + hcr_base);
1003        if (pmp != SATA_PMP_CTRL_PORT)
1004                iowrite32(pmp, CQPMP + hcr_base);
1005        iowrite32(1, CQ + hcr_base);
1006
1007        temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);
1008        if (temp & 0x1) {
1009                ata_port_warn(ap, "ATA_SRST issue failed\n");
1010
1011                DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
1012                        ioread32(CQ + hcr_base),
1013                        ioread32(CA + hcr_base), ioread32(CC + hcr_base));
1014
1015                sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
1016
1017                DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1018                DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1019                DPRINTK("Serror = 0x%x\n", Serror);
1020                goto err;
1021        }
1022
1023        ata_msleep(ap, 1);
1024
1025        /*
1026         * SATA device enters reset state after receiving a Control register
1027         * FIS with SRST bit asserted and it awaits another H2D Control reg.
1028         * FIS with SRST bit cleared, then the device does internal diags &
1029         * initialization, followed by indicating it's initialization status
1030         * using ATA signature D2H register FIS to the host controller.
1031         */
1032
1033        sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
1034                                      0, 0, 5);
1035
1036        tf.ctl &= ~ATA_SRST;    /* 2nd H2D Ctl. register FIS */
1037        ata_tf_to_fis(&tf, pmp, 0, cfis);
1038
1039        if (pmp != SATA_PMP_CTRL_PORT)
1040                iowrite32(pmp, CQPMP + hcr_base);
1041        iowrite32(1, CQ + hcr_base);
1042        ata_msleep(ap, 150);            /* ?? */
1043
1044        /*
1045         * The above command would have signalled an interrupt on command
1046         * complete, which needs special handling, by clearing the Nth
1047         * command bit of the CCreg
1048         */
1049        iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
1050
1051        DPRINTK("SATA FSL : Now checking device signature\n");
1052
1053        *class = ATA_DEV_NONE;
1054
1055        /* Verify if SStatus indicates device presence */
1056        if (ata_link_online(link)) {
1057                /*
1058                 * if we are here, device presence has been detected,
1059                 * 1st D2H FIS would have been received, but sfis in
1060                 * command desc. is not updated, but signature register
1061                 * would have been updated
1062                 */
1063
1064                *class = sata_fsl_dev_classify(ap);
1065
1066                DPRINTK("class = %d\n", *class);
1067                VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
1068                VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
1069        }
1070
1071        return 0;
1072
1073err:
1074        return -EIO;
1075}
1076
1077static void sata_fsl_error_handler(struct ata_port *ap)
1078{
1079
1080        DPRINTK("in xx_error_handler\n");
1081        sata_pmp_error_handler(ap);
1082
1083}
1084
1085static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
1086{
1087        if (qc->flags & ATA_QCFLAG_FAILED)
1088                qc->err_mask |= AC_ERR_OTHER;
1089
1090        if (qc->err_mask) {
1091                /* make DMA engine forget about the failed command */
1092
1093        }
1094}
1095
1096static void sata_fsl_error_intr(struct ata_port *ap)
1097{
1098        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1099        void __iomem *hcr_base = host_priv->hcr_base;
1100        u32 hstatus, dereg=0, cereg = 0, SError = 0;
1101        unsigned int err_mask = 0, action = 0;
1102        int freeze = 0, abort=0;
1103        struct ata_link *link = NULL;
1104        struct ata_queued_cmd *qc = NULL;
1105        struct ata_eh_info *ehi;
1106
1107        hstatus = ioread32(hcr_base + HSTATUS);
1108        cereg = ioread32(hcr_base + CE);
1109
1110        /* first, analyze and record host port events */
1111        link = &ap->link;
1112        ehi = &link->eh_info;
1113        ata_ehi_clear_desc(ehi);
1114
1115        /*
1116         * Handle & Clear SError
1117         */
1118
1119        sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1120        if (unlikely(SError & 0xFFFF0000))
1121                sata_fsl_scr_write(&ap->link, SCR_ERROR, SError);
1122
1123        DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
1124                hstatus, cereg, ioread32(hcr_base + DE), SError);
1125
1126        /* handle fatal errors */
1127        if (hstatus & FATAL_ERROR_DECODE) {
1128                ehi->err_mask |= AC_ERR_ATA_BUS;
1129                ehi->action |= ATA_EH_SOFTRESET;
1130
1131                freeze = 1;
1132        }
1133
1134        /* Handle SDB FIS receive & notify update */
1135        if (hstatus & INT_ON_SNOTIFY_UPDATE)
1136                sata_async_notification(ap);
1137
1138        /* Handle PHYRDY change notification */
1139        if (hstatus & INT_ON_PHYRDY_CHG) {
1140                DPRINTK("SATA FSL: PHYRDY change indication\n");
1141
1142                /* Setup a soft-reset EH action */
1143                ata_ehi_hotplugged(ehi);
1144                ata_ehi_push_desc(ehi, "%s", "PHY RDY changed");
1145                freeze = 1;
1146        }
1147
1148        /* handle single device errors */
1149        if (cereg) {
1150                /*
1151                 * clear the command error, also clears queue to the device
1152                 * in error, and we can (re)issue commands to this device.
1153                 * When a device is in error all commands queued into the
1154                 * host controller and at the device are considered aborted
1155                 * and the queue for that device is stopped. Now, after
1156                 * clearing the device error, we can issue commands to the
1157                 * device to interrogate it to find the source of the error.
1158                 */
1159                abort = 1;
1160
1161                DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1162                        ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1163
1164                /* find out the offending link and qc */
1165                if (ap->nr_pmp_links) {
1166                        unsigned int dev_num;
1167
1168                        dereg = ioread32(hcr_base + DE);
1169                        iowrite32(dereg, hcr_base + DE);
1170                        iowrite32(cereg, hcr_base + CE);
1171
1172                        dev_num = ffs(dereg) - 1;
1173                        if (dev_num < ap->nr_pmp_links && dereg != 0) {
1174                                link = &ap->pmp_link[dev_num];
1175                                ehi = &link->eh_info;
1176                                qc = ata_qc_from_tag(ap, link->active_tag);
1177                                /*
1178                                 * We should consider this as non fatal error,
1179                                 * and TF must be updated as done below.
1180                                 */
1181
1182                                err_mask |= AC_ERR_DEV;
1183
1184                        } else {
1185                                err_mask |= AC_ERR_HSM;
1186                                action |= ATA_EH_HARDRESET;
1187                                freeze = 1;
1188                        }
1189                } else {
1190                        dereg = ioread32(hcr_base + DE);
1191                        iowrite32(dereg, hcr_base + DE);
1192                        iowrite32(cereg, hcr_base + CE);
1193
1194                        qc = ata_qc_from_tag(ap, link->active_tag);
1195                        /*
1196                         * We should consider this as non fatal error,
1197                         * and TF must be updated as done below.
1198                        */
1199                        err_mask |= AC_ERR_DEV;
1200                }
1201        }
1202
1203        /* record error info */
1204        if (qc)
1205                qc->err_mask |= err_mask;
1206        else
1207                ehi->err_mask |= err_mask;
1208
1209        ehi->action |= action;
1210
1211        /* freeze or abort */
1212        if (freeze)
1213                ata_port_freeze(ap);
1214        else if (abort) {
1215                if (qc)
1216                        ata_link_abort(qc->dev->link);
1217                else
1218                        ata_port_abort(ap);
1219        }
1220}
1221
1222static void sata_fsl_host_intr(struct ata_port *ap)
1223{
1224        struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1225        void __iomem *hcr_base = host_priv->hcr_base;
1226        u32 hstatus, done_mask = 0;
1227        struct ata_queued_cmd *qc;
1228        u32 SError;
1229        u32 tag;
1230        u32 status_mask = INT_ON_ERROR;
1231
1232        hstatus = ioread32(hcr_base + HSTATUS);
1233
1234        sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1235
1236        /* Read command completed register */
1237        done_mask = ioread32(hcr_base + CC);
1238
1239        /* Workaround for data length mismatch errata */
1240        if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) {
1241                for (tag = 0; tag < ATA_MAX_QUEUE; tag++) {
1242                        qc = ata_qc_from_tag(ap, tag);
1243                        if (qc && ata_is_atapi(qc->tf.protocol)) {
1244                                u32 hcontrol;
1245                                /* Set HControl[27] to clear error registers */
1246                                hcontrol = ioread32(hcr_base + HCONTROL);
1247                                iowrite32(hcontrol | CLEAR_ERROR,
1248                                                hcr_base + HCONTROL);
1249
1250                                /* Clear HControl[27] */
1251                                iowrite32(hcontrol & ~CLEAR_ERROR,
1252                                                hcr_base + HCONTROL);
1253
1254                                /* Clear SError[E] bit */
1255                                sata_fsl_scr_write(&ap->link, SCR_ERROR,
1256                                                SError);
1257
1258                                /* Ignore fatal error and device error */
1259                                status_mask &= ~(INT_ON_SINGL_DEVICE_ERR
1260                                                | INT_ON_FATAL_ERR);
1261                                break;
1262                        }
1263                }
1264        }
1265
1266        if (unlikely(SError & 0xFFFF0000)) {
1267                DPRINTK("serror @host_intr : 0x%x\n", SError);
1268                sata_fsl_error_intr(ap);
1269        }
1270
1271        if (unlikely(hstatus & status_mask)) {
1272                DPRINTK("error interrupt!!\n");
1273                sata_fsl_error_intr(ap);
1274                return;
1275        }
1276
1277        VPRINTK("Status of all queues :\n");
1278        VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
1279                done_mask,
1280                ioread32(hcr_base + CA),
1281                ioread32(hcr_base + CE),
1282                ioread32(hcr_base + CQ),
1283                ap->qc_active);
1284
1285        if (done_mask & ap->qc_active) {
1286                int i;
1287                /* clear CC bit, this will also complete the interrupt */
1288                iowrite32(done_mask, hcr_base + CC);
1289
1290                DPRINTK("Status of all queues :\n");
1291                DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1292                        done_mask, ioread32(hcr_base + CA),
1293                        ioread32(hcr_base + CE));
1294
1295                for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1296                        if (done_mask & (1 << i))
1297                                DPRINTK
1298                                    ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1299                                     i, ioread32(hcr_base + CC),
1300                                     ioread32(hcr_base + CA));
1301                }
1302                ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
1303                return;
1304
1305        } else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) {
1306                iowrite32(1, hcr_base + CC);
1307                qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
1308
1309                DPRINTK("completing non-ncq cmd, CC=0x%x\n",
1310                         ioread32(hcr_base + CC));
1311
1312                if (qc) {
1313                        ata_qc_complete(qc);
1314                }
1315        } else {
1316                /* Spurious Interrupt!! */
1317                DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1318                        ioread32(hcr_base + CC));
1319                iowrite32(done_mask, hcr_base + CC);
1320                return;
1321        }
1322}
1323
1324static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1325{
1326        struct ata_host *host = dev_instance;
1327        struct sata_fsl_host_priv *host_priv = host->private_data;
1328        void __iomem *hcr_base = host_priv->hcr_base;
1329        u32 interrupt_enables;
1330        unsigned handled = 0;
1331        struct ata_port *ap;
1332
1333        /* ack. any pending IRQs for this controller/port */
1334        interrupt_enables = ioread32(hcr_base + HSTATUS);
1335        interrupt_enables &= 0x3F;
1336
1337        DPRINTK("interrupt status 0x%x\n", interrupt_enables);
1338
1339        if (!interrupt_enables)
1340                return IRQ_NONE;
1341
1342        spin_lock(&host->lock);
1343
1344        /* Assuming one port per host controller */
1345
1346        ap = host->ports[0];
1347        if (ap) {
1348                sata_fsl_host_intr(ap);
1349        } else {
1350                dev_warn(host->dev, "interrupt on disabled port 0\n");
1351        }
1352
1353        iowrite32(interrupt_enables, hcr_base + HSTATUS);
1354        handled = 1;
1355
1356        spin_unlock(&host->lock);
1357
1358        return IRQ_RETVAL(handled);
1359}
1360
1361/*
1362 * Multiple ports are represented by multiple SATA controllers with
1363 * one port per controller
1364 */
1365static int sata_fsl_init_controller(struct ata_host *host)
1366{
1367        struct sata_fsl_host_priv *host_priv = host->private_data;
1368        void __iomem *hcr_base = host_priv->hcr_base;
1369        u32 temp;
1370
1371        /*
1372         * NOTE : We cannot bring the controller online before setting
1373         * the CHBA, hence main controller initialization is done as
1374         * part of the port_start() callback
1375         */
1376
1377        /* sata controller to operate in enterprise mode */
1378        temp = ioread32(hcr_base + HCONTROL);
1379        iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL);
1380
1381        /* ack. any pending IRQs for this controller/port */
1382        temp = ioread32(hcr_base + HSTATUS);
1383        if (temp & 0x3F)
1384                iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1385
1386        /* Keep interrupts disabled on the controller */
1387        temp = ioread32(hcr_base + HCONTROL);
1388        iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1389
1390        /* Disable interrupt coalescing control(icc), for the moment */
1391        DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1392        iowrite32(0x01000000, hcr_base + ICC);
1393
1394        /* clear error registers, SError is cleared by libATA  */
1395        iowrite32(0x00000FFFF, hcr_base + CE);
1396        iowrite32(0x00000FFFF, hcr_base + DE);
1397
1398        /*
1399         * reset the number of command complete bits which will cause the
1400         * interrupt to be signaled
1401         */
1402        fsl_sata_set_irq_coalescing(host, intr_coalescing_count,
1403                        intr_coalescing_ticks);
1404
1405        /*
1406         * host controller will be brought on-line, during xx_port_start()
1407         * callback, that should also initiate the OOB, COMINIT sequence
1408         */
1409
1410        DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1411        DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1412
1413        return 0;
1414}
1415
1416/*
1417 * scsi mid-layer and libata interface structures
1418 */
1419static struct scsi_host_template sata_fsl_sht = {
1420        ATA_NCQ_SHT("sata_fsl"),
1421        .can_queue = SATA_FSL_QUEUE_DEPTH,
1422        .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1423        .dma_boundary = ATA_DMA_BOUNDARY,
1424};
1425
1426static struct ata_port_operations sata_fsl_ops = {
1427        .inherits               = &sata_pmp_port_ops,
1428
1429        .qc_defer = ata_std_qc_defer,
1430        .qc_prep = sata_fsl_qc_prep,
1431        .qc_issue = sata_fsl_qc_issue,
1432        .qc_fill_rtf = sata_fsl_qc_fill_rtf,
1433
1434        .scr_read = sata_fsl_scr_read,
1435        .scr_write = sata_fsl_scr_write,
1436
1437        .freeze = sata_fsl_freeze,
1438        .thaw = sata_fsl_thaw,
1439        .softreset = sata_fsl_softreset,
1440        .hardreset = sata_fsl_hardreset,
1441        .pmp_softreset = sata_fsl_softreset,
1442        .error_handler = sata_fsl_error_handler,
1443        .post_internal_cmd = sata_fsl_post_internal_cmd,
1444
1445        .port_start = sata_fsl_port_start,
1446        .port_stop = sata_fsl_port_stop,
1447
1448        .pmp_attach = sata_fsl_pmp_attach,
1449        .pmp_detach = sata_fsl_pmp_detach,
1450};
1451
1452static const struct ata_port_info sata_fsl_port_info[] = {
1453        {
1454         .flags = SATA_FSL_HOST_FLAGS,
1455         .pio_mask = ATA_PIO4,
1456         .udma_mask = ATA_UDMA6,
1457         .port_ops = &sata_fsl_ops,
1458         },
1459};
1460
1461static int sata_fsl_probe(struct platform_device *ofdev)
1462{
1463        int retval = -ENXIO;
1464        void __iomem *hcr_base = NULL;
1465        void __iomem *ssr_base = NULL;
1466        void __iomem *csr_base = NULL;
1467        struct sata_fsl_host_priv *host_priv = NULL;
1468        int irq;
1469        struct ata_host *host = NULL;
1470        u32 temp;
1471
1472        struct ata_port_info pi = sata_fsl_port_info[0];
1473        const struct ata_port_info *ppi[] = { &pi, NULL };
1474
1475        dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n");
1476
1477        hcr_base = of_iomap(ofdev->dev.of_node, 0);
1478        if (!hcr_base)
1479                goto error_exit_with_cleanup;
1480
1481        ssr_base = hcr_base + 0x100;
1482        csr_base = hcr_base + 0x140;
1483
1484        if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) {
1485                temp = ioread32(csr_base + TRANSCFG);
1486                temp = temp & 0xffffffe0;
1487                iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG);
1488        }
1489
1490        DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
1491        DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
1492        DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
1493
1494        host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1495        if (!host_priv)
1496                goto error_exit_with_cleanup;
1497
1498        host_priv->hcr_base = hcr_base;
1499        host_priv->ssr_base = ssr_base;
1500        host_priv->csr_base = csr_base;
1501
1502        irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1503        if (irq < 0) {
1504                dev_err(&ofdev->dev, "invalid irq from platform\n");
1505                goto error_exit_with_cleanup;
1506        }
1507        host_priv->irq = irq;
1508
1509        if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2"))
1510                host_priv->data_snoop = DATA_SNOOP_ENABLE_V2;
1511        else
1512                host_priv->data_snoop = DATA_SNOOP_ENABLE_V1;
1513
1514        /* allocate host structure */
1515        host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1516        if (!host) {
1517                retval = -ENOMEM;
1518                goto error_exit_with_cleanup;
1519        }
1520
1521        /* host->iomap is not used currently */
1522        host->private_data = host_priv;
1523
1524        /* initialize host controller */
1525        sata_fsl_init_controller(host);
1526
1527        /*
1528         * Now, register with libATA core, this will also initiate the
1529         * device discovery process, invoking our port_start() handler &
1530         * error_handler() to execute a dummy Softreset EH session
1531         */
1532        ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1533                          &sata_fsl_sht);
1534
1535        dev_set_drvdata(&ofdev->dev, host);
1536
1537        host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show;
1538        host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store;
1539        sysfs_attr_init(&host_priv->intr_coalescing.attr);
1540        host_priv->intr_coalescing.attr.name = "intr_coalescing";
1541        host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR;
1542        retval = device_create_file(host->dev, &host_priv->intr_coalescing);
1543        if (retval)
1544                goto error_exit_with_cleanup;
1545
1546        host_priv->rx_watermark.show = fsl_sata_rx_watermark_show;
1547        host_priv->rx_watermark.store = fsl_sata_rx_watermark_store;
1548        sysfs_attr_init(&host_priv->rx_watermark.attr);
1549        host_priv->rx_watermark.attr.name = "rx_watermark";
1550        host_priv->rx_watermark.attr.mode = S_IRUGO | S_IWUSR;
1551        retval = device_create_file(host->dev, &host_priv->rx_watermark);
1552        if (retval) {
1553                device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1554                goto error_exit_with_cleanup;
1555        }
1556
1557        return 0;
1558
1559error_exit_with_cleanup:
1560
1561        if (host) {
1562                dev_set_drvdata(&ofdev->dev, NULL);
1563                ata_host_detach(host);
1564        }
1565
1566        if (hcr_base)
1567                iounmap(hcr_base);
1568        kfree(host_priv);
1569
1570        return retval;
1571}
1572
1573static int sata_fsl_remove(struct platform_device *ofdev)
1574{
1575        struct ata_host *host = dev_get_drvdata(&ofdev->dev);
1576        struct sata_fsl_host_priv *host_priv = host->private_data;
1577
1578        device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1579        device_remove_file(&ofdev->dev, &host_priv->rx_watermark);
1580
1581        ata_host_detach(host);
1582
1583        dev_set_drvdata(&ofdev->dev, NULL);
1584
1585        irq_dispose_mapping(host_priv->irq);
1586        iounmap(host_priv->hcr_base);
1587        kfree(host_priv);
1588
1589        return 0;
1590}
1591
1592#ifdef CONFIG_PM
1593static int sata_fsl_suspend(struct platform_device *op, pm_message_t state)
1594{
1595        struct ata_host *host = dev_get_drvdata(&op->dev);
1596        return ata_host_suspend(host, state);
1597}
1598
1599static int sata_fsl_resume(struct platform_device *op)
1600{
1601        struct ata_host *host = dev_get_drvdata(&op->dev);
1602        struct sata_fsl_host_priv *host_priv = host->private_data;
1603        int ret;
1604        void __iomem *hcr_base = host_priv->hcr_base;
1605        struct ata_port *ap = host->ports[0];
1606        struct sata_fsl_port_priv *pp = ap->private_data;
1607
1608        ret = sata_fsl_init_controller(host);
1609        if (ret) {
1610                dev_err(&op->dev, "Error initializing hardware\n");
1611                return ret;
1612        }
1613
1614        /* Recovery the CHBA register in host controller cmd register set */
1615        iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
1616
1617        iowrite32((ioread32(hcr_base + HCONTROL)
1618                                | HCONTROL_ONLINE_PHY_RST
1619                                | HCONTROL_SNOOP_ENABLE
1620                                | HCONTROL_PMP_ATTACHED),
1621                        hcr_base + HCONTROL);
1622
1623        ata_host_resume(host);
1624        return 0;
1625}
1626#endif
1627
1628static struct of_device_id fsl_sata_match[] = {
1629        {
1630                .compatible = "fsl,pq-sata",
1631        },
1632        {
1633                .compatible = "fsl,pq-sata-v2",
1634        },
1635        {},
1636};
1637
1638MODULE_DEVICE_TABLE(of, fsl_sata_match);
1639
1640static struct platform_driver fsl_sata_driver = {
1641        .driver = {
1642                .name = "fsl-sata",
1643                .owner = THIS_MODULE,
1644                .of_match_table = fsl_sata_match,
1645        },
1646        .probe          = sata_fsl_probe,
1647        .remove         = sata_fsl_remove,
1648#ifdef CONFIG_PM
1649        .suspend        = sata_fsl_suspend,
1650        .resume         = sata_fsl_resume,
1651#endif
1652};
1653
1654module_platform_driver(fsl_sata_driver);
1655
1656MODULE_LICENSE("GPL");
1657MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1658MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1659MODULE_VERSION("1.10");
1660
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