linux/drivers/ata/ata_piix.c
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   1/*
   2 *    ata_piix.c - Intel PATA/SATA controllers
   3 *
   4 *    Maintained by:  Tejun Heo <tj@kernel.org>
   5 *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6 *                  on emails.
   7 *
   8 *
   9 *      Copyright 2003-2005 Red Hat Inc
  10 *      Copyright 2003-2005 Jeff Garzik
  11 *
  12 *
  13 *      Copyright header from piix.c:
  14 *
  15 *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
  16 *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
  17 *  Copyright (C) 2003 Red Hat Inc
  18 *
  19 *
  20 *  This program is free software; you can redistribute it and/or modify
  21 *  it under the terms of the GNU General Public License as published by
  22 *  the Free Software Foundation; either version 2, or (at your option)
  23 *  any later version.
  24 *
  25 *  This program is distributed in the hope that it will be useful,
  26 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  27 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28 *  GNU General Public License for more details.
  29 *
  30 *  You should have received a copy of the GNU General Public License
  31 *  along with this program; see the file COPYING.  If not, write to
  32 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  33 *
  34 *
  35 *  libata documentation is available via 'make {ps|pdf}docs',
  36 *  as Documentation/DocBook/libata.*
  37 *
  38 *  Hardware documentation available at http://developer.intel.com/
  39 *
  40 * Documentation
  41 *      Publicly available from Intel web site. Errata documentation
  42 * is also publicly available. As an aide to anyone hacking on this
  43 * driver the list of errata that are relevant is below, going back to
  44 * PIIX4. Older device documentation is now a bit tricky to find.
  45 *
  46 * The chipsets all follow very much the same design. The original Triton
  47 * series chipsets do _not_ support independent device timings, but this
  48 * is fixed in Triton II. With the odd mobile exception the chips then
  49 * change little except in gaining more modes until SATA arrives. This
  50 * driver supports only the chips with independent timing (that is those
  51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
  52 * for the early chip drivers.
  53 *
  54 * Errata of note:
  55 *
  56 * Unfixable
  57 *      PIIX4    errata #9      - Only on ultra obscure hw
  58 *      ICH3     errata #13     - Not observed to affect real hw
  59 *                                by Intel
  60 *
  61 * Things we must deal with
  62 *      PIIX4   errata #10      - BM IDE hang with non UDMA
  63 *                                (must stop/start dma to recover)
  64 *      440MX   errata #15      - As PIIX4 errata #10
  65 *      PIIX4   errata #15      - Must not read control registers
  66 *                                during a PIO transfer
  67 *      440MX   errata #13      - As PIIX4 errata #15
  68 *      ICH2    errata #21      - DMA mode 0 doesn't work right
  69 *      ICH0/1  errata #55      - As ICH2 errata #21
  70 *      ICH2    spec c #9       - Extra operations needed to handle
  71 *                                drive hotswap [NOT YET SUPPORTED]
  72 *      ICH2    spec c #20      - IDE PRD must not cross a 64K boundary
  73 *                                and must be dword aligned
  74 *      ICH2    spec c #24      - UDMA mode 4,5 t85/86 should be 6ns not 3.3
  75 *      ICH7    errata #16      - MWDMA1 timings are incorrect
  76 *
  77 * Should have been BIOS fixed:
  78 *      450NX:  errata #19      - DMA hangs on old 450NX
  79 *      450NX:  errata #20      - DMA hangs on old 450NX
  80 *      450NX:  errata #25      - Corruption with DMA on old 450NX
  81 *      ICH3    errata #15      - IDE deadlock under high load
  82 *                                (BIOS must set dev 31 fn 0 bit 23)
  83 *      ICH3    errata #18      - Don't use native mode
  84 */
  85
  86#include <linux/kernel.h>
  87#include <linux/module.h>
  88#include <linux/pci.h>
  89#include <linux/init.h>
  90#include <linux/blkdev.h>
  91#include <linux/delay.h>
  92#include <linux/device.h>
  93#include <linux/gfp.h>
  94#include <scsi/scsi_host.h>
  95#include <linux/libata.h>
  96#include <linux/dmi.h>
  97
  98#define DRV_NAME        "ata_piix"
  99#define DRV_VERSION     "2.13"
 100
 101enum {
 102        PIIX_IOCFG              = 0x54, /* IDE I/O configuration register */
 103        ICH5_PMR                = 0x90, /* port mapping register */
 104        ICH5_PCS                = 0x92, /* port control and status */
 105        PIIX_SIDPR_BAR          = 5,
 106        PIIX_SIDPR_LEN          = 16,
 107        PIIX_SIDPR_IDX          = 0,
 108        PIIX_SIDPR_DATA         = 4,
 109
 110        PIIX_FLAG_CHECKINTR     = (1 << 28), /* make sure PCI INTx enabled */
 111        PIIX_FLAG_SIDPR         = (1 << 29), /* SATA idx/data pair regs */
 112
 113        PIIX_PATA_FLAGS         = ATA_FLAG_SLAVE_POSS,
 114        PIIX_SATA_FLAGS         = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
 115
 116        PIIX_FLAG_PIO16         = (1 << 30), /*support 16bit PIO only*/
 117
 118        PIIX_80C_PRI            = (1 << 5) | (1 << 4),
 119        PIIX_80C_SEC            = (1 << 7) | (1 << 6),
 120
 121        /* constants for mapping table */
 122        P0                      = 0,  /* port 0 */
 123        P1                      = 1,  /* port 1 */
 124        P2                      = 2,  /* port 2 */
 125        P3                      = 3,  /* port 3 */
 126        IDE                     = -1, /* IDE */
 127        NA                      = -2, /* not available */
 128        RV                      = -3, /* reserved */
 129
 130        PIIX_AHCI_DEVICE        = 6,
 131
 132        /* host->flags bits */
 133        PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
 134};
 135
 136enum piix_controller_ids {
 137        /* controller IDs */
 138        piix_pata_mwdma,        /* PIIX3 MWDMA only */
 139        piix_pata_33,           /* PIIX4 at 33Mhz */
 140        ich_pata_33,            /* ICH up to UDMA 33 only */
 141        ich_pata_66,            /* ICH up to 66 Mhz */
 142        ich_pata_100,           /* ICH up to UDMA 100 */
 143        ich_pata_100_nomwdma1,  /* ICH up to UDMA 100 but with no MWDMA1*/
 144        ich5_sata,
 145        ich6_sata,
 146        ich6m_sata,
 147        ich8_sata,
 148        ich8_2port_sata,
 149        ich8m_apple_sata,       /* locks up on second port enable */
 150        tolapai_sata,
 151        piix_pata_vmw,                  /* PIIX4 for VMware, spurious DMA_ERR */
 152        ich8_sata_snb,
 153        ich8_2port_sata_snb,
 154        ich8_2port_sata_byt,
 155};
 156
 157struct piix_map_db {
 158        const u32 mask;
 159        const u16 port_enable;
 160        const int map[][4];
 161};
 162
 163struct piix_host_priv {
 164        const int *map;
 165        u32 saved_iocfg;
 166        void __iomem *sidpr;
 167};
 168
 169static unsigned int in_module_init = 1;
 170
 171static const struct pci_device_id piix_pci_tbl[] = {
 172        /* Intel PIIX3 for the 430HX etc */
 173        { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
 174        /* VMware ICH4 */
 175        { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
 176        /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
 177        /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
 178        { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
 179        /* Intel PIIX4 */
 180        { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
 181        /* Intel PIIX4 */
 182        { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
 183        /* Intel PIIX */
 184        { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
 185        /* Intel ICH (i810, i815, i840) UDMA 66*/
 186        { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
 187        /* Intel ICH0 : UDMA 33*/
 188        { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
 189        /* Intel ICH2M */
 190        { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 191        /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
 192        { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 193        /*  Intel ICH3M */
 194        { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 195        /* Intel ICH3 (E7500/1) UDMA 100 */
 196        { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 197        /* Intel ICH4-L */
 198        { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 199        /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
 200        { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 201        { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 202        /* Intel ICH5 */
 203        { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 204        /* C-ICH (i810E2) */
 205        { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 206        /* ESB (855GME/875P + 6300ESB) UDMA 100  */
 207        { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 208        /* ICH6 (and 6) (i915) UDMA 100 */
 209        { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 210        /* ICH7/7-R (i945, i975) UDMA 100*/
 211        { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
 212        { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
 213        /* ICH8 Mobile PATA Controller */
 214        { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
 215
 216        /* SATA ports */
 217
 218        /* 82801EB (ICH5) */
 219        { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
 220        /* 82801EB (ICH5) */
 221        { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
 222        /* 6300ESB (ICH5 variant with broken PCS present bits) */
 223        { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
 224        /* 6300ESB pretending RAID */
 225        { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
 226        /* 82801FB/FW (ICH6/ICH6W) */
 227        { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
 228        /* 82801FR/FRW (ICH6R/ICH6RW) */
 229        { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
 230        /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
 231         * Attach iff the controller is in IDE mode. */
 232        { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
 233          PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
 234        /* 82801GB/GR/GH (ICH7, identical to ICH6) */
 235        { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
 236        /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
 237        { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
 238        /* Enterprise Southbridge 2 (631xESB/632xESB) */
 239        { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
 240        /* SATA Controller 1 IDE (ICH8) */
 241        { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 242        /* SATA Controller 2 IDE (ICH8) */
 243        { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 244        /* Mobile SATA Controller IDE (ICH8M), Apple */
 245        { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
 246        { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
 247        { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
 248        /* Mobile SATA Controller IDE (ICH8M) */
 249        { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 250        /* SATA Controller IDE (ICH9) */
 251        { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 252        /* SATA Controller IDE (ICH9) */
 253        { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 254        /* SATA Controller IDE (ICH9) */
 255        { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 256        /* SATA Controller IDE (ICH9M) */
 257        { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 258        /* SATA Controller IDE (ICH9M) */
 259        { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 260        /* SATA Controller IDE (ICH9M) */
 261        { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 262        /* SATA Controller IDE (Tolapai) */
 263        { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
 264        /* SATA Controller IDE (ICH10) */
 265        { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 266        /* SATA Controller IDE (ICH10) */
 267        { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 268        /* SATA Controller IDE (ICH10) */
 269        { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 270        /* SATA Controller IDE (ICH10) */
 271        { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 272        /* SATA Controller IDE (PCH) */
 273        { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 274        /* SATA Controller IDE (PCH) */
 275        { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 276        /* SATA Controller IDE (PCH) */
 277        { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 278        /* SATA Controller IDE (PCH) */
 279        { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 280        /* SATA Controller IDE (PCH) */
 281        { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 282        /* SATA Controller IDE (PCH) */
 283        { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
 284        /* SATA Controller IDE (CPT) */
 285        { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 286        /* SATA Controller IDE (CPT) */
 287        { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 288        /* SATA Controller IDE (CPT) */
 289        { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 290        /* SATA Controller IDE (CPT) */
 291        { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 292        /* SATA Controller IDE (PBG) */
 293        { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 294        /* SATA Controller IDE (PBG) */
 295        { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 296        /* SATA Controller IDE (Panther Point) */
 297        { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 298        /* SATA Controller IDE (Panther Point) */
 299        { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 300        /* SATA Controller IDE (Panther Point) */
 301        { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 302        /* SATA Controller IDE (Panther Point) */
 303        { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 304        /* SATA Controller IDE (Lynx Point) */
 305        { 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 306        /* SATA Controller IDE (Lynx Point) */
 307        { 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 308        /* SATA Controller IDE (Lynx Point) */
 309        { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
 310        /* SATA Controller IDE (Lynx Point) */
 311        { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 312        /* SATA Controller IDE (Lynx Point-LP) */
 313        { 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 314        /* SATA Controller IDE (Lynx Point-LP) */
 315        { 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 316        /* SATA Controller IDE (Lynx Point-LP) */
 317        { 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 318        /* SATA Controller IDE (Lynx Point-LP) */
 319        { 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 320        /* SATA Controller IDE (DH89xxCC) */
 321        { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 322        /* SATA Controller IDE (Avoton) */
 323        { 0x8086, 0x1f20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 324        /* SATA Controller IDE (Avoton) */
 325        { 0x8086, 0x1f21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 326        /* SATA Controller IDE (Avoton) */
 327        { 0x8086, 0x1f30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 328        /* SATA Controller IDE (Avoton) */
 329        { 0x8086, 0x1f31, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 330        /* SATA Controller IDE (Wellsburg) */
 331        { 0x8086, 0x8d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 332        /* SATA Controller IDE (Wellsburg) */
 333        { 0x8086, 0x8d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 334        /* SATA Controller IDE (Wellsburg) */
 335        { 0x8086, 0x8d60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
 336        /* SATA Controller IDE (Wellsburg) */
 337        { 0x8086, 0x8d68, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
 338        /* SATA Controller IDE (BayTrail) */
 339        { 0x8086, 0x0F20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
 340        { 0x8086, 0x0F21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
 341
 342        { }     /* terminate list */
 343};
 344
 345static const struct piix_map_db ich5_map_db = {
 346        .mask = 0x7,
 347        .port_enable = 0x3,
 348        .map = {
 349                /* PM   PS   SM   SS       MAP  */
 350                {  P0,  NA,  P1,  NA }, /* 000b */
 351                {  P1,  NA,  P0,  NA }, /* 001b */
 352                {  RV,  RV,  RV,  RV },
 353                {  RV,  RV,  RV,  RV },
 354                {  P0,  P1, IDE, IDE }, /* 100b */
 355                {  P1,  P0, IDE, IDE }, /* 101b */
 356                { IDE, IDE,  P0,  P1 }, /* 110b */
 357                { IDE, IDE,  P1,  P0 }, /* 111b */
 358        },
 359};
 360
 361static const struct piix_map_db ich6_map_db = {
 362        .mask = 0x3,
 363        .port_enable = 0xf,
 364        .map = {
 365                /* PM   PS   SM   SS       MAP */
 366                {  P0,  P2,  P1,  P3 }, /* 00b */
 367                { IDE, IDE,  P1,  P3 }, /* 01b */
 368                {  P0,  P2, IDE, IDE }, /* 10b */
 369                {  RV,  RV,  RV,  RV },
 370        },
 371};
 372
 373static const struct piix_map_db ich6m_map_db = {
 374        .mask = 0x3,
 375        .port_enable = 0x5,
 376
 377        /* Map 01b isn't specified in the doc but some notebooks use
 378         * it anyway.  MAP 01b have been spotted on both ICH6M and
 379         * ICH7M.
 380         */
 381        .map = {
 382                /* PM   PS   SM   SS       MAP */
 383                {  P0,  P2,  NA,  NA }, /* 00b */
 384                { IDE, IDE,  P1,  P3 }, /* 01b */
 385                {  P0,  P2, IDE, IDE }, /* 10b */
 386                {  RV,  RV,  RV,  RV },
 387        },
 388};
 389
 390static const struct piix_map_db ich8_map_db = {
 391        .mask = 0x3,
 392        .port_enable = 0xf,
 393        .map = {
 394                /* PM   PS   SM   SS       MAP */
 395                {  P0,  P2,  P1,  P3 }, /* 00b (hardwired when in AHCI) */
 396                {  RV,  RV,  RV,  RV },
 397                {  P0,  P2, IDE, IDE }, /* 10b (IDE mode) */
 398                {  RV,  RV,  RV,  RV },
 399        },
 400};
 401
 402static const struct piix_map_db ich8_2port_map_db = {
 403        .mask = 0x3,
 404        .port_enable = 0x3,
 405        .map = {
 406                /* PM   PS   SM   SS       MAP */
 407                {  P0,  NA,  P1,  NA }, /* 00b */
 408                {  RV,  RV,  RV,  RV }, /* 01b */
 409                {  RV,  RV,  RV,  RV }, /* 10b */
 410                {  RV,  RV,  RV,  RV },
 411        },
 412};
 413
 414static const struct piix_map_db ich8m_apple_map_db = {
 415        .mask = 0x3,
 416        .port_enable = 0x1,
 417        .map = {
 418                /* PM   PS   SM   SS       MAP */
 419                {  P0,  NA,  NA,  NA }, /* 00b */
 420                {  RV,  RV,  RV,  RV },
 421                {  P0,  P2, IDE, IDE }, /* 10b */
 422                {  RV,  RV,  RV,  RV },
 423        },
 424};
 425
 426static const struct piix_map_db tolapai_map_db = {
 427        .mask = 0x3,
 428        .port_enable = 0x3,
 429        .map = {
 430                /* PM   PS   SM   SS       MAP */
 431                {  P0,  NA,  P1,  NA }, /* 00b */
 432                {  RV,  RV,  RV,  RV }, /* 01b */
 433                {  RV,  RV,  RV,  RV }, /* 10b */
 434                {  RV,  RV,  RV,  RV },
 435        },
 436};
 437
 438static const struct piix_map_db *piix_map_db_table[] = {
 439        [ich5_sata]             = &ich5_map_db,
 440        [ich6_sata]             = &ich6_map_db,
 441        [ich6m_sata]            = &ich6m_map_db,
 442        [ich8_sata]             = &ich8_map_db,
 443        [ich8_2port_sata]       = &ich8_2port_map_db,
 444        [ich8m_apple_sata]      = &ich8m_apple_map_db,
 445        [tolapai_sata]          = &tolapai_map_db,
 446        [ich8_sata_snb]         = &ich8_map_db,
 447        [ich8_2port_sata_snb]   = &ich8_2port_map_db,
 448        [ich8_2port_sata_byt]   = &ich8_2port_map_db,
 449};
 450
 451static struct pci_bits piix_enable_bits[] = {
 452        { 0x41U, 1U, 0x80UL, 0x80UL },  /* port 0 */
 453        { 0x43U, 1U, 0x80UL, 0x80UL },  /* port 1 */
 454};
 455
 456MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
 457MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
 458MODULE_LICENSE("GPL");
 459MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
 460MODULE_VERSION(DRV_VERSION);
 461
 462struct ich_laptop {
 463        u16 device;
 464        u16 subvendor;
 465        u16 subdevice;
 466};
 467
 468/*
 469 *      List of laptops that use short cables rather than 80 wire
 470 */
 471
 472static const struct ich_laptop ich_laptop[] = {
 473        /* devid, subvendor, subdev */
 474        { 0x27DF, 0x0005, 0x0280 },     /* ICH7 on Acer 5602WLMi */
 475        { 0x27DF, 0x1025, 0x0102 },     /* ICH7 on Acer 5602aWLMi */
 476        { 0x27DF, 0x1025, 0x0110 },     /* ICH7 on Acer 3682WLMi */
 477        { 0x27DF, 0x1028, 0x02b0 },     /* ICH7 on unknown Dell */
 478        { 0x27DF, 0x1043, 0x1267 },     /* ICH7 on Asus W5F */
 479        { 0x27DF, 0x103C, 0x30A1 },     /* ICH7 on HP Compaq nc2400 */
 480        { 0x27DF, 0x103C, 0x361a },     /* ICH7 on unknown HP  */
 481        { 0x27DF, 0x1071, 0xD221 },     /* ICH7 on Hercules EC-900 */
 482        { 0x27DF, 0x152D, 0x0778 },     /* ICH7 on unknown Intel */
 483        { 0x24CA, 0x1025, 0x0061 },     /* ICH4 on ACER Aspire 2023WLMi */
 484        { 0x24CA, 0x1025, 0x003d },     /* ICH4 on ACER TM290 */
 485        { 0x266F, 0x1025, 0x0066 },     /* ICH6 on ACER Aspire 1694WLMi */
 486        { 0x2653, 0x1043, 0x82D8 },     /* ICH6M on Asus Eee 701 */
 487        { 0x27df, 0x104d, 0x900e },     /* ICH7 on Sony TZ-90 */
 488        /* end marker */
 489        { 0, }
 490};
 491
 492static int piix_port_start(struct ata_port *ap)
 493{
 494        if (!(ap->flags & PIIX_FLAG_PIO16))
 495                ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
 496
 497        return ata_bmdma_port_start(ap);
 498}
 499
 500/**
 501 *      ich_pata_cable_detect - Probe host controller cable detect info
 502 *      @ap: Port for which cable detect info is desired
 503 *
 504 *      Read 80c cable indicator from ATA PCI device's PCI config
 505 *      register.  This register is normally set by firmware (BIOS).
 506 *
 507 *      LOCKING:
 508 *      None (inherited from caller).
 509 */
 510
 511static int ich_pata_cable_detect(struct ata_port *ap)
 512{
 513        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 514        struct piix_host_priv *hpriv = ap->host->private_data;
 515        const struct ich_laptop *lap = &ich_laptop[0];
 516        u8 mask;
 517
 518        /* Check for specials - Acer Aspire 5602WLMi */
 519        while (lap->device) {
 520                if (lap->device == pdev->device &&
 521                    lap->subvendor == pdev->subsystem_vendor &&
 522                    lap->subdevice == pdev->subsystem_device)
 523                        return ATA_CBL_PATA40_SHORT;
 524
 525                lap++;
 526        }
 527
 528        /* check BIOS cable detect results */
 529        mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
 530        if ((hpriv->saved_iocfg & mask) == 0)
 531                return ATA_CBL_PATA40;
 532        return ATA_CBL_PATA80;
 533}
 534
 535/**
 536 *      piix_pata_prereset - prereset for PATA host controller
 537 *      @link: Target link
 538 *      @deadline: deadline jiffies for the operation
 539 *
 540 *      LOCKING:
 541 *      None (inherited from caller).
 542 */
 543static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
 544{
 545        struct ata_port *ap = link->ap;
 546        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 547
 548        if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
 549                return -ENOENT;
 550        return ata_sff_prereset(link, deadline);
 551}
 552
 553static DEFINE_SPINLOCK(piix_lock);
 554
 555static void piix_set_timings(struct ata_port *ap, struct ata_device *adev,
 556                             u8 pio)
 557{
 558        struct pci_dev *dev     = to_pci_dev(ap->host->dev);
 559        unsigned long flags;
 560        unsigned int is_slave   = (adev->devno != 0);
 561        unsigned int master_port= ap->port_no ? 0x42 : 0x40;
 562        unsigned int slave_port = 0x44;
 563        u16 master_data;
 564        u8 slave_data;
 565        u8 udma_enable;
 566        int control = 0;
 567
 568        /*
 569         *      See Intel Document 298600-004 for the timing programing rules
 570         *      for ICH controllers.
 571         */
 572
 573        static const     /* ISP  RTC */
 574        u8 timings[][2] = { { 0, 0 },
 575                            { 0, 0 },
 576                            { 1, 0 },
 577                            { 2, 1 },
 578                            { 2, 3 }, };
 579
 580        if (pio >= 2)
 581                control |= 1;   /* TIME1 enable */
 582        if (ata_pio_need_iordy(adev))
 583                control |= 2;   /* IE enable */
 584        /* Intel specifies that the PPE functionality is for disk only */
 585        if (adev->class == ATA_DEV_ATA)
 586                control |= 4;   /* PPE enable */
 587        /*
 588         * If the drive MWDMA is faster than it can do PIO then
 589         * we must force PIO into PIO0
 590         */
 591        if (adev->pio_mode < XFER_PIO_0 + pio)
 592                /* Enable DMA timing only */
 593                control |= 8;   /* PIO cycles in PIO0 */
 594
 595        spin_lock_irqsave(&piix_lock, flags);
 596
 597        /* PIO configuration clears DTE unconditionally.  It will be
 598         * programmed in set_dmamode which is guaranteed to be called
 599         * after set_piomode if any DMA mode is available.
 600         */
 601        pci_read_config_word(dev, master_port, &master_data);
 602        if (is_slave) {
 603                /* clear TIME1|IE1|PPE1|DTE1 */
 604                master_data &= 0xff0f;
 605                /* enable PPE1, IE1 and TIME1 as needed */
 606                master_data |= (control << 4);
 607                pci_read_config_byte(dev, slave_port, &slave_data);
 608                slave_data &= (ap->port_no ? 0x0f : 0xf0);
 609                /* Load the timing nibble for this slave */
 610                slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
 611                                                << (ap->port_no ? 4 : 0);
 612        } else {
 613                /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
 614                master_data &= 0xccf0;
 615                /* Enable PPE, IE and TIME as appropriate */
 616                master_data |= control;
 617                /* load ISP and RCT */
 618                master_data |=
 619                        (timings[pio][0] << 12) |
 620                        (timings[pio][1] << 8);
 621        }
 622
 623        /* Enable SITRE (separate slave timing register) */
 624        master_data |= 0x4000;
 625        pci_write_config_word(dev, master_port, master_data);
 626        if (is_slave)
 627                pci_write_config_byte(dev, slave_port, slave_data);
 628
 629        /* Ensure the UDMA bit is off - it will be turned back on if
 630           UDMA is selected */
 631
 632        if (ap->udma_mask) {
 633                pci_read_config_byte(dev, 0x48, &udma_enable);
 634                udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
 635                pci_write_config_byte(dev, 0x48, udma_enable);
 636        }
 637
 638        spin_unlock_irqrestore(&piix_lock, flags);
 639}
 640
 641/**
 642 *      piix_set_piomode - Initialize host controller PATA PIO timings
 643 *      @ap: Port whose timings we are configuring
 644 *      @adev: Drive in question
 645 *
 646 *      Set PIO mode for device, in host controller PCI config space.
 647 *
 648 *      LOCKING:
 649 *      None (inherited from caller).
 650 */
 651
 652static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
 653{
 654        piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
 655}
 656
 657/**
 658 *      do_pata_set_dmamode - Initialize host controller PATA PIO timings
 659 *      @ap: Port whose timings we are configuring
 660 *      @adev: Drive in question
 661 *      @isich: set if the chip is an ICH device
 662 *
 663 *      Set UDMA mode for device, in host controller PCI config space.
 664 *
 665 *      LOCKING:
 666 *      None (inherited from caller).
 667 */
 668
 669static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
 670{
 671        struct pci_dev *dev     = to_pci_dev(ap->host->dev);
 672        unsigned long flags;
 673        u8 speed                = adev->dma_mode;
 674        int devid               = adev->devno + 2 * ap->port_no;
 675        u8 udma_enable          = 0;
 676
 677        if (speed >= XFER_UDMA_0) {
 678                unsigned int udma = speed - XFER_UDMA_0;
 679                u16 udma_timing;
 680                u16 ideconf;
 681                int u_clock, u_speed;
 682
 683                spin_lock_irqsave(&piix_lock, flags);
 684
 685                pci_read_config_byte(dev, 0x48, &udma_enable);
 686
 687                /*
 688                 * UDMA is handled by a combination of clock switching and
 689                 * selection of dividers
 690                 *
 691                 * Handy rule: Odd modes are UDMATIMx 01, even are 02
 692                 *             except UDMA0 which is 00
 693                 */
 694                u_speed = min(2 - (udma & 1), udma);
 695                if (udma == 5)
 696                        u_clock = 0x1000;       /* 100Mhz */
 697                else if (udma > 2)
 698                        u_clock = 1;            /* 66Mhz */
 699                else
 700                        u_clock = 0;            /* 33Mhz */
 701
 702                udma_enable |= (1 << devid);
 703
 704                /* Load the CT/RP selection */
 705                pci_read_config_word(dev, 0x4A, &udma_timing);
 706                udma_timing &= ~(3 << (4 * devid));
 707                udma_timing |= u_speed << (4 * devid);
 708                pci_write_config_word(dev, 0x4A, udma_timing);
 709
 710                if (isich) {
 711                        /* Select a 33/66/100Mhz clock */
 712                        pci_read_config_word(dev, 0x54, &ideconf);
 713                        ideconf &= ~(0x1001 << devid);
 714                        ideconf |= u_clock << devid;
 715                        /* For ICH or later we should set bit 10 for better
 716                           performance (WR_PingPong_En) */
 717                        pci_write_config_word(dev, 0x54, ideconf);
 718                }
 719
 720                pci_write_config_byte(dev, 0x48, udma_enable);
 721
 722                spin_unlock_irqrestore(&piix_lock, flags);
 723        } else {
 724                /* MWDMA is driven by the PIO timings. */
 725                unsigned int mwdma = speed - XFER_MW_DMA_0;
 726                const unsigned int needed_pio[3] = {
 727                        XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
 728                };
 729                int pio = needed_pio[mwdma] - XFER_PIO_0;
 730
 731                /* XFER_PIO_0 is never used currently */
 732                piix_set_timings(ap, adev, pio);
 733        }
 734}
 735
 736/**
 737 *      piix_set_dmamode - Initialize host controller PATA DMA timings
 738 *      @ap: Port whose timings we are configuring
 739 *      @adev: um
 740 *
 741 *      Set MW/UDMA mode for device, in host controller PCI config space.
 742 *
 743 *      LOCKING:
 744 *      None (inherited from caller).
 745 */
 746
 747static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 748{
 749        do_pata_set_dmamode(ap, adev, 0);
 750}
 751
 752/**
 753 *      ich_set_dmamode - Initialize host controller PATA DMA timings
 754 *      @ap: Port whose timings we are configuring
 755 *      @adev: um
 756 *
 757 *      Set MW/UDMA mode for device, in host controller PCI config space.
 758 *
 759 *      LOCKING:
 760 *      None (inherited from caller).
 761 */
 762
 763static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 764{
 765        do_pata_set_dmamode(ap, adev, 1);
 766}
 767
 768/*
 769 * Serial ATA Index/Data Pair Superset Registers access
 770 *
 771 * Beginning from ICH8, there's a sane way to access SCRs using index
 772 * and data register pair located at BAR5 which means that we have
 773 * separate SCRs for master and slave.  This is handled using libata
 774 * slave_link facility.
 775 */
 776static const int piix_sidx_map[] = {
 777        [SCR_STATUS]    = 0,
 778        [SCR_ERROR]     = 2,
 779        [SCR_CONTROL]   = 1,
 780};
 781
 782static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
 783{
 784        struct ata_port *ap = link->ap;
 785        struct piix_host_priv *hpriv = ap->host->private_data;
 786
 787        iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
 788                  hpriv->sidpr + PIIX_SIDPR_IDX);
 789}
 790
 791static int piix_sidpr_scr_read(struct ata_link *link,
 792                               unsigned int reg, u32 *val)
 793{
 794        struct piix_host_priv *hpriv = link->ap->host->private_data;
 795
 796        if (reg >= ARRAY_SIZE(piix_sidx_map))
 797                return -EINVAL;
 798
 799        piix_sidpr_sel(link, reg);
 800        *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
 801        return 0;
 802}
 803
 804static int piix_sidpr_scr_write(struct ata_link *link,
 805                                unsigned int reg, u32 val)
 806{
 807        struct piix_host_priv *hpriv = link->ap->host->private_data;
 808
 809        if (reg >= ARRAY_SIZE(piix_sidx_map))
 810                return -EINVAL;
 811
 812        piix_sidpr_sel(link, reg);
 813        iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
 814        return 0;
 815}
 816
 817static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
 818                              unsigned hints)
 819{
 820        return sata_link_scr_lpm(link, policy, false);
 821}
 822
 823static bool piix_irq_check(struct ata_port *ap)
 824{
 825        if (unlikely(!ap->ioaddr.bmdma_addr))
 826                return false;
 827
 828        return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
 829}
 830
 831#ifdef CONFIG_PM
 832static int piix_broken_suspend(void)
 833{
 834        static const struct dmi_system_id sysids[] = {
 835                {
 836                        .ident = "TECRA M3",
 837                        .matches = {
 838                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 839                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
 840                        },
 841                },
 842                {
 843                        .ident = "TECRA M3",
 844                        .matches = {
 845                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 846                                DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
 847                        },
 848                },
 849                {
 850                        .ident = "TECRA M4",
 851                        .matches = {
 852                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 853                                DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
 854                        },
 855                },
 856                {
 857                        .ident = "TECRA M4",
 858                        .matches = {
 859                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 860                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
 861                        },
 862                },
 863                {
 864                        .ident = "TECRA M5",
 865                        .matches = {
 866                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 867                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
 868                        },
 869                },
 870                {
 871                        .ident = "TECRA M6",
 872                        .matches = {
 873                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 874                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
 875                        },
 876                },
 877                {
 878                        .ident = "TECRA M7",
 879                        .matches = {
 880                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 881                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
 882                        },
 883                },
 884                {
 885                        .ident = "TECRA A8",
 886                        .matches = {
 887                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 888                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
 889                        },
 890                },
 891                {
 892                        .ident = "Satellite R20",
 893                        .matches = {
 894                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 895                                DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
 896                        },
 897                },
 898                {
 899                        .ident = "Satellite R25",
 900                        .matches = {
 901                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 902                                DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
 903                        },
 904                },
 905                {
 906                        .ident = "Satellite U200",
 907                        .matches = {
 908                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 909                                DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
 910                        },
 911                },
 912                {
 913                        .ident = "Satellite U200",
 914                        .matches = {
 915                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 916                                DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
 917                        },
 918                },
 919                {
 920                        .ident = "Satellite Pro U200",
 921                        .matches = {
 922                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 923                                DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
 924                        },
 925                },
 926                {
 927                        .ident = "Satellite U205",
 928                        .matches = {
 929                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 930                                DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
 931                        },
 932                },
 933                {
 934                        .ident = "SATELLITE U205",
 935                        .matches = {
 936                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 937                                DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
 938                        },
 939                },
 940                {
 941                        .ident = "Satellite Pro A120",
 942                        .matches = {
 943                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 944                                DMI_MATCH(DMI_PRODUCT_NAME, "Satellite Pro A120"),
 945                        },
 946                },
 947                {
 948                        .ident = "Portege M500",
 949                        .matches = {
 950                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 951                                DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
 952                        },
 953                },
 954                {
 955                        .ident = "VGN-BX297XP",
 956                        .matches = {
 957                                DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
 958                                DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
 959                        },
 960                },
 961
 962                { }     /* terminate list */
 963        };
 964        static const char *oemstrs[] = {
 965                "Tecra M3,",
 966        };
 967        int i;
 968
 969        if (dmi_check_system(sysids))
 970                return 1;
 971
 972        for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
 973                if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
 974                        return 1;
 975
 976        /* TECRA M4 sometimes forgets its identify and reports bogus
 977         * DMI information.  As the bogus information is a bit
 978         * generic, match as many entries as possible.  This manual
 979         * matching is necessary because dmi_system_id.matches is
 980         * limited to four entries.
 981         */
 982        if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
 983            dmi_match(DMI_PRODUCT_NAME, "000000") &&
 984            dmi_match(DMI_PRODUCT_VERSION, "000000") &&
 985            dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
 986            dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
 987            dmi_match(DMI_BOARD_NAME, "Portable PC") &&
 988            dmi_match(DMI_BOARD_VERSION, "Version A0"))
 989                return 1;
 990
 991        return 0;
 992}
 993
 994static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
 995{
 996        struct ata_host *host = dev_get_drvdata(&pdev->dev);
 997        unsigned long flags;
 998        int rc = 0;
 999
1000        rc = ata_host_suspend(host, mesg);
1001        if (rc)
1002                return rc;
1003
1004        /* Some braindamaged ACPI suspend implementations expect the
1005         * controller to be awake on entry; otherwise, it burns cpu
1006         * cycles and power trying to do something to the sleeping
1007         * beauty.
1008         */
1009        if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1010                pci_save_state(pdev);
1011
1012                /* mark its power state as "unknown", since we don't
1013                 * know if e.g. the BIOS will change its device state
1014                 * when we suspend.
1015                 */
1016                if (pdev->current_state == PCI_D0)
1017                        pdev->current_state = PCI_UNKNOWN;
1018
1019                /* tell resume that it's waking up from broken suspend */
1020                spin_lock_irqsave(&host->lock, flags);
1021                host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1022                spin_unlock_irqrestore(&host->lock, flags);
1023        } else
1024                ata_pci_device_do_suspend(pdev, mesg);
1025
1026        return 0;
1027}
1028
1029static int piix_pci_device_resume(struct pci_dev *pdev)
1030{
1031        struct ata_host *host = dev_get_drvdata(&pdev->dev);
1032        unsigned long flags;
1033        int rc;
1034
1035        if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1036                spin_lock_irqsave(&host->lock, flags);
1037                host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1038                spin_unlock_irqrestore(&host->lock, flags);
1039
1040                pci_set_power_state(pdev, PCI_D0);
1041                pci_restore_state(pdev);
1042
1043                /* PCI device wasn't disabled during suspend.  Use
1044                 * pci_reenable_device() to avoid affecting the enable
1045                 * count.
1046                 */
1047                rc = pci_reenable_device(pdev);
1048                if (rc)
1049                        dev_err(&pdev->dev,
1050                                "failed to enable device after resume (%d)\n",
1051                                rc);
1052        } else
1053                rc = ata_pci_device_do_resume(pdev);
1054
1055        if (rc == 0)
1056                ata_host_resume(host);
1057
1058        return rc;
1059}
1060#endif
1061
1062static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1063{
1064        return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1065}
1066
1067static struct scsi_host_template piix_sht = {
1068        ATA_BMDMA_SHT(DRV_NAME),
1069};
1070
1071static struct ata_port_operations piix_sata_ops = {
1072        .inherits               = &ata_bmdma32_port_ops,
1073        .sff_irq_check          = piix_irq_check,
1074        .port_start             = piix_port_start,
1075};
1076
1077static struct ata_port_operations piix_pata_ops = {
1078        .inherits               = &piix_sata_ops,
1079        .cable_detect           = ata_cable_40wire,
1080        .set_piomode            = piix_set_piomode,
1081        .set_dmamode            = piix_set_dmamode,
1082        .prereset               = piix_pata_prereset,
1083};
1084
1085static struct ata_port_operations piix_vmw_ops = {
1086        .inherits               = &piix_pata_ops,
1087        .bmdma_status           = piix_vmw_bmdma_status,
1088};
1089
1090static struct ata_port_operations ich_pata_ops = {
1091        .inherits               = &piix_pata_ops,
1092        .cable_detect           = ich_pata_cable_detect,
1093        .set_dmamode            = ich_set_dmamode,
1094};
1095
1096static struct device_attribute *piix_sidpr_shost_attrs[] = {
1097        &dev_attr_link_power_management_policy,
1098        NULL
1099};
1100
1101static struct scsi_host_template piix_sidpr_sht = {
1102        ATA_BMDMA_SHT(DRV_NAME),
1103        .shost_attrs            = piix_sidpr_shost_attrs,
1104};
1105
1106static struct ata_port_operations piix_sidpr_sata_ops = {
1107        .inherits               = &piix_sata_ops,
1108        .hardreset              = sata_std_hardreset,
1109        .scr_read               = piix_sidpr_scr_read,
1110        .scr_write              = piix_sidpr_scr_write,
1111        .set_lpm                = piix_sidpr_set_lpm,
1112};
1113
1114static struct ata_port_info piix_port_info[] = {
1115        [piix_pata_mwdma] =     /* PIIX3 MWDMA only */
1116        {
1117                .flags          = PIIX_PATA_FLAGS,
1118                .pio_mask       = ATA_PIO4,
1119                .mwdma_mask     = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1120                .port_ops       = &piix_pata_ops,
1121        },
1122
1123        [piix_pata_33] =        /* PIIX4 at 33MHz */
1124        {
1125                .flags          = PIIX_PATA_FLAGS,
1126                .pio_mask       = ATA_PIO4,
1127                .mwdma_mask     = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1128                .udma_mask      = ATA_UDMA2,
1129                .port_ops       = &piix_pata_ops,
1130        },
1131
1132        [ich_pata_33] =         /* ICH0 - ICH at 33Mhz*/
1133        {
1134                .flags          = PIIX_PATA_FLAGS,
1135                .pio_mask       = ATA_PIO4,
1136                .mwdma_mask     = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok  */
1137                .udma_mask      = ATA_UDMA2,
1138                .port_ops       = &ich_pata_ops,
1139        },
1140
1141        [ich_pata_66] =         /* ICH controllers up to 66MHz */
1142        {
1143                .flags          = PIIX_PATA_FLAGS,
1144                .pio_mask       = ATA_PIO4,
1145                .mwdma_mask     = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
1146                .udma_mask      = ATA_UDMA4,
1147                .port_ops       = &ich_pata_ops,
1148        },
1149
1150        [ich_pata_100] =
1151        {
1152                .flags          = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1153                .pio_mask       = ATA_PIO4,
1154                .mwdma_mask     = ATA_MWDMA12_ONLY,
1155                .udma_mask      = ATA_UDMA5,
1156                .port_ops       = &ich_pata_ops,
1157        },
1158
1159        [ich_pata_100_nomwdma1] =
1160        {
1161                .flags          = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1162                .pio_mask       = ATA_PIO4,
1163                .mwdma_mask     = ATA_MWDMA2_ONLY,
1164                .udma_mask      = ATA_UDMA5,
1165                .port_ops       = &ich_pata_ops,
1166        },
1167
1168        [ich5_sata] =
1169        {
1170                .flags          = PIIX_SATA_FLAGS,
1171                .pio_mask       = ATA_PIO4,
1172                .mwdma_mask     = ATA_MWDMA2,
1173                .udma_mask      = ATA_UDMA6,
1174                .port_ops       = &piix_sata_ops,
1175        },
1176
1177        [ich6_sata] =
1178        {
1179                .flags          = PIIX_SATA_FLAGS,
1180                .pio_mask       = ATA_PIO4,
1181                .mwdma_mask     = ATA_MWDMA2,
1182                .udma_mask      = ATA_UDMA6,
1183                .port_ops       = &piix_sata_ops,
1184        },
1185
1186        [ich6m_sata] =
1187        {
1188                .flags          = PIIX_SATA_FLAGS,
1189                .pio_mask       = ATA_PIO4,
1190                .mwdma_mask     = ATA_MWDMA2,
1191                .udma_mask      = ATA_UDMA6,
1192                .port_ops       = &piix_sata_ops,
1193        },
1194
1195        [ich8_sata] =
1196        {
1197                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1198                .pio_mask       = ATA_PIO4,
1199                .mwdma_mask     = ATA_MWDMA2,
1200                .udma_mask      = ATA_UDMA6,
1201                .port_ops       = &piix_sata_ops,
1202        },
1203
1204        [ich8_2port_sata] =
1205        {
1206                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1207                .pio_mask       = ATA_PIO4,
1208                .mwdma_mask     = ATA_MWDMA2,
1209                .udma_mask      = ATA_UDMA6,
1210                .port_ops       = &piix_sata_ops,
1211        },
1212
1213        [tolapai_sata] =
1214        {
1215                .flags          = PIIX_SATA_FLAGS,
1216                .pio_mask       = ATA_PIO4,
1217                .mwdma_mask     = ATA_MWDMA2,
1218                .udma_mask      = ATA_UDMA6,
1219                .port_ops       = &piix_sata_ops,
1220        },
1221
1222        [ich8m_apple_sata] =
1223        {
1224                .flags          = PIIX_SATA_FLAGS,
1225                .pio_mask       = ATA_PIO4,
1226                .mwdma_mask     = ATA_MWDMA2,
1227                .udma_mask      = ATA_UDMA6,
1228                .port_ops       = &piix_sata_ops,
1229        },
1230
1231        [piix_pata_vmw] =
1232        {
1233                .flags          = PIIX_PATA_FLAGS,
1234                .pio_mask       = ATA_PIO4,
1235                .mwdma_mask     = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1236                .udma_mask      = ATA_UDMA2,
1237                .port_ops       = &piix_vmw_ops,
1238        },
1239
1240        /*
1241         * some Sandybridge chipsets have broken 32 mode up to now,
1242         * see https://bugzilla.kernel.org/show_bug.cgi?id=40592
1243         */
1244        [ich8_sata_snb] =
1245        {
1246                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
1247                .pio_mask       = ATA_PIO4,
1248                .mwdma_mask     = ATA_MWDMA2,
1249                .udma_mask      = ATA_UDMA6,
1250                .port_ops       = &piix_sata_ops,
1251        },
1252
1253        [ich8_2port_sata_snb] =
1254        {
1255                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR
1256                                        | PIIX_FLAG_PIO16,
1257                .pio_mask       = ATA_PIO4,
1258                .mwdma_mask     = ATA_MWDMA2,
1259                .udma_mask      = ATA_UDMA6,
1260                .port_ops       = &piix_sata_ops,
1261        },
1262
1263        [ich8_2port_sata_byt] =
1264        {
1265                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
1266                .pio_mask       = ATA_PIO4,
1267                .mwdma_mask     = ATA_MWDMA2,
1268                .udma_mask      = ATA_UDMA6,
1269                .port_ops       = &piix_sata_ops,
1270        },
1271
1272};
1273
1274#define AHCI_PCI_BAR 5
1275#define AHCI_GLOBAL_CTL 0x04
1276#define AHCI_ENABLE (1 << 31)
1277static int piix_disable_ahci(struct pci_dev *pdev)
1278{
1279        void __iomem *mmio;
1280        u32 tmp;
1281        int rc = 0;
1282
1283        /* BUG: pci_enable_device has not yet been called.  This
1284         * works because this device is usually set up by BIOS.
1285         */
1286
1287        if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1288            !pci_resource_len(pdev, AHCI_PCI_BAR))
1289                return 0;
1290
1291        mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1292        if (!mmio)
1293                return -ENOMEM;
1294
1295        tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1296        if (tmp & AHCI_ENABLE) {
1297                tmp &= ~AHCI_ENABLE;
1298                iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1299
1300                tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1301                if (tmp & AHCI_ENABLE)
1302                        rc = -EIO;
1303        }
1304
1305        pci_iounmap(pdev, mmio);
1306        return rc;
1307}
1308
1309/**
1310 *      piix_check_450nx_errata -       Check for problem 450NX setup
1311 *      @ata_dev: the PCI device to check
1312 *
1313 *      Check for the present of 450NX errata #19 and errata #25. If
1314 *      they are found return an error code so we can turn off DMA
1315 */
1316
1317static int piix_check_450nx_errata(struct pci_dev *ata_dev)
1318{
1319        struct pci_dev *pdev = NULL;
1320        u16 cfg;
1321        int no_piix_dma = 0;
1322
1323        while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1324                /* Look for 450NX PXB. Check for problem configurations
1325                   A PCI quirk checks bit 6 already */
1326                pci_read_config_word(pdev, 0x41, &cfg);
1327                /* Only on the original revision: IDE DMA can hang */
1328                if (pdev->revision == 0x00)
1329                        no_piix_dma = 1;
1330                /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1331                else if (cfg & (1<<14) && pdev->revision < 5)
1332                        no_piix_dma = 2;
1333        }
1334        if (no_piix_dma)
1335                dev_warn(&ata_dev->dev,
1336                         "450NX errata present, disabling IDE DMA%s\n",
1337                         no_piix_dma == 2 ? " - a BIOS update may resolve this"
1338                         : "");
1339
1340        return no_piix_dma;
1341}
1342
1343static void piix_init_pcs(struct ata_host *host,
1344                          const struct piix_map_db *map_db)
1345{
1346        struct pci_dev *pdev = to_pci_dev(host->dev);
1347        u16 pcs, new_pcs;
1348
1349        pci_read_config_word(pdev, ICH5_PCS, &pcs);
1350
1351        new_pcs = pcs | map_db->port_enable;
1352
1353        if (new_pcs != pcs) {
1354                DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1355                pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1356                msleep(150);
1357        }
1358}
1359
1360static const int *piix_init_sata_map(struct pci_dev *pdev,
1361                                     struct ata_port_info *pinfo,
1362                                     const struct piix_map_db *map_db)
1363{
1364        const int *map;
1365        int i, invalid_map = 0;
1366        u8 map_value;
1367
1368        pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1369
1370        map = map_db->map[map_value & map_db->mask];
1371
1372        dev_info(&pdev->dev, "MAP [");
1373        for (i = 0; i < 4; i++) {
1374                switch (map[i]) {
1375                case RV:
1376                        invalid_map = 1;
1377                        pr_cont(" XX");
1378                        break;
1379
1380                case NA:
1381                        pr_cont(" --");
1382                        break;
1383
1384                case IDE:
1385                        WARN_ON((i & 1) || map[i + 1] != IDE);
1386                        pinfo[i / 2] = piix_port_info[ich_pata_100];
1387                        i++;
1388                        pr_cont(" IDE IDE");
1389                        break;
1390
1391                default:
1392                        pr_cont(" P%d", map[i]);
1393                        if (i & 1)
1394                                pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1395                        break;
1396                }
1397        }
1398        pr_cont(" ]\n");
1399
1400        if (invalid_map)
1401                dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
1402
1403        return map;
1404}
1405
1406static bool piix_no_sidpr(struct ata_host *host)
1407{
1408        struct pci_dev *pdev = to_pci_dev(host->dev);
1409
1410        /*
1411         * Samsung DB-P70 only has three ATA ports exposed and
1412         * curiously the unconnected first port reports link online
1413         * while not responding to SRST protocol causing excessive
1414         * detection delay.
1415         *
1416         * Unfortunately, the system doesn't carry enough DMI
1417         * information to identify the machine but does have subsystem
1418         * vendor and device set.  As it's unclear whether the
1419         * subsystem vendor/device is used only for this specific
1420         * board, the port can't be disabled solely with the
1421         * information; however, turning off SIDPR access works around
1422         * the problem.  Turn it off.
1423         *
1424         * This problem is reported in bnc#441240.
1425         *
1426         * https://bugzilla.novell.com/show_bug.cgi?id=441420
1427         */
1428        if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1429            pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1430            pdev->subsystem_device == 0xb049) {
1431                dev_warn(host->dev,
1432                         "Samsung DB-P70 detected, disabling SIDPR\n");
1433                return true;
1434        }
1435
1436        return false;
1437}
1438
1439static int piix_init_sidpr(struct ata_host *host)
1440{
1441        struct pci_dev *pdev = to_pci_dev(host->dev);
1442        struct piix_host_priv *hpriv = host->private_data;
1443        struct ata_link *link0 = &host->ports[0]->link;
1444        u32 scontrol;
1445        int i, rc;
1446
1447        /* check for availability */
1448        for (i = 0; i < 4; i++)
1449                if (hpriv->map[i] == IDE)
1450                        return 0;
1451
1452        /* is it blacklisted? */
1453        if (piix_no_sidpr(host))
1454                return 0;
1455
1456        if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1457                return 0;
1458
1459        if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1460            pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1461                return 0;
1462
1463        if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1464                return 0;
1465
1466        hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1467
1468        /* SCR access via SIDPR doesn't work on some configurations.
1469         * Give it a test drive by inhibiting power save modes which
1470         * we'll do anyway.
1471         */
1472        piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1473
1474        /* if IPM is already 3, SCR access is probably working.  Don't
1475         * un-inhibit power save modes as BIOS might have inhibited
1476         * them for a reason.
1477         */
1478        if ((scontrol & 0xf00) != 0x300) {
1479                scontrol |= 0x300;
1480                piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1481                piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1482
1483                if ((scontrol & 0xf00) != 0x300) {
1484                        dev_info(host->dev,
1485                                 "SCR access via SIDPR is available but doesn't work\n");
1486                        return 0;
1487                }
1488        }
1489
1490        /* okay, SCRs available, set ops and ask libata for slave_link */
1491        for (i = 0; i < 2; i++) {
1492                struct ata_port *ap = host->ports[i];
1493
1494                ap->ops = &piix_sidpr_sata_ops;
1495
1496                if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1497                        rc = ata_slave_link_init(ap);
1498                        if (rc)
1499                                return rc;
1500                }
1501        }
1502
1503        return 0;
1504}
1505
1506static void piix_iocfg_bit18_quirk(struct ata_host *host)
1507{
1508        static const struct dmi_system_id sysids[] = {
1509                {
1510                        /* Clevo M570U sets IOCFG bit 18 if the cdrom
1511                         * isn't used to boot the system which
1512                         * disables the channel.
1513                         */
1514                        .ident = "M570U",
1515                        .matches = {
1516                                DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1517                                DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1518                        },
1519                },
1520
1521                { }     /* terminate list */
1522        };
1523        struct pci_dev *pdev = to_pci_dev(host->dev);
1524        struct piix_host_priv *hpriv = host->private_data;
1525
1526        if (!dmi_check_system(sysids))
1527                return;
1528
1529        /* The datasheet says that bit 18 is NOOP but certain systems
1530         * seem to use it to disable a channel.  Clear the bit on the
1531         * affected systems.
1532         */
1533        if (hpriv->saved_iocfg & (1 << 18)) {
1534                dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
1535                pci_write_config_dword(pdev, PIIX_IOCFG,
1536                                       hpriv->saved_iocfg & ~(1 << 18));
1537        }
1538}
1539
1540static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1541{
1542        static const struct dmi_system_id broken_systems[] = {
1543                {
1544                        .ident = "HP Compaq 2510p",
1545                        .matches = {
1546                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1547                                DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1548                        },
1549                        /* PCI slot number of the controller */
1550                        .driver_data = (void *)0x1FUL,
1551                },
1552                {
1553                        .ident = "HP Compaq nc6000",
1554                        .matches = {
1555                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1556                                DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1557                        },
1558                        /* PCI slot number of the controller */
1559                        .driver_data = (void *)0x1FUL,
1560                },
1561
1562                { }     /* terminate list */
1563        };
1564        const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1565
1566        if (dmi) {
1567                unsigned long slot = (unsigned long)dmi->driver_data;
1568                /* apply the quirk only to on-board controllers */
1569                return slot == PCI_SLOT(pdev->devfn);
1570        }
1571
1572        return false;
1573}
1574
1575static int prefer_ms_hyperv = 1;
1576module_param(prefer_ms_hyperv, int, 0);
1577MODULE_PARM_DESC(prefer_ms_hyperv,
1578        "Prefer Hyper-V paravirtualization drivers instead of ATA, "
1579        "0 - Use ATA drivers, "
1580        "1 (Default) - Use the paravirtualization drivers.");
1581
1582static void piix_ignore_devices_quirk(struct ata_host *host)
1583{
1584#if IS_ENABLED(CONFIG_HYPERV_STORAGE)
1585        static const struct dmi_system_id ignore_hyperv[] = {
1586                {
1587                        /* On Hyper-V hypervisors the disks are exposed on
1588                         * both the emulated SATA controller and on the
1589                         * paravirtualised drivers.  The CD/DVD devices
1590                         * are only exposed on the emulated controller.
1591                         * Request we ignore ATA devices on this host.
1592                         */
1593                        .ident = "Hyper-V Virtual Machine",
1594                        .matches = {
1595                                DMI_MATCH(DMI_SYS_VENDOR,
1596                                                "Microsoft Corporation"),
1597                                DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1598                        },
1599                },
1600                { }     /* terminate list */
1601        };
1602        static const struct dmi_system_id allow_virtual_pc[] = {
1603                {
1604                        /* In MS Virtual PC guests the DMI ident is nearly
1605                         * identical to a Hyper-V guest. One difference is the
1606                         * product version which is used here to identify
1607                         * a Virtual PC guest. This entry allows ata_piix to
1608                         * drive the emulated hardware.
1609                         */
1610                        .ident = "MS Virtual PC 2007",
1611                        .matches = {
1612                                DMI_MATCH(DMI_SYS_VENDOR,
1613                                                "Microsoft Corporation"),
1614                                DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1615                                DMI_MATCH(DMI_PRODUCT_VERSION, "VS2005R2"),
1616                        },
1617                },
1618                { }     /* terminate list */
1619        };
1620        const struct dmi_system_id *ignore = dmi_first_match(ignore_hyperv);
1621        const struct dmi_system_id *allow = dmi_first_match(allow_virtual_pc);
1622
1623        if (ignore && !allow && prefer_ms_hyperv) {
1624                host->flags |= ATA_HOST_IGNORE_ATA;
1625                dev_info(host->dev, "%s detected, ATA device ignore set\n",
1626                        ignore->ident);
1627        }
1628#endif
1629}
1630
1631/**
1632 *      piix_init_one - Register PIIX ATA PCI device with kernel services
1633 *      @pdev: PCI device to register
1634 *      @ent: Entry in piix_pci_tbl matching with @pdev
1635 *
1636 *      Called from kernel PCI layer.  We probe for combined mode (sigh),
1637 *      and then hand over control to libata, for it to do the rest.
1638 *
1639 *      LOCKING:
1640 *      Inherited from PCI layer (may sleep).
1641 *
1642 *      RETURNS:
1643 *      Zero on success, or -ERRNO value.
1644 */
1645
1646static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1647{
1648        struct device *dev = &pdev->dev;
1649        struct ata_port_info port_info[2];
1650        const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1651        struct scsi_host_template *sht = &piix_sht;
1652        unsigned long port_flags;
1653        struct ata_host *host;
1654        struct piix_host_priv *hpriv;
1655        int rc;
1656
1657        ata_print_version_once(&pdev->dev, DRV_VERSION);
1658
1659        /* no hotplugging support for later devices (FIXME) */
1660        if (!in_module_init && ent->driver_data >= ich5_sata)
1661                return -ENODEV;
1662
1663        if (piix_broken_system_poweroff(pdev)) {
1664                piix_port_info[ent->driver_data].flags |=
1665                                ATA_FLAG_NO_POWEROFF_SPINDOWN |
1666                                        ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1667                dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1668                                "on poweroff and hibernation\n");
1669        }
1670
1671        port_info[0] = piix_port_info[ent->driver_data];
1672        port_info[1] = piix_port_info[ent->driver_data];
1673
1674        port_flags = port_info[0].flags;
1675
1676        /* enable device and prepare host */
1677        rc = pcim_enable_device(pdev);
1678        if (rc)
1679                return rc;
1680
1681        hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1682        if (!hpriv)
1683                return -ENOMEM;
1684
1685        /* Save IOCFG, this will be used for cable detection, quirk
1686         * detection and restoration on detach.  This is necessary
1687         * because some ACPI implementations mess up cable related
1688         * bits on _STM.  Reported on kernel bz#11879.
1689         */
1690        pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1691
1692        /* ICH6R may be driven by either ata_piix or ahci driver
1693         * regardless of BIOS configuration.  Make sure AHCI mode is
1694         * off.
1695         */
1696        if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1697                rc = piix_disable_ahci(pdev);
1698                if (rc)
1699                        return rc;
1700        }
1701
1702        /* SATA map init can change port_info, do it before prepping host */
1703        if (port_flags & ATA_FLAG_SATA)
1704                hpriv->map = piix_init_sata_map(pdev, port_info,
1705                                        piix_map_db_table[ent->driver_data]);
1706
1707        rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
1708        if (rc)
1709                return rc;
1710        host->private_data = hpriv;
1711
1712        /* initialize controller */
1713        if (port_flags & ATA_FLAG_SATA) {
1714                piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1715                rc = piix_init_sidpr(host);
1716                if (rc)
1717                        return rc;
1718                if (host->ports[0]->ops == &piix_sidpr_sata_ops)
1719                        sht = &piix_sidpr_sht;
1720        }
1721
1722        /* apply IOCFG bit18 quirk */
1723        piix_iocfg_bit18_quirk(host);
1724
1725        /* On ICH5, some BIOSen disable the interrupt using the
1726         * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1727         * On ICH6, this bit has the same effect, but only when
1728         * MSI is disabled (and it is disabled, as we don't use
1729         * message-signalled interrupts currently).
1730         */
1731        if (port_flags & PIIX_FLAG_CHECKINTR)
1732                pci_intx(pdev, 1);
1733
1734        if (piix_check_450nx_errata(pdev)) {
1735                /* This writes into the master table but it does not
1736                   really matter for this errata as we will apply it to
1737                   all the PIIX devices on the board */
1738                host->ports[0]->mwdma_mask = 0;
1739                host->ports[0]->udma_mask = 0;
1740                host->ports[1]->mwdma_mask = 0;
1741                host->ports[1]->udma_mask = 0;
1742        }
1743        host->flags |= ATA_HOST_PARALLEL_SCAN;
1744
1745        /* Allow hosts to specify device types to ignore when scanning. */
1746        piix_ignore_devices_quirk(host);
1747
1748        pci_set_master(pdev);
1749        return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
1750}
1751
1752static void piix_remove_one(struct pci_dev *pdev)
1753{
1754        struct ata_host *host = dev_get_drvdata(&pdev->dev);
1755        struct piix_host_priv *hpriv = host->private_data;
1756
1757        pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1758
1759        ata_pci_remove_one(pdev);
1760}
1761
1762static struct pci_driver piix_pci_driver = {
1763        .name                   = DRV_NAME,
1764        .id_table               = piix_pci_tbl,
1765        .probe                  = piix_init_one,
1766        .remove                 = piix_remove_one,
1767#ifdef CONFIG_PM
1768        .suspend                = piix_pci_device_suspend,
1769        .resume                 = piix_pci_device_resume,
1770#endif
1771};
1772
1773static int __init piix_init(void)
1774{
1775        int rc;
1776
1777        DPRINTK("pci_register_driver\n");
1778        rc = pci_register_driver(&piix_pci_driver);
1779        if (rc)
1780                return rc;
1781
1782        in_module_init = 0;
1783
1784        DPRINTK("done\n");
1785        return 0;
1786}
1787
1788static void __exit piix_exit(void)
1789{
1790        pci_unregister_driver(&piix_pci_driver);
1791}
1792
1793module_init(piix_init);
1794module_exit(piix_exit);
1795
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