linux/drivers/ata/ahci.c
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   1/*
   2 *  ahci.c - AHCI SATA support
   3 *
   4 *  Maintained by:  Tejun Heo <tj@kernel.org>
   5 *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6 *                  on emails.
   7 *
   8 *  Copyright 2004-2005 Red Hat, Inc.
   9 *
  10 *
  11 *  This program is free software; you can redistribute it and/or modify
  12 *  it under the terms of the GNU General Public License as published by
  13 *  the Free Software Foundation; either version 2, or (at your option)
  14 *  any later version.
  15 *
  16 *  This program is distributed in the hope that it will be useful,
  17 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 *  GNU General Public License for more details.
  20 *
  21 *  You should have received a copy of the GNU General Public License
  22 *  along with this program; see the file COPYING.  If not, write to
  23 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24 *
  25 *
  26 * libata documentation is available via 'make {ps|pdf}docs',
  27 * as Documentation/DocBook/libata.*
  28 *
  29 * AHCI hardware documentation:
  30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
  31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  32 *
  33 */
  34
  35#include <linux/kernel.h>
  36#include <linux/module.h>
  37#include <linux/pci.h>
  38#include <linux/init.h>
  39#include <linux/blkdev.h>
  40#include <linux/delay.h>
  41#include <linux/interrupt.h>
  42#include <linux/dma-mapping.h>
  43#include <linux/device.h>
  44#include <linux/dmi.h>
  45#include <linux/gfp.h>
  46#include <scsi/scsi_host.h>
  47#include <scsi/scsi_cmnd.h>
  48#include <linux/libata.h>
  49#include "ahci.h"
  50
  51#define DRV_NAME        "ahci"
  52#define DRV_VERSION     "3.0"
  53
  54enum {
  55        AHCI_PCI_BAR_STA2X11    = 0,
  56        AHCI_PCI_BAR_ENMOTUS    = 2,
  57        AHCI_PCI_BAR_STANDARD   = 5,
  58};
  59
  60enum board_ids {
  61        /* board IDs by feature in alphabetical order */
  62        board_ahci,
  63        board_ahci_ign_iferr,
  64        board_ahci_nosntf,
  65        board_ahci_yes_fbs,
  66
  67        /* board IDs for specific chipsets in alphabetical order */
  68        board_ahci_mcp65,
  69        board_ahci_mcp77,
  70        board_ahci_mcp89,
  71        board_ahci_mv,
  72        board_ahci_sb600,
  73        board_ahci_sb700,       /* for SB700 and SB800 */
  74        board_ahci_vt8251,
  75
  76        /* aliases */
  77        board_ahci_mcp_linux    = board_ahci_mcp65,
  78        board_ahci_mcp67        = board_ahci_mcp65,
  79        board_ahci_mcp73        = board_ahci_mcp65,
  80        board_ahci_mcp79        = board_ahci_mcp77,
  81};
  82
  83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
  85                                 unsigned long deadline);
  86static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
  87                                unsigned long deadline);
  88#ifdef CONFIG_PM
  89static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
  90static int ahci_pci_device_resume(struct pci_dev *pdev);
  91#endif
  92
  93static struct scsi_host_template ahci_sht = {
  94        AHCI_SHT("ahci"),
  95};
  96
  97static struct ata_port_operations ahci_vt8251_ops = {
  98        .inherits               = &ahci_ops,
  99        .hardreset              = ahci_vt8251_hardreset,
 100};
 101
 102static struct ata_port_operations ahci_p5wdh_ops = {
 103        .inherits               = &ahci_ops,
 104        .hardreset              = ahci_p5wdh_hardreset,
 105};
 106
 107static const struct ata_port_info ahci_port_info[] = {
 108        /* by features */
 109        [board_ahci] = {
 110                .flags          = AHCI_FLAG_COMMON,
 111                .pio_mask       = ATA_PIO4,
 112                .udma_mask      = ATA_UDMA6,
 113                .port_ops       = &ahci_ops,
 114        },
 115        [board_ahci_ign_iferr] = {
 116                AHCI_HFLAGS     (AHCI_HFLAG_IGN_IRQ_IF_ERR),
 117                .flags          = AHCI_FLAG_COMMON,
 118                .pio_mask       = ATA_PIO4,
 119                .udma_mask      = ATA_UDMA6,
 120                .port_ops       = &ahci_ops,
 121        },
 122        [board_ahci_nosntf] = {
 123                AHCI_HFLAGS     (AHCI_HFLAG_NO_SNTF),
 124                .flags          = AHCI_FLAG_COMMON,
 125                .pio_mask       = ATA_PIO4,
 126                .udma_mask      = ATA_UDMA6,
 127                .port_ops       = &ahci_ops,
 128        },
 129        [board_ahci_yes_fbs] = {
 130                AHCI_HFLAGS     (AHCI_HFLAG_YES_FBS),
 131                .flags          = AHCI_FLAG_COMMON,
 132                .pio_mask       = ATA_PIO4,
 133                .udma_mask      = ATA_UDMA6,
 134                .port_ops       = &ahci_ops,
 135        },
 136        /* by chipsets */
 137        [board_ahci_mcp65] = {
 138                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
 139                                 AHCI_HFLAG_YES_NCQ),
 140                .flags          = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
 141                .pio_mask       = ATA_PIO4,
 142                .udma_mask      = ATA_UDMA6,
 143                .port_ops       = &ahci_ops,
 144        },
 145        [board_ahci_mcp77] = {
 146                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
 147                .flags          = AHCI_FLAG_COMMON,
 148                .pio_mask       = ATA_PIO4,
 149                .udma_mask      = ATA_UDMA6,
 150                .port_ops       = &ahci_ops,
 151        },
 152        [board_ahci_mcp89] = {
 153                AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA),
 154                .flags          = AHCI_FLAG_COMMON,
 155                .pio_mask       = ATA_PIO4,
 156                .udma_mask      = ATA_UDMA6,
 157                .port_ops       = &ahci_ops,
 158        },
 159        [board_ahci_mv] = {
 160                AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
 161                                 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
 162                .flags          = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
 163                .pio_mask       = ATA_PIO4,
 164                .udma_mask      = ATA_UDMA6,
 165                .port_ops       = &ahci_ops,
 166        },
 167        [board_ahci_sb600] = {
 168                AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL |
 169                                 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
 170                                 AHCI_HFLAG_32BIT_ONLY),
 171                .flags          = AHCI_FLAG_COMMON,
 172                .pio_mask       = ATA_PIO4,
 173                .udma_mask      = ATA_UDMA6,
 174                .port_ops       = &ahci_pmp_retry_srst_ops,
 175        },
 176        [board_ahci_sb700] = {  /* for SB700 and SB800 */
 177                AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL),
 178                .flags          = AHCI_FLAG_COMMON,
 179                .pio_mask       = ATA_PIO4,
 180                .udma_mask      = ATA_UDMA6,
 181                .port_ops       = &ahci_pmp_retry_srst_ops,
 182        },
 183        [board_ahci_vt8251] = {
 184                AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
 185                .flags          = AHCI_FLAG_COMMON,
 186                .pio_mask       = ATA_PIO4,
 187                .udma_mask      = ATA_UDMA6,
 188                .port_ops       = &ahci_vt8251_ops,
 189        },
 190};
 191
 192static const struct pci_device_id ahci_pci_tbl[] = {
 193        /* Intel */
 194        { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
 195        { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
 196        { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
 197        { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
 198        { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
 199        { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
 200        { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
 201        { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
 202        { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
 203        { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
 204        { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
 205        { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
 206        { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
 207        { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
 208        { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
 209        { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
 210        { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
 211        { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
 212        { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
 213        { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
 214        { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
 215        { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
 216        { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
 217        { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
 218        { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
 219        { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
 220        { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
 221        { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
 222        { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
 223        { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
 224        { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
 225        { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
 226        { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
 227        { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
 228        { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
 229        { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
 230        { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
 231        { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
 232        { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
 233        { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
 234        { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
 235        { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
 236        { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
 237        { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
 238        { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
 239        { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
 240        { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
 241        { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
 242        { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
 243        { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
 244        { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
 245        { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
 246        { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
 247        { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
 248        { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
 249        { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
 250        { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
 251        { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
 252        { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
 253        { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
 254        { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
 255        { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
 256        { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
 257        { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
 258        { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
 259        { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
 260        { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
 261        { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
 262        { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
 263        { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
 264        { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
 265        { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
 266        { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
 267        { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
 268        { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
 269        { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
 270        { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
 271        { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
 272        { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
 273        { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
 274        { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
 275        { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
 276        { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
 277        { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
 278        { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
 279        { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
 280        { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
 281        { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
 282        { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
 283        { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
 284        { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
 285        { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
 286        { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
 287        { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
 288        { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
 289        { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
 290        { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
 291        { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
 292        { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
 293        { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
 294
 295        /* JMicron 360/1/3/5/6, match class to avoid IDE function */
 296        { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 297          PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
 298        /* JMicron 362B and 362C have an AHCI function with IDE class code */
 299        { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
 300        { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
 301
 302        /* ATI */
 303        { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
 304        { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
 305        { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
 306        { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
 307        { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
 308        { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
 309        { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
 310
 311        /* AMD */
 312        { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
 313        /* AMD is using RAID class only for ahci controllers */
 314        { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 315          PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
 316
 317        /* VIA */
 318        { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
 319        { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
 320
 321        /* NVIDIA */
 322        { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 },      /* MCP65 */
 323        { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 },      /* MCP65 */
 324        { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 },      /* MCP65 */
 325        { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 },      /* MCP65 */
 326        { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 },      /* MCP65 */
 327        { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },      /* MCP65 */
 328        { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },      /* MCP65 */
 329        { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },      /* MCP65 */
 330        { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 },      /* MCP67 */
 331        { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 },      /* MCP67 */
 332        { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 },      /* MCP67 */
 333        { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 },      /* MCP67 */
 334        { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 },      /* MCP67 */
 335        { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 },      /* MCP67 */
 336        { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 },      /* MCP67 */
 337        { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 },      /* MCP67 */
 338        { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 },      /* MCP67 */
 339        { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 },      /* MCP67 */
 340        { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 },      /* MCP67 */
 341        { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 },      /* MCP67 */
 342        { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux },  /* Linux ID */
 343        { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux },  /* Linux ID */
 344        { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux },  /* Linux ID */
 345        { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux },  /* Linux ID */
 346        { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux },  /* Linux ID */
 347        { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux },  /* Linux ID */
 348        { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux },  /* Linux ID */
 349        { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux },  /* Linux ID */
 350        { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux },  /* Linux ID */
 351        { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux },  /* Linux ID */
 352        { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux },  /* Linux ID */
 353        { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux },  /* Linux ID */
 354        { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux },  /* Linux ID */
 355        { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux },  /* Linux ID */
 356        { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux },  /* Linux ID */
 357        { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux },  /* Linux ID */
 358        { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 },      /* MCP73 */
 359        { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 },      /* MCP73 */
 360        { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 },      /* MCP73 */
 361        { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 },      /* MCP73 */
 362        { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 },      /* MCP73 */
 363        { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 },      /* MCP73 */
 364        { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 },      /* MCP73 */
 365        { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 },      /* MCP73 */
 366        { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 },      /* MCP73 */
 367        { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 },      /* MCP73 */
 368        { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 },      /* MCP73 */
 369        { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 },      /* MCP73 */
 370        { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 },      /* MCP77 */
 371        { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 },      /* MCP77 */
 372        { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 },      /* MCP77 */
 373        { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 },      /* MCP77 */
 374        { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 },      /* MCP77 */
 375        { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 },      /* MCP77 */
 376        { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 },      /* MCP77 */
 377        { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 },      /* MCP77 */
 378        { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 },      /* MCP77 */
 379        { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 },      /* MCP77 */
 380        { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 },      /* MCP77 */
 381        { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 },      /* MCP77 */
 382        { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 },      /* MCP79 */
 383        { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 },      /* MCP79 */
 384        { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 },      /* MCP79 */
 385        { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 },      /* MCP79 */
 386        { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 },      /* MCP79 */
 387        { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 },      /* MCP79 */
 388        { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 },      /* MCP79 */
 389        { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 },      /* MCP79 */
 390        { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 },      /* MCP79 */
 391        { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 },      /* MCP79 */
 392        { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 },      /* MCP79 */
 393        { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 },      /* MCP79 */
 394        { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 },      /* MCP89 */
 395        { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 },      /* MCP89 */
 396        { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 },      /* MCP89 */
 397        { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 },      /* MCP89 */
 398        { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 },      /* MCP89 */
 399        { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 },      /* MCP89 */
 400        { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 },      /* MCP89 */
 401        { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 },      /* MCP89 */
 402        { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 },      /* MCP89 */
 403        { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 },      /* MCP89 */
 404        { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 },      /* MCP89 */
 405        { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 },      /* MCP89 */
 406
 407        /* SiS */
 408        { PCI_VDEVICE(SI, 0x1184), board_ahci },                /* SiS 966 */
 409        { PCI_VDEVICE(SI, 0x1185), board_ahci },                /* SiS 968 */
 410        { PCI_VDEVICE(SI, 0x0186), board_ahci },                /* SiS 968 */
 411
 412        /* ST Microelectronics */
 413        { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci },           /* ST ConneXt */
 414
 415        /* Marvell */
 416        { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },        /* 6145 */
 417        { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },        /* 6121 */
 418        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
 419          .class = PCI_CLASS_STORAGE_SATA_AHCI,
 420          .class_mask = 0xffffff,
 421          .driver_data = board_ahci_yes_fbs },                  /* 88se9128 */
 422        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
 423          .driver_data = board_ahci_yes_fbs },                  /* 88se9125 */
 424        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
 425          .driver_data = board_ahci_yes_fbs },                  /* 88se9172 */
 426        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
 427          .driver_data = board_ahci_yes_fbs },                  /* 88se9172 */
 428        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
 429          .driver_data = board_ahci_yes_fbs },                  /* 88se9172 on some Gigabyte */
 430        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
 431          .driver_data = board_ahci_yes_fbs },
 432
 433        /* Promise */
 434        { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },   /* PDC42819 */
 435
 436        /* Asmedia */
 437        { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci },   /* ASM1060 */
 438        { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci },   /* ASM1060 */
 439        { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci },   /* ASM1061 */
 440        { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci },   /* ASM1062 */
 441
 442        /* Enmotus */
 443        { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
 444
 445        /* Generic, PCI class code for AHCI */
 446        { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 447          PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
 448
 449        { }     /* terminate list */
 450};
 451
 452
 453static struct pci_driver ahci_pci_driver = {
 454        .name                   = DRV_NAME,
 455        .id_table               = ahci_pci_tbl,
 456        .probe                  = ahci_init_one,
 457        .remove                 = ata_pci_remove_one,
 458#ifdef CONFIG_PM
 459        .suspend                = ahci_pci_device_suspend,
 460        .resume                 = ahci_pci_device_resume,
 461#endif
 462};
 463
 464#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
 465static int marvell_enable;
 466#else
 467static int marvell_enable = 1;
 468#endif
 469module_param(marvell_enable, int, 0644);
 470MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
 471
 472
 473static void ahci_pci_save_initial_config(struct pci_dev *pdev,
 474                                         struct ahci_host_priv *hpriv)
 475{
 476        unsigned int force_port_map = 0;
 477        unsigned int mask_port_map = 0;
 478
 479        if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
 480                dev_info(&pdev->dev, "JMB361 has only one port\n");
 481                force_port_map = 1;
 482        }
 483
 484        /*
 485         * Temporary Marvell 6145 hack: PATA port presence
 486         * is asserted through the standard AHCI port
 487         * presence register, as bit 4 (counting from 0)
 488         */
 489        if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
 490                if (pdev->device == 0x6121)
 491                        mask_port_map = 0x3;
 492                else
 493                        mask_port_map = 0xf;
 494                dev_info(&pdev->dev,
 495                          "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
 496        }
 497
 498        ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
 499                                 mask_port_map);
 500}
 501
 502static int ahci_pci_reset_controller(struct ata_host *host)
 503{
 504        struct pci_dev *pdev = to_pci_dev(host->dev);
 505
 506        ahci_reset_controller(host);
 507
 508        if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 509                struct ahci_host_priv *hpriv = host->private_data;
 510                u16 tmp16;
 511
 512                /* configure PCS */
 513                pci_read_config_word(pdev, 0x92, &tmp16);
 514                if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
 515                        tmp16 |= hpriv->port_map;
 516                        pci_write_config_word(pdev, 0x92, tmp16);
 517                }
 518        }
 519
 520        return 0;
 521}
 522
 523static void ahci_pci_init_controller(struct ata_host *host)
 524{
 525        struct ahci_host_priv *hpriv = host->private_data;
 526        struct pci_dev *pdev = to_pci_dev(host->dev);
 527        void __iomem *port_mmio;
 528        u32 tmp;
 529        int mv;
 530
 531        if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
 532                if (pdev->device == 0x6121)
 533                        mv = 2;
 534                else
 535                        mv = 4;
 536                port_mmio = __ahci_port_base(host, mv);
 537
 538                writel(0, port_mmio + PORT_IRQ_MASK);
 539
 540                /* clear port IRQ */
 541                tmp = readl(port_mmio + PORT_IRQ_STAT);
 542                VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
 543                if (tmp)
 544                        writel(tmp, port_mmio + PORT_IRQ_STAT);
 545        }
 546
 547        ahci_init_controller(host);
 548}
 549
 550static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 551                                 unsigned long deadline)
 552{
 553        struct ata_port *ap = link->ap;
 554        bool online;
 555        int rc;
 556
 557        DPRINTK("ENTER\n");
 558
 559        ahci_stop_engine(ap);
 560
 561        rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
 562                                 deadline, &online, NULL);
 563
 564        ahci_start_engine(ap);
 565
 566        DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
 567
 568        /* vt8251 doesn't clear BSY on signature FIS reception,
 569         * request follow-up softreset.
 570         */
 571        return online ? -EAGAIN : rc;
 572}
 573
 574static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
 575                                unsigned long deadline)
 576{
 577        struct ata_port *ap = link->ap;
 578        struct ahci_port_priv *pp = ap->private_data;
 579        u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
 580        struct ata_taskfile tf;
 581        bool online;
 582        int rc;
 583
 584        ahci_stop_engine(ap);
 585
 586        /* clear D2H reception area to properly wait for D2H FIS */
 587        ata_tf_init(link->device, &tf);
 588        tf.command = 0x80;
 589        ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 590
 591        rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
 592                                 deadline, &online, NULL);
 593
 594        ahci_start_engine(ap);
 595
 596        /* The pseudo configuration device on SIMG4726 attached to
 597         * ASUS P5W-DH Deluxe doesn't send signature FIS after
 598         * hardreset if no device is attached to the first downstream
 599         * port && the pseudo device locks up on SRST w/ PMP==0.  To
 600         * work around this, wait for !BSY only briefly.  If BSY isn't
 601         * cleared, perform CLO and proceed to IDENTIFY (achieved by
 602         * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
 603         *
 604         * Wait for two seconds.  Devices attached to downstream port
 605         * which can't process the following IDENTIFY after this will
 606         * have to be reset again.  For most cases, this should
 607         * suffice while making probing snappish enough.
 608         */
 609        if (online) {
 610                rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
 611                                          ahci_check_ready);
 612                if (rc)
 613                        ahci_kick_engine(ap);
 614        }
 615        return rc;
 616}
 617
 618#ifdef CONFIG_PM
 619static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
 620{
 621        struct ata_host *host = dev_get_drvdata(&pdev->dev);
 622        struct ahci_host_priv *hpriv = host->private_data;
 623        void __iomem *mmio = hpriv->mmio;
 624        u32 ctl;
 625
 626        if (mesg.event & PM_EVENT_SUSPEND &&
 627            hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
 628                dev_err(&pdev->dev,
 629                        "BIOS update required for suspend/resume\n");
 630                return -EIO;
 631        }
 632
 633        if (mesg.event & PM_EVENT_SLEEP) {
 634                /* AHCI spec rev1.1 section 8.3.3:
 635                 * Software must disable interrupts prior to requesting a
 636                 * transition of the HBA to D3 state.
 637                 */
 638                ctl = readl(mmio + HOST_CTL);
 639                ctl &= ~HOST_IRQ_EN;
 640                writel(ctl, mmio + HOST_CTL);
 641                readl(mmio + HOST_CTL); /* flush */
 642        }
 643
 644        return ata_pci_device_suspend(pdev, mesg);
 645}
 646
 647static int ahci_pci_device_resume(struct pci_dev *pdev)
 648{
 649        struct ata_host *host = dev_get_drvdata(&pdev->dev);
 650        int rc;
 651
 652        rc = ata_pci_device_do_resume(pdev);
 653        if (rc)
 654                return rc;
 655
 656        if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
 657                rc = ahci_pci_reset_controller(host);
 658                if (rc)
 659                        return rc;
 660
 661                ahci_pci_init_controller(host);
 662        }
 663
 664        ata_host_resume(host);
 665
 666        return 0;
 667}
 668#endif
 669
 670static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
 671{
 672        int rc;
 673
 674        /*
 675         * If the device fixup already set the dma_mask to some non-standard
 676         * value, don't extend it here. This happens on STA2X11, for example.
 677         */
 678        if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
 679                return 0;
 680
 681        if (using_dac &&
 682            !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
 683                rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
 684                if (rc) {
 685                        rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 686                        if (rc) {
 687                                dev_err(&pdev->dev,
 688                                        "64-bit DMA enable failed\n");
 689                                return rc;
 690                        }
 691                }
 692        } else {
 693                rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 694                if (rc) {
 695                        dev_err(&pdev->dev, "32-bit DMA enable failed\n");
 696                        return rc;
 697                }
 698                rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 699                if (rc) {
 700                        dev_err(&pdev->dev,
 701                                "32-bit consistent DMA enable failed\n");
 702                        return rc;
 703                }
 704        }
 705        return 0;
 706}
 707
 708static void ahci_pci_print_info(struct ata_host *host)
 709{
 710        struct pci_dev *pdev = to_pci_dev(host->dev);
 711        u16 cc;
 712        const char *scc_s;
 713
 714        pci_read_config_word(pdev, 0x0a, &cc);
 715        if (cc == PCI_CLASS_STORAGE_IDE)
 716                scc_s = "IDE";
 717        else if (cc == PCI_CLASS_STORAGE_SATA)
 718                scc_s = "SATA";
 719        else if (cc == PCI_CLASS_STORAGE_RAID)
 720                scc_s = "RAID";
 721        else
 722                scc_s = "unknown";
 723
 724        ahci_print_info(host, scc_s);
 725}
 726
 727/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
 728 * hardwired to on-board SIMG 4726.  The chipset is ICH8 and doesn't
 729 * support PMP and the 4726 either directly exports the device
 730 * attached to the first downstream port or acts as a hardware storage
 731 * controller and emulate a single ATA device (can be RAID 0/1 or some
 732 * other configuration).
 733 *
 734 * When there's no device attached to the first downstream port of the
 735 * 4726, "Config Disk" appears, which is a pseudo ATA device to
 736 * configure the 4726.  However, ATA emulation of the device is very
 737 * lame.  It doesn't send signature D2H Reg FIS after the initial
 738 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
 739 *
 740 * The following function works around the problem by always using
 741 * hardreset on the port and not depending on receiving signature FIS
 742 * afterward.  If signature FIS isn't received soon, ATA class is
 743 * assumed without follow-up softreset.
 744 */
 745static void ahci_p5wdh_workaround(struct ata_host *host)
 746{
 747        static struct dmi_system_id sysids[] = {
 748                {
 749                        .ident = "P5W DH Deluxe",
 750                        .matches = {
 751                                DMI_MATCH(DMI_SYS_VENDOR,
 752                                          "ASUSTEK COMPUTER INC"),
 753                                DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
 754                        },
 755                },
 756                { }
 757        };
 758        struct pci_dev *pdev = to_pci_dev(host->dev);
 759
 760        if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
 761            dmi_check_system(sysids)) {
 762                struct ata_port *ap = host->ports[1];
 763
 764                dev_info(&pdev->dev,
 765                         "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
 766
 767                ap->ops = &ahci_p5wdh_ops;
 768                ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
 769        }
 770}
 771
 772/* only some SB600 ahci controllers can do 64bit DMA */
 773static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
 774{
 775        static const struct dmi_system_id sysids[] = {
 776                /*
 777                 * The oldest version known to be broken is 0901 and
 778                 * working is 1501 which was released on 2007-10-26.
 779                 * Enable 64bit DMA on 1501 and anything newer.
 780                 *
 781                 * Please read bko#9412 for more info.
 782                 */
 783                {
 784                        .ident = "ASUS M2A-VM",
 785                        .matches = {
 786                                DMI_MATCH(DMI_BOARD_VENDOR,
 787                                          "ASUSTeK Computer INC."),
 788                                DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
 789                        },
 790                        .driver_data = "20071026",      /* yyyymmdd */
 791                },
 792                /*
 793                 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
 794                 * support 64bit DMA.
 795                 *
 796                 * BIOS versions earlier than 1.5 had the Manufacturer DMI
 797                 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
 798                 * This spelling mistake was fixed in BIOS version 1.5, so
 799                 * 1.5 and later have the Manufacturer as
 800                 * "MICRO-STAR INTERNATIONAL CO.,LTD".
 801                 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
 802                 *
 803                 * BIOS versions earlier than 1.9 had a Board Product Name
 804                 * DMI field of "MS-7376". This was changed to be
 805                 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
 806                 * match on DMI_BOARD_NAME of "MS-7376".
 807                 */
 808                {
 809                        .ident = "MSI K9A2 Platinum",
 810                        .matches = {
 811                                DMI_MATCH(DMI_BOARD_VENDOR,
 812                                          "MICRO-STAR INTER"),
 813                                DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
 814                        },
 815                },
 816                /*
 817                 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
 818                 * 64bit DMA.
 819                 *
 820                 * This board also had the typo mentioned above in the
 821                 * Manufacturer DMI field (fixed in BIOS version 1.5), so
 822                 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
 823                 */
 824                {
 825                        .ident = "MSI K9AGM2",
 826                        .matches = {
 827                                DMI_MATCH(DMI_BOARD_VENDOR,
 828                                          "MICRO-STAR INTER"),
 829                                DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
 830                        },
 831                },
 832                /*
 833                 * All BIOS versions for the Asus M3A support 64bit DMA.
 834                 * (all release versions from 0301 to 1206 were tested)
 835                 */
 836                {
 837                        .ident = "ASUS M3A",
 838                        .matches = {
 839                                DMI_MATCH(DMI_BOARD_VENDOR,
 840                                          "ASUSTeK Computer INC."),
 841                                DMI_MATCH(DMI_BOARD_NAME, "M3A"),
 842                        },
 843                },
 844                { }
 845        };
 846        const struct dmi_system_id *match;
 847        int year, month, date;
 848        char buf[9];
 849
 850        match = dmi_first_match(sysids);
 851        if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
 852            !match)
 853                return false;
 854
 855        if (!match->driver_data)
 856                goto enable_64bit;
 857
 858        dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
 859        snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
 860
 861        if (strcmp(buf, match->driver_data) >= 0)
 862                goto enable_64bit;
 863        else {
 864                dev_warn(&pdev->dev,
 865                         "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
 866                         match->ident);
 867                return false;
 868        }
 869
 870enable_64bit:
 871        dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
 872        return true;
 873}
 874
 875static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
 876{
 877        static const struct dmi_system_id broken_systems[] = {
 878                {
 879                        .ident = "HP Compaq nx6310",
 880                        .matches = {
 881                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 882                                DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
 883                        },
 884                        /* PCI slot number of the controller */
 885                        .driver_data = (void *)0x1FUL,
 886                },
 887                {
 888                        .ident = "HP Compaq 6720s",
 889                        .matches = {
 890                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 891                                DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
 892                        },
 893                        /* PCI slot number of the controller */
 894                        .driver_data = (void *)0x1FUL,
 895                },
 896
 897                { }     /* terminate list */
 898        };
 899        const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
 900
 901        if (dmi) {
 902                unsigned long slot = (unsigned long)dmi->driver_data;
 903                /* apply the quirk only to on-board controllers */
 904                return slot == PCI_SLOT(pdev->devfn);
 905        }
 906
 907        return false;
 908}
 909
 910static bool ahci_broken_suspend(struct pci_dev *pdev)
 911{
 912        static const struct dmi_system_id sysids[] = {
 913                /*
 914                 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
 915                 * to the harddisk doesn't become online after
 916                 * resuming from STR.  Warn and fail suspend.
 917                 *
 918                 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
 919                 *
 920                 * Use dates instead of versions to match as HP is
 921                 * apparently recycling both product and version
 922                 * strings.
 923                 *
 924                 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
 925                 */
 926                {
 927                        .ident = "dv4",
 928                        .matches = {
 929                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 930                                DMI_MATCH(DMI_PRODUCT_NAME,
 931                                          "HP Pavilion dv4 Notebook PC"),
 932                        },
 933                        .driver_data = "20090105",      /* F.30 */
 934                },
 935                {
 936                        .ident = "dv5",
 937                        .matches = {
 938                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 939                                DMI_MATCH(DMI_PRODUCT_NAME,
 940                                          "HP Pavilion dv5 Notebook PC"),
 941                        },
 942                        .driver_data = "20090506",      /* F.16 */
 943                },
 944                {
 945                        .ident = "dv6",
 946                        .matches = {
 947                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 948                                DMI_MATCH(DMI_PRODUCT_NAME,
 949                                          "HP Pavilion dv6 Notebook PC"),
 950                        },
 951                        .driver_data = "20090423",      /* F.21 */
 952                },
 953                {
 954                        .ident = "HDX18",
 955                        .matches = {
 956                                DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
 957                                DMI_MATCH(DMI_PRODUCT_NAME,
 958                                          "HP HDX18 Notebook PC"),
 959                        },
 960                        .driver_data = "20090430",      /* F.23 */
 961                },
 962                /*
 963                 * Acer eMachines G725 has the same problem.  BIOS
 964                 * V1.03 is known to be broken.  V3.04 is known to
 965                 * work.  Between, there are V1.06, V2.06 and V3.03
 966                 * that we don't have much idea about.  For now,
 967                 * blacklist anything older than V3.04.
 968                 *
 969                 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
 970                 */
 971                {
 972                        .ident = "G725",
 973                        .matches = {
 974                                DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
 975                                DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
 976                        },
 977                        .driver_data = "20091216",      /* V3.04 */
 978                },
 979                { }     /* terminate list */
 980        };
 981        const struct dmi_system_id *dmi = dmi_first_match(sysids);
 982        int year, month, date;
 983        char buf[9];
 984
 985        if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
 986                return false;
 987
 988        dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
 989        snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
 990
 991        return strcmp(buf, dmi->driver_data) < 0;
 992}
 993
 994static bool ahci_broken_online(struct pci_dev *pdev)
 995{
 996#define ENCODE_BUSDEVFN(bus, slot, func)                        \
 997        (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
 998        static const struct dmi_system_id sysids[] = {
 999                /*
1000                 * There are several gigabyte boards which use
1001                 * SIMG5723s configured as hardware RAID.  Certain
1002                 * 5723 firmware revisions shipped there keep the link
1003                 * online but fail to answer properly to SRST or
1004                 * IDENTIFY when no device is attached downstream
1005                 * causing libata to retry quite a few times leading
1006                 * to excessive detection delay.
1007                 *
1008                 * As these firmwares respond to the second reset try
1009                 * with invalid device signature, considering unknown
1010                 * sig as offline works around the problem acceptably.
1011                 */
1012                {
1013                        .ident = "EP45-DQ6",
1014                        .matches = {
1015                                DMI_MATCH(DMI_BOARD_VENDOR,
1016                                          "Gigabyte Technology Co., Ltd."),
1017                                DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1018                        },
1019                        .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1020                },
1021                {
1022                        .ident = "EP45-DS5",
1023                        .matches = {
1024                                DMI_MATCH(DMI_BOARD_VENDOR,
1025                                          "Gigabyte Technology Co., Ltd."),
1026                                DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1027                        },
1028                        .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1029                },
1030                { }     /* terminate list */
1031        };
1032#undef ENCODE_BUSDEVFN
1033        const struct dmi_system_id *dmi = dmi_first_match(sysids);
1034        unsigned int val;
1035
1036        if (!dmi)
1037                return false;
1038
1039        val = (unsigned long)dmi->driver_data;
1040
1041        return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1042}
1043
1044#ifdef CONFIG_ATA_ACPI
1045static void ahci_gtf_filter_workaround(struct ata_host *host)
1046{
1047        static const struct dmi_system_id sysids[] = {
1048                /*
1049                 * Aspire 3810T issues a bunch of SATA enable commands
1050                 * via _GTF including an invalid one and one which is
1051                 * rejected by the device.  Among the successful ones
1052                 * is FPDMA non-zero offset enable which when enabled
1053                 * only on the drive side leads to NCQ command
1054                 * failures.  Filter it out.
1055                 */
1056                {
1057                        .ident = "Aspire 3810T",
1058                        .matches = {
1059                                DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1060                                DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1061                        },
1062                        .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1063                },
1064                { }
1065        };
1066        const struct dmi_system_id *dmi = dmi_first_match(sysids);
1067        unsigned int filter;
1068        int i;
1069
1070        if (!dmi)
1071                return;
1072
1073        filter = (unsigned long)dmi->driver_data;
1074        dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1075                 filter, dmi->ident);
1076
1077        for (i = 0; i < host->n_ports; i++) {
1078                struct ata_port *ap = host->ports[i];
1079                struct ata_link *link;
1080                struct ata_device *dev;
1081
1082                ata_for_each_link(link, ap, EDGE)
1083                        ata_for_each_dev(dev, link, ALL)
1084                                dev->gtf_filter |= filter;
1085        }
1086}
1087#else
1088static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1089{}
1090#endif
1091
1092int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1093{
1094        int rc;
1095        unsigned int maxvec;
1096
1097        if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {
1098                rc = pci_enable_msi_block_auto(pdev, &maxvec);
1099                if (rc > 0) {
1100                        if ((rc == maxvec) || (rc == 1))
1101                                return rc;
1102                        /*
1103                         * Assume that advantage of multipe MSIs is negated,
1104                         * so fallback to single MSI mode to save resources
1105                         */
1106                        pci_disable_msi(pdev);
1107                        if (!pci_enable_msi(pdev))
1108                                return 1;
1109                }
1110        }
1111
1112        pci_intx(pdev, 1);
1113        return 0;
1114}
1115
1116/**
1117 *      ahci_host_activate - start AHCI host, request IRQs and register it
1118 *      @host: target ATA host
1119 *      @irq: base IRQ number to request
1120 *      @n_msis: number of MSIs allocated for this host
1121 *      @irq_handler: irq_handler used when requesting IRQs
1122 *      @irq_flags: irq_flags used when requesting IRQs
1123 *
1124 *      Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1125 *      when multiple MSIs were allocated. That is one MSI per port, starting
1126 *      from @irq.
1127 *
1128 *      LOCKING:
1129 *      Inherited from calling layer (may sleep).
1130 *
1131 *      RETURNS:
1132 *      0 on success, -errno otherwise.
1133 */
1134int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1135{
1136        int i, rc;
1137
1138        /* Sharing Last Message among several ports is not supported */
1139        if (n_msis < host->n_ports)
1140                return -EINVAL;
1141
1142        rc = ata_host_start(host);
1143        if (rc)
1144                return rc;
1145
1146        for (i = 0; i < host->n_ports; i++) {
1147                rc = devm_request_threaded_irq(host->dev,
1148                        irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
1149                        dev_driver_string(host->dev), host->ports[i]);
1150                if (rc)
1151                        goto out_free_irqs;
1152        }
1153
1154        for (i = 0; i < host->n_ports; i++)
1155                ata_port_desc(host->ports[i], "irq %d", irq + i);
1156
1157        rc = ata_host_register(host, &ahci_sht);
1158        if (rc)
1159                goto out_free_all_irqs;
1160
1161        return 0;
1162
1163out_free_all_irqs:
1164        i = host->n_ports;
1165out_free_irqs:
1166        for (i--; i >= 0; i--)
1167                devm_free_irq(host->dev, irq + i, host->ports[i]);
1168
1169        return rc;
1170}
1171
1172static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1173{
1174        unsigned int board_id = ent->driver_data;
1175        struct ata_port_info pi = ahci_port_info[board_id];
1176        const struct ata_port_info *ppi[] = { &pi, NULL };
1177        struct device *dev = &pdev->dev;
1178        struct ahci_host_priv *hpriv;
1179        struct ata_host *host;
1180        int n_ports, n_msis, i, rc;
1181        int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1182
1183        VPRINTK("ENTER\n");
1184
1185        WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1186
1187        ata_print_version_once(&pdev->dev, DRV_VERSION);
1188
1189        /* The AHCI driver can only drive the SATA ports, the PATA driver
1190           can drive them all so if both drivers are selected make sure
1191           AHCI stays out of the way */
1192        if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1193                return -ENODEV;
1194
1195        /*
1196         * For some reason, MCP89 on MacBook 7,1 doesn't work with
1197         * ahci, use ata_generic instead.
1198         */
1199        if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1200            pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1201            pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1202            pdev->subsystem_device == 0xcb89)
1203                return -ENODEV;
1204
1205        /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1206         * At the moment, we can only use the AHCI mode. Let the users know
1207         * that for SAS drives they're out of luck.
1208         */
1209        if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1210                dev_info(&pdev->dev,
1211                         "PDC42819 can only drive SATA devices with this driver\n");
1212
1213        /* Both Connext and Enmotus devices use non-standard BARs */
1214        if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1215                ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1216        else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1217                ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1218
1219        /* acquire resources */
1220        rc = pcim_enable_device(pdev);
1221        if (rc)
1222                return rc;
1223
1224        /* AHCI controllers often implement SFF compatible interface.
1225         * Grab all PCI BARs just in case.
1226         */
1227        rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1228        if (rc == -EBUSY)
1229                pcim_pin_device(pdev);
1230        if (rc)
1231                return rc;
1232
1233        if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1234            (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1235                u8 map;
1236
1237                /* ICH6s share the same PCI ID for both piix and ahci
1238                 * modes.  Enabling ahci mode while MAP indicates
1239                 * combined mode is a bad idea.  Yield to ata_piix.
1240                 */
1241                pci_read_config_byte(pdev, ICH_MAP, &map);
1242                if (map & 0x3) {
1243                        dev_info(&pdev->dev,
1244                                 "controller is in combined mode, can't enable AHCI mode\n");
1245                        return -ENODEV;
1246                }
1247        }
1248
1249        hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1250        if (!hpriv)
1251                return -ENOMEM;
1252        hpriv->flags |= (unsigned long)pi.private_data;
1253
1254        /* MCP65 revision A1 and A2 can't do MSI */
1255        if (board_id == board_ahci_mcp65 &&
1256            (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1257                hpriv->flags |= AHCI_HFLAG_NO_MSI;
1258
1259        /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1260        if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1261                hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1262
1263        /* only some SB600s can do 64bit DMA */
1264        if (ahci_sb600_enable_64bit(pdev))
1265                hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1266
1267        hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1268
1269        n_msis = ahci_init_interrupts(pdev, hpriv);
1270        if (n_msis > 1)
1271                hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1272
1273        /* save initial config */
1274        ahci_pci_save_initial_config(pdev, hpriv);
1275
1276        /* prepare host */
1277        if (hpriv->cap & HOST_CAP_NCQ) {
1278                pi.flags |= ATA_FLAG_NCQ;
1279                /*
1280                 * Auto-activate optimization is supposed to be
1281                 * supported on all AHCI controllers indicating NCQ
1282                 * capability, but it seems to be broken on some
1283                 * chipsets including NVIDIAs.
1284                 */
1285                if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1286                        pi.flags |= ATA_FLAG_FPDMA_AA;
1287        }
1288
1289        if (hpriv->cap & HOST_CAP_PMP)
1290                pi.flags |= ATA_FLAG_PMP;
1291
1292        ahci_set_em_messages(hpriv, &pi);
1293
1294        if (ahci_broken_system_poweroff(pdev)) {
1295                pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1296                dev_info(&pdev->dev,
1297                        "quirky BIOS, skipping spindown on poweroff\n");
1298        }
1299
1300        if (ahci_broken_suspend(pdev)) {
1301                hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1302                dev_warn(&pdev->dev,
1303                         "BIOS update required for suspend/resume\n");
1304        }
1305
1306        if (ahci_broken_online(pdev)) {
1307                hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1308                dev_info(&pdev->dev,
1309                         "online status unreliable, applying workaround\n");
1310        }
1311
1312        /* CAP.NP sometimes indicate the index of the last enabled
1313         * port, at other times, that of the last possible port, so
1314         * determining the maximum port number requires looking at
1315         * both CAP.NP and port_map.
1316         */
1317        n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1318
1319        host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1320        if (!host)
1321                return -ENOMEM;
1322        host->private_data = hpriv;
1323
1324        if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1325                host->flags |= ATA_HOST_PARALLEL_SCAN;
1326        else
1327                printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1328
1329        if (pi.flags & ATA_FLAG_EM)
1330                ahci_reset_em(host);
1331
1332        for (i = 0; i < host->n_ports; i++) {
1333                struct ata_port *ap = host->ports[i];
1334
1335                ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1336                ata_port_pbar_desc(ap, ahci_pci_bar,
1337                                   0x100 + ap->port_no * 0x80, "port");
1338
1339                /* set enclosure management message type */
1340                if (ap->flags & ATA_FLAG_EM)
1341                        ap->em_message_type = hpriv->em_msg_type;
1342
1343
1344                /* disabled/not-implemented port */
1345                if (!(hpriv->port_map & (1 << i)))
1346                        ap->ops = &ata_dummy_port_ops;
1347        }
1348
1349        /* apply workaround for ASUS P5W DH Deluxe mainboard */
1350        ahci_p5wdh_workaround(host);
1351
1352        /* apply gtf filter quirk */
1353        ahci_gtf_filter_workaround(host);
1354
1355        /* initialize adapter */
1356        rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1357        if (rc)
1358                return rc;
1359
1360        rc = ahci_pci_reset_controller(host);
1361        if (rc)
1362                return rc;
1363
1364        ahci_pci_init_controller(host);
1365        ahci_pci_print_info(host);
1366
1367        pci_set_master(pdev);
1368
1369        if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1370                return ahci_host_activate(host, pdev->irq, n_msis);
1371
1372        return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1373                                 &ahci_sht);
1374}
1375
1376module_pci_driver(ahci_pci_driver);
1377
1378MODULE_AUTHOR("Jeff Garzik");
1379MODULE_DESCRIPTION("AHCI SATA low-level driver");
1380MODULE_LICENSE("GPL");
1381MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1382MODULE_VERSION(DRV_VERSION);
1383
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