linux/drivers/pci/probe.c
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   1/*
   2 * probe.c - PCI detection and setup code
   3 */
   4
   5#include <linux/kernel.h>
   6#include <linux/delay.h>
   7#include <linux/init.h>
   8#include <linux/pci.h>
   9#include <linux/slab.h>
  10#include <linux/module.h>
  11#include <linux/cpumask.h>
  12#include <linux/pci-aspm.h>
  13#include "pci.h"
  14
  15#define CARDBUS_LATENCY_TIMER   176     /* secondary latency timer */
  16#define CARDBUS_RESERVE_BUSNR   3
  17
  18/* Ugh.  Need to stop exporting this to modules. */
  19LIST_HEAD(pci_root_buses);
  20EXPORT_SYMBOL(pci_root_buses);
  21
  22
  23static int find_anything(struct device *dev, void *data)
  24{
  25        return 1;
  26}
  27
  28/*
  29 * Some device drivers need know if pci is initiated.
  30 * Basically, we think pci is not initiated when there
  31 * is no device to be found on the pci_bus_type.
  32 */
  33int no_pci_devices(void)
  34{
  35        struct device *dev;
  36        int no_devices;
  37
  38        dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
  39        no_devices = (dev == NULL);
  40        put_device(dev);
  41        return no_devices;
  42}
  43EXPORT_SYMBOL(no_pci_devices);
  44
  45/*
  46 * PCI Bus Class Devices
  47 */
  48static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
  49                                        int type,
  50                                        struct device_attribute *attr,
  51                                        char *buf)
  52{
  53        int ret;
  54        const struct cpumask *cpumask;
  55
  56        cpumask = cpumask_of_pcibus(to_pci_bus(dev));
  57        ret = type?
  58                cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask) :
  59                cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
  60        buf[ret++] = '\n';
  61        buf[ret] = '\0';
  62        return ret;
  63}
  64
  65static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev,
  66                                        struct device_attribute *attr,
  67                                        char *buf)
  68{
  69        return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
  70}
  71
  72static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev,
  73                                        struct device_attribute *attr,
  74                                        char *buf)
  75{
  76        return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
  77}
  78
  79DEVICE_ATTR(cpuaffinity,     S_IRUGO, pci_bus_show_cpumaskaffinity, NULL);
  80DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL);
  81
  82/*
  83 * PCI Bus Class
  84 */
  85static void release_pcibus_dev(struct device *dev)
  86{
  87        struct pci_bus *pci_bus = to_pci_bus(dev);
  88
  89        if (pci_bus->bridge)
  90                put_device(pci_bus->bridge);
  91        pci_bus_remove_resources(pci_bus);
  92        kfree(pci_bus);
  93}
  94
  95static struct class pcibus_class = {
  96        .name           = "pci_bus",
  97        .dev_release    = &release_pcibus_dev,
  98};
  99
 100static int __init pcibus_class_init(void)
 101{
 102        return class_register(&pcibus_class);
 103}
 104postcore_initcall(pcibus_class_init);
 105
 106/*
 107 * Translate the low bits of the PCI base
 108 * to the resource type
 109 */
 110static inline unsigned int pci_calc_resource_flags(unsigned int flags)
 111{
 112        if (flags & PCI_BASE_ADDRESS_SPACE_IO)
 113                return IORESOURCE_IO;
 114
 115        if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
 116                return IORESOURCE_MEM | IORESOURCE_PREFETCH;
 117
 118        return IORESOURCE_MEM;
 119}
 120
 121static u64 pci_size(u64 base, u64 maxbase, u64 mask)
 122{
 123        u64 size = mask & maxbase;      /* Find the significant bits */
 124        if (!size)
 125                return 0;
 126
 127        /* Get the lowest of them to find the decode size, and
 128           from that the extent.  */
 129        size = (size & ~(size-1)) - 1;
 130
 131        /* base == maxbase can be valid only if the BAR has
 132           already been programmed with all 1s.  */
 133        if (base == maxbase && ((base | size) & mask) != mask)
 134                return 0;
 135
 136        return size;
 137}
 138
 139static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
 140{
 141        if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
 142                res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
 143                return pci_bar_io;
 144        }
 145
 146        res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
 147
 148        if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
 149                return pci_bar_mem64;
 150        return pci_bar_mem32;
 151}
 152
 153/**
 154 * pci_read_base - read a PCI BAR
 155 * @dev: the PCI device
 156 * @type: type of the BAR
 157 * @res: resource buffer to be filled in
 158 * @pos: BAR position in the config space
 159 *
 160 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
 161 */
 162int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
 163                        struct resource *res, unsigned int pos)
 164{
 165        u32 l, sz, mask;
 166        u16 orig_cmd;
 167
 168        mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
 169
 170        if (!dev->mmio_always_on) {
 171                pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
 172                pci_write_config_word(dev, PCI_COMMAND,
 173                        orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
 174        }
 175
 176        res->name = pci_name(dev);
 177
 178        pci_read_config_dword(dev, pos, &l);
 179        pci_write_config_dword(dev, pos, l | mask);
 180        pci_read_config_dword(dev, pos, &sz);
 181        pci_write_config_dword(dev, pos, l);
 182
 183        if (!dev->mmio_always_on)
 184                pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
 185
 186        /*
 187         * All bits set in sz means the device isn't working properly.
 188         * If the BAR isn't implemented, all bits must be 0.  If it's a
 189         * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
 190         * 1 must be clear.
 191         */
 192        if (!sz || sz == 0xffffffff)
 193                goto fail;
 194
 195        /*
 196         * I don't know how l can have all bits set.  Copied from old code.
 197         * Maybe it fixes a bug on some ancient platform.
 198         */
 199        if (l == 0xffffffff)
 200                l = 0;
 201
 202        if (type == pci_bar_unknown) {
 203                type = decode_bar(res, l);
 204                res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
 205                if (type == pci_bar_io) {
 206                        l &= PCI_BASE_ADDRESS_IO_MASK;
 207                        mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;
 208                } else {
 209                        l &= PCI_BASE_ADDRESS_MEM_MASK;
 210                        mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
 211                }
 212        } else {
 213                res->flags |= (l & IORESOURCE_ROM_ENABLE);
 214                l &= PCI_ROM_ADDRESS_MASK;
 215                mask = (u32)PCI_ROM_ADDRESS_MASK;
 216        }
 217
 218        if (type == pci_bar_mem64) {
 219                u64 l64 = l;
 220                u64 sz64 = sz;
 221                u64 mask64 = mask | (u64)~0 << 32;
 222
 223                pci_read_config_dword(dev, pos + 4, &l);
 224                pci_write_config_dword(dev, pos + 4, ~0);
 225                pci_read_config_dword(dev, pos + 4, &sz);
 226                pci_write_config_dword(dev, pos + 4, l);
 227
 228                l64 |= ((u64)l << 32);
 229                sz64 |= ((u64)sz << 32);
 230
 231                sz64 = pci_size(l64, sz64, mask64);
 232
 233                if (!sz64)
 234                        goto fail;
 235
 236                if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
 237                        dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n",
 238                                pos);
 239                        goto fail;
 240                }
 241
 242                res->flags |= IORESOURCE_MEM_64;
 243                if ((sizeof(resource_size_t) < 8) && l) {
 244                        /* Address above 32-bit boundary; disable the BAR */
 245                        pci_write_config_dword(dev, pos, 0);
 246                        pci_write_config_dword(dev, pos + 4, 0);
 247                        res->start = 0;
 248                        res->end = sz64;
 249                } else {
 250                        res->start = l64;
 251                        res->end = l64 + sz64;
 252                        dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
 253                                   pos, res);
 254                }
 255        } else {
 256                sz = pci_size(l, sz, mask);
 257
 258                if (!sz)
 259                        goto fail;
 260
 261                res->start = l;
 262                res->end = l + sz;
 263
 264                dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
 265        }
 266
 267 out:
 268        return (type == pci_bar_mem64) ? 1 : 0;
 269 fail:
 270        res->flags = 0;
 271        goto out;
 272}
 273
 274static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
 275{
 276        unsigned int pos, reg;
 277
 278        for (pos = 0; pos < howmany; pos++) {
 279                struct resource *res = &dev->resource[pos];
 280                reg = PCI_BASE_ADDRESS_0 + (pos << 2);
 281                pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
 282        }
 283
 284        if (rom) {
 285                struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
 286                dev->rom_base_reg = rom;
 287                res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
 288                                IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
 289                                IORESOURCE_SIZEALIGN;
 290                __pci_read_base(dev, pci_bar_mem32, res, rom);
 291        }
 292}
 293
 294static void __devinit pci_read_bridge_io(struct pci_bus *child)
 295{
 296        struct pci_dev *dev = child->self;
 297        u8 io_base_lo, io_limit_lo;
 298        unsigned long base, limit;
 299        struct resource *res;
 300
 301        res = child->resource[0];
 302        pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
 303        pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
 304        base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
 305        limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
 306
 307        if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
 308                u16 io_base_hi, io_limit_hi;
 309                pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
 310                pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
 311                base |= (io_base_hi << 16);
 312                limit |= (io_limit_hi << 16);
 313        }
 314
 315        if (base && base <= limit) {
 316                res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
 317                if (!res->start)
 318                        res->start = base;
 319                if (!res->end)
 320                        res->end = limit + 0xfff;
 321                dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
 322        } else {
 323                dev_printk(KERN_DEBUG, &dev->dev,
 324                         "  bridge window [io  %#06lx-%#06lx] (disabled)\n",
 325                                 base, limit);
 326        }
 327}
 328
 329static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
 330{
 331        struct pci_dev *dev = child->self;
 332        u16 mem_base_lo, mem_limit_lo;
 333        unsigned long base, limit;
 334        struct resource *res;
 335
 336        res = child->resource[1];
 337        pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
 338        pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
 339        base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
 340        limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
 341        if (base && base <= limit) {
 342                res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
 343                res->start = base;
 344                res->end = limit + 0xfffff;
 345                dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
 346        } else {
 347                dev_printk(KERN_DEBUG, &dev->dev,
 348                        "  bridge window [mem %#010lx-%#010lx] (disabled)\n",
 349                                         base, limit + 0xfffff);
 350        }
 351}
 352
 353static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
 354{
 355        struct pci_dev *dev = child->self;
 356        u16 mem_base_lo, mem_limit_lo;
 357        unsigned long base, limit;
 358        struct resource *res;
 359
 360        res = child->resource[2];
 361        pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
 362        pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
 363        base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
 364        limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
 365
 366        if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
 367                u32 mem_base_hi, mem_limit_hi;
 368                pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
 369                pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
 370
 371                /*
 372                 * Some bridges set the base > limit by default, and some
 373                 * (broken) BIOSes do not initialize them.  If we find
 374                 * this, just assume they are not being used.
 375                 */
 376                if (mem_base_hi <= mem_limit_hi) {
 377#if BITS_PER_LONG == 64
 378                        base |= ((long) mem_base_hi) << 32;
 379                        limit |= ((long) mem_limit_hi) << 32;
 380#else
 381                        if (mem_base_hi || mem_limit_hi) {
 382                                dev_err(&dev->dev, "can't handle 64-bit "
 383                                        "address space for bridge\n");
 384                                return;
 385                        }
 386#endif
 387                }
 388        }
 389        if (base && base <= limit) {
 390                res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
 391                                         IORESOURCE_MEM | IORESOURCE_PREFETCH;
 392                if (res->flags & PCI_PREF_RANGE_TYPE_64)
 393                        res->flags |= IORESOURCE_MEM_64;
 394                res->start = base;
 395                res->end = limit + 0xfffff;
 396                dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
 397        } else {
 398                dev_printk(KERN_DEBUG, &dev->dev,
 399                     "  bridge window [mem %#010lx-%#010lx pref] (disabled)\n",
 400                                         base, limit + 0xfffff);
 401        }
 402}
 403
 404void __devinit pci_read_bridge_bases(struct pci_bus *child)
 405{
 406        struct pci_dev *dev = child->self;
 407        struct resource *res;
 408        int i;
 409
 410        if (pci_is_root_bus(child))     /* It's a host bus, nothing to read */
 411                return;
 412
 413        dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n",
 414                 child->secondary, child->subordinate,
 415                 dev->transparent ? " (subtractive decode)" : "");
 416
 417        pci_bus_remove_resources(child);
 418        for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
 419                child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
 420
 421        pci_read_bridge_io(child);
 422        pci_read_bridge_mmio(child);
 423        pci_read_bridge_mmio_pref(child);
 424
 425        if (dev->transparent) {
 426                pci_bus_for_each_resource(child->parent, res, i) {
 427                        if (res) {
 428                                pci_bus_add_resource(child, res,
 429                                                     PCI_SUBTRACTIVE_DECODE);
 430                                dev_printk(KERN_DEBUG, &dev->dev,
 431                                           "  bridge window %pR (subtractive decode)\n",
 432                                           res);
 433                        }
 434                }
 435        }
 436}
 437
 438static struct pci_bus * pci_alloc_bus(void)
 439{
 440        struct pci_bus *b;
 441
 442        b = kzalloc(sizeof(*b), GFP_KERNEL);
 443        if (b) {
 444                INIT_LIST_HEAD(&b->node);
 445                INIT_LIST_HEAD(&b->children);
 446                INIT_LIST_HEAD(&b->devices);
 447                INIT_LIST_HEAD(&b->slots);
 448                INIT_LIST_HEAD(&b->resources);
 449                b->max_bus_speed = PCI_SPEED_UNKNOWN;
 450                b->cur_bus_speed = PCI_SPEED_UNKNOWN;
 451        }
 452        return b;
 453}
 454
 455static unsigned char pcix_bus_speed[] = {
 456        PCI_SPEED_UNKNOWN,              /* 0 */
 457        PCI_SPEED_66MHz_PCIX,           /* 1 */
 458        PCI_SPEED_100MHz_PCIX,          /* 2 */
 459        PCI_SPEED_133MHz_PCIX,          /* 3 */
 460        PCI_SPEED_UNKNOWN,              /* 4 */
 461        PCI_SPEED_66MHz_PCIX_ECC,       /* 5 */
 462        PCI_SPEED_100MHz_PCIX_ECC,      /* 6 */
 463        PCI_SPEED_133MHz_PCIX_ECC,      /* 7 */
 464        PCI_SPEED_UNKNOWN,              /* 8 */
 465        PCI_SPEED_66MHz_PCIX_266,       /* 9 */
 466        PCI_SPEED_100MHz_PCIX_266,      /* A */
 467        PCI_SPEED_133MHz_PCIX_266,      /* B */
 468        PCI_SPEED_UNKNOWN,              /* C */
 469        PCI_SPEED_66MHz_PCIX_533,       /* D */
 470        PCI_SPEED_100MHz_PCIX_533,      /* E */
 471        PCI_SPEED_133MHz_PCIX_533       /* F */
 472};
 473
 474static unsigned char pcie_link_speed[] = {
 475        PCI_SPEED_UNKNOWN,              /* 0 */
 476        PCIE_SPEED_2_5GT,               /* 1 */
 477        PCIE_SPEED_5_0GT,               /* 2 */
 478        PCIE_SPEED_8_0GT,               /* 3 */
 479        PCI_SPEED_UNKNOWN,              /* 4 */
 480        PCI_SPEED_UNKNOWN,              /* 5 */
 481        PCI_SPEED_UNKNOWN,              /* 6 */
 482        PCI_SPEED_UNKNOWN,              /* 7 */
 483        PCI_SPEED_UNKNOWN,              /* 8 */
 484        PCI_SPEED_UNKNOWN,              /* 9 */
 485        PCI_SPEED_UNKNOWN,              /* A */
 486        PCI_SPEED_UNKNOWN,              /* B */
 487        PCI_SPEED_UNKNOWN,              /* C */
 488        PCI_SPEED_UNKNOWN,              /* D */
 489        PCI_SPEED_UNKNOWN,              /* E */
 490        PCI_SPEED_UNKNOWN               /* F */
 491};
 492
 493void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
 494{
 495        bus->cur_bus_speed = pcie_link_speed[linksta & 0xf];
 496}
 497EXPORT_SYMBOL_GPL(pcie_update_link_speed);
 498
 499static unsigned char agp_speeds[] = {
 500        AGP_UNKNOWN,
 501        AGP_1X,
 502        AGP_2X,
 503        AGP_4X,
 504        AGP_8X
 505};
 506
 507static enum pci_bus_speed agp_speed(int agp3, int agpstat)
 508{
 509        int index = 0;
 510
 511        if (agpstat & 4)
 512                index = 3;
 513        else if (agpstat & 2)
 514                index = 2;
 515        else if (agpstat & 1)
 516                index = 1;
 517        else
 518                goto out;
 519        
 520        if (agp3) {
 521                index += 2;
 522                if (index == 5)
 523                        index = 0;
 524        }
 525
 526 out:
 527        return agp_speeds[index];
 528}
 529
 530
 531static void pci_set_bus_speed(struct pci_bus *bus)
 532{
 533        struct pci_dev *bridge = bus->self;
 534        int pos;
 535
 536        pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
 537        if (!pos)
 538                pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
 539        if (pos) {
 540                u32 agpstat, agpcmd;
 541
 542                pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
 543                bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
 544
 545                pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
 546                bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
 547        }
 548
 549        pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
 550        if (pos) {
 551                u16 status;
 552                enum pci_bus_speed max;
 553                pci_read_config_word(bridge, pos + 2, &status);
 554
 555                if (status & 0x8000) {
 556                        max = PCI_SPEED_133MHz_PCIX_533;
 557                } else if (status & 0x4000) {
 558                        max = PCI_SPEED_133MHz_PCIX_266;
 559                } else if (status & 0x0002) {
 560                        if (((status >> 12) & 0x3) == 2) {
 561                                max = PCI_SPEED_133MHz_PCIX_ECC;
 562                        } else {
 563                                max = PCI_SPEED_133MHz_PCIX;
 564                        }
 565                } else {
 566                        max = PCI_SPEED_66MHz_PCIX;
 567                }
 568
 569                bus->max_bus_speed = max;
 570                bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
 571
 572                return;
 573        }
 574
 575        pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
 576        if (pos) {
 577                u32 linkcap;
 578                u16 linksta;
 579
 580                pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
 581                bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
 582
 583                pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
 584                pcie_update_link_speed(bus, linksta);
 585        }
 586}
 587
 588
 589static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
 590                                           struct pci_dev *bridge, int busnr)
 591{
 592        struct pci_bus *child;
 593        int i;
 594
 595        /*
 596         * Allocate a new bus, and inherit stuff from the parent..
 597         */
 598        child = pci_alloc_bus();
 599        if (!child)
 600                return NULL;
 601
 602        child->parent = parent;
 603        child->ops = parent->ops;
 604        child->sysdata = parent->sysdata;
 605        child->bus_flags = parent->bus_flags;
 606
 607        /* initialize some portions of the bus device, but don't register it
 608         * now as the parent is not properly set up yet.  This device will get
 609         * registered later in pci_bus_add_devices()
 610         */
 611        child->dev.class = &pcibus_class;
 612        dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
 613
 614        /*
 615         * Set up the primary, secondary and subordinate
 616         * bus numbers.
 617         */
 618        child->number = child->secondary = busnr;
 619        child->primary = parent->secondary;
 620        child->subordinate = 0xff;
 621
 622        if (!bridge)
 623                return child;
 624
 625        child->self = bridge;
 626        child->bridge = get_device(&bridge->dev);
 627
 628        pci_set_bus_speed(child);
 629
 630        /* Set up default resource pointers and names.. */
 631        for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
 632                child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
 633                child->resource[i]->name = child->name;
 634        }
 635        bridge->subordinate = child;
 636
 637        return child;
 638}
 639
 640struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
 641{
 642        struct pci_bus *child;
 643
 644        child = pci_alloc_child_bus(parent, dev, busnr);
 645        if (child) {
 646                down_write(&pci_bus_sem);
 647                list_add_tail(&child->node, &parent->children);
 648                up_write(&pci_bus_sem);
 649        }
 650        return child;
 651}
 652
 653static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
 654{
 655        struct pci_bus *parent = child->parent;
 656
 657        /* Attempts to fix that up are really dangerous unless
 658           we're going to re-assign all bus numbers. */
 659        if (!pcibios_assign_all_busses())
 660                return;
 661
 662        while (parent->parent && parent->subordinate < max) {
 663                parent->subordinate = max;
 664                pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
 665                parent = parent->parent;
 666        }
 667}
 668
 669/*
 670 * If it's a bridge, configure it and scan the bus behind it.
 671 * For CardBus bridges, we don't scan behind as the devices will
 672 * be handled by the bridge driver itself.
 673 *
 674 * We need to process bridges in two passes -- first we scan those
 675 * already configured by the BIOS and after we are done with all of
 676 * them, we proceed to assigning numbers to the remaining buses in
 677 * order to avoid overlaps between old and new bus numbers.
 678 */
 679int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
 680{
 681        struct pci_bus *child;
 682        int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
 683        u32 buses, i, j = 0;
 684        u16 bctl;
 685        u8 primary, secondary, subordinate;
 686        int broken = 0;
 687
 688        pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
 689        primary = buses & 0xFF;
 690        secondary = (buses >> 8) & 0xFF;
 691        subordinate = (buses >> 16) & 0xFF;
 692
 693        dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
 694                secondary, subordinate, pass);
 695
 696        /* Check if setup is sensible at all */
 697        if (!pass &&
 698            (primary != bus->number || secondary <= bus->number)) {
 699                dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
 700                broken = 1;
 701        }
 702
 703        /* Disable MasterAbortMode during probing to avoid reporting
 704           of bus errors (in some architectures) */ 
 705        pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
 706        pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
 707                              bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
 708
 709        if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
 710            !is_cardbus && !broken) {
 711                unsigned int cmax;
 712                /*
 713                 * Bus already configured by firmware, process it in the first
 714                 * pass and just note the configuration.
 715                 */
 716                if (pass)
 717                        goto out;
 718
 719                /*
 720                 * If we already got to this bus through a different bridge,
 721                 * don't re-add it. This can happen with the i450NX chipset.
 722                 *
 723                 * However, we continue to descend down the hierarchy and
 724                 * scan remaining child buses.
 725                 */
 726                child = pci_find_bus(pci_domain_nr(bus), secondary);
 727                if (!child) {
 728                        child = pci_add_new_bus(bus, dev, secondary);
 729                        if (!child)
 730                                goto out;
 731                        child->primary = primary;
 732                        child->subordinate = subordinate;
 733                        child->bridge_ctl = bctl;
 734                }
 735
 736                cmax = pci_scan_child_bus(child);
 737                if (cmax > max)
 738                        max = cmax;
 739                if (child->subordinate > max)
 740                        max = child->subordinate;
 741        } else {
 742                /*
 743                 * We need to assign a number to this bus which we always
 744                 * do in the second pass.
 745                 */
 746                if (!pass) {
 747                        if (pcibios_assign_all_busses() || broken)
 748                                /* Temporarily disable forwarding of the
 749                                   configuration cycles on all bridges in
 750                                   this bus segment to avoid possible
 751                                   conflicts in the second pass between two
 752                                   bridges programmed with overlapping
 753                                   bus ranges. */
 754                                pci_write_config_dword(dev, PCI_PRIMARY_BUS,
 755                                                       buses & ~0xffffff);
 756                        goto out;
 757                }
 758
 759                /* Clear errors */
 760                pci_write_config_word(dev, PCI_STATUS, 0xffff);
 761
 762                /* Prevent assigning a bus number that already exists.
 763                 * This can happen when a bridge is hot-plugged */
 764                if (pci_find_bus(pci_domain_nr(bus), max+1))
 765                        goto out;
 766                child = pci_add_new_bus(bus, dev, ++max);
 767                if (!child)
 768                        goto out;
 769                buses = (buses & 0xff000000)
 770                      | ((unsigned int)(child->primary)     <<  0)
 771                      | ((unsigned int)(child->secondary)   <<  8)
 772                      | ((unsigned int)(child->subordinate) << 16);
 773
 774                /*
 775                 * yenta.c forces a secondary latency timer of 176.
 776                 * Copy that behaviour here.
 777                 */
 778                if (is_cardbus) {
 779                        buses &= ~0xff000000;
 780                        buses |= CARDBUS_LATENCY_TIMER << 24;
 781                }
 782
 783                /*
 784                 * We need to blast all three values with a single write.
 785                 */
 786                pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
 787
 788                if (!is_cardbus) {
 789                        child->bridge_ctl = bctl;
 790                        /*
 791                         * Adjust subordinate busnr in parent buses.
 792                         * We do this before scanning for children because
 793                         * some devices may not be detected if the bios
 794                         * was lazy.
 795                         */
 796                        pci_fixup_parent_subordinate_busnr(child, max);
 797                        /* Now we can scan all subordinate buses... */
 798                        max = pci_scan_child_bus(child);
 799                        /*
 800                         * now fix it up again since we have found
 801                         * the real value of max.
 802                         */
 803                        pci_fixup_parent_subordinate_busnr(child, max);
 804                } else {
 805                        /*
 806                         * For CardBus bridges, we leave 4 bus numbers
 807                         * as cards with a PCI-to-PCI bridge can be
 808                         * inserted later.
 809                         */
 810                        for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
 811                                struct pci_bus *parent = bus;
 812                                if (pci_find_bus(pci_domain_nr(bus),
 813                                                        max+i+1))
 814                                        break;
 815                                while (parent->parent) {
 816                                        if ((!pcibios_assign_all_busses()) &&
 817                                            (parent->subordinate > max) &&
 818                                            (parent->subordinate <= max+i)) {
 819                                                j = 1;
 820                                        }
 821                                        parent = parent->parent;
 822                                }
 823                                if (j) {
 824                                        /*
 825                                         * Often, there are two cardbus bridges
 826                                         * -- try to leave one valid bus number
 827                                         * for each one.
 828                                         */
 829                                        i /= 2;
 830                                        break;
 831                                }
 832                        }
 833                        max += i;
 834                        pci_fixup_parent_subordinate_busnr(child, max);
 835                }
 836                /*
 837                 * Set the subordinate bus number to its real value.
 838                 */
 839                child->subordinate = max;
 840                pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
 841        }
 842
 843        sprintf(child->name,
 844                (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
 845                pci_domain_nr(bus), child->number);
 846
 847        /* Has only triggered on CardBus, fixup is in yenta_socket */
 848        while (bus->parent) {
 849                if ((child->subordinate > bus->subordinate) ||
 850                    (child->number > bus->subordinate) ||
 851                    (child->number < bus->number) ||
 852                    (child->subordinate < bus->number)) {
 853                        dev_info(&child->dev, "[bus %02x-%02x] %s "
 854                                "hidden behind%s bridge %s [bus %02x-%02x]\n",
 855                                child->number, child->subordinate,
 856                                (bus->number > child->subordinate &&
 857                                 bus->subordinate < child->number) ?
 858                                        "wholly" : "partially",
 859                                bus->self->transparent ? " transparent" : "",
 860                                dev_name(&bus->dev),
 861                                bus->number, bus->subordinate);
 862                }
 863                bus = bus->parent;
 864        }
 865
 866out:
 867        pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
 868
 869        return max;
 870}
 871
 872/*
 873 * Read interrupt line and base address registers.
 874 * The architecture-dependent code can tweak these, of course.
 875 */
 876static void pci_read_irq(struct pci_dev *dev)
 877{
 878        unsigned char irq;
 879
 880        pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
 881        dev->pin = irq;
 882        if (irq)
 883                pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 884        dev->irq = irq;
 885}
 886
 887void set_pcie_port_type(struct pci_dev *pdev)
 888{
 889        int pos;
 890        u16 reg16;
 891
 892        pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
 893        if (!pos)
 894                return;
 895        pdev->is_pcie = 1;
 896        pdev->pcie_cap = pos;
 897        pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
 898        pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
 899}
 900
 901void set_pcie_hotplug_bridge(struct pci_dev *pdev)
 902{
 903        int pos;
 904        u16 reg16;
 905        u32 reg32;
 906
 907        pos = pci_pcie_cap(pdev);
 908        if (!pos)
 909                return;
 910        pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
 911        if (!(reg16 & PCI_EXP_FLAGS_SLOT))
 912                return;
 913        pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &reg32);
 914        if (reg32 & PCI_EXP_SLTCAP_HPC)
 915                pdev->is_hotplug_bridge = 1;
 916}
 917
 918#define LEGACY_IO_RESOURCE      (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
 919
 920/**
 921 * pci_setup_device - fill in class and map information of a device
 922 * @dev: the device structure to fill
 923 *
 924 * Initialize the device structure with information about the device's 
 925 * vendor,class,memory and IO-space addresses,IRQ lines etc.
 926 * Called at initialisation of the PCI subsystem and by CardBus services.
 927 * Returns 0 on success and negative if unknown type of device (not normal,
 928 * bridge or CardBus).
 929 */
 930int pci_setup_device(struct pci_dev *dev)
 931{
 932        u32 class;
 933        u8 hdr_type;
 934        struct pci_slot *slot;
 935        int pos = 0;
 936
 937        if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
 938                return -EIO;
 939
 940        dev->sysdata = dev->bus->sysdata;
 941        dev->dev.parent = dev->bus->bridge;
 942        dev->dev.bus = &pci_bus_type;
 943        dev->hdr_type = hdr_type & 0x7f;
 944        dev->multifunction = !!(hdr_type & 0x80);
 945        dev->error_state = pci_channel_io_normal;
 946        set_pcie_port_type(dev);
 947
 948        list_for_each_entry(slot, &dev->bus->slots, list)
 949                if (PCI_SLOT(dev->devfn) == slot->number)
 950                        dev->slot = slot;
 951
 952        /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
 953           set this higher, assuming the system even supports it.  */
 954        dev->dma_mask = 0xffffffff;
 955
 956        dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
 957                     dev->bus->number, PCI_SLOT(dev->devfn),
 958                     PCI_FUNC(dev->devfn));
 959
 960        pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
 961        dev->revision = class & 0xff;
 962        class >>= 8;                                /* upper 3 bytes */
 963        dev->class = class;
 964        class >>= 8;
 965
 966        dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %d class %#08x\n",
 967                   dev->vendor, dev->device, dev->hdr_type, class);
 968
 969        /* need to have dev->class ready */
 970        dev->cfg_size = pci_cfg_space_size(dev);
 971
 972        /* "Unknown power state" */
 973        dev->current_state = PCI_UNKNOWN;
 974
 975        /* Early fixups, before probing the BARs */
 976        pci_fixup_device(pci_fixup_early, dev);
 977        /* device class may be changed after fixup */
 978        class = dev->class >> 8;
 979
 980        switch (dev->hdr_type) {                    /* header type */
 981        case PCI_HEADER_TYPE_NORMAL:                /* standard header */
 982                if (class == PCI_CLASS_BRIDGE_PCI)
 983                        goto bad;
 984                pci_read_irq(dev);
 985                pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
 986                pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
 987                pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
 988
 989                /*
 990                 *      Do the ugly legacy mode stuff here rather than broken chip
 991                 *      quirk code. Legacy mode ATA controllers have fixed
 992                 *      addresses. These are not always echoed in BAR0-3, and
 993                 *      BAR0-3 in a few cases contain junk!
 994                 */
 995                if (class == PCI_CLASS_STORAGE_IDE) {
 996                        u8 progif;
 997                        pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
 998                        if ((progif & 1) == 0) {
 999                                dev->resource[0].start = 0x1F0;
1000                                dev->resource[0].end = 0x1F7;
1001                                dev->resource[0].flags = LEGACY_IO_RESOURCE;
1002                                dev->resource[1].start = 0x3F6;
1003                                dev->resource[1].end = 0x3F6;
1004                                dev->resource[1].flags = LEGACY_IO_RESOURCE;
1005                        }
1006                        if ((progif & 4) == 0) {
1007                                dev->resource[2].start = 0x170;
1008                                dev->resource[2].end = 0x177;
1009                                dev->resource[2].flags = LEGACY_IO_RESOURCE;
1010                                dev->resource[3].start = 0x376;
1011                                dev->resource[3].end = 0x376;
1012                                dev->resource[3].flags = LEGACY_IO_RESOURCE;
1013                        }
1014                }
1015                break;
1016
1017        case PCI_HEADER_TYPE_BRIDGE:                /* bridge header */
1018                if (class != PCI_CLASS_BRIDGE_PCI)
1019                        goto bad;
1020                /* The PCI-to-PCI bridge spec requires that subtractive
1021                   decoding (i.e. transparent) bridge must have programming
1022                   interface code of 0x01. */ 
1023                pci_read_irq(dev);
1024                dev->transparent = ((dev->class & 0xff) == 1);
1025                pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1026                set_pcie_hotplug_bridge(dev);
1027                pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1028                if (pos) {
1029                        pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1030                        pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1031                }
1032                break;
1033
1034        case PCI_HEADER_TYPE_CARDBUS:               /* CardBus bridge header */
1035                if (class != PCI_CLASS_BRIDGE_CARDBUS)
1036                        goto bad;
1037                pci_read_irq(dev);
1038                pci_read_bases(dev, 1, 0);
1039                pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1040                pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1041                break;
1042
1043        default:                                    /* unknown header */
1044                dev_err(&dev->dev, "unknown header type %02x, "
1045                        "ignoring device\n", dev->hdr_type);
1046                return -EIO;
1047
1048        bad:
1049                dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
1050                        "type %02x)\n", class, dev->hdr_type);
1051                dev->class = PCI_CLASS_NOT_DEFINED;
1052        }
1053
1054        /* We found a fine healthy device, go go go... */
1055        return 0;
1056}
1057
1058static void pci_release_capabilities(struct pci_dev *dev)
1059{
1060        pci_vpd_release(dev);
1061        pci_iov_release(dev);
1062}
1063
1064/**
1065 * pci_release_dev - free a pci device structure when all users of it are finished.
1066 * @dev: device that's been disconnected
1067 *
1068 * Will be called only by the device core when all users of this pci device are
1069 * done.
1070 */
1071static void pci_release_dev(struct device *dev)
1072{
1073        struct pci_dev *pci_dev;
1074
1075        pci_dev = to_pci_dev(dev);
1076        pci_release_capabilities(pci_dev);
1077        kfree(pci_dev);
1078}
1079
1080/**
1081 * pci_cfg_space_size - get the configuration space size of the PCI device.
1082 * @dev: PCI device
1083 *
1084 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1085 * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
1086 * access it.  Maybe we don't have a way to generate extended config space
1087 * accesses, or the device is behind a reverse Express bridge.  So we try
1088 * reading the dword at 0x100 which must either be 0 or a valid extended
1089 * capability header.
1090 */
1091int pci_cfg_space_size_ext(struct pci_dev *dev)
1092{
1093        u32 status;
1094        int pos = PCI_CFG_SPACE_SIZE;
1095
1096        if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1097                goto fail;
1098        if (status == 0xffffffff)
1099                goto fail;
1100
1101        return PCI_CFG_SPACE_EXP_SIZE;
1102
1103 fail:
1104        return PCI_CFG_SPACE_SIZE;
1105}
1106
1107int pci_cfg_space_size(struct pci_dev *dev)
1108{
1109        int pos;
1110        u32 status;
1111        u16 class;
1112
1113        class = dev->class >> 8;
1114        if (class == PCI_CLASS_BRIDGE_HOST)
1115                return pci_cfg_space_size_ext(dev);
1116
1117        pos = pci_pcie_cap(dev);
1118        if (!pos) {
1119                pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1120                if (!pos)
1121                        goto fail;
1122
1123                pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1124                if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1125                        goto fail;
1126        }
1127
1128        return pci_cfg_space_size_ext(dev);
1129
1130 fail:
1131        return PCI_CFG_SPACE_SIZE;
1132}
1133
1134static void pci_release_bus_bridge_dev(struct device *dev)
1135{
1136        kfree(dev);
1137}
1138
1139struct pci_dev *alloc_pci_dev(void)
1140{
1141        struct pci_dev *dev;
1142
1143        dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1144        if (!dev)
1145                return NULL;
1146
1147        INIT_LIST_HEAD(&dev->bus_list);
1148
1149        return dev;
1150}
1151EXPORT_SYMBOL(alloc_pci_dev);
1152
1153/*
1154 * Read the config data for a PCI device, sanity-check it
1155 * and fill in the dev structure...
1156 */
1157static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1158{
1159        struct pci_dev *dev;
1160        u32 l;
1161        int delay = 1;
1162
1163        if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1164                return NULL;
1165
1166        /* some broken boards return 0 or ~0 if a slot is empty: */
1167        if (l == 0xffffffff || l == 0x00000000 ||
1168            l == 0x0000ffff || l == 0xffff0000)
1169                return NULL;
1170
1171        /* Configuration request Retry Status */
1172        while (l == 0xffff0001) {
1173                msleep(delay);
1174                delay *= 2;
1175                if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1176                        return NULL;
1177                /* Card hasn't responded in 60 seconds?  Must be stuck. */
1178                if (delay > 60 * 1000) {
1179                        printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
1180                                        "responding\n", pci_domain_nr(bus),
1181                                        bus->number, PCI_SLOT(devfn),
1182                                        PCI_FUNC(devfn));
1183                        return NULL;
1184                }
1185        }
1186
1187        dev = alloc_pci_dev();
1188        if (!dev)
1189                return NULL;
1190
1191        dev->bus = bus;
1192        dev->devfn = devfn;
1193        dev->vendor = l & 0xffff;
1194        dev->device = (l >> 16) & 0xffff;
1195
1196        if (pci_setup_device(dev)) {
1197                kfree(dev);
1198                return NULL;
1199        }
1200
1201        return dev;
1202}
1203
1204static void pci_init_capabilities(struct pci_dev *dev)
1205{
1206        /* MSI/MSI-X list */
1207        pci_msi_init_pci_dev(dev);
1208
1209        /* Buffers for saving PCIe and PCI-X capabilities */
1210        pci_allocate_cap_save_buffers(dev);
1211
1212        /* Power Management */
1213        pci_pm_init(dev);
1214        platform_pci_wakeup_init(dev);
1215
1216        /* Vital Product Data */
1217        pci_vpd_pci22_init(dev);
1218
1219        /* Alternative Routing-ID Forwarding */
1220        pci_enable_ari(dev);
1221
1222        /* Single Root I/O Virtualization */
1223        pci_iov_init(dev);
1224
1225        /* Enable ACS P2P upstream forwarding */
1226        pci_enable_acs(dev);
1227}
1228
1229void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1230{
1231        device_initialize(&dev->dev);
1232        dev->dev.release = pci_release_dev;
1233        pci_dev_get(dev);
1234
1235        dev->dev.dma_mask = &dev->dma_mask;
1236        dev->dev.dma_parms = &dev->dma_parms;
1237        dev->dev.coherent_dma_mask = 0xffffffffull;
1238
1239        pci_set_dma_max_seg_size(dev, 65536);
1240        pci_set_dma_seg_boundary(dev, 0xffffffff);
1241
1242        /* Fix up broken headers */
1243        pci_fixup_device(pci_fixup_header, dev);
1244
1245        /* Clear the state_saved flag. */
1246        dev->state_saved = false;
1247
1248        /* Initialize various capabilities */
1249        pci_init_capabilities(dev);
1250
1251        /*
1252         * Add the device to our list of discovered devices
1253         * and the bus list for fixup functions, etc.
1254         */
1255        down_write(&pci_bus_sem);
1256        list_add_tail(&dev->bus_list, &bus->devices);
1257        up_write(&pci_bus_sem);
1258}
1259
1260struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1261{
1262        struct pci_dev *dev;
1263
1264        dev = pci_get_slot(bus, devfn);
1265        if (dev) {
1266                pci_dev_put(dev);
1267                return dev;
1268        }
1269
1270        dev = pci_scan_device(bus, devfn);
1271        if (!dev)
1272                return NULL;
1273
1274        pci_device_add(dev, bus);
1275
1276        return dev;
1277}
1278EXPORT_SYMBOL(pci_scan_single_device);
1279
1280static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
1281{
1282        u16 cap;
1283        unsigned pos, next_fn;
1284
1285        if (!dev)
1286                return 0;
1287
1288        pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1289        if (!pos)
1290                return 0;
1291        pci_read_config_word(dev, pos + 4, &cap);
1292        next_fn = cap >> 8;
1293        if (next_fn <= fn)
1294                return 0;
1295        return next_fn;
1296}
1297
1298static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
1299{
1300        return (fn + 1) % 8;
1301}
1302
1303static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
1304{
1305        return 0;
1306}
1307
1308static int only_one_child(struct pci_bus *bus)
1309{
1310        struct pci_dev *parent = bus->self;
1311        if (!parent || !pci_is_pcie(parent))
1312                return 0;
1313        if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
1314            parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
1315                return 1;
1316        return 0;
1317}
1318
1319/**
1320 * pci_scan_slot - scan a PCI slot on a bus for devices.
1321 * @bus: PCI bus to scan
1322 * @devfn: slot number to scan (must have zero function.)
1323 *
1324 * Scan a PCI slot on the specified PCI bus for devices, adding
1325 * discovered devices to the @bus->devices list.  New devices
1326 * will not have is_added set.
1327 *
1328 * Returns the number of new devices found.
1329 */
1330int pci_scan_slot(struct pci_bus *bus, int devfn)
1331{
1332        unsigned fn, nr = 0;
1333        struct pci_dev *dev;
1334        unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
1335
1336        if (only_one_child(bus) && (devfn > 0))
1337                return 0; /* Already scanned the entire slot */
1338
1339        dev = pci_scan_single_device(bus, devfn);
1340        if (!dev)
1341                return 0;
1342        if (!dev->is_added)
1343                nr++;
1344
1345        if (pci_ari_enabled(bus))
1346                next_fn = next_ari_fn;
1347        else if (dev->multifunction)
1348                next_fn = next_trad_fn;
1349
1350        for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
1351                dev = pci_scan_single_device(bus, devfn + fn);
1352                if (dev) {
1353                        if (!dev->is_added)
1354                                nr++;
1355                        dev->multifunction = 1;
1356                }
1357        }
1358
1359        /* only one slot has pcie device */
1360        if (bus->self && nr)
1361                pcie_aspm_init_link_state(bus->self);
1362
1363        return nr;
1364}
1365
1366unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1367{
1368        unsigned int devfn, pass, max = bus->secondary;
1369        struct pci_dev *dev;
1370
1371        dev_dbg(&bus->dev, "scanning bus\n");
1372
1373        /* Go find them, Rover! */
1374        for (devfn = 0; devfn < 0x100; devfn += 8)
1375                pci_scan_slot(bus, devfn);
1376
1377        /* Reserve buses for SR-IOV capability. */
1378        max += pci_iov_bus_range(bus);
1379
1380        /*
1381         * After performing arch-dependent fixup of the bus, look behind
1382         * all PCI-to-PCI bridges on this bus.
1383         */
1384        if (!bus->is_added) {
1385                dev_dbg(&bus->dev, "fixups for bus\n");
1386                pcibios_fixup_bus(bus);
1387                if (pci_is_root_bus(bus))
1388                        bus->is_added = 1;
1389        }
1390
1391        for (pass=0; pass < 2; pass++)
1392                list_for_each_entry(dev, &bus->devices, bus_list) {
1393                        if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1394                            dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1395                                max = pci_scan_bridge(bus, dev, max, pass);
1396                }
1397
1398        /*
1399         * We've scanned the bus and so we know all about what's on
1400         * the other side of any bridges that may be on this bus plus
1401         * any devices.
1402         *
1403         * Return how far we've got finding sub-buses.
1404         */
1405        dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1406        return max;
1407}
1408
1409struct pci_bus * pci_create_bus(struct device *parent,
1410                int bus, struct pci_ops *ops, void *sysdata)
1411{
1412        int error;
1413        struct pci_bus *b, *b2;
1414        struct device *dev;
1415
1416        b = pci_alloc_bus();
1417        if (!b)
1418                return NULL;
1419
1420        dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1421        if (!dev){
1422                kfree(b);
1423                return NULL;
1424        }
1425
1426        b->sysdata = sysdata;
1427        b->ops = ops;
1428
1429        b2 = pci_find_bus(pci_domain_nr(b), bus);
1430        if (b2) {
1431                /* If we already got to this bus through a different bridge, ignore it */
1432                dev_dbg(&b2->dev, "bus already known\n");
1433                goto err_out;
1434        }
1435
1436        down_write(&pci_bus_sem);
1437        list_add_tail(&b->node, &pci_root_buses);
1438        up_write(&pci_bus_sem);
1439
1440        dev->parent = parent;
1441        dev->release = pci_release_bus_bridge_dev;
1442        dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1443        error = device_register(dev);
1444        if (error)
1445                goto dev_reg_err;
1446        b->bridge = get_device(dev);
1447        device_enable_async_suspend(b->bridge);
1448
1449        if (!parent)
1450                set_dev_node(b->bridge, pcibus_to_node(b));
1451
1452        b->dev.class = &pcibus_class;
1453        b->dev.parent = b->bridge;
1454        dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1455        error = device_register(&b->dev);
1456        if (error)
1457                goto class_dev_reg_err;
1458        error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1459        if (error)
1460                goto dev_create_file_err;
1461
1462        /* Create legacy_io and legacy_mem files for this bus */
1463        pci_create_legacy_files(b);
1464
1465        b->number = b->secondary = bus;
1466        b->resource[0] = &ioport_resource;
1467        b->resource[1] = &iomem_resource;
1468
1469        return b;
1470
1471dev_create_file_err:
1472        device_unregister(&b->dev);
1473class_dev_reg_err:
1474        device_unregister(dev);
1475dev_reg_err:
1476        down_write(&pci_bus_sem);
1477        list_del(&b->node);
1478        up_write(&pci_bus_sem);
1479err_out:
1480        kfree(dev);
1481        kfree(b);
1482        return NULL;
1483}
1484
1485struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1486                int bus, struct pci_ops *ops, void *sysdata)
1487{
1488        struct pci_bus *b;
1489
1490        b = pci_create_bus(parent, bus, ops, sysdata);
1491        if (b)
1492                b->subordinate = pci_scan_child_bus(b);
1493        return b;
1494}
1495EXPORT_SYMBOL(pci_scan_bus_parented);
1496
1497#ifdef CONFIG_HOTPLUG
1498/**
1499 * pci_rescan_bus - scan a PCI bus for devices.
1500 * @bus: PCI bus to scan
1501 *
1502 * Scan a PCI bus and child buses for new devices, adds them,
1503 * and enables them.
1504 *
1505 * Returns the max number of subordinate bus discovered.
1506 */
1507unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1508{
1509        unsigned int max;
1510        struct pci_dev *dev;
1511
1512        max = pci_scan_child_bus(bus);
1513
1514        down_read(&pci_bus_sem);
1515        list_for_each_entry(dev, &bus->devices, bus_list)
1516                if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1517                    dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1518                        if (dev->subordinate)
1519                                pci_bus_size_bridges(dev->subordinate);
1520        up_read(&pci_bus_sem);
1521
1522        pci_bus_assign_resources(bus);
1523        pci_enable_bridges(bus);
1524        pci_bus_add_devices(bus);
1525
1526        return max;
1527}
1528EXPORT_SYMBOL_GPL(pci_rescan_bus);
1529
1530EXPORT_SYMBOL(pci_add_new_bus);
1531EXPORT_SYMBOL(pci_scan_slot);
1532EXPORT_SYMBOL(pci_scan_bridge);
1533EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1534#endif
1535
1536static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1537{
1538        const struct pci_dev *a = to_pci_dev(d_a);
1539        const struct pci_dev *b = to_pci_dev(d_b);
1540
1541        if      (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1542        else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return  1;
1543
1544        if      (a->bus->number < b->bus->number) return -1;
1545        else if (a->bus->number > b->bus->number) return  1;
1546
1547        if      (a->devfn < b->devfn) return -1;
1548        else if (a->devfn > b->devfn) return  1;
1549
1550        return 0;
1551}
1552
1553void __init pci_sort_breadthfirst(void)
1554{
1555        bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
1556}
1557
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