linux/drivers/pci/pci.c
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   1/*
   2 *      PCI Bus Services, see include/linux/pci.h for further explanation.
   3 *
   4 *      Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
   5 *      David Mosberger-Tang
   6 *
   7 *      Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
   8 */
   9
  10#include <linux/kernel.h>
  11#include <linux/delay.h>
  12#include <linux/init.h>
  13#include <linux/pci.h>
  14#include <linux/pm.h>
  15#include <linux/slab.h>
  16#include <linux/module.h>
  17#include <linux/spinlock.h>
  18#include <linux/string.h>
  19#include <linux/log2.h>
  20#include <linux/pci-aspm.h>
  21#include <linux/pm_wakeup.h>
  22#include <linux/interrupt.h>
  23#include <linux/device.h>
  24#include <linux/pm_runtime.h>
  25#include <asm/setup.h>
  26#include "pci.h"
  27
  28const char *pci_power_names[] = {
  29        "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
  30};
  31EXPORT_SYMBOL_GPL(pci_power_names);
  32
  33int isa_dma_bridge_buggy;
  34EXPORT_SYMBOL(isa_dma_bridge_buggy);
  35
  36int pci_pci_problems;
  37EXPORT_SYMBOL(pci_pci_problems);
  38
  39unsigned int pci_pm_d3_delay;
  40
  41static void pci_pme_list_scan(struct work_struct *work);
  42
  43static LIST_HEAD(pci_pme_list);
  44static DEFINE_MUTEX(pci_pme_list_mutex);
  45static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
  46
  47struct pci_pme_device {
  48        struct list_head list;
  49        struct pci_dev *dev;
  50};
  51
  52#define PME_TIMEOUT 1000 /* How long between PME checks */
  53
  54static void pci_dev_d3_sleep(struct pci_dev *dev)
  55{
  56        unsigned int delay = dev->d3_delay;
  57
  58        if (delay < pci_pm_d3_delay)
  59                delay = pci_pm_d3_delay;
  60
  61        msleep(delay);
  62}
  63
  64#ifdef CONFIG_PCI_DOMAINS
  65int pci_domains_supported = 1;
  66#endif
  67
  68#define DEFAULT_CARDBUS_IO_SIZE         (256)
  69#define DEFAULT_CARDBUS_MEM_SIZE        (64*1024*1024)
  70/* pci=cbmemsize=nnM,cbiosize=nn can override this */
  71unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
  72unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
  73
  74#define DEFAULT_HOTPLUG_IO_SIZE         (256)
  75#define DEFAULT_HOTPLUG_MEM_SIZE        (2*1024*1024)
  76/* pci=hpmemsize=nnM,hpiosize=nn can override this */
  77unsigned long pci_hotplug_io_size  = DEFAULT_HOTPLUG_IO_SIZE;
  78unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
  79
  80/*
  81 * The default CLS is used if arch didn't set CLS explicitly and not
  82 * all pci devices agree on the same value.  Arch can override either
  83 * the dfl or actual value as it sees fit.  Don't forget this is
  84 * measured in 32-bit words, not bytes.
  85 */
  86u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
  87u8 pci_cache_line_size;
  88
  89/**
  90 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
  91 * @bus: pointer to PCI bus structure to search
  92 *
  93 * Given a PCI bus, returns the highest PCI bus number present in the set
  94 * including the given PCI bus and its list of child PCI buses.
  95 */
  96unsigned char pci_bus_max_busnr(struct pci_bus* bus)
  97{
  98        struct list_head *tmp;
  99        unsigned char max, n;
 100
 101        max = bus->subordinate;
 102        list_for_each(tmp, &bus->children) {
 103                n = pci_bus_max_busnr(pci_bus_b(tmp));
 104                if(n > max)
 105                        max = n;
 106        }
 107        return max;
 108}
 109EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
 110
 111#ifdef CONFIG_HAS_IOMEM
 112void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
 113{
 114        /*
 115         * Make sure the BAR is actually a memory resource, not an IO resource
 116         */
 117        if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
 118                WARN_ON(1);
 119                return NULL;
 120        }
 121        return ioremap_nocache(pci_resource_start(pdev, bar),
 122                                     pci_resource_len(pdev, bar));
 123}
 124EXPORT_SYMBOL_GPL(pci_ioremap_bar);
 125#endif
 126
 127#if 0
 128/**
 129 * pci_max_busnr - returns maximum PCI bus number
 130 *
 131 * Returns the highest PCI bus number present in the system global list of
 132 * PCI buses.
 133 */
 134unsigned char __devinit
 135pci_max_busnr(void)
 136{
 137        struct pci_bus *bus = NULL;
 138        unsigned char max, n;
 139
 140        max = 0;
 141        while ((bus = pci_find_next_bus(bus)) != NULL) {
 142                n = pci_bus_max_busnr(bus);
 143                if(n > max)
 144                        max = n;
 145        }
 146        return max;
 147}
 148
 149#endif  /*  0  */
 150
 151#define PCI_FIND_CAP_TTL        48
 152
 153static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
 154                                   u8 pos, int cap, int *ttl)
 155{
 156        u8 id;
 157
 158        while ((*ttl)--) {
 159                pci_bus_read_config_byte(bus, devfn, pos, &pos);
 160                if (pos < 0x40)
 161                        break;
 162                pos &= ~3;
 163                pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
 164                                         &id);
 165                if (id == 0xff)
 166                        break;
 167                if (id == cap)
 168                        return pos;
 169                pos += PCI_CAP_LIST_NEXT;
 170        }
 171        return 0;
 172}
 173
 174static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
 175                               u8 pos, int cap)
 176{
 177        int ttl = PCI_FIND_CAP_TTL;
 178
 179        return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
 180}
 181
 182int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
 183{
 184        return __pci_find_next_cap(dev->bus, dev->devfn,
 185                                   pos + PCI_CAP_LIST_NEXT, cap);
 186}
 187EXPORT_SYMBOL_GPL(pci_find_next_capability);
 188
 189static int __pci_bus_find_cap_start(struct pci_bus *bus,
 190                                    unsigned int devfn, u8 hdr_type)
 191{
 192        u16 status;
 193
 194        pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
 195        if (!(status & PCI_STATUS_CAP_LIST))
 196                return 0;
 197
 198        switch (hdr_type) {
 199        case PCI_HEADER_TYPE_NORMAL:
 200        case PCI_HEADER_TYPE_BRIDGE:
 201                return PCI_CAPABILITY_LIST;
 202        case PCI_HEADER_TYPE_CARDBUS:
 203                return PCI_CB_CAPABILITY_LIST;
 204        default:
 205                return 0;
 206        }
 207
 208        return 0;
 209}
 210
 211/**
 212 * pci_find_capability - query for devices' capabilities 
 213 * @dev: PCI device to query
 214 * @cap: capability code
 215 *
 216 * Tell if a device supports a given PCI capability.
 217 * Returns the address of the requested capability structure within the
 218 * device's PCI configuration space or 0 in case the device does not
 219 * support it.  Possible values for @cap:
 220 *
 221 *  %PCI_CAP_ID_PM           Power Management 
 222 *  %PCI_CAP_ID_AGP          Accelerated Graphics Port 
 223 *  %PCI_CAP_ID_VPD          Vital Product Data 
 224 *  %PCI_CAP_ID_SLOTID       Slot Identification 
 225 *  %PCI_CAP_ID_MSI          Message Signalled Interrupts
 226 *  %PCI_CAP_ID_CHSWP        CompactPCI HotSwap 
 227 *  %PCI_CAP_ID_PCIX         PCI-X
 228 *  %PCI_CAP_ID_EXP          PCI Express
 229 */
 230int pci_find_capability(struct pci_dev *dev, int cap)
 231{
 232        int pos;
 233
 234        pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
 235        if (pos)
 236                pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
 237
 238        return pos;
 239}
 240
 241/**
 242 * pci_bus_find_capability - query for devices' capabilities 
 243 * @bus:   the PCI bus to query
 244 * @devfn: PCI device to query
 245 * @cap:   capability code
 246 *
 247 * Like pci_find_capability() but works for pci devices that do not have a
 248 * pci_dev structure set up yet. 
 249 *
 250 * Returns the address of the requested capability structure within the
 251 * device's PCI configuration space or 0 in case the device does not
 252 * support it.
 253 */
 254int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
 255{
 256        int pos;
 257        u8 hdr_type;
 258
 259        pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
 260
 261        pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
 262        if (pos)
 263                pos = __pci_find_next_cap(bus, devfn, pos, cap);
 264
 265        return pos;
 266}
 267
 268/**
 269 * pci_find_ext_capability - Find an extended capability
 270 * @dev: PCI device to query
 271 * @cap: capability code
 272 *
 273 * Returns the address of the requested extended capability structure
 274 * within the device's PCI configuration space or 0 if the device does
 275 * not support it.  Possible values for @cap:
 276 *
 277 *  %PCI_EXT_CAP_ID_ERR         Advanced Error Reporting
 278 *  %PCI_EXT_CAP_ID_VC          Virtual Channel
 279 *  %PCI_EXT_CAP_ID_DSN         Device Serial Number
 280 *  %PCI_EXT_CAP_ID_PWR         Power Budgeting
 281 */
 282int pci_find_ext_capability(struct pci_dev *dev, int cap)
 283{
 284        u32 header;
 285        int ttl;
 286        int pos = PCI_CFG_SPACE_SIZE;
 287
 288        /* minimum 8 bytes per capability */
 289        ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
 290
 291        if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
 292                return 0;
 293
 294        if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
 295                return 0;
 296
 297        /*
 298         * If we have no capabilities, this is indicated by cap ID,
 299         * cap version and next pointer all being 0.
 300         */
 301        if (header == 0)
 302                return 0;
 303
 304        while (ttl-- > 0) {
 305                if (PCI_EXT_CAP_ID(header) == cap)
 306                        return pos;
 307
 308                pos = PCI_EXT_CAP_NEXT(header);
 309                if (pos < PCI_CFG_SPACE_SIZE)
 310                        break;
 311
 312                if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
 313                        break;
 314        }
 315
 316        return 0;
 317}
 318EXPORT_SYMBOL_GPL(pci_find_ext_capability);
 319
 320/**
 321 * pci_bus_find_ext_capability - find an extended capability
 322 * @bus:   the PCI bus to query
 323 * @devfn: PCI device to query
 324 * @cap:   capability code
 325 *
 326 * Like pci_find_ext_capability() but works for pci devices that do not have a
 327 * pci_dev structure set up yet.
 328 *
 329 * Returns the address of the requested capability structure within the
 330 * device's PCI configuration space or 0 in case the device does not
 331 * support it.
 332 */
 333int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
 334                                int cap)
 335{
 336        u32 header;
 337        int ttl;
 338        int pos = PCI_CFG_SPACE_SIZE;
 339
 340        /* minimum 8 bytes per capability */
 341        ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
 342
 343        if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
 344                return 0;
 345        if (header == 0xffffffff || header == 0)
 346                return 0;
 347
 348        while (ttl-- > 0) {
 349                if (PCI_EXT_CAP_ID(header) == cap)
 350                        return pos;
 351
 352                pos = PCI_EXT_CAP_NEXT(header);
 353                if (pos < PCI_CFG_SPACE_SIZE)
 354                        break;
 355
 356                if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
 357                        break;
 358        }
 359
 360        return 0;
 361}
 362
 363static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
 364{
 365        int rc, ttl = PCI_FIND_CAP_TTL;
 366        u8 cap, mask;
 367
 368        if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
 369                mask = HT_3BIT_CAP_MASK;
 370        else
 371                mask = HT_5BIT_CAP_MASK;
 372
 373        pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
 374                                      PCI_CAP_ID_HT, &ttl);
 375        while (pos) {
 376                rc = pci_read_config_byte(dev, pos + 3, &cap);
 377                if (rc != PCIBIOS_SUCCESSFUL)
 378                        return 0;
 379
 380                if ((cap & mask) == ht_cap)
 381                        return pos;
 382
 383                pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
 384                                              pos + PCI_CAP_LIST_NEXT,
 385                                              PCI_CAP_ID_HT, &ttl);
 386        }
 387
 388        return 0;
 389}
 390/**
 391 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
 392 * @dev: PCI device to query
 393 * @pos: Position from which to continue searching
 394 * @ht_cap: Hypertransport capability code
 395 *
 396 * To be used in conjunction with pci_find_ht_capability() to search for
 397 * all capabilities matching @ht_cap. @pos should always be a value returned
 398 * from pci_find_ht_capability().
 399 *
 400 * NB. To be 100% safe against broken PCI devices, the caller should take
 401 * steps to avoid an infinite loop.
 402 */
 403int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
 404{
 405        return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
 406}
 407EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
 408
 409/**
 410 * pci_find_ht_capability - query a device's Hypertransport capabilities
 411 * @dev: PCI device to query
 412 * @ht_cap: Hypertransport capability code
 413 *
 414 * Tell if a device supports a given Hypertransport capability.
 415 * Returns an address within the device's PCI configuration space
 416 * or 0 in case the device does not support the request capability.
 417 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
 418 * which has a Hypertransport capability matching @ht_cap.
 419 */
 420int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
 421{
 422        int pos;
 423
 424        pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
 425        if (pos)
 426                pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
 427
 428        return pos;
 429}
 430EXPORT_SYMBOL_GPL(pci_find_ht_capability);
 431
 432/**
 433 * pci_find_parent_resource - return resource region of parent bus of given region
 434 * @dev: PCI device structure contains resources to be searched
 435 * @res: child resource record for which parent is sought
 436 *
 437 *  For given resource region of given device, return the resource
 438 *  region of parent bus the given region is contained in or where
 439 *  it should be allocated from.
 440 */
 441struct resource *
 442pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
 443{
 444        const struct pci_bus *bus = dev->bus;
 445        int i;
 446        struct resource *best = NULL, *r;
 447
 448        pci_bus_for_each_resource(bus, r, i) {
 449                if (!r)
 450                        continue;
 451                if (res->start && !(res->start >= r->start && res->end <= r->end))
 452                        continue;       /* Not contained */
 453                if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
 454                        continue;       /* Wrong type */
 455                if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
 456                        return r;       /* Exact match */
 457                /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
 458                if (r->flags & IORESOURCE_PREFETCH)
 459                        continue;
 460                /* .. but we can put a prefetchable resource inside a non-prefetchable one */
 461                if (!best)
 462                        best = r;
 463        }
 464        return best;
 465}
 466
 467/**
 468 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
 469 * @dev: PCI device to have its BARs restored
 470 *
 471 * Restore the BAR values for a given device, so as to make it
 472 * accessible by its driver.
 473 */
 474static void
 475pci_restore_bars(struct pci_dev *dev)
 476{
 477        int i;
 478
 479        for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
 480                pci_update_resource(dev, i);
 481}
 482
 483static struct pci_platform_pm_ops *pci_platform_pm;
 484
 485int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
 486{
 487        if (!ops->is_manageable || !ops->set_state || !ops->choose_state
 488            || !ops->sleep_wake || !ops->can_wakeup)
 489                return -EINVAL;
 490        pci_platform_pm = ops;
 491        return 0;
 492}
 493
 494static inline bool platform_pci_power_manageable(struct pci_dev *dev)
 495{
 496        return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
 497}
 498
 499static inline int platform_pci_set_power_state(struct pci_dev *dev,
 500                                                pci_power_t t)
 501{
 502        return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
 503}
 504
 505static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
 506{
 507        return pci_platform_pm ?
 508                        pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
 509}
 510
 511static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
 512{
 513        return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
 514}
 515
 516static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
 517{
 518        return pci_platform_pm ?
 519                        pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
 520}
 521
 522static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
 523{
 524        return pci_platform_pm ?
 525                        pci_platform_pm->run_wake(dev, enable) : -ENODEV;
 526}
 527
 528/**
 529 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
 530 *                           given PCI device
 531 * @dev: PCI device to handle.
 532 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
 533 *
 534 * RETURN VALUE:
 535 * -EINVAL if the requested state is invalid.
 536 * -EIO if device does not support PCI PM or its PM capabilities register has a
 537 * wrong version, or device doesn't support the requested state.
 538 * 0 if device already is in the requested state.
 539 * 0 if device's power state has been successfully changed.
 540 */
 541static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
 542{
 543        u16 pmcsr;
 544        bool need_restore = false;
 545
 546        /* Check if we're already there */
 547        if (dev->current_state == state)
 548                return 0;
 549
 550        if (!dev->pm_cap)
 551                return -EIO;
 552
 553        if (state < PCI_D0 || state > PCI_D3hot)
 554                return -EINVAL;
 555
 556        /* Validate current state:
 557         * Can enter D0 from any state, but if we can only go deeper 
 558         * to sleep if we're already in a low power state
 559         */
 560        if (state != PCI_D0 && dev->current_state <= PCI_D3cold
 561            && dev->current_state > state) {
 562                dev_err(&dev->dev, "invalid power transition "
 563                        "(from state %d to %d)\n", dev->current_state, state);
 564                return -EINVAL;
 565        }
 566
 567        /* check if this device supports the desired state */
 568        if ((state == PCI_D1 && !dev->d1_support)
 569           || (state == PCI_D2 && !dev->d2_support))
 570                return -EIO;
 571
 572        pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
 573
 574        /* If we're (effectively) in D3, force entire word to 0.
 575         * This doesn't affect PME_Status, disables PME_En, and
 576         * sets PowerState to 0.
 577         */
 578        switch (dev->current_state) {
 579        case PCI_D0:
 580        case PCI_D1:
 581        case PCI_D2:
 582                pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
 583                pmcsr |= state;
 584                break;
 585        case PCI_D3hot:
 586        case PCI_D3cold:
 587        case PCI_UNKNOWN: /* Boot-up */
 588                if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
 589                 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
 590                        need_restore = true;
 591                /* Fall-through: force to D0 */
 592        default:
 593                pmcsr = 0;
 594                break;
 595        }
 596
 597        /* enter specified state */
 598        pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
 599
 600        /* Mandatory power management transition delays */
 601        /* see PCI PM 1.1 5.6.1 table 18 */
 602        if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
 603                pci_dev_d3_sleep(dev);
 604        else if (state == PCI_D2 || dev->current_state == PCI_D2)
 605                udelay(PCI_PM_D2_DELAY);
 606
 607        pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
 608        dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
 609        if (dev->current_state != state && printk_ratelimit())
 610                dev_info(&dev->dev, "Refused to change power state, "
 611                        "currently in D%d\n", dev->current_state);
 612
 613        /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
 614         * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
 615         * from D3hot to D0 _may_ perform an internal reset, thereby
 616         * going to "D0 Uninitialized" rather than "D0 Initialized".
 617         * For example, at least some versions of the 3c905B and the
 618         * 3c556B exhibit this behaviour.
 619         *
 620         * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
 621         * devices in a D3hot state at boot.  Consequently, we need to
 622         * restore at least the BARs so that the device will be
 623         * accessible to its driver.
 624         */
 625        if (need_restore)
 626                pci_restore_bars(dev);
 627
 628        if (dev->bus->self)
 629                pcie_aspm_pm_state_change(dev->bus->self);
 630
 631        return 0;
 632}
 633
 634/**
 635 * pci_update_current_state - Read PCI power state of given device from its
 636 *                            PCI PM registers and cache it
 637 * @dev: PCI device to handle.
 638 * @state: State to cache in case the device doesn't have the PM capability
 639 */
 640void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
 641{
 642        if (dev->pm_cap) {
 643                u16 pmcsr;
 644
 645                pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
 646                dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
 647        } else {
 648                dev->current_state = state;
 649        }
 650}
 651
 652/**
 653 * pci_platform_power_transition - Use platform to change device power state
 654 * @dev: PCI device to handle.
 655 * @state: State to put the device into.
 656 */
 657static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
 658{
 659        int error;
 660
 661        if (platform_pci_power_manageable(dev)) {
 662                error = platform_pci_set_power_state(dev, state);
 663                if (!error)
 664                        pci_update_current_state(dev, state);
 665        } else {
 666                error = -ENODEV;
 667                /* Fall back to PCI_D0 if native PM is not supported */
 668                if (!dev->pm_cap)
 669                        dev->current_state = PCI_D0;
 670        }
 671
 672        return error;
 673}
 674
 675/**
 676 * __pci_start_power_transition - Start power transition of a PCI device
 677 * @dev: PCI device to handle.
 678 * @state: State to put the device into.
 679 */
 680static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
 681{
 682        if (state == PCI_D0)
 683                pci_platform_power_transition(dev, PCI_D0);
 684}
 685
 686/**
 687 * __pci_complete_power_transition - Complete power transition of a PCI device
 688 * @dev: PCI device to handle.
 689 * @state: State to put the device into.
 690 *
 691 * This function should not be called directly by device drivers.
 692 */
 693int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
 694{
 695        return state >= PCI_D0 ?
 696                        pci_platform_power_transition(dev, state) : -EINVAL;
 697}
 698EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
 699
 700/**
 701 * pci_set_power_state - Set the power state of a PCI device
 702 * @dev: PCI device to handle.
 703 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
 704 *
 705 * Transition a device to a new power state, using the platform firmware and/or
 706 * the device's PCI PM registers.
 707 *
 708 * RETURN VALUE:
 709 * -EINVAL if the requested state is invalid.
 710 * -EIO if device does not support PCI PM or its PM capabilities register has a
 711 * wrong version, or device doesn't support the requested state.
 712 * 0 if device already is in the requested state.
 713 * 0 if device's power state has been successfully changed.
 714 */
 715int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
 716{
 717        int error;
 718
 719        /* bound the state we're entering */
 720        if (state > PCI_D3hot)
 721                state = PCI_D3hot;
 722        else if (state < PCI_D0)
 723                state = PCI_D0;
 724        else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
 725                /*
 726                 * If the device or the parent bridge do not support PCI PM,
 727                 * ignore the request if we're doing anything other than putting
 728                 * it into D0 (which would only happen on boot).
 729                 */
 730                return 0;
 731
 732        __pci_start_power_transition(dev, state);
 733
 734        /* This device is quirked not to be put into D3, so
 735           don't put it in D3 */
 736        if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
 737                return 0;
 738
 739        error = pci_raw_set_power_state(dev, state);
 740
 741        if (!__pci_complete_power_transition(dev, state))
 742                error = 0;
 743        /*
 744         * When aspm_policy is "powersave" this call ensures
 745         * that ASPM is configured.
 746         */
 747        if (!error && dev->bus->self)
 748                pcie_aspm_powersave_config_link(dev->bus->self);
 749
 750        return error;
 751}
 752
 753/**
 754 * pci_choose_state - Choose the power state of a PCI device
 755 * @dev: PCI device to be suspended
 756 * @state: target sleep state for the whole system. This is the value
 757 *      that is passed to suspend() function.
 758 *
 759 * Returns PCI power state suitable for given device and given system
 760 * message.
 761 */
 762
 763pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
 764{
 765        pci_power_t ret;
 766
 767        if (!pci_find_capability(dev, PCI_CAP_ID_PM))
 768                return PCI_D0;
 769
 770        ret = platform_pci_choose_state(dev);
 771        if (ret != PCI_POWER_ERROR)
 772                return ret;
 773
 774        switch (state.event) {
 775        case PM_EVENT_ON:
 776                return PCI_D0;
 777        case PM_EVENT_FREEZE:
 778        case PM_EVENT_PRETHAW:
 779                /* REVISIT both freeze and pre-thaw "should" use D0 */
 780        case PM_EVENT_SUSPEND:
 781        case PM_EVENT_HIBERNATE:
 782                return PCI_D3hot;
 783        default:
 784                dev_info(&dev->dev, "unrecognized suspend event %d\n",
 785                         state.event);
 786                BUG();
 787        }
 788        return PCI_D0;
 789}
 790
 791EXPORT_SYMBOL(pci_choose_state);
 792
 793#define PCI_EXP_SAVE_REGS       7
 794
 795#define pcie_cap_has_devctl(type, flags)        1
 796#define pcie_cap_has_lnkctl(type, flags)                \
 797                ((flags & PCI_EXP_FLAGS_VERS) > 1 ||    \
 798                 (type == PCI_EXP_TYPE_ROOT_PORT ||     \
 799                  type == PCI_EXP_TYPE_ENDPOINT ||      \
 800                  type == PCI_EXP_TYPE_LEG_END))
 801#define pcie_cap_has_sltctl(type, flags)                \
 802                ((flags & PCI_EXP_FLAGS_VERS) > 1 ||    \
 803                 ((type == PCI_EXP_TYPE_ROOT_PORT) ||   \
 804                  (type == PCI_EXP_TYPE_DOWNSTREAM &&   \
 805                   (flags & PCI_EXP_FLAGS_SLOT))))
 806#define pcie_cap_has_rtctl(type, flags)                 \
 807                ((flags & PCI_EXP_FLAGS_VERS) > 1 ||    \
 808                 (type == PCI_EXP_TYPE_ROOT_PORT ||     \
 809                  type == PCI_EXP_TYPE_RC_EC))
 810#define pcie_cap_has_devctl2(type, flags)               \
 811                ((flags & PCI_EXP_FLAGS_VERS) > 1)
 812#define pcie_cap_has_lnkctl2(type, flags)               \
 813                ((flags & PCI_EXP_FLAGS_VERS) > 1)
 814#define pcie_cap_has_sltctl2(type, flags)               \
 815                ((flags & PCI_EXP_FLAGS_VERS) > 1)
 816
 817static int pci_save_pcie_state(struct pci_dev *dev)
 818{
 819        int pos, i = 0;
 820        struct pci_cap_saved_state *save_state;
 821        u16 *cap;
 822        u16 flags;
 823
 824        pos = pci_pcie_cap(dev);
 825        if (!pos)
 826                return 0;
 827
 828        save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
 829        if (!save_state) {
 830                dev_err(&dev->dev, "buffer not found in %s\n", __func__);
 831                return -ENOMEM;
 832        }
 833        cap = (u16 *)&save_state->data[0];
 834
 835        pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
 836
 837        if (pcie_cap_has_devctl(dev->pcie_type, flags))
 838                pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
 839        if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
 840                pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
 841        if (pcie_cap_has_sltctl(dev->pcie_type, flags))
 842                pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
 843        if (pcie_cap_has_rtctl(dev->pcie_type, flags))
 844                pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
 845        if (pcie_cap_has_devctl2(dev->pcie_type, flags))
 846                pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
 847        if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
 848                pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
 849        if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
 850                pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
 851
 852        return 0;
 853}
 854
 855static void pci_restore_pcie_state(struct pci_dev *dev)
 856{
 857        int i = 0, pos;
 858        struct pci_cap_saved_state *save_state;
 859        u16 *cap;
 860        u16 flags;
 861
 862        save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
 863        pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
 864        if (!save_state || pos <= 0)
 865                return;
 866        cap = (u16 *)&save_state->data[0];
 867
 868        pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
 869
 870        if (pcie_cap_has_devctl(dev->pcie_type, flags))
 871                pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
 872        if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
 873                pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
 874        if (pcie_cap_has_sltctl(dev->pcie_type, flags))
 875                pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
 876        if (pcie_cap_has_rtctl(dev->pcie_type, flags))
 877                pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
 878        if (pcie_cap_has_devctl2(dev->pcie_type, flags))
 879                pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
 880        if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
 881                pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
 882        if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
 883                pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
 884}
 885
 886
 887static int pci_save_pcix_state(struct pci_dev *dev)
 888{
 889        int pos;
 890        struct pci_cap_saved_state *save_state;
 891
 892        pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
 893        if (pos <= 0)
 894                return 0;
 895
 896        save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
 897        if (!save_state) {
 898                dev_err(&dev->dev, "buffer not found in %s\n", __func__);
 899                return -ENOMEM;
 900        }
 901
 902        pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);
 903
 904        return 0;
 905}
 906
 907static void pci_restore_pcix_state(struct pci_dev *dev)
 908{
 909        int i = 0, pos;
 910        struct pci_cap_saved_state *save_state;
 911        u16 *cap;
 912
 913        save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
 914        pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
 915        if (!save_state || pos <= 0)
 916                return;
 917        cap = (u16 *)&save_state->data[0];
 918
 919        pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
 920}
 921
 922
 923/**
 924 * pci_save_state - save the PCI configuration space of a device before suspending
 925 * @dev: - PCI device that we're dealing with
 926 */
 927int
 928pci_save_state(struct pci_dev *dev)
 929{
 930        int i;
 931        /* XXX: 100% dword access ok here? */
 932        for (i = 0; i < 16; i++)
 933                pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
 934        dev->state_saved = true;
 935        if ((i = pci_save_pcie_state(dev)) != 0)
 936                return i;
 937        if ((i = pci_save_pcix_state(dev)) != 0)
 938                return i;
 939        return 0;
 940}
 941
 942/** 
 943 * pci_restore_state - Restore the saved state of a PCI device
 944 * @dev: - PCI device that we're dealing with
 945 */
 946void pci_restore_state(struct pci_dev *dev)
 947{
 948        int i;
 949        u32 val;
 950
 951        if (!dev->state_saved)
 952                return;
 953
 954        /* PCI Express register must be restored first */
 955        pci_restore_pcie_state(dev);
 956
 957        /*
 958         * The Base Address register should be programmed before the command
 959         * register(s)
 960         */
 961        for (i = 15; i >= 0; i--) {
 962                pci_read_config_dword(dev, i * 4, &val);
 963                if (val != dev->saved_config_space[i]) {
 964                        dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
 965                                "space at offset %#x (was %#x, writing %#x)\n",
 966                                i, val, (int)dev->saved_config_space[i]);
 967                        pci_write_config_dword(dev,i * 4,
 968                                dev->saved_config_space[i]);
 969                }
 970        }
 971        pci_restore_pcix_state(dev);
 972        pci_restore_msi_state(dev);
 973        pci_restore_iov_state(dev);
 974
 975        dev->state_saved = false;
 976}
 977
 978static int do_pci_enable_device(struct pci_dev *dev, int bars)
 979{
 980        int err;
 981
 982        err = pci_set_power_state(dev, PCI_D0);
 983        if (err < 0 && err != -EIO)
 984                return err;
 985        err = pcibios_enable_device(dev, bars);
 986        if (err < 0)
 987                return err;
 988        pci_fixup_device(pci_fixup_enable, dev);
 989
 990        return 0;
 991}
 992
 993/**
 994 * pci_reenable_device - Resume abandoned device
 995 * @dev: PCI device to be resumed
 996 *
 997 *  Note this function is a backend of pci_default_resume and is not supposed
 998 *  to be called by normal code, write proper resume handler and use it instead.
 999 */
1000int pci_reenable_device(struct pci_dev *dev)
1001{
1002        if (pci_is_enabled(dev))
1003                return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1004        return 0;
1005}
1006
1007static int __pci_enable_device_flags(struct pci_dev *dev,
1008                                     resource_size_t flags)
1009{
1010        int err;
1011        int i, bars = 0;
1012
1013        /*
1014         * Power state could be unknown at this point, either due to a fresh
1015         * boot or a device removal call.  So get the current power state
1016         * so that things like MSI message writing will behave as expected
1017         * (e.g. if the device really is in D0 at enable time).
1018         */
1019        if (dev->pm_cap) {
1020                u16 pmcsr;
1021                pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1022                dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1023        }
1024
1025        if (atomic_add_return(1, &dev->enable_cnt) > 1)
1026                return 0;               /* already enabled */
1027
1028        for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1029                if (dev->resource[i].flags & flags)
1030                        bars |= (1 << i);
1031
1032        err = do_pci_enable_device(dev, bars);
1033        if (err < 0)
1034                atomic_dec(&dev->enable_cnt);
1035        return err;
1036}
1037
1038/**
1039 * pci_enable_device_io - Initialize a device for use with IO space
1040 * @dev: PCI device to be initialized
1041 *
1042 *  Initialize device before it's used by a driver. Ask low-level code
1043 *  to enable I/O resources. Wake up the device if it was suspended.
1044 *  Beware, this function can fail.
1045 */
1046int pci_enable_device_io(struct pci_dev *dev)
1047{
1048        return __pci_enable_device_flags(dev, IORESOURCE_IO);
1049}
1050
1051/**
1052 * pci_enable_device_mem - Initialize a device for use with Memory space
1053 * @dev: PCI device to be initialized
1054 *
1055 *  Initialize device before it's used by a driver. Ask low-level code
1056 *  to enable Memory resources. Wake up the device if it was suspended.
1057 *  Beware, this function can fail.
1058 */
1059int pci_enable_device_mem(struct pci_dev *dev)
1060{
1061        return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1062}
1063
1064/**
1065 * pci_enable_device - Initialize device before it's used by a driver.
1066 * @dev: PCI device to be initialized
1067 *
1068 *  Initialize device before it's used by a driver. Ask low-level code
1069 *  to enable I/O and memory. Wake up the device if it was suspended.
1070 *  Beware, this function can fail.
1071 *
1072 *  Note we don't actually enable the device many times if we call
1073 *  this function repeatedly (we just increment the count).
1074 */
1075int pci_enable_device(struct pci_dev *dev)
1076{
1077        return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1078}
1079
1080/*
1081 * Managed PCI resources.  This manages device on/off, intx/msi/msix
1082 * on/off and BAR regions.  pci_dev itself records msi/msix status, so
1083 * there's no need to track it separately.  pci_devres is initialized
1084 * when a device is enabled using managed PCI device enable interface.
1085 */
1086struct pci_devres {
1087        unsigned int enabled:1;
1088        unsigned int pinned:1;
1089        unsigned int orig_intx:1;
1090        unsigned int restore_intx:1;
1091        u32 region_mask;
1092};
1093
1094static void pcim_release(struct device *gendev, void *res)
1095{
1096        struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1097        struct pci_devres *this = res;
1098        int i;
1099
1100        if (dev->msi_enabled)
1101                pci_disable_msi(dev);
1102        if (dev->msix_enabled)
1103                pci_disable_msix(dev);
1104
1105        for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1106                if (this->region_mask & (1 << i))
1107                        pci_release_region(dev, i);
1108
1109        if (this->restore_intx)
1110                pci_intx(dev, this->orig_intx);
1111
1112        if (this->enabled && !this->pinned)
1113                pci_disable_device(dev);
1114}
1115
1116static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1117{
1118        struct pci_devres *dr, *new_dr;
1119
1120        dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1121        if (dr)
1122                return dr;
1123
1124        new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1125        if (!new_dr)
1126                return NULL;
1127        return devres_get(&pdev->dev, new_dr, NULL, NULL);
1128}
1129
1130static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1131{
1132        if (pci_is_managed(pdev))
1133                return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1134        return NULL;
1135}
1136
1137/**
1138 * pcim_enable_device - Managed pci_enable_device()
1139 * @pdev: PCI device to be initialized
1140 *
1141 * Managed pci_enable_device().
1142 */
1143int pcim_enable_device(struct pci_dev *pdev)
1144{
1145        struct pci_devres *dr;
1146        int rc;
1147
1148        dr = get_pci_dr(pdev);
1149        if (unlikely(!dr))
1150                return -ENOMEM;
1151        if (dr->enabled)
1152                return 0;
1153
1154        rc = pci_enable_device(pdev);
1155        if (!rc) {
1156                pdev->is_managed = 1;
1157                dr->enabled = 1;
1158        }
1159        return rc;
1160}
1161
1162/**
1163 * pcim_pin_device - Pin managed PCI device
1164 * @pdev: PCI device to pin
1165 *
1166 * Pin managed PCI device @pdev.  Pinned device won't be disabled on
1167 * driver detach.  @pdev must have been enabled with
1168 * pcim_enable_device().
1169 */
1170void pcim_pin_device(struct pci_dev *pdev)
1171{
1172        struct pci_devres *dr;
1173
1174        dr = find_pci_dr(pdev);
1175        WARN_ON(!dr || !dr->enabled);
1176        if (dr)
1177                dr->pinned = 1;
1178}
1179
1180/**
1181 * pcibios_disable_device - disable arch specific PCI resources for device dev
1182 * @dev: the PCI device to disable
1183 *
1184 * Disables architecture specific PCI resources for the device. This
1185 * is the default implementation. Architecture implementations can
1186 * override this.
1187 */
1188void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1189
1190static void do_pci_disable_device(struct pci_dev *dev)
1191{
1192        u16 pci_command;
1193
1194        pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1195        if (pci_command & PCI_COMMAND_MASTER) {
1196                pci_command &= ~PCI_COMMAND_MASTER;
1197                pci_write_config_word(dev, PCI_COMMAND, pci_command);
1198        }
1199
1200        pcibios_disable_device(dev);
1201}
1202
1203/**
1204 * pci_disable_enabled_device - Disable device without updating enable_cnt
1205 * @dev: PCI device to disable
1206 *
1207 * NOTE: This function is a backend of PCI power management routines and is
1208 * not supposed to be called drivers.
1209 */
1210void pci_disable_enabled_device(struct pci_dev *dev)
1211{
1212        if (pci_is_enabled(dev))
1213                do_pci_disable_device(dev);
1214}
1215
1216/**
1217 * pci_disable_device - Disable PCI device after use
1218 * @dev: PCI device to be disabled
1219 *
1220 * Signal to the system that the PCI device is not in use by the system
1221 * anymore.  This only involves disabling PCI bus-mastering, if active.
1222 *
1223 * Note we don't actually disable the device until all callers of
1224 * pci_enable_device() have called pci_disable_device().
1225 */
1226void
1227pci_disable_device(struct pci_dev *dev)
1228{
1229        struct pci_devres *dr;
1230
1231        dr = find_pci_dr(dev);
1232        if (dr)
1233                dr->enabled = 0;
1234
1235        if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1236                return;
1237
1238        do_pci_disable_device(dev);
1239
1240        dev->is_busmaster = 0;
1241}
1242
1243/**
1244 * pcibios_set_pcie_reset_state - set reset state for device dev
1245 * @dev: the PCIe device reset
1246 * @state: Reset state to enter into
1247 *
1248 *
1249 * Sets the PCIe reset state for the device. This is the default
1250 * implementation. Architecture implementations can override this.
1251 */
1252int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1253                                                        enum pcie_reset_state state)
1254{
1255        return -EINVAL;
1256}
1257
1258/**
1259 * pci_set_pcie_reset_state - set reset state for device dev
1260 * @dev: the PCIe device reset
1261 * @state: Reset state to enter into
1262 *
1263 *
1264 * Sets the PCI reset state for the device.
1265 */
1266int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1267{
1268        return pcibios_set_pcie_reset_state(dev, state);
1269}
1270
1271/**
1272 * pci_check_pme_status - Check if given device has generated PME.
1273 * @dev: Device to check.
1274 *
1275 * Check the PME status of the device and if set, clear it and clear PME enable
1276 * (if set).  Return 'true' if PME status and PME enable were both set or
1277 * 'false' otherwise.
1278 */
1279bool pci_check_pme_status(struct pci_dev *dev)
1280{
1281        int pmcsr_pos;
1282        u16 pmcsr;
1283        bool ret = false;
1284
1285        if (!dev->pm_cap)
1286                return false;
1287
1288        pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1289        pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1290        if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1291                return false;
1292
1293        /* Clear PME status. */
1294        pmcsr |= PCI_PM_CTRL_PME_STATUS;
1295        if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1296                /* Disable PME to avoid interrupt flood. */
1297                pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1298                ret = true;
1299        }
1300
1301        pci_write_config_word(dev, pmcsr_pos, pmcsr);
1302
1303        return ret;
1304}
1305
1306/**
1307 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1308 * @dev: Device to handle.
1309 * @ign: Ignored.
1310 *
1311 * Check if @dev has generated PME and queue a resume request for it in that
1312 * case.
1313 */
1314static int pci_pme_wakeup(struct pci_dev *dev, void *ign)
1315{
1316        if (pci_check_pme_status(dev)) {
1317                pci_wakeup_event(dev);
1318                pm_request_resume(&dev->dev);
1319        }
1320        return 0;
1321}
1322
1323/**
1324 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1325 * @bus: Top bus of the subtree to walk.
1326 */
1327void pci_pme_wakeup_bus(struct pci_bus *bus)
1328{
1329        if (bus)
1330                pci_walk_bus(bus, pci_pme_wakeup, NULL);
1331}
1332
1333/**
1334 * pci_pme_capable - check the capability of PCI device to generate PME#
1335 * @dev: PCI device to handle.
1336 * @state: PCI state from which device will issue PME#.
1337 */
1338bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1339{
1340        if (!dev->pm_cap)
1341                return false;
1342
1343        return !!(dev->pme_support & (1 << state));
1344}
1345
1346static void pci_pme_list_scan(struct work_struct *work)
1347{
1348        struct pci_pme_device *pme_dev;
1349
1350        mutex_lock(&pci_pme_list_mutex);
1351        if (!list_empty(&pci_pme_list)) {
1352                list_for_each_entry(pme_dev, &pci_pme_list, list)
1353                        pci_pme_wakeup(pme_dev->dev, NULL);
1354                schedule_delayed_work(&pci_pme_work, msecs_to_jiffies(PME_TIMEOUT));
1355        }
1356        mutex_unlock(&pci_pme_list_mutex);
1357}
1358
1359/**
1360 * pci_external_pme - is a device an external PCI PME source?
1361 * @dev: PCI device to check
1362 *
1363 */
1364
1365static bool pci_external_pme(struct pci_dev *dev)
1366{
1367        if (pci_is_pcie(dev) || dev->bus->number == 0)
1368                return false;
1369        return true;
1370}
1371
1372/**
1373 * pci_pme_active - enable or disable PCI device's PME# function
1374 * @dev: PCI device to handle.
1375 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1376 *
1377 * The caller must verify that the device is capable of generating PME# before
1378 * calling this function with @enable equal to 'true'.
1379 */
1380void pci_pme_active(struct pci_dev *dev, bool enable)
1381{
1382        u16 pmcsr;
1383
1384        if (!dev->pm_cap)
1385                return;
1386
1387        pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1388        /* Clear PME_Status by writing 1 to it and enable PME# */
1389        pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1390        if (!enable)
1391                pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1392
1393        pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1394
1395        /* PCI (as opposed to PCIe) PME requires that the device have
1396           its PME# line hooked up correctly. Not all hardware vendors
1397           do this, so the PME never gets delivered and the device
1398           remains asleep. The easiest way around this is to
1399           periodically walk the list of suspended devices and check
1400           whether any have their PME flag set. The assumption is that
1401           we'll wake up often enough anyway that this won't be a huge
1402           hit, and the power savings from the devices will still be a
1403           win. */
1404
1405        if (pci_external_pme(dev)) {
1406                struct pci_pme_device *pme_dev;
1407                if (enable) {
1408                        pme_dev = kmalloc(sizeof(struct pci_pme_device),
1409                                          GFP_KERNEL);
1410                        if (!pme_dev)
1411                                goto out;
1412                        pme_dev->dev = dev;
1413                        mutex_lock(&pci_pme_list_mutex);
1414                        list_add(&pme_dev->list, &pci_pme_list);
1415                        if (list_is_singular(&pci_pme_list))
1416                                schedule_delayed_work(&pci_pme_work,
1417                                                      msecs_to_jiffies(PME_TIMEOUT));
1418                        mutex_unlock(&pci_pme_list_mutex);
1419                } else {
1420                        mutex_lock(&pci_pme_list_mutex);
1421                        list_for_each_entry(pme_dev, &pci_pme_list, list) {
1422                                if (pme_dev->dev == dev) {
1423                                        list_del(&pme_dev->list);
1424                                        kfree(pme_dev);
1425                                        break;
1426                                }
1427                        }
1428                        mutex_unlock(&pci_pme_list_mutex);
1429                }
1430        }
1431
1432out:
1433        dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
1434                        enable ? "enabled" : "disabled");
1435}
1436
1437/**
1438 * __pci_enable_wake - enable PCI device as wakeup event source
1439 * @dev: PCI device affected
1440 * @state: PCI state from which device will issue wakeup events
1441 * @runtime: True if the events are to be generated at run time
1442 * @enable: True to enable event generation; false to disable
1443 *
1444 * This enables the device as a wakeup event source, or disables it.
1445 * When such events involves platform-specific hooks, those hooks are
1446 * called automatically by this routine.
1447 *
1448 * Devices with legacy power management (no standard PCI PM capabilities)
1449 * always require such platform hooks.
1450 *
1451 * RETURN VALUE:
1452 * 0 is returned on success
1453 * -EINVAL is returned if device is not supposed to wake up the system
1454 * Error code depending on the platform is returned if both the platform and
1455 * the native mechanism fail to enable the generation of wake-up events
1456 */
1457int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1458                      bool runtime, bool enable)
1459{
1460        int ret = 0;
1461
1462        if (enable && !runtime && !device_may_wakeup(&dev->dev))
1463                return -EINVAL;
1464
1465        /* Don't do the same thing twice in a row for one device. */
1466        if (!!enable == !!dev->wakeup_prepared)
1467                return 0;
1468
1469        /*
1470         * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1471         * Anderson we should be doing PME# wake enable followed by ACPI wake
1472         * enable.  To disable wake-up we call the platform first, for symmetry.
1473         */
1474
1475        if (enable) {
1476                int error;
1477
1478                if (pci_pme_capable(dev, state))
1479                        pci_pme_active(dev, true);
1480                else
1481                        ret = 1;
1482                error = runtime ? platform_pci_run_wake(dev, true) :
1483                                        platform_pci_sleep_wake(dev, true);
1484                if (ret)
1485                        ret = error;
1486                if (!ret)
1487                        dev->wakeup_prepared = true;
1488        } else {
1489                if (runtime)
1490                        platform_pci_run_wake(dev, false);
1491                else
1492                        platform_pci_sleep_wake(dev, false);
1493                pci_pme_active(dev, false);
1494                dev->wakeup_prepared = false;
1495        }
1496
1497        return ret;
1498}
1499EXPORT_SYMBOL(__pci_enable_wake);
1500
1501/**
1502 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1503 * @dev: PCI device to prepare
1504 * @enable: True to enable wake-up event generation; false to disable
1505 *
1506 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1507 * and this function allows them to set that up cleanly - pci_enable_wake()
1508 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1509 * ordering constraints.
1510 *
1511 * This function only returns error code if the device is not capable of
1512 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1513 * enable wake-up power for it.
1514 */
1515int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1516{
1517        return pci_pme_capable(dev, PCI_D3cold) ?
1518                        pci_enable_wake(dev, PCI_D3cold, enable) :
1519                        pci_enable_wake(dev, PCI_D3hot, enable);
1520}
1521
1522/**
1523 * pci_target_state - find an appropriate low power state for a given PCI dev
1524 * @dev: PCI device
1525 *
1526 * Use underlying platform code to find a supported low power state for @dev.
1527 * If the platform can't manage @dev, return the deepest state from which it
1528 * can generate wake events, based on any available PME info.
1529 */
1530pci_power_t pci_target_state(struct pci_dev *dev)
1531{
1532        pci_power_t target_state = PCI_D3hot;
1533
1534        if (platform_pci_power_manageable(dev)) {
1535                /*
1536                 * Call the platform to choose the target state of the device
1537                 * and enable wake-up from this state if supported.
1538                 */
1539                pci_power_t state = platform_pci_choose_state(dev);
1540
1541                switch (state) {
1542                case PCI_POWER_ERROR:
1543                case PCI_UNKNOWN:
1544                        break;
1545                case PCI_D1:
1546                case PCI_D2:
1547                        if (pci_no_d1d2(dev))
1548                                break;
1549                default:
1550                        target_state = state;
1551                }
1552        } else if (!dev->pm_cap) {
1553                target_state = PCI_D0;
1554        } else if (device_may_wakeup(&dev->dev)) {
1555                /*
1556                 * Find the deepest state from which the device can generate
1557                 * wake-up events, make it the target state and enable device
1558                 * to generate PME#.
1559                 */
1560                if (dev->pme_support) {
1561                        while (target_state
1562                              && !(dev->pme_support & (1 << target_state)))
1563                                target_state--;
1564                }
1565        }
1566
1567        return target_state;
1568}
1569
1570/**
1571 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1572 * @dev: Device to handle.
1573 *
1574 * Choose the power state appropriate for the device depending on whether
1575 * it can wake up the system and/or is power manageable by the platform
1576 * (PCI_D3hot is the default) and put the device into that state.
1577 */
1578int pci_prepare_to_sleep(struct pci_dev *dev)
1579{
1580        pci_power_t target_state = pci_target_state(dev);
1581        int error;
1582
1583        if (target_state == PCI_POWER_ERROR)
1584                return -EIO;
1585
1586        pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1587
1588        error = pci_set_power_state(dev, target_state);
1589
1590        if (error)
1591                pci_enable_wake(dev, target_state, false);
1592
1593        return error;
1594}
1595
1596/**
1597 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1598 * @dev: Device to handle.
1599 *
1600 * Disable device's system wake-up capability and put it into D0.
1601 */
1602int pci_back_from_sleep(struct pci_dev *dev)
1603{
1604        pci_enable_wake(dev, PCI_D0, false);
1605        return pci_set_power_state(dev, PCI_D0);
1606}
1607
1608/**
1609 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1610 * @dev: PCI device being suspended.
1611 *
1612 * Prepare @dev to generate wake-up events at run time and put it into a low
1613 * power state.
1614 */
1615int pci_finish_runtime_suspend(struct pci_dev *dev)
1616{
1617        pci_power_t target_state = pci_target_state(dev);
1618        int error;
1619
1620        if (target_state == PCI_POWER_ERROR)
1621                return -EIO;
1622
1623        __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1624
1625        error = pci_set_power_state(dev, target_state);
1626
1627        if (error)
1628                __pci_enable_wake(dev, target_state, true, false);
1629
1630        return error;
1631}
1632
1633/**
1634 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1635 * @dev: Device to check.
1636 *
1637 * Return true if the device itself is cabable of generating wake-up events
1638 * (through the platform or using the native PCIe PME) or if the device supports
1639 * PME and one of its upstream bridges can generate wake-up events.
1640 */
1641bool pci_dev_run_wake(struct pci_dev *dev)
1642{
1643        struct pci_bus *bus = dev->bus;
1644
1645        if (device_run_wake(&dev->dev))
1646                return true;
1647
1648        if (!dev->pme_support)
1649                return false;
1650
1651        while (bus->parent) {
1652                struct pci_dev *bridge = bus->self;
1653
1654                if (device_run_wake(&bridge->dev))
1655                        return true;
1656
1657                bus = bus->parent;
1658        }
1659
1660        /* We have reached the root bus. */
1661        if (bus->bridge)
1662                return device_run_wake(bus->bridge);
1663
1664        return false;
1665}
1666EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1667
1668/**
1669 * pci_pm_init - Initialize PM functions of given PCI device
1670 * @dev: PCI device to handle.
1671 */
1672void pci_pm_init(struct pci_dev *dev)
1673{
1674        int pm;
1675        u16 pmc;
1676
1677        pm_runtime_forbid(&dev->dev);
1678        device_enable_async_suspend(&dev->dev);
1679        dev->wakeup_prepared = false;
1680
1681        dev->pm_cap = 0;
1682
1683        /* find PCI PM capability in list */
1684        pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1685        if (!pm)
1686                return;
1687        /* Check device's ability to generate PME# */
1688        pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1689
1690        if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1691                dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1692                        pmc & PCI_PM_CAP_VER_MASK);
1693                return;
1694        }
1695
1696        dev->pm_cap = pm;
1697        dev->d3_delay = PCI_PM_D3_WAIT;
1698
1699        dev->d1_support = false;
1700        dev->d2_support = false;
1701        if (!pci_no_d1d2(dev)) {
1702                if (pmc & PCI_PM_CAP_D1)
1703                        dev->d1_support = true;
1704                if (pmc & PCI_PM_CAP_D2)
1705                        dev->d2_support = true;
1706
1707                if (dev->d1_support || dev->d2_support)
1708                        dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1709                                   dev->d1_support ? " D1" : "",
1710                                   dev->d2_support ? " D2" : "");
1711        }
1712
1713        pmc &= PCI_PM_CAP_PME_MASK;
1714        if (pmc) {
1715                dev_printk(KERN_DEBUG, &dev->dev,
1716                         "PME# supported from%s%s%s%s%s\n",
1717                         (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1718                         (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1719                         (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1720                         (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1721                         (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1722                dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1723                /*
1724                 * Make device's PM flags reflect the wake-up capability, but
1725                 * let the user space enable it to wake up the system as needed.
1726                 */
1727                device_set_wakeup_capable(&dev->dev, true);
1728                /* Disable the PME# generation functionality */
1729                pci_pme_active(dev, false);
1730        } else {
1731                dev->pme_support = 0;
1732        }
1733}
1734
1735/**
1736 * platform_pci_wakeup_init - init platform wakeup if present
1737 * @dev: PCI device
1738 *
1739 * Some devices don't have PCI PM caps but can still generate wakeup
1740 * events through platform methods (like ACPI events).  If @dev supports
1741 * platform wakeup events, set the device flag to indicate as much.  This
1742 * may be redundant if the device also supports PCI PM caps, but double
1743 * initialization should be safe in that case.
1744 */
1745void platform_pci_wakeup_init(struct pci_dev *dev)
1746{
1747        if (!platform_pci_can_wakeup(dev))
1748                return;
1749
1750        device_set_wakeup_capable(&dev->dev, true);
1751        platform_pci_sleep_wake(dev, false);
1752}
1753
1754/**
1755 * pci_add_save_buffer - allocate buffer for saving given capability registers
1756 * @dev: the PCI device
1757 * @cap: the capability to allocate the buffer for
1758 * @size: requested size of the buffer
1759 */
1760static int pci_add_cap_save_buffer(
1761        struct pci_dev *dev, char cap, unsigned int size)
1762{
1763        int pos;
1764        struct pci_cap_saved_state *save_state;
1765
1766        pos = pci_find_capability(dev, cap);
1767        if (pos <= 0)
1768                return 0;
1769
1770        save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1771        if (!save_state)
1772                return -ENOMEM;
1773
1774        save_state->cap_nr = cap;
1775        pci_add_saved_cap(dev, save_state);
1776
1777        return 0;
1778}
1779
1780/**
1781 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1782 * @dev: the PCI device
1783 */
1784void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1785{
1786        int error;
1787
1788        error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1789                                        PCI_EXP_SAVE_REGS * sizeof(u16));
1790        if (error)
1791                dev_err(&dev->dev,
1792                        "unable to preallocate PCI Express save buffer\n");
1793
1794        error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1795        if (error)
1796                dev_err(&dev->dev,
1797                        "unable to preallocate PCI-X save buffer\n");
1798}
1799
1800/**
1801 * pci_enable_ari - enable ARI forwarding if hardware support it
1802 * @dev: the PCI device
1803 */
1804void pci_enable_ari(struct pci_dev *dev)
1805{
1806        int pos;
1807        u32 cap;
1808        u16 ctrl;
1809        struct pci_dev *bridge;
1810
1811        if (!pci_is_pcie(dev) || dev->devfn)
1812                return;
1813
1814        pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1815        if (!pos)
1816                return;
1817
1818        bridge = dev->bus->self;
1819        if (!bridge || !pci_is_pcie(bridge))
1820                return;
1821
1822        pos = pci_pcie_cap(bridge);
1823        if (!pos)
1824                return;
1825
1826        pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
1827        if (!(cap & PCI_EXP_DEVCAP2_ARI))
1828                return;
1829
1830        pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
1831        ctrl |= PCI_EXP_DEVCTL2_ARI;
1832        pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
1833
1834        bridge->ari_enabled = 1;
1835}
1836
1837static int pci_acs_enable;
1838
1839/**
1840 * pci_request_acs - ask for ACS to be enabled if supported
1841 */
1842void pci_request_acs(void)
1843{
1844        pci_acs_enable = 1;
1845}
1846
1847/**
1848 * pci_enable_acs - enable ACS if hardware support it
1849 * @dev: the PCI device
1850 */
1851void pci_enable_acs(struct pci_dev *dev)
1852{
1853        int pos;
1854        u16 cap;
1855        u16 ctrl;
1856
1857        if (!pci_acs_enable)
1858                return;
1859
1860        if (!pci_is_pcie(dev))
1861                return;
1862
1863        pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
1864        if (!pos)
1865                return;
1866
1867        pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
1868        pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
1869
1870        /* Source Validation */
1871        ctrl |= (cap & PCI_ACS_SV);
1872
1873        /* P2P Request Redirect */
1874        ctrl |= (cap & PCI_ACS_RR);
1875
1876        /* P2P Completion Redirect */
1877        ctrl |= (cap & PCI_ACS_CR);
1878
1879        /* Upstream Forwarding */
1880        ctrl |= (cap & PCI_ACS_UF);
1881
1882        pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
1883}
1884
1885/**
1886 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1887 * @dev: the PCI device
1888 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1889 *
1890 * Perform INTx swizzling for a device behind one level of bridge.  This is
1891 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1892 * behind bridges on add-in cards.  For devices with ARI enabled, the slot
1893 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
1894 * the PCI Express Base Specification, Revision 2.1)
1895 */
1896u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
1897{
1898        int slot;
1899
1900        if (pci_ari_enabled(dev->bus))
1901                slot = 0;
1902        else
1903                slot = PCI_SLOT(dev->devfn);
1904
1905        return (((pin - 1) + slot) % 4) + 1;
1906}
1907
1908int
1909pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1910{
1911        u8 pin;
1912
1913        pin = dev->pin;
1914        if (!pin)
1915                return -1;
1916
1917        while (!pci_is_root_bus(dev->bus)) {
1918                pin = pci_swizzle_interrupt_pin(dev, pin);
1919                dev = dev->bus->self;
1920        }
1921        *bridge = dev;
1922        return pin;
1923}
1924
1925/**
1926 * pci_common_swizzle - swizzle INTx all the way to root bridge
1927 * @dev: the PCI device
1928 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1929 *
1930 * Perform INTx swizzling for a device.  This traverses through all PCI-to-PCI
1931 * bridges all the way up to a PCI root bus.
1932 */
1933u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
1934{
1935        u8 pin = *pinp;
1936
1937        while (!pci_is_root_bus(dev->bus)) {
1938                pin = pci_swizzle_interrupt_pin(dev, pin);
1939                dev = dev->bus->self;
1940        }
1941        *pinp = pin;
1942        return PCI_SLOT(dev->devfn);
1943}
1944
1945/**
1946 *      pci_release_region - Release a PCI bar
1947 *      @pdev: PCI device whose resources were previously reserved by pci_request_region
1948 *      @bar: BAR to release
1949 *
1950 *      Releases the PCI I/O and memory resources previously reserved by a
1951 *      successful call to pci_request_region.  Call this function only
1952 *      after all use of the PCI regions has ceased.
1953 */
1954void pci_release_region(struct pci_dev *pdev, int bar)
1955{
1956        struct pci_devres *dr;
1957
1958        if (pci_resource_len(pdev, bar) == 0)
1959                return;
1960        if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1961                release_region(pci_resource_start(pdev, bar),
1962                                pci_resource_len(pdev, bar));
1963        else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1964                release_mem_region(pci_resource_start(pdev, bar),
1965                                pci_resource_len(pdev, bar));
1966
1967        dr = find_pci_dr(pdev);
1968        if (dr)
1969                dr->region_mask &= ~(1 << bar);
1970}
1971
1972/**
1973 *      __pci_request_region - Reserved PCI I/O and memory resource
1974 *      @pdev: PCI device whose resources are to be reserved
1975 *      @bar: BAR to be reserved
1976 *      @res_name: Name to be associated with resource.
1977 *      @exclusive: whether the region access is exclusive or not
1978 *
1979 *      Mark the PCI region associated with PCI device @pdev BR @bar as
1980 *      being reserved by owner @res_name.  Do not access any
1981 *      address inside the PCI regions unless this call returns
1982 *      successfully.
1983 *
1984 *      If @exclusive is set, then the region is marked so that userspace
1985 *      is explicitly not allowed to map the resource via /dev/mem or
1986 *      sysfs MMIO access.
1987 *
1988 *      Returns 0 on success, or %EBUSY on error.  A warning
1989 *      message is also printed on failure.
1990 */
1991static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
1992                                                                        int exclusive)
1993{
1994        struct pci_devres *dr;
1995
1996        if (pci_resource_len(pdev, bar) == 0)
1997                return 0;
1998                
1999        if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2000                if (!request_region(pci_resource_start(pdev, bar),
2001                            pci_resource_len(pdev, bar), res_name))
2002                        goto err_out;
2003        }
2004        else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2005                if (!__request_mem_region(pci_resource_start(pdev, bar),
2006                                        pci_resource_len(pdev, bar), res_name,
2007                                        exclusive))
2008                        goto err_out;
2009        }
2010
2011        dr = find_pci_dr(pdev);
2012        if (dr)
2013                dr->region_mask |= 1 << bar;
2014
2015        return 0;
2016
2017err_out:
2018        dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2019                 &pdev->resource[bar]);
2020        return -EBUSY;
2021}
2022
2023/**
2024 *      pci_request_region - Reserve PCI I/O and memory resource
2025 *      @pdev: PCI device whose resources are to be reserved
2026 *      @bar: BAR to be reserved
2027 *      @res_name: Name to be associated with resource
2028 *
2029 *      Mark the PCI region associated with PCI device @pdev BAR @bar as
2030 *      being reserved by owner @res_name.  Do not access any
2031 *      address inside the PCI regions unless this call returns
2032 *      successfully.
2033 *
2034 *      Returns 0 on success, or %EBUSY on error.  A warning
2035 *      message is also printed on failure.
2036 */
2037int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2038{
2039        return __pci_request_region(pdev, bar, res_name, 0);
2040}
2041
2042/**
2043 *      pci_request_region_exclusive - Reserved PCI I/O and memory resource
2044 *      @pdev: PCI device whose resources are to be reserved
2045 *      @bar: BAR to be reserved
2046 *      @res_name: Name to be associated with resource.
2047 *
2048 *      Mark the PCI region associated with PCI device @pdev BR @bar as
2049 *      being reserved by owner @res_name.  Do not access any
2050 *      address inside the PCI regions unless this call returns
2051 *      successfully.
2052 *
2053 *      Returns 0 on success, or %EBUSY on error.  A warning
2054 *      message is also printed on failure.
2055 *
2056 *      The key difference that _exclusive makes it that userspace is
2057 *      explicitly not allowed to map the resource via /dev/mem or
2058 *      sysfs.
2059 */
2060int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2061{
2062        return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2063}
2064/**
2065 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2066 * @pdev: PCI device whose resources were previously reserved
2067 * @bars: Bitmask of BARs to be released
2068 *
2069 * Release selected PCI I/O and memory resources previously reserved.
2070 * Call this function only after all use of the PCI regions has ceased.
2071 */
2072void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2073{
2074        int i;
2075
2076        for (i = 0; i < 6; i++)
2077                if (bars & (1 << i))
2078                        pci_release_region(pdev, i);
2079}
2080
2081int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2082                                 const char *res_name, int excl)
2083{
2084        int i;
2085
2086        for (i = 0; i < 6; i++)
2087                if (bars & (1 << i))
2088                        if (__pci_request_region(pdev, i, res_name, excl))
2089                                goto err_out;
2090        return 0;
2091
2092err_out:
2093        while(--i >= 0)
2094                if (bars & (1 << i))
2095                        pci_release_region(pdev, i);
2096
2097        return -EBUSY;
2098}
2099
2100
2101/**
2102 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2103 * @pdev: PCI device whose resources are to be reserved
2104 * @bars: Bitmask of BARs to be requested
2105 * @res_name: Name to be associated with resource
2106 */
2107int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2108                                 const char *res_name)
2109{
2110        return __pci_request_selected_regions(pdev, bars, res_name, 0);
2111}
2112
2113int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2114                                 int bars, const char *res_name)
2115{
2116        return __pci_request_selected_regions(pdev, bars, res_name,
2117                        IORESOURCE_EXCLUSIVE);
2118}
2119
2120/**
2121 *      pci_release_regions - Release reserved PCI I/O and memory resources
2122 *      @pdev: PCI device whose resources were previously reserved by pci_request_regions
2123 *
2124 *      Releases all PCI I/O and memory resources previously reserved by a
2125 *      successful call to pci_request_regions.  Call this function only
2126 *      after all use of the PCI regions has ceased.
2127 */
2128
2129void pci_release_regions(struct pci_dev *pdev)
2130{
2131        pci_release_selected_regions(pdev, (1 << 6) - 1);
2132}
2133
2134/**
2135 *      pci_request_regions - Reserved PCI I/O and memory resources
2136 *      @pdev: PCI device whose resources are to be reserved
2137 *      @res_name: Name to be associated with resource.
2138 *
2139 *      Mark all PCI regions associated with PCI device @pdev as
2140 *      being reserved by owner @res_name.  Do not access any
2141 *      address inside the PCI regions unless this call returns
2142 *      successfully.
2143 *
2144 *      Returns 0 on success, or %EBUSY on error.  A warning
2145 *      message is also printed on failure.
2146 */
2147int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2148{
2149        return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2150}
2151
2152/**
2153 *      pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2154 *      @pdev: PCI device whose resources are to be reserved
2155 *      @res_name: Name to be associated with resource.
2156 *
2157 *      Mark all PCI regions associated with PCI device @pdev as
2158 *      being reserved by owner @res_name.  Do not access any
2159 *      address inside the PCI regions unless this call returns
2160 *      successfully.
2161 *
2162 *      pci_request_regions_exclusive() will mark the region so that
2163 *      /dev/mem and the sysfs MMIO access will not be allowed.
2164 *
2165 *      Returns 0 on success, or %EBUSY on error.  A warning
2166 *      message is also printed on failure.
2167 */
2168int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2169{
2170        return pci_request_selected_regions_exclusive(pdev,
2171                                        ((1 << 6) - 1), res_name);
2172}
2173
2174static void __pci_set_master(struct pci_dev *dev, bool enable)
2175{
2176        u16 old_cmd, cmd;
2177
2178        pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2179        if (enable)
2180                cmd = old_cmd | PCI_COMMAND_MASTER;
2181        else
2182                cmd = old_cmd & ~PCI_COMMAND_MASTER;
2183        if (cmd != old_cmd) {
2184                dev_dbg(&dev->dev, "%s bus mastering\n",
2185                        enable ? "enabling" : "disabling");
2186                pci_write_config_word(dev, PCI_COMMAND, cmd);
2187        }
2188        dev->is_busmaster = enable;
2189}
2190
2191/**
2192 * pci_set_master - enables bus-mastering for device dev
2193 * @dev: the PCI device to enable
2194 *
2195 * Enables bus-mastering on the device and calls pcibios_set_master()
2196 * to do the needed arch specific settings.
2197 */
2198void pci_set_master(struct pci_dev *dev)
2199{
2200        __pci_set_master(dev, true);
2201        pcibios_set_master(dev);
2202}
2203
2204/**
2205 * pci_clear_master - disables bus-mastering for device dev
2206 * @dev: the PCI device to disable
2207 */
2208void pci_clear_master(struct pci_dev *dev)
2209{
2210        __pci_set_master(dev, false);
2211}
2212
2213/**
2214 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2215 * @dev: the PCI device for which MWI is to be enabled
2216 *
2217 * Helper function for pci_set_mwi.
2218 * Originally copied from drivers/net/acenic.c.
2219 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2220 *
2221 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2222 */
2223int pci_set_cacheline_size(struct pci_dev *dev)
2224{
2225        u8 cacheline_size;
2226
2227        if (!pci_cache_line_size)
2228                return -EINVAL;
2229
2230        /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2231           equal to or multiple of the right value. */
2232        pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2233        if (cacheline_size >= pci_cache_line_size &&
2234            (cacheline_size % pci_cache_line_size) == 0)
2235                return 0;
2236
2237        /* Write the correct value. */
2238        pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2239        /* Read it back. */
2240        pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2241        if (cacheline_size == pci_cache_line_size)
2242                return 0;
2243
2244        dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2245                   "supported\n", pci_cache_line_size << 2);
2246
2247        return -EINVAL;
2248}
2249EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2250
2251#ifdef PCI_DISABLE_MWI
2252int pci_set_mwi(struct pci_dev *dev)
2253{
2254        return 0;
2255}
2256
2257int pci_try_set_mwi(struct pci_dev *dev)
2258{
2259        return 0;
2260}
2261
2262void pci_clear_mwi(struct pci_dev *dev)
2263{
2264}
2265
2266#else
2267
2268/**
2269 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2270 * @dev: the PCI device for which MWI is enabled
2271 *
2272 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2273 *
2274 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2275 */
2276int
2277pci_set_mwi(struct pci_dev *dev)
2278{
2279        int rc;
2280        u16 cmd;
2281
2282        rc = pci_set_cacheline_size(dev);
2283        if (rc)
2284                return rc;
2285
2286        pci_read_config_word(dev, PCI_COMMAND, &cmd);
2287        if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2288                dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2289                cmd |= PCI_COMMAND_INVALIDATE;
2290                pci_write_config_word(dev, PCI_COMMAND, cmd);
2291        }
2292        
2293        return 0;
2294}
2295
2296/**
2297 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2298 * @dev: the PCI device for which MWI is enabled
2299 *
2300 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2301 * Callers are not required to check the return value.
2302 *
2303 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2304 */
2305int pci_try_set_mwi(struct pci_dev *dev)
2306{
2307        int rc = pci_set_mwi(dev);
2308        return rc;
2309}
2310
2311/**
2312 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2313 * @dev: the PCI device to disable
2314 *
2315 * Disables PCI Memory-Write-Invalidate transaction on the device
2316 */
2317void
2318pci_clear_mwi(struct pci_dev *dev)
2319{
2320        u16 cmd;
2321
2322        pci_read_config_word(dev, PCI_COMMAND, &cmd);
2323        if (cmd & PCI_COMMAND_INVALIDATE) {
2324                cmd &= ~PCI_COMMAND_INVALIDATE;
2325                pci_write_config_word(dev, PCI_COMMAND, cmd);
2326        }
2327}
2328#endif /* ! PCI_DISABLE_MWI */
2329
2330/**
2331 * pci_intx - enables/disables PCI INTx for device dev
2332 * @pdev: the PCI device to operate on
2333 * @enable: boolean: whether to enable or disable PCI INTx
2334 *
2335 * Enables/disables PCI INTx for device dev
2336 */
2337void
2338pci_intx(struct pci_dev *pdev, int enable)
2339{
2340        u16 pci_command, new;
2341
2342        pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2343
2344        if (enable) {
2345                new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2346        } else {
2347                new = pci_command | PCI_COMMAND_INTX_DISABLE;
2348        }
2349
2350        if (new != pci_command) {
2351                struct pci_devres *dr;
2352
2353                pci_write_config_word(pdev, PCI_COMMAND, new);
2354
2355                dr = find_pci_dr(pdev);
2356                if (dr && !dr->restore_intx) {
2357                        dr->restore_intx = 1;
2358                        dr->orig_intx = !enable;
2359                }
2360        }
2361}
2362
2363/**
2364 * pci_msi_off - disables any msi or msix capabilities
2365 * @dev: the PCI device to operate on
2366 *
2367 * If you want to use msi see pci_enable_msi and friends.
2368 * This is a lower level primitive that allows us to disable
2369 * msi operation at the device level.
2370 */
2371void pci_msi_off(struct pci_dev *dev)
2372{
2373        int pos;
2374        u16 control;
2375
2376        pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2377        if (pos) {
2378                pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2379                control &= ~PCI_MSI_FLAGS_ENABLE;
2380                pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2381        }
2382        pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2383        if (pos) {
2384                pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2385                control &= ~PCI_MSIX_FLAGS_ENABLE;
2386                pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2387        }
2388}
2389EXPORT_SYMBOL_GPL(pci_msi_off);
2390
2391int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2392{
2393        return dma_set_max_seg_size(&dev->dev, size);
2394}
2395EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2396
2397int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2398{
2399        return dma_set_seg_boundary(&dev->dev, mask);
2400}
2401EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2402
2403static int pcie_flr(struct pci_dev *dev, int probe)
2404{
2405        int i;
2406        int pos;
2407        u32 cap;
2408        u16 status, control;
2409
2410        pos = pci_pcie_cap(dev);
2411        if (!pos)
2412                return -ENOTTY;
2413
2414        pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
2415        if (!(cap & PCI_EXP_DEVCAP_FLR))
2416                return -ENOTTY;
2417
2418        if (probe)
2419                return 0;
2420
2421        /* Wait for Transaction Pending bit clean */
2422        for (i = 0; i < 4; i++) {
2423                if (i)
2424                        msleep((1 << (i - 1)) * 100);
2425
2426                pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2427                if (!(status & PCI_EXP_DEVSTA_TRPND))
2428                        goto clear;
2429        }
2430
2431        dev_err(&dev->dev, "transaction is not cleared; "
2432                        "proceeding with reset anyway\n");
2433
2434clear:
2435        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
2436        control |= PCI_EXP_DEVCTL_BCR_FLR;
2437        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
2438
2439        msleep(100);
2440
2441        return 0;
2442}
2443
2444static int pci_af_flr(struct pci_dev *dev, int probe)
2445{
2446        int i;
2447        int pos;
2448        u8 cap;
2449        u8 status;
2450
2451        pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2452        if (!pos)
2453                return -ENOTTY;
2454
2455        pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
2456        if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2457                return -ENOTTY;
2458
2459        if (probe)
2460                return 0;
2461
2462        /* Wait for Transaction Pending bit clean */
2463        for (i = 0; i < 4; i++) {
2464                if (i)
2465                        msleep((1 << (i - 1)) * 100);
2466
2467                pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2468                if (!(status & PCI_AF_STATUS_TP))
2469                        goto clear;
2470        }
2471
2472        dev_err(&dev->dev, "transaction is not cleared; "
2473                        "proceeding with reset anyway\n");
2474
2475clear:
2476        pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
2477        msleep(100);
2478
2479        return 0;
2480}
2481
2482static int pci_pm_reset(struct pci_dev *dev, int probe)
2483{
2484        u16 csr;
2485
2486        if (!dev->pm_cap)
2487                return -ENOTTY;
2488
2489        pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2490        if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2491                return -ENOTTY;
2492
2493        if (probe)
2494                return 0;
2495
2496        if (dev->current_state != PCI_D0)
2497                return -EINVAL;
2498
2499        csr &= ~PCI_PM_CTRL_STATE_MASK;
2500        csr |= PCI_D3hot;
2501        pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2502        pci_dev_d3_sleep(dev);
2503
2504        csr &= ~PCI_PM_CTRL_STATE_MASK;
2505        csr |= PCI_D0;
2506        pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2507        pci_dev_d3_sleep(dev);
2508
2509        return 0;
2510}
2511
2512static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2513{
2514        u16 ctrl;
2515        struct pci_dev *pdev;
2516
2517        if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
2518                return -ENOTTY;
2519
2520        list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2521                if (pdev != dev)
2522                        return -ENOTTY;
2523
2524        if (probe)
2525                return 0;
2526
2527        pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2528        ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2529        pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2530        msleep(100);
2531
2532        ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2533        pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2534        msleep(100);
2535
2536        return 0;
2537}
2538
2539static int pci_dev_reset(struct pci_dev *dev, int probe)
2540{
2541        int rc;
2542
2543        might_sleep();
2544
2545        if (!probe) {
2546                pci_block_user_cfg_access(dev);
2547                /* block PM suspend, driver probe, etc. */
2548                device_lock(&dev->dev);
2549        }
2550
2551        rc = pci_dev_specific_reset(dev, probe);
2552        if (rc != -ENOTTY)
2553                goto done;
2554
2555        rc = pcie_flr(dev, probe);
2556        if (rc != -ENOTTY)
2557                goto done;
2558
2559        rc = pci_af_flr(dev, probe);
2560        if (rc != -ENOTTY)
2561                goto done;
2562
2563        rc = pci_pm_reset(dev, probe);
2564        if (rc != -ENOTTY)
2565                goto done;
2566
2567        rc = pci_parent_bus_reset(dev, probe);
2568done:
2569        if (!probe) {
2570                device_unlock(&dev->dev);
2571                pci_unblock_user_cfg_access(dev);
2572        }
2573
2574        return rc;
2575}
2576
2577/**
2578 * __pci_reset_function - reset a PCI device function
2579 * @dev: PCI device to reset
2580 *
2581 * Some devices allow an individual function to be reset without affecting
2582 * other functions in the same device.  The PCI device must be responsive
2583 * to PCI config space in order to use this function.
2584 *
2585 * The device function is presumed to be unused when this function is called.
2586 * Resetting the device will make the contents of PCI configuration space
2587 * random, so any caller of this must be prepared to reinitialise the
2588 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2589 * etc.
2590 *
2591 * Returns 0 if the device function was successfully reset or negative if the
2592 * device doesn't support resetting a single function.
2593 */
2594int __pci_reset_function(struct pci_dev *dev)
2595{
2596        return pci_dev_reset(dev, 0);
2597}
2598EXPORT_SYMBOL_GPL(__pci_reset_function);
2599
2600/**
2601 * pci_probe_reset_function - check whether the device can be safely reset
2602 * @dev: PCI device to reset
2603 *
2604 * Some devices allow an individual function to be reset without affecting
2605 * other functions in the same device.  The PCI device must be responsive
2606 * to PCI config space in order to use this function.
2607 *
2608 * Returns 0 if the device function can be reset or negative if the
2609 * device doesn't support resetting a single function.
2610 */
2611int pci_probe_reset_function(struct pci_dev *dev)
2612{
2613        return pci_dev_reset(dev, 1);
2614}
2615
2616/**
2617 * pci_reset_function - quiesce and reset a PCI device function
2618 * @dev: PCI device to reset
2619 *
2620 * Some devices allow an individual function to be reset without affecting
2621 * other functions in the same device.  The PCI device must be responsive
2622 * to PCI config space in order to use this function.
2623 *
2624 * This function does not just reset the PCI portion of a device, but
2625 * clears all the state associated with the device.  This function differs
2626 * from __pci_reset_function in that it saves and restores device state
2627 * over the reset.
2628 *
2629 * Returns 0 if the device function was successfully reset or negative if the
2630 * device doesn't support resetting a single function.
2631 */
2632int pci_reset_function(struct pci_dev *dev)
2633{
2634        int rc;
2635
2636        rc = pci_dev_reset(dev, 1);
2637        if (rc)
2638                return rc;
2639
2640        pci_save_state(dev);
2641
2642        /*
2643         * both INTx and MSI are disabled after the Interrupt Disable bit
2644         * is set and the Bus Master bit is cleared.
2645         */
2646        pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
2647
2648        rc = pci_dev_reset(dev, 0);
2649
2650        pci_restore_state(dev);
2651
2652        return rc;
2653}
2654EXPORT_SYMBOL_GPL(pci_reset_function);
2655
2656/**
2657 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2658 * @dev: PCI device to query
2659 *
2660 * Returns mmrbc: maximum designed memory read count in bytes
2661 *    or appropriate error value.
2662 */
2663int pcix_get_max_mmrbc(struct pci_dev *dev)
2664{
2665        int cap;
2666        u32 stat;
2667
2668        cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2669        if (!cap)
2670                return -EINVAL;
2671
2672        if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
2673                return -EINVAL;
2674
2675        return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
2676}
2677EXPORT_SYMBOL(pcix_get_max_mmrbc);
2678
2679/**
2680 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2681 * @dev: PCI device to query
2682 *
2683 * Returns mmrbc: maximum memory read count in bytes
2684 *    or appropriate error value.
2685 */
2686int pcix_get_mmrbc(struct pci_dev *dev)
2687{
2688        int cap;
2689        u16 cmd;
2690
2691        cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2692        if (!cap)
2693                return -EINVAL;
2694
2695        if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
2696                return -EINVAL;
2697
2698        return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
2699}
2700EXPORT_SYMBOL(pcix_get_mmrbc);
2701
2702/**
2703 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2704 * @dev: PCI device to query
2705 * @mmrbc: maximum memory read count in bytes
2706 *    valid values are 512, 1024, 2048, 4096
2707 *
2708 * If possible sets maximum memory read byte count, some bridges have erratas
2709 * that prevent this.
2710 */
2711int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
2712{
2713        int cap;
2714        u32 stat, v, o;
2715        u16 cmd;
2716
2717        if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
2718                return -EINVAL;
2719
2720        v = ffs(mmrbc) - 10;
2721
2722        cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2723        if (!cap)
2724                return -EINVAL;
2725
2726        if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
2727                return -EINVAL;
2728
2729        if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
2730                return -E2BIG;
2731
2732        if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
2733                return -EINVAL;
2734
2735        o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
2736        if (o != v) {
2737                if (v > o && dev->bus &&
2738                   (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
2739                        return -EIO;
2740
2741                cmd &= ~PCI_X_CMD_MAX_READ;
2742                cmd |= v << 2;
2743                if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
2744                        return -EIO;
2745        }
2746        return 0;
2747}
2748EXPORT_SYMBOL(pcix_set_mmrbc);
2749
2750/**
2751 * pcie_get_readrq - get PCI Express read request size
2752 * @dev: PCI device to query
2753 *
2754 * Returns maximum memory read request in bytes
2755 *    or appropriate error value.
2756 */
2757int pcie_get_readrq(struct pci_dev *dev)
2758{
2759        int ret, cap;
2760        u16 ctl;
2761
2762        cap = pci_pcie_cap(dev);
2763        if (!cap)
2764                return -EINVAL;
2765
2766        ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2767        if (!ret)
2768                ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
2769
2770        return ret;
2771}
2772EXPORT_SYMBOL(pcie_get_readrq);
2773
2774/**
2775 * pcie_set_readrq - set PCI Express maximum memory read request
2776 * @dev: PCI device to query
2777 * @rq: maximum memory read count in bytes
2778 *    valid values are 128, 256, 512, 1024, 2048, 4096
2779 *
2780 * If possible sets maximum read byte count
2781 */
2782int pcie_set_readrq(struct pci_dev *dev, int rq)
2783{
2784        int cap, err = -EINVAL;
2785        u16 ctl, v;
2786
2787        if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
2788                goto out;
2789
2790        v = (ffs(rq) - 8) << 12;
2791
2792        cap = pci_pcie_cap(dev);
2793        if (!cap)
2794                goto out;
2795
2796        err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2797        if (err)
2798                goto out;
2799
2800        if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
2801                ctl &= ~PCI_EXP_DEVCTL_READRQ;
2802                ctl |= v;
2803                err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
2804        }
2805
2806out:
2807        return err;
2808}
2809EXPORT_SYMBOL(pcie_set_readrq);
2810
2811/**
2812 * pci_select_bars - Make BAR mask from the type of resource
2813 * @dev: the PCI device for which BAR mask is made
2814 * @flags: resource type mask to be selected
2815 *
2816 * This helper routine makes bar mask from the type of resource.
2817 */
2818int pci_select_bars(struct pci_dev *dev, unsigned long flags)
2819{
2820        int i, bars = 0;
2821        for (i = 0; i < PCI_NUM_RESOURCES; i++)
2822                if (pci_resource_flags(dev, i) & flags)
2823                        bars |= (1 << i);
2824        return bars;
2825}
2826
2827/**
2828 * pci_resource_bar - get position of the BAR associated with a resource
2829 * @dev: the PCI device
2830 * @resno: the resource number
2831 * @type: the BAR type to be filled in
2832 *
2833 * Returns BAR position in config space, or 0 if the BAR is invalid.
2834 */
2835int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
2836{
2837        int reg;
2838
2839        if (resno < PCI_ROM_RESOURCE) {
2840                *type = pci_bar_unknown;
2841                return PCI_BASE_ADDRESS_0 + 4 * resno;
2842        } else if (resno == PCI_ROM_RESOURCE) {
2843                *type = pci_bar_mem32;
2844                return dev->rom_base_reg;
2845        } else if (resno < PCI_BRIDGE_RESOURCES) {
2846                /* device specific resource */
2847                reg = pci_iov_resource_bar(dev, resno, type);
2848                if (reg)
2849                        return reg;
2850        }
2851
2852        dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
2853        return 0;
2854}
2855
2856/* Some architectures require additional programming to enable VGA */
2857static arch_set_vga_state_t arch_set_vga_state;
2858
2859void __init pci_register_set_vga_state(arch_set_vga_state_t func)
2860{
2861        arch_set_vga_state = func;      /* NULL disables */
2862}
2863
2864static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
2865                      unsigned int command_bits, bool change_bridge)
2866{
2867        if (arch_set_vga_state)
2868                return arch_set_vga_state(dev, decode, command_bits,
2869                                                change_bridge);
2870        return 0;
2871}
2872
2873/**
2874 * pci_set_vga_state - set VGA decode state on device and parents if requested
2875 * @dev: the PCI device
2876 * @decode: true = enable decoding, false = disable decoding
2877 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
2878 * @change_bridge: traverse ancestors and change bridges
2879 */
2880int pci_set_vga_state(struct pci_dev *dev, bool decode,
2881                      unsigned int command_bits, bool change_bridge)
2882{
2883        struct pci_bus *bus;
2884        struct pci_dev *bridge;
2885        u16 cmd;
2886        int rc;
2887
2888        WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
2889
2890        /* ARCH specific VGA enables */
2891        rc = pci_set_vga_state_arch(dev, decode, command_bits, change_bridge);
2892        if (rc)
2893                return rc;
2894
2895        pci_read_config_word(dev, PCI_COMMAND, &cmd);
2896        if (decode == true)
2897                cmd |= command_bits;
2898        else
2899                cmd &= ~command_bits;
2900        pci_write_config_word(dev, PCI_COMMAND, cmd);
2901
2902        if (change_bridge == false)
2903                return 0;
2904
2905        bus = dev->bus;
2906        while (bus) {
2907                bridge = bus->self;
2908                if (bridge) {
2909                        pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
2910                                             &cmd);
2911                        if (decode == true)
2912                                cmd |= PCI_BRIDGE_CTL_VGA;
2913                        else
2914                                cmd &= ~PCI_BRIDGE_CTL_VGA;
2915                        pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
2916                                              cmd);
2917                }
2918                bus = bus->parent;
2919        }
2920        return 0;
2921}
2922
2923#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2924static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
2925static DEFINE_SPINLOCK(resource_alignment_lock);
2926
2927/**
2928 * pci_specified_resource_alignment - get resource alignment specified by user.
2929 * @dev: the PCI device to get
2930 *
2931 * RETURNS: Resource alignment if it is specified.
2932 *          Zero if it is not specified.
2933 */
2934resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
2935{
2936        int seg, bus, slot, func, align_order, count;
2937        resource_size_t align = 0;
2938        char *p;
2939
2940        spin_lock(&resource_alignment_lock);
2941        p = resource_alignment_param;
2942        while (*p) {
2943                count = 0;
2944                if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
2945                                                        p[count] == '@') {
2946                        p += count + 1;
2947                } else {
2948                        align_order = -1;
2949                }
2950                if (sscanf(p, "%x:%x:%x.%x%n",
2951                        &seg, &bus, &slot, &func, &count) != 4) {
2952                        seg = 0;
2953                        if (sscanf(p, "%x:%x.%x%n",
2954                                        &bus, &slot, &func, &count) != 3) {
2955                                /* Invalid format */
2956                                printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
2957                                        p);
2958                                break;
2959                        }
2960                }
2961                p += count;
2962                if (seg == pci_domain_nr(dev->bus) &&
2963                        bus == dev->bus->number &&
2964                        slot == PCI_SLOT(dev->devfn) &&
2965                        func == PCI_FUNC(dev->devfn)) {
2966                        if (align_order == -1) {
2967                                align = PAGE_SIZE;
2968                        } else {
2969                                align = 1 << align_order;
2970                        }
2971                        /* Found */
2972                        break;
2973                }
2974                if (*p != ';' && *p != ',') {
2975                        /* End of param or invalid format */
2976                        break;
2977                }
2978                p++;
2979        }
2980        spin_unlock(&resource_alignment_lock);
2981        return align;
2982}
2983
2984/**
2985 * pci_is_reassigndev - check if specified PCI is target device to reassign
2986 * @dev: the PCI device to check
2987 *
2988 * RETURNS: non-zero for PCI device is a target device to reassign,
2989 *          or zero is not.
2990 */
2991int pci_is_reassigndev(struct pci_dev *dev)
2992{
2993        return (pci_specified_resource_alignment(dev) != 0);
2994}
2995
2996ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
2997{
2998        if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
2999                count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
3000        spin_lock(&resource_alignment_lock);
3001        strncpy(resource_alignment_param, buf, count);
3002        resource_alignment_param[count] = '\0';
3003        spin_unlock(&resource_alignment_lock);
3004        return count;
3005}
3006
3007ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
3008{
3009        size_t count;
3010        spin_lock(&resource_alignment_lock);
3011        count = snprintf(buf, size, "%s", resource_alignment_param);
3012        spin_unlock(&resource_alignment_lock);
3013        return count;
3014}
3015
3016static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
3017{
3018        return pci_get_resource_alignment_param(buf, PAGE_SIZE);
3019}
3020
3021static ssize_t pci_resource_alignment_store(struct bus_type *bus,
3022                                        const char *buf, size_t count)
3023{
3024        return pci_set_resource_alignment_param(buf, count);
3025}
3026
3027BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
3028                                        pci_resource_alignment_store);
3029
3030static int __init pci_resource_alignment_sysfs_init(void)
3031{
3032        return bus_create_file(&pci_bus_type,
3033                                        &bus_attr_resource_alignment);
3034}
3035
3036late_initcall(pci_resource_alignment_sysfs_init);
3037
3038static void __devinit pci_no_domains(void)
3039{
3040#ifdef CONFIG_PCI_DOMAINS
3041        pci_domains_supported = 0;
3042#endif
3043}
3044
3045/**
3046 * pci_ext_cfg_enabled - can we access extended PCI config space?
3047 * @dev: The PCI device of the root bridge.
3048 *
3049 * Returns 1 if we can access PCI extended config space (offsets
3050 * greater than 0xff). This is the default implementation. Architecture
3051 * implementations can override this.
3052 */
3053int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
3054{
3055        return 1;
3056}
3057
3058void __weak pci_fixup_cardbus(struct pci_bus *bus)
3059{
3060}
3061EXPORT_SYMBOL(pci_fixup_cardbus);
3062
3063static int __init pci_setup(char *str)
3064{
3065        while (str) {
3066                char *k = strchr(str, ',');
3067                if (k)
3068                        *k++ = 0;
3069                if (*str && (str = pcibios_setup(str)) && *str) {
3070                        if (!strcmp(str, "nomsi")) {
3071                                pci_no_msi();
3072                        } else if (!strcmp(str, "noaer")) {
3073                                pci_no_aer();
3074                        } else if (!strcmp(str, "nodomains")) {
3075                                pci_no_domains();
3076                        } else if (!strncmp(str, "cbiosize=", 9)) {
3077                                pci_cardbus_io_size = memparse(str + 9, &str);
3078                        } else if (!strncmp(str, "cbmemsize=", 10)) {
3079                                pci_cardbus_mem_size = memparse(str + 10, &str);
3080                        } else if (!strncmp(str, "resource_alignment=", 19)) {
3081                                pci_set_resource_alignment_param(str + 19,
3082                                                        strlen(str + 19));
3083                        } else if (!strncmp(str, "ecrc=", 5)) {
3084                                pcie_ecrc_get_policy(str + 5);
3085                        } else if (!strncmp(str, "hpiosize=", 9)) {
3086                                pci_hotplug_io_size = memparse(str + 9, &str);
3087                        } else if (!strncmp(str, "hpmemsize=", 10)) {
3088                                pci_hotplug_mem_size = memparse(str + 10, &str);
3089                        } else {
3090                                printk(KERN_ERR "PCI: Unknown option `%s'\n",
3091                                                str);
3092                        }
3093                }
3094                str = k;
3095        }
3096        return 0;
3097}
3098early_param("pci", pci_setup);
3099
3100EXPORT_SYMBOL(pci_reenable_device);
3101EXPORT_SYMBOL(pci_enable_device_io);
3102EXPORT_SYMBOL(pci_enable_device_mem);
3103EXPORT_SYMBOL(pci_enable_device);
3104EXPORT_SYMBOL(pcim_enable_device);
3105EXPORT_SYMBOL(pcim_pin_device);
3106EXPORT_SYMBOL(pci_disable_device);
3107EXPORT_SYMBOL(pci_find_capability);
3108EXPORT_SYMBOL(pci_bus_find_capability);
3109EXPORT_SYMBOL(pci_release_regions);
3110EXPORT_SYMBOL(pci_request_regions);
3111EXPORT_SYMBOL(pci_request_regions_exclusive);
3112EXPORT_SYMBOL(pci_release_region);
3113EXPORT_SYMBOL(pci_request_region);
3114EXPORT_SYMBOL(pci_request_region_exclusive);
3115EXPORT_SYMBOL(pci_release_selected_regions);
3116EXPORT_SYMBOL(pci_request_selected_regions);
3117EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3118EXPORT_SYMBOL(pci_set_master);
3119EXPORT_SYMBOL(pci_clear_master);
3120EXPORT_SYMBOL(pci_set_mwi);
3121EXPORT_SYMBOL(pci_try_set_mwi);
3122EXPORT_SYMBOL(pci_clear_mwi);
3123EXPORT_SYMBOL_GPL(pci_intx);
3124EXPORT_SYMBOL(pci_assign_resource);
3125EXPORT_SYMBOL(pci_find_parent_resource);
3126EXPORT_SYMBOL(pci_select_bars);
3127
3128EXPORT_SYMBOL(pci_set_power_state);
3129EXPORT_SYMBOL(pci_save_state);
3130EXPORT_SYMBOL(pci_restore_state);
3131EXPORT_SYMBOL(pci_pme_capable);
3132EXPORT_SYMBOL(pci_pme_active);
3133EXPORT_SYMBOL(pci_wake_from_d3);
3134EXPORT_SYMBOL(pci_target_state);
3135EXPORT_SYMBOL(pci_prepare_to_sleep);
3136EXPORT_SYMBOL(pci_back_from_sleep);
3137EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
3138
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