LXR linux/drivers/staging/brcm80211/include/siutils.h

   1/*
   2 * Copyright (c) 2010 Broadcom Corporation
   3 *
   4 * Permission to use, copy, modify, and/or distribute this software for any
   5 * purpose with or without fee is hereby granted, provided that the above
   6 * copyright notice and this permission notice appear in all copies.
   7 *
   8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15 */
  16
  17#ifndef _siutils_h_
  18#define _siutils_h_
  19
  20#include <hndsoc.h>
  21
  22#if !defined(WLC_LOW)
  23#include "bcm_rpc.h"
  24#endif
  25/*
  26 * Data structure to export all chip specific common variables
  27 *   public (read-only) portion of siutils handle returned by si_attach()
  28 */
  29struct si_pub {
  30        uint socitype;          /* SOCI_SB, SOCI_AI */
  31
  32        uint bustype;           /* SI_BUS, PCI_BUS */
  33        uint buscoretype;       /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
  34        uint buscorerev;        /* buscore rev */
  35        uint buscoreidx;        /* buscore index */
  36        int ccrev;              /* chip common core rev */
  37        u32 cccaps;             /* chip common capabilities */
  38        u32 cccaps_ext; /* chip common capabilities extension */
  39        int pmurev;             /* pmu core rev */
  40        u32 pmucaps;            /* pmu capabilities */
  41        uint boardtype;         /* board type */
  42        uint boardvendor;       /* board vendor */
  43        uint boardflags;        /* board flags */
  44        uint boardflags2;       /* board flags2 */
  45        uint chip;              /* chip number */
  46        uint chiprev;           /* chip revision */
  47        uint chippkg;           /* chip package option */
  48        u32 chipst;             /* chip status */
  49        bool issim;             /* chip is in simulation or emulation */
  50        uint socirev;           /* SOC interconnect rev */
  51        bool pci_pr32414;
  52
  53#if !defined(WLC_LOW)
  54        rpc_info_t *rpc;
  55#endif
  56};
  57
  58/* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver
  59 * for monolithic driver, it is readonly to prevent accident change
  60 */
  61#if !defined(WLC_LOW)
  62typedef struct si_pub si_t;
  63#else
  64typedef const struct si_pub si_t;
  65#endif
  66
  67/*
  68 * Many of the routines below take an 'sih' handle as their first arg.
  69 * Allocate this by calling si_attach().  Free it by calling si_detach().
  70 * At any one time, the sih is logically focused on one particular si core
  71 * (the "current core").
  72 * Use si_setcore() or si_setcoreidx() to change the association to another core.
  73 */
  74
  75#define BADIDX          (SI_MAXCORES + 1)
  76
  77/* clkctl xtal what flags */
  78#define XTAL                    0x1     /* primary crystal oscillator (2050) */
  79#define PLL                     0x2     /* main chip pll */
  80
  81/* clkctl clk mode */
  82#define CLK_FAST                0       /* force fast (pll) clock */
  83#define CLK_DYNAMIC             2       /* enable dynamic clock control */
  84
  85/* GPIO usage priorities */
  86#define GPIO_DRV_PRIORITY       0       /* Driver */
  87#define GPIO_APP_PRIORITY       1       /* Application */
  88#define GPIO_HI_PRIORITY        2       /* Highest priority. Ignore GPIO reservation */
  89
  90/* GPIO pull up/down */
  91#define GPIO_PULLUP             0
  92#define GPIO_PULLDN             1
  93
  94/* GPIO event regtype */
  95#define GPIO_REGEVT             0       /* GPIO register event */
  96#define GPIO_REGEVT_INTMSK      1       /* GPIO register event int mask */
  97#define GPIO_REGEVT_INTPOL      2       /* GPIO register event int polarity */
  98
  99/* device path */
 100#define SI_DEVPATH_BUFSZ        16      /* min buffer size in bytes */
 101
 102/* SI routine enumeration: to be used by update function with multiple hooks */
 103#define SI_DOATTACH     1
 104#define SI_PCIDOWN      2
 105#define SI_PCIUP        3
 106
 107#define ISSIM_ENAB(sih) 0
 108
 109/* PMU clock/power control */
 110#if defined(BCMPMUCTL)
 111#define PMUCTL_ENAB(sih)        (BCMPMUCTL)
 112#else
 113#define PMUCTL_ENAB(sih)        ((sih)->cccaps & CC_CAP_PMU)
 114#endif
 115
 116/* chipcommon clock/power control (exclusive with PMU's) */
 117#if defined(BCMPMUCTL) && BCMPMUCTL
 118#define CCCTL_ENAB(sih)         (0)
 119#define CCPLL_ENAB(sih)         (0)
 120#else
 121#define CCCTL_ENAB(sih)         ((sih)->cccaps & CC_CAP_PWR_CTL)
 122#define CCPLL_ENAB(sih)         ((sih)->cccaps & CC_CAP_PLL_MASK)
 123#endif
 124
 125typedef void (*gpio_handler_t) (u32 stat, void *arg);
 126
 127/* External PA enable mask */
 128#define GPIO_CTRL_EPA_EN_MASK 0x40
 129
 130/* === exported functions === */
 131extern si_t *si_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
 132                       void *sdh, char **vars, uint *varsz);
 133
 134extern void si_detach(si_t *sih);
 135extern bool si_pci_war16165(si_t *sih);
 136
 137extern uint si_coreid(si_t *sih);
 138extern uint si_flag(si_t *sih);
 139extern uint si_coreidx(si_t *sih);
 140extern uint si_corerev(si_t *sih);
 141extern void *si_osh(si_t *sih);
 142extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
 143                uint val);
 144extern void si_write_wrapperreg(si_t *sih, u32 offset, u32 val);
 145extern u32 si_core_cflags(si_t *sih, u32 mask, u32 val);
 146extern u32 si_core_sflags(si_t *sih, u32 mask, u32 val);
 147extern bool si_iscoreup(si_t *sih);
 148extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
 149#ifndef BCMSDIO
 150extern void *si_setcoreidx(si_t *sih, uint coreidx);
 151#endif
 152extern void *si_setcore(si_t *sih, uint coreid, uint coreunit);
 153extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx,
 154                            uint *intr_val);
 155extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
 156extern void si_core_reset(si_t *sih, u32 bits, u32 resetbits);
 157extern void si_core_disable(si_t *sih, u32 bits);
 158extern u32 si_alp_clock(si_t *sih);
 159extern u32 si_ilp_clock(si_t *sih);
 160extern void si_pci_setup(si_t *sih, uint coremask);
 161extern void si_setint(si_t *sih, int siflag);
 162extern bool si_backplane64(si_t *sih);
 163extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn,
 164                                      void *intrsrestore_fn,
 165                                      void *intrsenabled_fn, void *intr_arg);
 166extern void si_deregister_intr_callback(si_t *sih);
 167extern void si_clkctl_init(si_t *sih);
 168extern u16 si_clkctl_fast_pwrup_delay(si_t *sih);
 169extern bool si_clkctl_cc(si_t *sih, uint mode);
 170extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
 171extern bool si_deviceremoved(si_t *sih);
 172extern u32 si_socram_size(si_t *sih);
 173
 174extern void si_watchdog(si_t *sih, uint ticks);
 175extern u32 si_gpiocontrol(si_t *sih, u32 mask, u32 val,
 176                             u8 priority);
 177
 178#ifdef BCMSDIO
 179extern void si_sdio_init(si_t *sih);
 180#endif
 181
 182#define si_eci(sih) 0
 183#define si_eci_init(sih) (0)
 184#define si_eci_notify_bt(sih, type, val)  (0)
 185#define si_seci(sih) 0
 186static inline void *si_seci_init(si_t *sih, u8 use_seci)
 187{
 188        return NULL;
 189}
 190
 191/* OTP status */
 192extern bool si_is_otp_disabled(si_t *sih);
 193extern bool si_is_otp_powered(si_t *sih);
 194extern void si_otp_power(si_t *sih, bool on);
 195
 196/* SPROM availability */
 197extern bool si_is_sprom_available(si_t *sih);
 198#ifdef SI_SPROM_PROBE
 199extern void si_sprom_init(si_t *sih);
 200#endif                          /* SI_SPROM_PROBE */
 201
 202#define SI_ERROR(args)
 203
 204#ifdef BCMDBG
 205#define SI_MSG(args)    printf args
 206#else
 207#define SI_MSG(args)
 208#endif                          /* BCMDBG */
 209
 210/* Define SI_VMSG to printf for verbose debugging, but don't check it in */
 211#define SI_VMSG(args)
 212
 213#define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
 214
 215typedef u32(*si_intrsoff_t) (void *intr_arg);
 216typedef void (*si_intrsrestore_t) (void *intr_arg, u32 arg);
 217typedef bool(*si_intrsenabled_t) (void *intr_arg);
 218
 219typedef struct gpioh_item {
 220        void *arg;
 221        bool level;
 222        gpio_handler_t handler;
 223        u32 event;
 224        struct gpioh_item *next;
 225} gpioh_item_t;
 226
 227/* misc si info needed by some of the routines */
 228typedef struct si_info {
 229        struct si_pub pub;      /* back plane public state (must be first field) */
 230        void *osh;              /* osl os handle */
 231        void *sdh;              /* bcmsdh handle */
 232        uint dev_coreid;        /* the core provides driver functions */
 233        void *intr_arg;         /* interrupt callback function arg */
 234        si_intrsoff_t intrsoff_fn;      /* turns chip interrupts off */
 235        si_intrsrestore_t intrsrestore_fn;      /* restore chip interrupts */
 236        si_intrsenabled_t intrsenabled_fn;      /* check if interrupts are enabled */
 237
 238        void *pch;              /* PCI/E core handle */
 239
 240        gpioh_item_t *gpioh_head;       /* GPIO event handlers list */
 241
 242        bool memseg;            /* flag to toggle MEM_SEG register */
 243
 244        char *vars;
 245        uint varsz;
 246
 247        void *curmap;           /* current regs va */
 248        void *regs[SI_MAXCORES];        /* other regs va */
 249
 250        uint curidx;            /* current core index */
 251        uint numcores;          /* # discovered cores */
 252        uint coreid[SI_MAXCORES];       /* id of each core */
 253        u32 coresba[SI_MAXCORES];       /* backplane address of each core */
 254        void *regs2[SI_MAXCORES];       /* va of each core second register set (usbh20) */
 255        u32 coresba2[SI_MAXCORES];      /* address of each core second register set (usbh20) */
 256        u32 coresba_size[SI_MAXCORES];  /* backplane address space size */
 257        u32 coresba2_size[SI_MAXCORES]; /* second address space size */
 258
 259        void *curwrap;          /* current wrapper va */
 260        void *wrappers[SI_MAXCORES];    /* other cores wrapper va */
 261        u32 wrapba[SI_MAXCORES];        /* address of controlling wrapper */
 262
 263        u32 cia[SI_MAXCORES];   /* erom cia entry for each core */
 264        u32 cib[SI_MAXCORES];   /* erom cia entry for each core */
 265        u32 oob_router; /* oob router registers for axi */
 266} si_info_t;
 267
 268#define SI_INFO(sih)    (si_info_t *)sih
 269
 270#define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
 271                IS_ALIGNED((x), SI_CORE_SIZE))
 272#define GOODREGS(regs)  ((regs) != NULL && IS_ALIGNED((unsigned long)(regs), SI_CORE_SIZE))
 273#define BADCOREADDR     0
 274#define GOODIDX(idx)    (((uint)idx) < SI_MAXCORES)
 275#define NOREV           -1      /* Invalid rev */
 276
 277/* Newer chips can access PCI/PCIE and CC core without requiring to change
 278 * PCI BAR0 WIN
 279 */
 280#define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \
 281                     (((si)->pub.buscoretype == PCI_CORE_ID) && (si)->pub.buscorerev >= 13))
 282
 283#define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
 284#define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
 285
 286/*
 287 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts
 288 * before after core switching to avoid invalid register accesss inside ISR.
 289 */
 290#define INTR_OFF(si, intr_val) \
 291        if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) {      \
 292                intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
 293#define INTR_RESTORE(si, intr_val) \
 294        if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) {  \
 295                (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
 296
 297/* dynamic clock control defines */
 298#define LPOMINFREQ              25000   /* low power oscillator min */
 299#define LPOMAXFREQ              43000   /* low power oscillator max */
 300#define XTALMINFREQ             19800000        /* 20 MHz - 1% */
 301#define XTALMAXFREQ             20200000        /* 20 MHz + 1% */
 302#define PCIMINFREQ              25000000        /* 25 MHz */
 303#define PCIMAXFREQ              34000000        /* 33 MHz + fudge */
 304
 305#define ILP_DIV_5MHZ            0       /* ILP = 5 MHz */
 306#define ILP_DIV_1MHZ            4       /* ILP = 1 MHz */
 307
 308#define PCI(si)         ((BUSTYPE((si)->pub.bustype) == PCI_BUS) &&     \
 309                         ((si)->pub.buscoretype == PCI_CORE_ID))
 310#define PCIE(si)        ((BUSTYPE((si)->pub.bustype) == PCI_BUS) &&     \
 311                         ((si)->pub.buscoretype == PCIE_CORE_ID))
 312#define PCI_FORCEHT(si) \
 313        (PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID))
 314
 315/* GPIO Based LED powersave defines */
 316#define DEFAULT_GPIO_ONTIME     10      /* Default: 10% on */
 317#define DEFAULT_GPIO_OFFTIME    90      /* Default: 10% on */
 318
 319#ifndef DEFAULT_GPIOTIMERVAL
 320#define DEFAULT_GPIOTIMERVAL  ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
 321#endif
 322
 323/*
 324 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
 325 * The returned path is NULL terminated and has trailing '/'.
 326 * Return 0 on success, nonzero otherwise.
 327 */
 328extern int si_devpath(si_t *sih, char *path, int size);
 329/* Read variable with prepending the devpath to the name */
 330extern char *si_getdevpathvar(si_t *sih, const char *name);
 331extern int si_getdevpathintvar(si_t *sih, const char *name);
 332
 333extern void si_war42780_clkreq(si_t *sih, bool clkreq);
 334extern void si_pci_sleep(si_t *sih);
 335extern void si_pci_down(si_t *sih);
 336extern void si_pci_up(si_t *sih);
 337extern void si_pcie_extendL1timer(si_t *sih, bool extend);
 338extern int si_pci_fixcfg(si_t *sih);
 339
 340extern void si_chipcontrl_epa4331(si_t *sih, bool on);
 341/* Enable Ex-PA for 4313 */
 342extern void si_epa_4313war(si_t *sih);
 343
 344char *si_getnvramflvar(si_t *sih, const char *name);
 345
 346/* AMBA Interconnect exported externs */
 347extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
 348                       void *sdh, char **vars, uint *varsz);
 349extern si_t *ai_kattach(osl_t *osh);
 350extern void ai_scan(si_t *sih, void *regs, uint devid);
 351
 352extern uint ai_flag(si_t *sih);
 353extern void ai_setint(si_t *sih, int siflag);
 354extern uint ai_coreidx(si_t *sih);
 355extern uint ai_corevendor(si_t *sih);
 356extern uint ai_corerev(si_t *sih);
 357extern bool ai_iscoreup(si_t *sih);
 358extern void *ai_setcoreidx(si_t *sih, uint coreidx);
 359extern u32 ai_core_cflags(si_t *sih, u32 mask, u32 val);
 360extern void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val);
 361extern u32 ai_core_sflags(si_t *sih, u32 mask, u32 val);
 362extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
 363                       uint val);
 364extern void ai_core_reset(si_t *sih, u32 bits, u32 resetbits);
 365extern void ai_core_disable(si_t *sih, u32 bits);
 366extern int ai_numaddrspaces(si_t *sih);
 367extern u32 ai_addrspace(si_t *sih, uint asidx);
 368extern u32 ai_addrspacesize(si_t *sih, uint asidx);
 369extern void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val);
 370
 371#ifdef BCMSDIO
 372#define si_setcoreidx(sih, idx) sb_setcoreidx(sih, idx)
 373#define si_coreid(sih) sb_coreid(sih)
 374#define si_corerev(sih) sb_corerev(sih)
 375#endif
 376
 377#endif                          /* _siutils_h_ */
 378