1#ifndef _CAN_PLATFORM_SJA1000_H_ 2#define _CAN_PLATFORM_SJA1000_H_ 3 4/* clock divider register */ 5#define CDR_CLKOUT_MASK 0x07 6#define CDR_CLK_OFF 0x08 /* Clock off (CLKOUT pin) */ 7#define CDR_RXINPEN 0x20 /* TX1 output is RX irq output */ 8#define CDR_CBP 0x40 /* CAN input comparator bypass */ 9#define CDR_PELICAN 0x80 /* PeliCAN mode */ 10 11/* output control register */ 12#define OCR_MODE_BIPHASE 0x00 13#define OCR_MODE_TEST 0x01 14#define OCR_MODE_NORMAL 0x02 15#define OCR_MODE_CLOCK 0x03 16#define OCR_MODE_MASK 0x07 17#define OCR_TX0_INVERT 0x04 18#define OCR_TX0_PULLDOWN 0x08 19#define OCR_TX0_PULLUP 0x10 20#define OCR_TX0_PUSHPULL 0x18 21#define OCR_TX1_INVERT 0x20 22#define OCR_TX1_PULLDOWN 0x40 23#define OCR_TX1_PULLUP 0x80 24#define OCR_TX1_PUSHPULL 0xc0 25#define OCR_TX_MASK 0xfc 26#define OCR_TX_SHIFT 2 27 28struct sja1000_platform_data { 29 u32 osc_freq; /* CAN bus oscillator frequency in Hz */ 30 31 u8 ocr; /* output control register */ 32 u8 cdr; /* clock divider register */ 33}; 34 35#endif /* !_CAN_PLATFORM_SJA1000_H_ */ 36