1menu "Memory management options" 2 3config QUICKLIST 4 def_bool y 5 6config MMU 7 bool "Support for memory management hardware" 8 depends on !CPU_SH2 9 default y 10 help 11 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to 12 boot on these systems, this option must not be set. 13 14 On other systems (such as the SH-3 and 4) where an MMU exists, 15 turning this off will boot the kernel on these machines with the 16 MMU implicitly switched off. 17 18config PAGE_OFFSET 19 hex 20 default "0x80000000" if MMU && SUPERH32 21 default "0x20000000" if MMU && SUPERH64 22 default "0x00000000" 23 24config FORCE_MAX_ZONEORDER 25 int "Maximum zone order" 26 range 9 64 if PAGE_SIZE_16KB 27 default "9" if PAGE_SIZE_16KB 28 range 7 64 if PAGE_SIZE_64KB 29 default "7" if PAGE_SIZE_64KB 30 range 11 64 31 default "14" if !MMU 32 default "11" 33 help 34 The kernel memory allocator divides physically contiguous memory 35 blocks into "zones", where each zone is a power of two number of 36 pages. This option selects the largest power of two that the kernel 37 keeps in the memory allocator. If you need to allocate very large 38 blocks of physically contiguous memory, then you may need to 39 increase this value. 40 41 This config option is actually maximum order plus one. For example, 42 a value of 11 means that the largest free memory block is 2^10 pages. 43 44 The page size is not necessarily 4KB. Keep this in mind when 45 choosing a value for this option. 46 47config MEMORY_START 48 hex "Physical memory start address" 49 default "0x08000000" 50 ---help--- 51 Computers built with Hitachi SuperH processors always 52 map the ROM starting at address zero. But the processor 53 does not specify the range that RAM takes. 54 55 The physical memory (RAM) start address will be automatically 56 set to 08000000. Other platforms, such as the Solution Engine 57 boards typically map RAM at 0C000000. 58 59 Tweak this only when porting to a new machine which does not 60 already have a defconfig. Changing it from the known correct 61 value on any of the known systems will only lead to disaster. 62 63config MEMORY_SIZE 64 hex "Physical memory size" 65 default "0x04000000" 66 help 67 This sets the default memory size assumed by your SH kernel. It can 68 be overridden as normal by the 'mem=' argument on the kernel command 69 line. If unsure, consult your board specifications or just leave it 70 as 0x04000000 which was the default value before this became 71 configurable. 72 73# Physical addressing modes 74 75config 29BIT 76 def_bool !32BIT 77 depends on SUPERH32 78 select UNCACHED_MAPPING 79 80config 32BIT 81 bool 82 default y if CPU_SH5 83 84config PMB 85 bool "Support 32-bit physical addressing through PMB" 86 depends on MMU && EXPERIMENTAL && CPU_SH4A && !CPU_SH4AL_DSP 87 select 32BIT 88 select UNCACHED_MAPPING 89 help 90 If you say Y here, physical addressing will be extended to 91 32-bits through the SH-4A PMB. If this is not set, legacy 92 29-bit physical addressing will be used. 93 94config X2TLB 95 def_bool y 96 depends on (CPU_SHX2 || CPU_SHX3) && MMU 97 98config VSYSCALL 99 bool "Support vsyscall page" 100 depends on MMU && (CPU_SH3 || CPU_SH4) 101 default y 102 help 103 This will enable support for the kernel mapping a vDSO page 104 in process space, and subsequently handing down the entry point 105 to the libc through the ELF auxiliary vector. 106 107 From the kernel side this is used for the signal trampoline. 108 For systems with an MMU that can afford to give up a page, 109 (the default value) say Y. 110 111config NUMA 112 bool "Non Uniform Memory Access (NUMA) Support" 113 depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL 114 default n 115 help 116 Some SH systems have many various memories scattered around 117 the address space, each with varying latencies. This enables 118 support for these blocks by binding them to nodes and allowing 119 memory policies to be used for prioritizing and controlling 120 allocation behaviour. 121 122config NODES_SHIFT 123 int 124 default "3" if CPU_SUBTYPE_SHX3 125 default "1" 126 depends on NEED_MULTIPLE_NODES 127 128config ARCH_FLATMEM_ENABLE 129 def_bool y 130 depends on !NUMA 131 132config ARCH_SPARSEMEM_ENABLE 133 def_bool y 134 select SPARSEMEM_STATIC 135 136config ARCH_SPARSEMEM_DEFAULT 137 def_bool y 138 139config MAX_ACTIVE_REGIONS 140 int 141 default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM) 142 default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \ 143 CPU_SUBTYPE_SH7785) 144 default "1" 145 146config ARCH_POPULATES_NODE_MAP 147 def_bool y 148 149config ARCH_SELECT_MEMORY_MODEL 150 def_bool y 151 152config ARCH_ENABLE_MEMORY_HOTPLUG 153 def_bool y 154 depends on SPARSEMEM && MMU 155 156config ARCH_ENABLE_MEMORY_HOTREMOVE 157 def_bool y 158 depends on SPARSEMEM && MMU 159 160config ARCH_MEMORY_PROBE 161 def_bool y 162 depends on MEMORY_HOTPLUG 163 164config IOREMAP_FIXED 165 def_bool y 166 depends on X2TLB || SUPERH64 167 168config UNCACHED_MAPPING 169 bool 170 171choice 172 prompt "Kernel page size" 173 default PAGE_SIZE_4KB 174 175config PAGE_SIZE_4KB 176 bool "4kB" 177 help 178 This is the default page size used by all SuperH CPUs. 179 180config PAGE_SIZE_8KB 181 bool "8kB" 182 depends on !MMU || X2TLB 183 help 184 This enables 8kB pages as supported by SH-X2 and later MMUs. 185 186config PAGE_SIZE_16KB 187 bool "16kB" 188 depends on !MMU 189 help 190 This enables 16kB pages on MMU-less SH systems. 191 192config PAGE_SIZE_64KB 193 bool "64kB" 194 depends on !MMU || CPU_SH4 || CPU_SH5 195 help 196 This enables support for 64kB pages, possible on all SH-4 197 CPUs and later. 198 199endchoice 200 201choice 202 prompt "HugeTLB page size" 203 depends on HUGETLB_PAGE 204 default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB 205 default HUGETLB_PAGE_SIZE_64K 206 207config HUGETLB_PAGE_SIZE_64K 208 bool "64kB" 209 depends on !PAGE_SIZE_64KB 210 211config HUGETLB_PAGE_SIZE_256K 212 bool "256kB" 213 depends on X2TLB 214 215config HUGETLB_PAGE_SIZE_1MB 216 bool "1MB" 217 218config HUGETLB_PAGE_SIZE_4MB 219 bool "4MB" 220 depends on X2TLB 221 222config HUGETLB_PAGE_SIZE_64MB 223 bool "64MB" 224 depends on X2TLB 225 226config HUGETLB_PAGE_SIZE_512MB 227 bool "512MB" 228 depends on CPU_SH5 229 230endchoice 231 232source "mm/Kconfig" 233 234config SCHED_MC 235 bool "Multi-core scheduler support" 236 depends on SMP 237 default y 238 help 239 Multi-core scheduler support improves the CPU scheduler's decision 240 making when dealing with multi-core CPU chips at a cost of slightly 241 increased overhead in some places. If unsure say N here. 242 243endmenu 244 245menu "Cache configuration" 246 247config SH7705_CACHE_32KB 248 bool "Enable 32KB cache size for SH7705" 249 depends on CPU_SUBTYPE_SH7705 250 default y 251 252choice 253 prompt "Cache mode" 254 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5 255 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A) 256 257config CACHE_WRITEBACK 258 bool "Write-back" 259 260config CACHE_WRITETHROUGH 261 bool "Write-through" 262 help 263 Selecting this option will configure the caches in write-through 264 mode, as opposed to the default write-back configuration. 265 266 Since there's sill some aliasing issues on SH-4, this option will 267 unfortunately still require the majority of flushing functions to 268 be implemented to deal with aliasing. 269 270 If unsure, say N. 271 272config CACHE_OFF 273 bool "Off" 274 275endchoice 276 277endmenu 278