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45#include <linux/version.h>
46#include <linux/kernel.h>
47#include <linux/module.h>
48#include <linux/errno.h>
49#include <linux/init.h>
50#include <linux/slab.h>
51#include <linux/types.h>
52#include <linux/pci.h>
53#include <linux/kdev_t.h>
54#include <linux/blkdev.h>
55#include <linux/delay.h>
56#include <linux/interrupt.h>
57#include <linux/dma-mapping.h>
58#include <linux/sort.h>
59#include <linux/io.h>
60#include <linux/time.h>
61#include <linux/aer.h>
62
63#include "mpt2sas_base.h"
64
65static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
66
67#define FAULT_POLLING_INTERVAL 1000
68#define MPT2SAS_MAX_REQUEST_QUEUE 600
69
70static int max_queue_depth = -1;
71module_param(max_queue_depth, int, 0);
72MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
73
74static int max_sgl_entries = -1;
75module_param(max_sgl_entries, int, 0);
76MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
77
78static int msix_disable = -1;
79module_param(msix_disable, int, 0);
80MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
81
82
83
84
85
86
87
88
89static int diag_buffer_enable;
90module_param(diag_buffer_enable, int, 0);
91MODULE_PARM_DESC(diag_buffer_enable, " post diag buffers "
92 "(TRACE=1/SNAPSHOT=2/EXTENDED=4/default=0)");
93
94int mpt2sas_fwfault_debug;
95MODULE_PARM_DESC(mpt2sas_fwfault_debug, " enable detection of firmware fault "
96 "and halt firmware - (default=0)");
97
98
99
100
101
102static int
103_scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
104{
105 int ret = param_set_int(val, kp);
106 struct MPT2SAS_ADAPTER *ioc;
107
108 if (ret)
109 return ret;
110
111 printk(KERN_INFO "setting fwfault_debug(%d)\n", mpt2sas_fwfault_debug);
112 list_for_each_entry(ioc, &mpt2sas_ioc_list, list)
113 ioc->fwfault_debug = mpt2sas_fwfault_debug;
114 return 0;
115}
116module_param_call(mpt2sas_fwfault_debug, _scsih_set_fwfault_debug,
117 param_get_int, &mpt2sas_fwfault_debug, 0644);
118
119
120
121
122
123
124
125
126static void
127_base_fault_reset_work(struct work_struct *work)
128{
129 struct MPT2SAS_ADAPTER *ioc =
130 container_of(work, struct MPT2SAS_ADAPTER, fault_reset_work.work);
131 unsigned long flags;
132 u32 doorbell;
133 int rc;
134
135 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
136 if (ioc->shost_recovery)
137 goto rearm_timer;
138 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
139
140 doorbell = mpt2sas_base_get_iocstate(ioc, 0);
141 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
142 rc = mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
143 FORCE_BIG_HAMMER);
144 printk(MPT2SAS_WARN_FMT "%s: hard reset: %s\n", ioc->name,
145 __func__, (rc == 0) ? "success" : "failed");
146 doorbell = mpt2sas_base_get_iocstate(ioc, 0);
147 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
148 mpt2sas_base_fault_info(ioc, doorbell &
149 MPI2_DOORBELL_DATA_MASK);
150 }
151
152 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
153 rearm_timer:
154 if (ioc->fault_reset_work_q)
155 queue_delayed_work(ioc->fault_reset_work_q,
156 &ioc->fault_reset_work,
157 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
158 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
159}
160
161
162
163
164
165
166
167
168void
169mpt2sas_base_start_watchdog(struct MPT2SAS_ADAPTER *ioc)
170{
171 unsigned long flags;
172
173 if (ioc->fault_reset_work_q)
174 return;
175
176
177 INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
178 snprintf(ioc->fault_reset_work_q_name,
179 sizeof(ioc->fault_reset_work_q_name), "poll_%d_status", ioc->id);
180 ioc->fault_reset_work_q =
181 create_singlethread_workqueue(ioc->fault_reset_work_q_name);
182 if (!ioc->fault_reset_work_q) {
183 printk(MPT2SAS_ERR_FMT "%s: failed (line=%d)\n",
184 ioc->name, __func__, __LINE__);
185 return;
186 }
187 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
188 if (ioc->fault_reset_work_q)
189 queue_delayed_work(ioc->fault_reset_work_q,
190 &ioc->fault_reset_work,
191 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
192 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
193}
194
195
196
197
198
199
200
201
202void
203mpt2sas_base_stop_watchdog(struct MPT2SAS_ADAPTER *ioc)
204{
205 unsigned long flags;
206 struct workqueue_struct *wq;
207
208 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
209 wq = ioc->fault_reset_work_q;
210 ioc->fault_reset_work_q = NULL;
211 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
212 if (wq) {
213 if (!cancel_delayed_work(&ioc->fault_reset_work))
214 flush_workqueue(wq);
215 destroy_workqueue(wq);
216 }
217}
218
219
220
221
222
223
224
225
226void
227mpt2sas_base_fault_info(struct MPT2SAS_ADAPTER *ioc , u16 fault_code)
228{
229 printk(MPT2SAS_ERR_FMT "fault_state(0x%04x)!\n",
230 ioc->name, fault_code);
231}
232
233
234
235
236
237
238
239
240
241
242void
243mpt2sas_halt_firmware(struct MPT2SAS_ADAPTER *ioc)
244{
245 u32 doorbell;
246
247 if (!ioc->fwfault_debug)
248 return;
249
250 dump_stack();
251
252 doorbell = readl(&ioc->chip->Doorbell);
253 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
254 mpt2sas_base_fault_info(ioc , doorbell);
255 else {
256 writel(0xC0FFEE00, &ioc->chip->Doorbell);
257 printk(MPT2SAS_ERR_FMT "Firmware is halted due to command "
258 "timeout\n", ioc->name);
259 }
260
261 panic("panic in %s\n", __func__);
262}
263
264#ifdef CONFIG_SCSI_MPT2SAS_LOGGING
265
266
267
268
269
270
271
272
273static void
274_base_sas_ioc_info(struct MPT2SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
275 MPI2RequestHeader_t *request_hdr)
276{
277 u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
278 MPI2_IOCSTATUS_MASK;
279 char *desc = NULL;
280 u16 frame_sz;
281 char *func_str = NULL;
282
283
284 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
285 request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
286 request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
287 return;
288
289 if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
290 return;
291
292 switch (ioc_status) {
293
294
295
296
297
298 case MPI2_IOCSTATUS_INVALID_FUNCTION:
299 desc = "invalid function";
300 break;
301 case MPI2_IOCSTATUS_BUSY:
302 desc = "busy";
303 break;
304 case MPI2_IOCSTATUS_INVALID_SGL:
305 desc = "invalid sgl";
306 break;
307 case MPI2_IOCSTATUS_INTERNAL_ERROR:
308 desc = "internal error";
309 break;
310 case MPI2_IOCSTATUS_INVALID_VPID:
311 desc = "invalid vpid";
312 break;
313 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
314 desc = "insufficient resources";
315 break;
316 case MPI2_IOCSTATUS_INVALID_FIELD:
317 desc = "invalid field";
318 break;
319 case MPI2_IOCSTATUS_INVALID_STATE:
320 desc = "invalid state";
321 break;
322 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
323 desc = "op state not supported";
324 break;
325
326
327
328
329
330 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
331 desc = "config invalid action";
332 break;
333 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
334 desc = "config invalid type";
335 break;
336 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
337 desc = "config invalid page";
338 break;
339 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
340 desc = "config invalid data";
341 break;
342 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
343 desc = "config no defaults";
344 break;
345 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
346 desc = "config cant commit";
347 break;
348
349
350
351
352
353 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
354 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
355 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
356 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
357 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
358 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
359 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
360 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
361 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
362 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
363 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
364 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
365 break;
366
367
368
369
370
371 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
372 desc = "eedp guard error";
373 break;
374 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
375 desc = "eedp ref tag error";
376 break;
377 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
378 desc = "eedp app tag error";
379 break;
380
381
382
383
384
385 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
386 desc = "target invalid io index";
387 break;
388 case MPI2_IOCSTATUS_TARGET_ABORTED:
389 desc = "target aborted";
390 break;
391 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
392 desc = "target no conn retryable";
393 break;
394 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
395 desc = "target no connection";
396 break;
397 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
398 desc = "target xfer count mismatch";
399 break;
400 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
401 desc = "target data offset error";
402 break;
403 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
404 desc = "target too much write data";
405 break;
406 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
407 desc = "target iu too short";
408 break;
409 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
410 desc = "target ack nak timeout";
411 break;
412 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
413 desc = "target nak received";
414 break;
415
416
417
418
419
420 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
421 desc = "smp request failed";
422 break;
423 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
424 desc = "smp data overrun";
425 break;
426
427
428
429
430
431 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
432 desc = "diagnostic released";
433 break;
434 default:
435 break;
436 }
437
438 if (!desc)
439 return;
440
441 switch (request_hdr->Function) {
442 case MPI2_FUNCTION_CONFIG:
443 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
444 func_str = "config_page";
445 break;
446 case MPI2_FUNCTION_SCSI_TASK_MGMT:
447 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
448 func_str = "task_mgmt";
449 break;
450 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
451 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
452 func_str = "sas_iounit_ctl";
453 break;
454 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
455 frame_sz = sizeof(Mpi2SepRequest_t);
456 func_str = "enclosure";
457 break;
458 case MPI2_FUNCTION_IOC_INIT:
459 frame_sz = sizeof(Mpi2IOCInitRequest_t);
460 func_str = "ioc_init";
461 break;
462 case MPI2_FUNCTION_PORT_ENABLE:
463 frame_sz = sizeof(Mpi2PortEnableRequest_t);
464 func_str = "port_enable";
465 break;
466 case MPI2_FUNCTION_SMP_PASSTHROUGH:
467 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
468 func_str = "smp_passthru";
469 break;
470 default:
471 frame_sz = 32;
472 func_str = "unknown";
473 break;
474 }
475
476 printk(MPT2SAS_WARN_FMT "ioc_status: %s(0x%04x), request(0x%p),"
477 " (%s)\n", ioc->name, desc, ioc_status, request_hdr, func_str);
478
479 _debug_dump_mf(request_hdr, frame_sz/4);
480}
481
482
483
484
485
486
487
488
489static void
490_base_display_event_data(struct MPT2SAS_ADAPTER *ioc,
491 Mpi2EventNotificationReply_t *mpi_reply)
492{
493 char *desc = NULL;
494 u16 event;
495
496 if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
497 return;
498
499 event = le16_to_cpu(mpi_reply->Event);
500
501 switch (event) {
502 case MPI2_EVENT_LOG_DATA:
503 desc = "Log Data";
504 break;
505 case MPI2_EVENT_STATE_CHANGE:
506 desc = "Status Change";
507 break;
508 case MPI2_EVENT_HARD_RESET_RECEIVED:
509 desc = "Hard Reset Received";
510 break;
511 case MPI2_EVENT_EVENT_CHANGE:
512 desc = "Event Change";
513 break;
514 case MPI2_EVENT_TASK_SET_FULL:
515 desc = "Task Set Full";
516 break;
517 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
518 desc = "Device Status Change";
519 break;
520 case MPI2_EVENT_IR_OPERATION_STATUS:
521 desc = "IR Operation Status";
522 break;
523 case MPI2_EVENT_SAS_DISCOVERY:
524 {
525 Mpi2EventDataSasDiscovery_t *event_data =
526 (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
527 printk(MPT2SAS_INFO_FMT "Discovery: (%s)", ioc->name,
528 (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
529 "start" : "stop");
530 if (event_data->DiscoveryStatus)
531 printk("discovery_status(0x%08x)",
532 le32_to_cpu(event_data->DiscoveryStatus));
533 printk("\n");
534 return;
535 }
536 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
537 desc = "SAS Broadcast Primitive";
538 break;
539 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
540 desc = "SAS Init Device Status Change";
541 break;
542 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
543 desc = "SAS Init Table Overflow";
544 break;
545 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
546 desc = "SAS Topology Change List";
547 break;
548 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
549 desc = "SAS Enclosure Device Status Change";
550 break;
551 case MPI2_EVENT_IR_VOLUME:
552 desc = "IR Volume";
553 break;
554 case MPI2_EVENT_IR_PHYSICAL_DISK:
555 desc = "IR Physical Disk";
556 break;
557 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
558 desc = "IR Configuration Change List";
559 break;
560 case MPI2_EVENT_LOG_ENTRY_ADDED:
561 desc = "Log Entry Added";
562 break;
563 }
564
565 if (!desc)
566 return;
567
568 printk(MPT2SAS_INFO_FMT "%s\n", ioc->name, desc);
569}
570#endif
571
572
573
574
575
576
577
578
579static void
580_base_sas_log_info(struct MPT2SAS_ADAPTER *ioc , u32 log_info)
581{
582 union loginfo_type {
583 u32 loginfo;
584 struct {
585 u32 subcode:16;
586 u32 code:8;
587 u32 originator:4;
588 u32 bus_type:4;
589 } dw;
590 };
591 union loginfo_type sas_loginfo;
592 char *originator_str = NULL;
593
594 sas_loginfo.loginfo = log_info;
595 if (sas_loginfo.dw.bus_type != 3 )
596 return;
597
598
599 if (log_info == 0x31170000)
600 return;
601
602
603 if (ioc->ignore_loginfos && (log_info == 30050000 || log_info ==
604 0x31140000 || log_info == 0x31130000))
605 return;
606
607 switch (sas_loginfo.dw.originator) {
608 case 0:
609 originator_str = "IOP";
610 break;
611 case 1:
612 originator_str = "PL";
613 break;
614 case 2:
615 originator_str = "IR";
616 break;
617 }
618
619 printk(MPT2SAS_WARN_FMT "log_info(0x%08x): originator(%s), "
620 "code(0x%02x), sub_code(0x%04x)\n", ioc->name, log_info,
621 originator_str, sas_loginfo.dw.code,
622 sas_loginfo.dw.subcode);
623}
624
625
626
627
628
629
630
631
632
633
634static void
635_base_display_reply_info(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
636 u32 reply)
637{
638 MPI2DefaultReply_t *mpi_reply;
639 u16 ioc_status;
640
641 mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
642 ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
643#ifdef CONFIG_SCSI_MPT2SAS_LOGGING
644 if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
645 (ioc->logging_level & MPT_DEBUG_REPLY)) {
646 _base_sas_ioc_info(ioc , mpi_reply,
647 mpt2sas_base_get_msg_frame(ioc, smid));
648 }
649#endif
650 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE)
651 _base_sas_log_info(ioc, le32_to_cpu(mpi_reply->IOCLogInfo));
652}
653
654
655
656
657
658
659
660
661
662
663
664u8
665mpt2sas_base_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
666 u32 reply)
667{
668 MPI2DefaultReply_t *mpi_reply;
669
670 mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
671 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
672 return 1;
673
674 if (ioc->base_cmds.status == MPT2_CMD_NOT_USED)
675 return 1;
676
677 ioc->base_cmds.status |= MPT2_CMD_COMPLETE;
678 if (mpi_reply) {
679 ioc->base_cmds.status |= MPT2_CMD_REPLY_VALID;
680 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
681 }
682 ioc->base_cmds.status &= ~MPT2_CMD_PENDING;
683 complete(&ioc->base_cmds.done);
684 return 1;
685}
686
687
688
689
690
691
692
693
694
695
696static u8
697_base_async_event(struct MPT2SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
698{
699 Mpi2EventNotificationReply_t *mpi_reply;
700 Mpi2EventAckRequest_t *ack_request;
701 u16 smid;
702
703 mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
704 if (!mpi_reply)
705 return 1;
706 if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
707 return 1;
708#ifdef CONFIG_SCSI_MPT2SAS_LOGGING
709 _base_display_event_data(ioc, mpi_reply);
710#endif
711 if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
712 goto out;
713 smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
714 if (!smid) {
715 printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
716 ioc->name, __func__);
717 goto out;
718 }
719
720 ack_request = mpt2sas_base_get_msg_frame(ioc, smid);
721 memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
722 ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
723 ack_request->Event = mpi_reply->Event;
724 ack_request->EventContext = mpi_reply->EventContext;
725 ack_request->VF_ID = 0;
726 ack_request->VP_ID = 0;
727 mpt2sas_base_put_smid_default(ioc, smid);
728
729 out:
730
731
732 mpt2sas_scsih_event_callback(ioc, msix_index, reply);
733
734
735 mpt2sas_ctl_event_callback(ioc, msix_index, reply);
736
737 return 1;
738}
739
740
741
742
743
744
745
746
747static u8
748_base_get_cb_idx(struct MPT2SAS_ADAPTER *ioc, u16 smid)
749{
750 int i;
751 u8 cb_idx = 0xFF;
752
753 if (smid >= ioc->hi_priority_smid) {
754 if (smid < ioc->internal_smid) {
755 i = smid - ioc->hi_priority_smid;
756 cb_idx = ioc->hpr_lookup[i].cb_idx;
757 } else {
758 i = smid - ioc->internal_smid;
759 cb_idx = ioc->internal_lookup[i].cb_idx;
760 }
761 } else {
762 i = smid - 1;
763 cb_idx = ioc->scsi_lookup[i].cb_idx;
764 }
765 return cb_idx;
766}
767
768
769
770
771
772
773
774
775
776static void
777_base_mask_interrupts(struct MPT2SAS_ADAPTER *ioc)
778{
779 u32 him_register;
780
781 ioc->mask_interrupts = 1;
782 him_register = readl(&ioc->chip->HostInterruptMask);
783 him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
784 writel(him_register, &ioc->chip->HostInterruptMask);
785 readl(&ioc->chip->HostInterruptMask);
786}
787
788
789
790
791
792
793
794
795
796static void
797_base_unmask_interrupts(struct MPT2SAS_ADAPTER *ioc)
798{
799 u32 him_register;
800
801 him_register = readl(&ioc->chip->HostInterruptMask);
802 him_register &= ~MPI2_HIM_RIM;
803 writel(him_register, &ioc->chip->HostInterruptMask);
804 ioc->mask_interrupts = 0;
805}
806
807union reply_descriptor {
808 u64 word;
809 struct {
810 u32 low;
811 u32 high;
812 } u;
813};
814
815
816
817
818
819
820
821
822
823static irqreturn_t
824_base_interrupt(int irq, void *bus_id)
825{
826 union reply_descriptor rd;
827 u32 completed_cmds;
828 u8 request_desript_type;
829 u16 smid;
830 u8 cb_idx;
831 u32 reply;
832 u8 msix_index;
833 struct MPT2SAS_ADAPTER *ioc = bus_id;
834 Mpi2ReplyDescriptorsUnion_t *rpf;
835 u8 rc;
836
837 if (ioc->mask_interrupts)
838 return IRQ_NONE;
839
840 rpf = &ioc->reply_post_free[ioc->reply_post_host_index];
841 request_desript_type = rpf->Default.ReplyFlags
842 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
843 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
844 return IRQ_NONE;
845
846 completed_cmds = 0;
847 do {
848 rd.word = rpf->Words;
849 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
850 goto out;
851 reply = 0;
852 cb_idx = 0xFF;
853 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
854 msix_index = rpf->Default.MSIxIndex;
855 if (request_desript_type ==
856 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
857 reply = le32_to_cpu
858 (rpf->AddressReply.ReplyFrameAddress);
859 } else if (request_desript_type ==
860 MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER)
861 goto next;
862 else if (request_desript_type ==
863 MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS)
864 goto next;
865 if (smid)
866 cb_idx = _base_get_cb_idx(ioc, smid);
867 if (smid && cb_idx != 0xFF) {
868 rc = mpt_callbacks[cb_idx](ioc, smid, msix_index,
869 reply);
870 if (reply)
871 _base_display_reply_info(ioc, smid, msix_index,
872 reply);
873 if (rc)
874 mpt2sas_base_free_smid(ioc, smid);
875 }
876 if (!smid)
877 _base_async_event(ioc, msix_index, reply);
878
879
880 if (reply) {
881 ioc->reply_free_host_index =
882 (ioc->reply_free_host_index ==
883 (ioc->reply_free_queue_depth - 1)) ?
884 0 : ioc->reply_free_host_index + 1;
885 ioc->reply_free[ioc->reply_free_host_index] =
886 cpu_to_le32(reply);
887 wmb();
888 writel(ioc->reply_free_host_index,
889 &ioc->chip->ReplyFreeHostIndex);
890 }
891
892 next:
893
894 rpf->Words = ULLONG_MAX;
895 ioc->reply_post_host_index = (ioc->reply_post_host_index ==
896 (ioc->reply_post_queue_depth - 1)) ? 0 :
897 ioc->reply_post_host_index + 1;
898 request_desript_type =
899 ioc->reply_post_free[ioc->reply_post_host_index].Default.
900 ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
901 completed_cmds++;
902 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
903 goto out;
904 if (!ioc->reply_post_host_index)
905 rpf = ioc->reply_post_free;
906 else
907 rpf++;
908 } while (1);
909
910 out:
911
912 if (!completed_cmds)
913 return IRQ_NONE;
914
915 wmb();
916 writel(ioc->reply_post_host_index, &ioc->chip->ReplyPostHostIndex);
917 return IRQ_HANDLED;
918}
919
920
921
922
923
924
925
926void
927mpt2sas_base_release_callback_handler(u8 cb_idx)
928{
929 mpt_callbacks[cb_idx] = NULL;
930}
931
932
933
934
935
936
937
938u8
939mpt2sas_base_register_callback_handler(MPT_CALLBACK cb_func)
940{
941 u8 cb_idx;
942
943 for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
944 if (mpt_callbacks[cb_idx] == NULL)
945 break;
946
947 mpt_callbacks[cb_idx] = cb_func;
948 return cb_idx;
949}
950
951
952
953
954
955
956void
957mpt2sas_base_initialize_callback_handler(void)
958{
959 u8 cb_idx;
960
961 for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
962 mpt2sas_base_release_callback_handler(cb_idx);
963}
964
965
966
967
968
969
970
971
972
973
974
975
976void
977mpt2sas_base_build_zero_len_sge(struct MPT2SAS_ADAPTER *ioc, void *paddr)
978{
979 u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
980 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
981 MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
982 MPI2_SGE_FLAGS_SHIFT);
983 ioc->base_add_sg_single(paddr, flags_length, -1);
984}
985
986
987
988
989
990
991
992
993
994static void
995_base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
996{
997 Mpi2SGESimple32_t *sgel = paddr;
998
999 flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
1000 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1001 sgel->FlagsLength = cpu_to_le32(flags_length);
1002 sgel->Address = cpu_to_le32(dma_addr);
1003}
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014static void
1015_base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1016{
1017 Mpi2SGESimple64_t *sgel = paddr;
1018
1019 flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
1020 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1021 sgel->FlagsLength = cpu_to_le32(flags_length);
1022 sgel->Address = cpu_to_le64(dma_addr);
1023}
1024
1025#define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
1026
1027
1028
1029
1030
1031
1032
1033
1034static int
1035_base_config_dma_addressing(struct MPT2SAS_ADAPTER *ioc, struct pci_dev *pdev)
1036{
1037 struct sysinfo s;
1038 char *desc = NULL;
1039
1040 if (sizeof(dma_addr_t) > 4) {
1041 const uint64_t required_mask =
1042 dma_get_required_mask(&pdev->dev);
1043 if ((required_mask > DMA_BIT_MASK(32)) && !pci_set_dma_mask(pdev,
1044 DMA_BIT_MASK(64)) && !pci_set_consistent_dma_mask(pdev,
1045 DMA_BIT_MASK(64))) {
1046 ioc->base_add_sg_single = &_base_add_sg_single_64;
1047 ioc->sge_size = sizeof(Mpi2SGESimple64_t);
1048 desc = "64";
1049 goto out;
1050 }
1051 }
1052
1053 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1054 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1055 ioc->base_add_sg_single = &_base_add_sg_single_32;
1056 ioc->sge_size = sizeof(Mpi2SGESimple32_t);
1057 desc = "32";
1058 } else
1059 return -ENODEV;
1060
1061 out:
1062 si_meminfo(&s);
1063 printk(MPT2SAS_INFO_FMT "%s BIT PCI BUS DMA ADDRESSING SUPPORTED, "
1064 "total mem (%ld kB)\n", ioc->name, desc, convert_to_kb(s.totalram));
1065
1066 return 0;
1067}
1068
1069
1070
1071
1072
1073
1074
1075static void
1076_base_save_msix_table(struct MPT2SAS_ADAPTER *ioc)
1077{
1078 int i;
1079
1080 if (!ioc->msix_enable || ioc->msix_table_backup == NULL)
1081 return;
1082
1083 for (i = 0; i < ioc->msix_vector_count; i++)
1084 ioc->msix_table_backup[i] = ioc->msix_table[i];
1085}
1086
1087
1088
1089
1090
1091
1092static void
1093_base_restore_msix_table(struct MPT2SAS_ADAPTER *ioc)
1094{
1095 int i;
1096
1097 if (!ioc->msix_enable || ioc->msix_table_backup == NULL)
1098 return;
1099
1100 for (i = 0; i < ioc->msix_vector_count; i++)
1101 ioc->msix_table[i] = ioc->msix_table_backup[i];
1102}
1103
1104
1105
1106
1107
1108
1109
1110
1111static int
1112_base_check_enable_msix(struct MPT2SAS_ADAPTER *ioc)
1113{
1114 int base;
1115 u16 message_control;
1116 u32 msix_table_offset;
1117
1118 base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
1119 if (!base) {
1120 dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "msix not "
1121 "supported\n", ioc->name));
1122 return -EINVAL;
1123 }
1124
1125
1126 pci_read_config_word(ioc->pdev, base + 2, &message_control);
1127 ioc->msix_vector_count = (message_control & 0x3FF) + 1;
1128
1129
1130 pci_read_config_dword(ioc->pdev, base + 4, &msix_table_offset);
1131 msix_table_offset &= 0xFFFFFFF8;
1132 ioc->msix_table = (u32 *)((void *)ioc->chip + msix_table_offset);
1133
1134 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "msix is supported, "
1135 "vector_count(%d), table_offset(0x%08x), table(%p)\n", ioc->name,
1136 ioc->msix_vector_count, msix_table_offset, ioc->msix_table));
1137 return 0;
1138}
1139
1140
1141
1142
1143
1144
1145static void
1146_base_disable_msix(struct MPT2SAS_ADAPTER *ioc)
1147{
1148 if (ioc->msix_enable) {
1149 pci_disable_msix(ioc->pdev);
1150 kfree(ioc->msix_table_backup);
1151 ioc->msix_table_backup = NULL;
1152 ioc->msix_enable = 0;
1153 }
1154}
1155
1156
1157
1158
1159
1160
1161static int
1162_base_enable_msix(struct MPT2SAS_ADAPTER *ioc)
1163{
1164 struct msix_entry entries;
1165 int r;
1166 u8 try_msix = 0;
1167
1168 if (msix_disable == -1 || msix_disable == 0)
1169 try_msix = 1;
1170
1171 if (!try_msix)
1172 goto try_ioapic;
1173
1174 if (_base_check_enable_msix(ioc) != 0)
1175 goto try_ioapic;
1176
1177 ioc->msix_table_backup = kcalloc(ioc->msix_vector_count,
1178 sizeof(u32), GFP_KERNEL);
1179 if (!ioc->msix_table_backup) {
1180 dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "allocation for "
1181 "msix_table_backup failed!!!\n", ioc->name));
1182 goto try_ioapic;
1183 }
1184
1185 memset(&entries, 0, sizeof(struct msix_entry));
1186 r = pci_enable_msix(ioc->pdev, &entries, 1);
1187 if (r) {
1188 dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "pci_enable_msix "
1189 "failed (r=%d) !!!\n", ioc->name, r));
1190 goto try_ioapic;
1191 }
1192
1193 r = request_irq(entries.vector, _base_interrupt, IRQF_SHARED,
1194 ioc->name, ioc);
1195 if (r) {
1196 dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "unable to allocate "
1197 "interrupt %d !!!\n", ioc->name, entries.vector));
1198 pci_disable_msix(ioc->pdev);
1199 goto try_ioapic;
1200 }
1201
1202 ioc->pci_irq = entries.vector;
1203 ioc->msix_enable = 1;
1204 return 0;
1205
1206
1207 try_ioapic:
1208
1209 r = request_irq(ioc->pdev->irq, _base_interrupt, IRQF_SHARED,
1210 ioc->name, ioc);
1211 if (r) {
1212 printk(MPT2SAS_ERR_FMT "unable to allocate interrupt %d!\n",
1213 ioc->name, ioc->pdev->irq);
1214 r = -EBUSY;
1215 goto out_fail;
1216 }
1217
1218 ioc->pci_irq = ioc->pdev->irq;
1219 return 0;
1220
1221 out_fail:
1222 return r;
1223}
1224
1225
1226
1227
1228
1229
1230
1231int
1232mpt2sas_base_map_resources(struct MPT2SAS_ADAPTER *ioc)
1233{
1234 struct pci_dev *pdev = ioc->pdev;
1235 u32 memap_sz;
1236 u32 pio_sz;
1237 int i, r = 0;
1238 u64 pio_chip = 0;
1239 u64 chip_phys = 0;
1240
1241 dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n",
1242 ioc->name, __func__));
1243
1244 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
1245 if (pci_enable_device_mem(pdev)) {
1246 printk(MPT2SAS_WARN_FMT "pci_enable_device_mem: "
1247 "failed\n", ioc->name);
1248 return -ENODEV;
1249 }
1250
1251
1252 if (pci_request_selected_regions(pdev, ioc->bars,
1253 MPT2SAS_DRIVER_NAME)) {
1254 printk(MPT2SAS_WARN_FMT "pci_request_selected_regions: "
1255 "failed\n", ioc->name);
1256 r = -ENODEV;
1257 goto out_fail;
1258 }
1259
1260
1261 pci_enable_pcie_error_reporting(pdev);
1262
1263 pci_set_master(pdev);
1264
1265 if (_base_config_dma_addressing(ioc, pdev) != 0) {
1266 printk(MPT2SAS_WARN_FMT "no suitable DMA mask for %s\n",
1267 ioc->name, pci_name(pdev));
1268 r = -ENODEV;
1269 goto out_fail;
1270 }
1271
1272 for (i = 0, memap_sz = 0, pio_sz = 0 ; i < DEVICE_COUNT_RESOURCE; i++) {
1273 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1274 if (pio_sz)
1275 continue;
1276 pio_chip = (u64)pci_resource_start(pdev, i);
1277 pio_sz = pci_resource_len(pdev, i);
1278 } else {
1279 if (memap_sz)
1280 continue;
1281
1282 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
1283 ioc->chip_phys = pci_resource_start(pdev, i);
1284 chip_phys = (u64)ioc->chip_phys;
1285 memap_sz = pci_resource_len(pdev, i);
1286 ioc->chip = ioremap(ioc->chip_phys, memap_sz);
1287 if (ioc->chip == NULL) {
1288 printk(MPT2SAS_ERR_FMT "unable to map "
1289 "adapter memory!\n", ioc->name);
1290 r = -EINVAL;
1291 goto out_fail;
1292 }
1293 }
1294 }
1295 }
1296
1297 _base_mask_interrupts(ioc);
1298 r = _base_enable_msix(ioc);
1299 if (r)
1300 goto out_fail;
1301
1302 printk(MPT2SAS_INFO_FMT "%s: IRQ %d\n",
1303 ioc->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
1304 "IO-APIC enabled"), ioc->pci_irq);
1305 printk(MPT2SAS_INFO_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
1306 ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
1307 printk(MPT2SAS_INFO_FMT "ioport(0x%016llx), size(%d)\n",
1308 ioc->name, (unsigned long long)pio_chip, pio_sz);
1309
1310 return 0;
1311
1312 out_fail:
1313 if (ioc->chip_phys)
1314 iounmap(ioc->chip);
1315 ioc->chip_phys = 0;
1316 ioc->pci_irq = -1;
1317 pci_release_selected_regions(ioc->pdev, ioc->bars);
1318 pci_disable_pcie_error_reporting(pdev);
1319 pci_disable_device(pdev);
1320 return r;
1321}
1322
1323
1324
1325
1326
1327
1328
1329
1330void *
1331mpt2sas_base_get_msg_frame(struct MPT2SAS_ADAPTER *ioc, u16 smid)
1332{
1333 return (void *)(ioc->request + (smid * ioc->request_sz));
1334}
1335
1336
1337
1338
1339
1340
1341
1342
1343void *
1344mpt2sas_base_get_sense_buffer(struct MPT2SAS_ADAPTER *ioc, u16 smid)
1345{
1346 return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
1347}
1348
1349
1350
1351
1352
1353
1354
1355
1356__le32
1357mpt2sas_base_get_sense_buffer_dma(struct MPT2SAS_ADAPTER *ioc, u16 smid)
1358{
1359 return cpu_to_le32(ioc->sense_dma +
1360 ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
1361}
1362
1363
1364
1365
1366
1367
1368
1369
1370void *
1371mpt2sas_base_get_reply_virt_addr(struct MPT2SAS_ADAPTER *ioc, u32 phys_addr)
1372{
1373 if (!phys_addr)
1374 return NULL;
1375 return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
1376}
1377
1378
1379
1380
1381
1382
1383
1384
1385u16
1386mpt2sas_base_get_smid(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx)
1387{
1388 unsigned long flags;
1389 struct request_tracker *request;
1390 u16 smid;
1391
1392 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1393 if (list_empty(&ioc->internal_free_list)) {
1394 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1395 printk(MPT2SAS_ERR_FMT "%s: smid not available\n",
1396 ioc->name, __func__);
1397 return 0;
1398 }
1399
1400 request = list_entry(ioc->internal_free_list.next,
1401 struct request_tracker, tracker_list);
1402 request->cb_idx = cb_idx;
1403 smid = request->smid;
1404 list_del(&request->tracker_list);
1405 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1406 return smid;
1407}
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417u16
1418mpt2sas_base_get_smid_scsiio(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx,
1419 struct scsi_cmnd *scmd)
1420{
1421 unsigned long flags;
1422 struct request_tracker *request;
1423 u16 smid;
1424
1425 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1426 if (list_empty(&ioc->free_list)) {
1427 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1428 printk(MPT2SAS_ERR_FMT "%s: smid not available\n",
1429 ioc->name, __func__);
1430 return 0;
1431 }
1432
1433 request = list_entry(ioc->free_list.next,
1434 struct request_tracker, tracker_list);
1435 request->scmd = scmd;
1436 request->cb_idx = cb_idx;
1437 smid = request->smid;
1438 list_del(&request->tracker_list);
1439 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1440 return smid;
1441}
1442
1443
1444
1445
1446
1447
1448
1449
1450u16
1451mpt2sas_base_get_smid_hpr(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx)
1452{
1453 unsigned long flags;
1454 struct request_tracker *request;
1455 u16 smid;
1456
1457 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1458 if (list_empty(&ioc->hpr_free_list)) {
1459 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1460 return 0;
1461 }
1462
1463 request = list_entry(ioc->hpr_free_list.next,
1464 struct request_tracker, tracker_list);
1465 request->cb_idx = cb_idx;
1466 smid = request->smid;
1467 list_del(&request->tracker_list);
1468 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1469 return smid;
1470}
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480void
1481mpt2sas_base_free_smid(struct MPT2SAS_ADAPTER *ioc, u16 smid)
1482{
1483 unsigned long flags;
1484 int i;
1485
1486 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1487 if (smid >= ioc->hi_priority_smid) {
1488 if (smid < ioc->internal_smid) {
1489
1490 i = smid - ioc->hi_priority_smid;
1491 ioc->hpr_lookup[i].cb_idx = 0xFF;
1492 list_add_tail(&ioc->hpr_lookup[i].tracker_list,
1493 &ioc->hpr_free_list);
1494 } else {
1495
1496 i = smid - ioc->internal_smid;
1497 ioc->internal_lookup[i].cb_idx = 0xFF;
1498 list_add_tail(&ioc->internal_lookup[i].tracker_list,
1499 &ioc->internal_free_list);
1500 }
1501 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1502 return;
1503 }
1504
1505
1506 i = smid - 1;
1507 ioc->scsi_lookup[i].cb_idx = 0xFF;
1508 ioc->scsi_lookup[i].scmd = NULL;
1509 list_add_tail(&ioc->scsi_lookup[i].tracker_list,
1510 &ioc->free_list);
1511 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1512
1513
1514
1515
1516 if (ioc->shost_recovery && ioc->pending_io_count) {
1517 if (ioc->pending_io_count == 1)
1518 wake_up(&ioc->reset_wq);
1519 ioc->pending_io_count--;
1520 }
1521}
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534#ifndef writeq
1535static inline void _base_writeq(__u64 b, volatile void __iomem *addr,
1536 spinlock_t *writeq_lock)
1537{
1538 unsigned long flags;
1539 __u64 data_out = cpu_to_le64(b);
1540
1541 spin_lock_irqsave(writeq_lock, flags);
1542 writel((u32)(data_out), addr);
1543 writel((u32)(data_out >> 32), (addr + 4));
1544 spin_unlock_irqrestore(writeq_lock, flags);
1545}
1546#else
1547static inline void _base_writeq(__u64 b, volatile void __iomem *addr,
1548 spinlock_t *writeq_lock)
1549{
1550 writeq(cpu_to_le64(b), addr);
1551}
1552#endif
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562void
1563mpt2sas_base_put_smid_scsi_io(struct MPT2SAS_ADAPTER *ioc, u16 smid, u16 handle)
1564{
1565 Mpi2RequestDescriptorUnion_t descriptor;
1566 u64 *request = (u64 *)&descriptor;
1567
1568
1569 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
1570 descriptor.SCSIIO.MSIxIndex = 0;
1571 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
1572 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
1573 descriptor.SCSIIO.LMID = 0;
1574 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
1575 &ioc->scsi_lookup_lock);
1576}
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586void
1587mpt2sas_base_put_smid_hi_priority(struct MPT2SAS_ADAPTER *ioc, u16 smid)
1588{
1589 Mpi2RequestDescriptorUnion_t descriptor;
1590 u64 *request = (u64 *)&descriptor;
1591
1592 descriptor.HighPriority.RequestFlags =
1593 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
1594 descriptor.HighPriority.MSIxIndex = 0;
1595 descriptor.HighPriority.SMID = cpu_to_le16(smid);
1596 descriptor.HighPriority.LMID = 0;
1597 descriptor.HighPriority.Reserved1 = 0;
1598 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
1599 &ioc->scsi_lookup_lock);
1600}
1601
1602
1603
1604
1605
1606
1607
1608
1609void
1610mpt2sas_base_put_smid_default(struct MPT2SAS_ADAPTER *ioc, u16 smid)
1611{
1612 Mpi2RequestDescriptorUnion_t descriptor;
1613 u64 *request = (u64 *)&descriptor;
1614
1615 descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
1616 descriptor.Default.MSIxIndex = 0;
1617 descriptor.Default.SMID = cpu_to_le16(smid);
1618 descriptor.Default.LMID = 0;
1619 descriptor.Default.DescriptorTypeDependent = 0;
1620 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
1621 &ioc->scsi_lookup_lock);
1622}
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632void
1633mpt2sas_base_put_smid_target_assist(struct MPT2SAS_ADAPTER *ioc, u16 smid,
1634 u16 io_index)
1635{
1636 Mpi2RequestDescriptorUnion_t descriptor;
1637 u64 *request = (u64 *)&descriptor;
1638
1639 descriptor.SCSITarget.RequestFlags =
1640 MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET;
1641 descriptor.SCSITarget.MSIxIndex = 0;
1642 descriptor.SCSITarget.SMID = cpu_to_le16(smid);
1643 descriptor.SCSITarget.LMID = 0;
1644 descriptor.SCSITarget.IoIndex = cpu_to_le16(io_index);
1645 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
1646 &ioc->scsi_lookup_lock);
1647}
1648
1649
1650
1651
1652
1653
1654
1655static void
1656_base_display_dell_branding(struct MPT2SAS_ADAPTER *ioc)
1657{
1658 char dell_branding[MPT2SAS_DELL_BRANDING_SIZE];
1659
1660 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_DELL)
1661 return;
1662
1663 memset(dell_branding, 0, MPT2SAS_DELL_BRANDING_SIZE);
1664 switch (ioc->pdev->subsystem_device) {
1665 case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
1666 strncpy(dell_branding, MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING,
1667 MPT2SAS_DELL_BRANDING_SIZE - 1);
1668 break;
1669 case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
1670 strncpy(dell_branding, MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING,
1671 MPT2SAS_DELL_BRANDING_SIZE - 1);
1672 break;
1673 case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
1674 strncpy(dell_branding,
1675 MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING,
1676 MPT2SAS_DELL_BRANDING_SIZE - 1);
1677 break;
1678 case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
1679 strncpy(dell_branding,
1680 MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING,
1681 MPT2SAS_DELL_BRANDING_SIZE - 1);
1682 break;
1683 case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
1684 strncpy(dell_branding,
1685 MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING,
1686 MPT2SAS_DELL_BRANDING_SIZE - 1);
1687 break;
1688 case MPT2SAS_DELL_PERC_H200_SSDID:
1689 strncpy(dell_branding, MPT2SAS_DELL_PERC_H200_BRANDING,
1690 MPT2SAS_DELL_BRANDING_SIZE - 1);
1691 break;
1692 case MPT2SAS_DELL_6GBPS_SAS_SSDID:
1693 strncpy(dell_branding, MPT2SAS_DELL_6GBPS_SAS_BRANDING,
1694 MPT2SAS_DELL_BRANDING_SIZE - 1);
1695 break;
1696 default:
1697 sprintf(dell_branding, "0x%4X", ioc->pdev->subsystem_device);
1698 break;
1699 }
1700
1701 printk(MPT2SAS_INFO_FMT "%s: Vendor(0x%04X), Device(0x%04X),"
1702 " SSVID(0x%04X), SSDID(0x%04X)\n", ioc->name, dell_branding,
1703 ioc->pdev->vendor, ioc->pdev->device, ioc->pdev->subsystem_vendor,
1704 ioc->pdev->subsystem_device);
1705}
1706
1707
1708
1709
1710
1711
1712
1713static void
1714_base_display_ioc_capabilities(struct MPT2SAS_ADAPTER *ioc)
1715{
1716 int i = 0;
1717 char desc[16];
1718 u8 revision;
1719 u32 iounit_pg1_flags;
1720
1721 pci_read_config_byte(ioc->pdev, PCI_CLASS_REVISION, &revision);
1722 strncpy(desc, ioc->manu_pg0.ChipName, 16);
1723 printk(MPT2SAS_INFO_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "
1724 "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
1725 ioc->name, desc,
1726 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
1727 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
1728 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
1729 ioc->facts.FWVersion.Word & 0x000000FF,
1730 revision,
1731 (ioc->bios_pg3.BiosVersion & 0xFF000000) >> 24,
1732 (ioc->bios_pg3.BiosVersion & 0x00FF0000) >> 16,
1733 (ioc->bios_pg3.BiosVersion & 0x0000FF00) >> 8,
1734 ioc->bios_pg3.BiosVersion & 0x000000FF);
1735
1736 _base_display_dell_branding(ioc);
1737
1738 printk(MPT2SAS_INFO_FMT "Protocol=(", ioc->name);
1739
1740 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
1741 printk("Initiator");
1742 i++;
1743 }
1744
1745 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
1746 printk("%sTarget", i ? "," : "");
1747 i++;
1748 }
1749
1750 i = 0;
1751 printk("), ");
1752 printk("Capabilities=(");
1753
1754 if (ioc->facts.IOCCapabilities &
1755 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
1756 printk("Raid");
1757 i++;
1758 }
1759
1760 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
1761 printk("%sTLR", i ? "," : "");
1762 i++;
1763 }
1764
1765 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
1766 printk("%sMulticast", i ? "," : "");
1767 i++;
1768 }
1769
1770 if (ioc->facts.IOCCapabilities &
1771 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
1772 printk("%sBIDI Target", i ? "," : "");
1773 i++;
1774 }
1775
1776 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
1777 printk("%sEEDP", i ? "," : "");
1778 i++;
1779 }
1780
1781 if (ioc->facts.IOCCapabilities &
1782 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
1783 printk("%sSnapshot Buffer", i ? "," : "");
1784 i++;
1785 }
1786
1787 if (ioc->facts.IOCCapabilities &
1788 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
1789 printk("%sDiag Trace Buffer", i ? "," : "");
1790 i++;
1791 }
1792
1793 if (ioc->facts.IOCCapabilities &
1794 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
1795 printk(KERN_INFO "%sDiag Extended Buffer", i ? "," : "");
1796 i++;
1797 }
1798
1799 if (ioc->facts.IOCCapabilities &
1800 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
1801 printk("%sTask Set Full", i ? "," : "");
1802 i++;
1803 }
1804
1805 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
1806 if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
1807 printk("%sNCQ", i ? "," : "");
1808 i++;
1809 }
1810
1811 printk(")\n");
1812}
1813
1814
1815
1816
1817
1818
1819
1820static void
1821_base_static_config_pages(struct MPT2SAS_ADAPTER *ioc)
1822{
1823 Mpi2ConfigReply_t mpi_reply;
1824 u32 iounit_pg1_flags;
1825
1826 mpt2sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
1827 if (ioc->ir_firmware)
1828 mpt2sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
1829 &ioc->manu_pg10);
1830 mpt2sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
1831 mpt2sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
1832 mpt2sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
1833 mpt2sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
1834 mpt2sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
1835 _base_display_ioc_capabilities(ioc);
1836
1837
1838
1839
1840
1841 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
1842 if ((ioc->facts.IOCCapabilities &
1843 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
1844 iounit_pg1_flags &=
1845 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
1846 else
1847 iounit_pg1_flags |=
1848 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
1849 ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
1850 mpt2sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
1851}
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861static void
1862_base_release_memory_pools(struct MPT2SAS_ADAPTER *ioc)
1863{
1864 dexitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
1865 __func__));
1866
1867 if (ioc->request) {
1868 pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
1869 ioc->request, ioc->request_dma);
1870 dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "request_pool(0x%p)"
1871 ": free\n", ioc->name, ioc->request));
1872 ioc->request = NULL;
1873 }
1874
1875 if (ioc->sense) {
1876 pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
1877 if (ioc->sense_dma_pool)
1878 pci_pool_destroy(ioc->sense_dma_pool);
1879 dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "sense_pool(0x%p)"
1880 ": free\n", ioc->name, ioc->sense));
1881 ioc->sense = NULL;
1882 }
1883
1884 if (ioc->reply) {
1885 pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
1886 if (ioc->reply_dma_pool)
1887 pci_pool_destroy(ioc->reply_dma_pool);
1888 dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_pool(0x%p)"
1889 ": free\n", ioc->name, ioc->reply));
1890 ioc->reply = NULL;
1891 }
1892
1893 if (ioc->reply_free) {
1894 pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
1895 ioc->reply_free_dma);
1896 if (ioc->reply_free_dma_pool)
1897 pci_pool_destroy(ioc->reply_free_dma_pool);
1898 dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free_pool"
1899 "(0x%p): free\n", ioc->name, ioc->reply_free));
1900 ioc->reply_free = NULL;
1901 }
1902
1903 if (ioc->reply_post_free) {
1904 pci_pool_free(ioc->reply_post_free_dma_pool,
1905 ioc->reply_post_free, ioc->reply_post_free_dma);
1906 if (ioc->reply_post_free_dma_pool)
1907 pci_pool_destroy(ioc->reply_post_free_dma_pool);
1908 dexitprintk(ioc, printk(MPT2SAS_INFO_FMT
1909 "reply_post_free_pool(0x%p): free\n", ioc->name,
1910 ioc->reply_post_free));
1911 ioc->reply_post_free = NULL;
1912 }
1913
1914 if (ioc->config_page) {
1915 dexitprintk(ioc, printk(MPT2SAS_INFO_FMT
1916 "config_page(0x%p): free\n", ioc->name,
1917 ioc->config_page));
1918 pci_free_consistent(ioc->pdev, ioc->config_page_sz,
1919 ioc->config_page, ioc->config_page_dma);
1920 }
1921
1922 if (ioc->scsi_lookup) {
1923 free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages);
1924 ioc->scsi_lookup = NULL;
1925 }
1926 kfree(ioc->hpr_lookup);
1927 kfree(ioc->internal_lookup);
1928}
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938static int
1939_base_allocate_memory_pools(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
1940{
1941 Mpi2IOCFactsReply_t *facts;
1942 u32 queue_size, queue_diff;
1943 u16 max_sge_elements;
1944 u16 num_of_reply_frames;
1945 u16 chains_needed_per_io;
1946 u32 sz, total_sz;
1947 u32 retry_sz;
1948 u16 max_request_credit;
1949
1950 dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
1951 __func__));
1952
1953 retry_sz = 0;
1954 facts = &ioc->facts;
1955
1956
1957 if (max_sgl_entries != -1) {
1958 ioc->shost->sg_tablesize = (max_sgl_entries <
1959 MPT2SAS_SG_DEPTH) ? max_sgl_entries :
1960 MPT2SAS_SG_DEPTH;
1961 } else {
1962 ioc->shost->sg_tablesize = MPT2SAS_SG_DEPTH;
1963 }
1964
1965
1966 if (max_queue_depth != -1) {
1967 max_request_credit = (max_queue_depth < facts->RequestCredit)
1968 ? max_queue_depth : facts->RequestCredit;
1969 } else {
1970 max_request_credit = (facts->RequestCredit >
1971 MPT2SAS_MAX_REQUEST_QUEUE) ? MPT2SAS_MAX_REQUEST_QUEUE :
1972 facts->RequestCredit;
1973 }
1974
1975 ioc->hba_queue_depth = max_request_credit;
1976 ioc->hi_priority_depth = facts->HighPriorityCredit;
1977 ioc->internal_depth = ioc->hi_priority_depth + 5;
1978
1979
1980 ioc->request_sz = facts->IOCRequestFrameSize * 4;
1981
1982
1983 ioc->reply_sz = facts->ReplyFrameSize * 4;
1984
1985 retry_allocation:
1986 total_sz = 0;
1987
1988 max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
1989 sizeof(Mpi2SGEIOUnion_t)) + ioc->sge_size);
1990 ioc->max_sges_in_main_message = max_sge_elements/ioc->sge_size;
1991
1992
1993 max_sge_elements = ioc->request_sz - ioc->sge_size;
1994 ioc->max_sges_in_chain_message = max_sge_elements/ioc->sge_size;
1995
1996 ioc->chain_offset_value_for_main_message =
1997 ((sizeof(Mpi2SCSIIORequest_t) - sizeof(Mpi2SGEIOUnion_t)) +
1998 (ioc->max_sges_in_chain_message * ioc->sge_size)) / 4;
1999
2000
2001
2002
2003 chains_needed_per_io = ((ioc->shost->sg_tablesize -
2004 ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
2005 + 1;
2006 if (chains_needed_per_io > facts->MaxChainDepth) {
2007 chains_needed_per_io = facts->MaxChainDepth;
2008 ioc->shost->sg_tablesize = min_t(u16,
2009 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
2010 * chains_needed_per_io), ioc->shost->sg_tablesize);
2011 }
2012 ioc->chains_needed_per_io = chains_needed_per_io;
2013
2014
2015 num_of_reply_frames = ioc->hba_queue_depth + 32;
2016
2017
2018
2019 if (!(num_of_reply_frames % 16))
2020 num_of_reply_frames--;
2021
2022
2023
2024
2025
2026
2027 queue_size = num_of_reply_frames;
2028 queue_size += 16 - (queue_size % 16);
2029 ioc->reply_free_queue_depth = queue_size;
2030
2031
2032
2033
2034
2035
2036 queue_size = ioc->hba_queue_depth + num_of_reply_frames + 1;
2037
2038 if (queue_size % 16)
2039 queue_size += 16 - (queue_size % 16);
2040
2041
2042 if (queue_size > facts->MaxReplyDescriptorPostQueueDepth) {
2043 queue_diff = queue_size -
2044 facts->MaxReplyDescriptorPostQueueDepth;
2045
2046
2047 if (queue_diff % 16)
2048 queue_diff += 16 - (queue_diff % 16);
2049
2050
2051
2052
2053 ioc->hba_queue_depth -= queue_diff;
2054 ioc->reply_free_queue_depth -= queue_diff;
2055 queue_size -= queue_diff;
2056 }
2057 ioc->reply_post_queue_depth = queue_size;
2058
2059 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scatter gather: "
2060 "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
2061 "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
2062 ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
2063 ioc->chains_needed_per_io));
2064
2065 ioc->scsiio_depth = ioc->hba_queue_depth -
2066 ioc->hi_priority_depth - ioc->internal_depth;
2067
2068
2069
2070
2071 ioc->shost->can_queue = ioc->scsiio_depth - (2);
2072 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scsi host: "
2073 "can_queue depth (%d)\n", ioc->name, ioc->shost->can_queue));
2074
2075
2076
2077
2078 ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
2079 sz = ((ioc->scsiio_depth + 1 + ioc->chain_depth) * ioc->request_sz);
2080
2081
2082 sz += (ioc->hi_priority_depth * ioc->request_sz);
2083
2084
2085 sz += (ioc->internal_depth * ioc->request_sz);
2086
2087 ioc->request_dma_sz = sz;
2088 ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
2089 if (!ioc->request) {
2090 printk(MPT2SAS_ERR_FMT "request pool: pci_alloc_consistent "
2091 "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
2092 "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
2093 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
2094 if (ioc->scsiio_depth < MPT2SAS_SAS_QUEUE_DEPTH)
2095 goto out;
2096 retry_sz += 64;
2097 ioc->hba_queue_depth = max_request_credit - retry_sz;
2098 goto retry_allocation;
2099 }
2100
2101 if (retry_sz)
2102 printk(MPT2SAS_ERR_FMT "request pool: pci_alloc_consistent "
2103 "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
2104 "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
2105 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
2106
2107
2108
2109 ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
2110 ioc->request_sz);
2111 ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
2112 ioc->request_sz);
2113
2114
2115 ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
2116 ioc->request_sz);
2117 ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
2118 ioc->request_sz);
2119
2120 ioc->chain = ioc->internal + (ioc->internal_depth *
2121 ioc->request_sz);
2122 ioc->chain_dma = ioc->internal_dma + (ioc->internal_depth *
2123 ioc->request_sz);
2124
2125 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request pool(0x%p): "
2126 "depth(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name,
2127 ioc->request, ioc->hba_queue_depth, ioc->request_sz,
2128 (ioc->hba_queue_depth * ioc->request_sz)/1024));
2129 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "chain pool(0x%p): depth"
2130 "(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name, ioc->chain,
2131 ioc->chain_depth, ioc->request_sz, ((ioc->chain_depth *
2132 ioc->request_sz))/1024));
2133 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request pool: dma(0x%llx)\n",
2134 ioc->name, (unsigned long long) ioc->request_dma));
2135 total_sz += sz;
2136
2137 sz = ioc->scsiio_depth * sizeof(struct request_tracker);
2138 ioc->scsi_lookup_pages = get_order(sz);
2139 ioc->scsi_lookup = (struct request_tracker *)__get_free_pages(
2140 GFP_KERNEL, ioc->scsi_lookup_pages);
2141 if (!ioc->scsi_lookup) {
2142 printk(MPT2SAS_ERR_FMT "scsi_lookup: get_free_pages failed, "
2143 "sz(%d)\n", ioc->name, (int)sz);
2144 goto out;
2145 }
2146
2147 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scsiio(0x%p): "
2148 "depth(%d)\n", ioc->name, ioc->request,
2149 ioc->scsiio_depth));
2150
2151
2152 ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
2153 sizeof(struct request_tracker), GFP_KERNEL);
2154 if (!ioc->hpr_lookup) {
2155 printk(MPT2SAS_ERR_FMT "hpr_lookup: kcalloc failed\n",
2156 ioc->name);
2157 goto out;
2158 }
2159 ioc->hi_priority_smid = ioc->scsiio_depth + 1;
2160 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "hi_priority(0x%p): "
2161 "depth(%d), start smid(%d)\n", ioc->name, ioc->hi_priority,
2162 ioc->hi_priority_depth, ioc->hi_priority_smid));
2163
2164
2165 ioc->internal_lookup = kcalloc(ioc->internal_depth,
2166 sizeof(struct request_tracker), GFP_KERNEL);
2167 if (!ioc->internal_lookup) {
2168 printk(MPT2SAS_ERR_FMT "internal_lookup: kcalloc failed\n",
2169 ioc->name);
2170 goto out;
2171 }
2172 ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
2173 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "internal(0x%p): "
2174 "depth(%d), start smid(%d)\n", ioc->name, ioc->internal,
2175 ioc->internal_depth, ioc->internal_smid));
2176
2177
2178 sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
2179 ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
2180 0);
2181 if (!ioc->sense_dma_pool) {
2182 printk(MPT2SAS_ERR_FMT "sense pool: pci_pool_create failed\n",
2183 ioc->name);
2184 goto out;
2185 }
2186 ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
2187 &ioc->sense_dma);
2188 if (!ioc->sense) {
2189 printk(MPT2SAS_ERR_FMT "sense pool: pci_pool_alloc failed\n",
2190 ioc->name);
2191 goto out;
2192 }
2193 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT
2194 "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
2195 "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
2196 SCSI_SENSE_BUFFERSIZE, sz/1024));
2197 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "sense_dma(0x%llx)\n",
2198 ioc->name, (unsigned long long)ioc->sense_dma));
2199 total_sz += sz;
2200
2201
2202 sz = ioc->reply_free_queue_depth * ioc->reply_sz;
2203 ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
2204 0);
2205 if (!ioc->reply_dma_pool) {
2206 printk(MPT2SAS_ERR_FMT "reply pool: pci_pool_create failed\n",
2207 ioc->name);
2208 goto out;
2209 }
2210 ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
2211 &ioc->reply_dma);
2212 if (!ioc->reply) {
2213 printk(MPT2SAS_ERR_FMT "reply pool: pci_pool_alloc failed\n",
2214 ioc->name);
2215 goto out;
2216 }
2217 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply pool(0x%p): depth"
2218 "(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name, ioc->reply,
2219 ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
2220 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_dma(0x%llx)\n",
2221 ioc->name, (unsigned long long)ioc->reply_dma));
2222 total_sz += sz;
2223
2224
2225 sz = ioc->reply_free_queue_depth * 4;
2226 ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
2227 ioc->pdev, sz, 16, 0);
2228 if (!ioc->reply_free_dma_pool) {
2229 printk(MPT2SAS_ERR_FMT "reply_free pool: pci_pool_create "
2230 "failed\n", ioc->name);
2231 goto out;
2232 }
2233 ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
2234 &ioc->reply_free_dma);
2235 if (!ioc->reply_free) {
2236 printk(MPT2SAS_ERR_FMT "reply_free pool: pci_pool_alloc "
2237 "failed\n", ioc->name);
2238 goto out;
2239 }
2240 memset(ioc->reply_free, 0, sz);
2241 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free pool(0x%p): "
2242 "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
2243 ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
2244 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free_dma"
2245 "(0x%llx)\n", ioc->name, (unsigned long long)ioc->reply_free_dma));
2246 total_sz += sz;
2247
2248
2249 sz = ioc->reply_post_queue_depth * sizeof(Mpi2DefaultReplyDescriptor_t);
2250 ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
2251 ioc->pdev, sz, 16, 0);
2252 if (!ioc->reply_post_free_dma_pool) {
2253 printk(MPT2SAS_ERR_FMT "reply_post_free pool: pci_pool_create "
2254 "failed\n", ioc->name);
2255 goto out;
2256 }
2257 ioc->reply_post_free = pci_pool_alloc(ioc->reply_post_free_dma_pool ,
2258 GFP_KERNEL, &ioc->reply_post_free_dma);
2259 if (!ioc->reply_post_free) {
2260 printk(MPT2SAS_ERR_FMT "reply_post_free pool: pci_pool_alloc "
2261 "failed\n", ioc->name);
2262 goto out;
2263 }
2264 memset(ioc->reply_post_free, 0, sz);
2265 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply post free pool"
2266 "(0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n",
2267 ioc->name, ioc->reply_post_free, ioc->reply_post_queue_depth, 8,
2268 sz/1024));
2269 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_post_free_dma = "
2270 "(0x%llx)\n", ioc->name, (unsigned long long)
2271 ioc->reply_post_free_dma));
2272 total_sz += sz;
2273
2274 ioc->config_page_sz = 512;
2275 ioc->config_page = pci_alloc_consistent(ioc->pdev,
2276 ioc->config_page_sz, &ioc->config_page_dma);
2277 if (!ioc->config_page) {
2278 printk(MPT2SAS_ERR_FMT "config page: pci_pool_alloc "
2279 "failed\n", ioc->name);
2280 goto out;
2281 }
2282 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "config page(0x%p): size"
2283 "(%d)\n", ioc->name, ioc->config_page, ioc->config_page_sz));
2284 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "config_page_dma"
2285 "(0x%llx)\n", ioc->name, (unsigned long long)ioc->config_page_dma));
2286 total_sz += ioc->config_page_sz;
2287
2288 printk(MPT2SAS_INFO_FMT "Allocated physical memory: size(%d kB)\n",
2289 ioc->name, total_sz/1024);
2290 printk(MPT2SAS_INFO_FMT "Current Controller Queue Depth(%d), "
2291 "Max Controller Queue Depth(%d)\n",
2292 ioc->name, ioc->shost->can_queue, facts->RequestCredit);
2293 printk(MPT2SAS_INFO_FMT "Scatter Gather Elements per IO(%d)\n",
2294 ioc->name, ioc->shost->sg_tablesize);
2295 return 0;
2296
2297 out:
2298 _base_release_memory_pools(ioc);
2299 return -ENOMEM;
2300}
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311u32
2312mpt2sas_base_get_iocstate(struct MPT2SAS_ADAPTER *ioc, int cooked)
2313{
2314 u32 s, sc;
2315
2316 s = readl(&ioc->chip->Doorbell);
2317 sc = s & MPI2_IOC_STATE_MASK;
2318 return cooked ? sc : s;
2319}
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329static int
2330_base_wait_on_iocstate(struct MPT2SAS_ADAPTER *ioc, u32 ioc_state, int timeout,
2331 int sleep_flag)
2332{
2333 u32 count, cntdn;
2334 u32 current_state;
2335
2336 count = 0;
2337 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
2338 do {
2339 current_state = mpt2sas_base_get_iocstate(ioc, 1);
2340 if (current_state == ioc_state)
2341 return 0;
2342 if (count && current_state == MPI2_IOC_STATE_FAULT)
2343 break;
2344 if (sleep_flag == CAN_SLEEP)
2345 msleep(1);
2346 else
2347 udelay(500);
2348 count++;
2349 } while (--cntdn);
2350
2351 return current_state;
2352}
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365static int
2366_base_wait_for_doorbell_int(struct MPT2SAS_ADAPTER *ioc, int timeout,
2367 int sleep_flag)
2368{
2369 u32 cntdn, count;
2370 u32 int_status;
2371
2372 count = 0;
2373 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
2374 do {
2375 int_status = readl(&ioc->chip->HostInterruptStatus);
2376 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
2377 dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
2378 "successfull count(%d), timeout(%d)\n", ioc->name,
2379 __func__, count, timeout));
2380 return 0;
2381 }
2382 if (sleep_flag == CAN_SLEEP)
2383 msleep(1);
2384 else
2385 udelay(500);
2386 count++;
2387 } while (--cntdn);
2388
2389 printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
2390 "int_status(%x)!\n", ioc->name, __func__, count, int_status);
2391 return -EFAULT;
2392}
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405static int
2406_base_wait_for_doorbell_ack(struct MPT2SAS_ADAPTER *ioc, int timeout,
2407 int sleep_flag)
2408{
2409 u32 cntdn, count;
2410 u32 int_status;
2411 u32 doorbell;
2412
2413 count = 0;
2414 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
2415 do {
2416 int_status = readl(&ioc->chip->HostInterruptStatus);
2417 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
2418 dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
2419 "successfull count(%d), timeout(%d)\n", ioc->name,
2420 __func__, count, timeout));
2421 return 0;
2422 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
2423 doorbell = readl(&ioc->chip->Doorbell);
2424 if ((doorbell & MPI2_IOC_STATE_MASK) ==
2425 MPI2_IOC_STATE_FAULT) {
2426 mpt2sas_base_fault_info(ioc , doorbell);
2427 return -EFAULT;
2428 }
2429 } else if (int_status == 0xFFFFFFFF)
2430 goto out;
2431
2432 if (sleep_flag == CAN_SLEEP)
2433 msleep(1);
2434 else
2435 udelay(500);
2436 count++;
2437 } while (--cntdn);
2438
2439 out:
2440 printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
2441 "int_status(%x)!\n", ioc->name, __func__, count, int_status);
2442 return -EFAULT;
2443}
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454static int
2455_base_wait_for_doorbell_not_used(struct MPT2SAS_ADAPTER *ioc, int timeout,
2456 int sleep_flag)
2457{
2458 u32 cntdn, count;
2459 u32 doorbell_reg;
2460
2461 count = 0;
2462 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
2463 do {
2464 doorbell_reg = readl(&ioc->chip->Doorbell);
2465 if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
2466 dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
2467 "successfull count(%d), timeout(%d)\n", ioc->name,
2468 __func__, count, timeout));
2469 return 0;
2470 }
2471 if (sleep_flag == CAN_SLEEP)
2472 msleep(1);
2473 else
2474 udelay(500);
2475 count++;
2476 } while (--cntdn);
2477
2478 printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
2479 "doorbell_reg(%x)!\n", ioc->name, __func__, count, doorbell_reg);
2480 return -EFAULT;
2481}
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492static int
2493_base_send_ioc_reset(struct MPT2SAS_ADAPTER *ioc, u8 reset_type, int timeout,
2494 int sleep_flag)
2495{
2496 u32 ioc_state;
2497 int r = 0;
2498
2499 if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
2500 printk(MPT2SAS_ERR_FMT "%s: unknown reset_type\n",
2501 ioc->name, __func__);
2502 return -EFAULT;
2503 }
2504
2505 if (!(ioc->facts.IOCCapabilities &
2506 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
2507 return -EFAULT;
2508
2509 printk(MPT2SAS_INFO_FMT "sending message unit reset !!\n", ioc->name);
2510
2511 writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
2512 &ioc->chip->Doorbell);
2513 if ((_base_wait_for_doorbell_ack(ioc, 15, sleep_flag))) {
2514 r = -EFAULT;
2515 goto out;
2516 }
2517 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
2518 timeout, sleep_flag);
2519 if (ioc_state) {
2520 printk(MPT2SAS_ERR_FMT "%s: failed going to ready state "
2521 " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state);
2522 r = -EFAULT;
2523 goto out;
2524 }
2525 out:
2526 printk(MPT2SAS_INFO_FMT "message unit reset: %s\n",
2527 ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
2528 return r;
2529}
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543static int
2544_base_handshake_req_reply_wait(struct MPT2SAS_ADAPTER *ioc, int request_bytes,
2545 u32 *request, int reply_bytes, u16 *reply, int timeout, int sleep_flag)
2546{
2547 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
2548 int i;
2549 u8 failed;
2550 u16 dummy;
2551 u32 *mfp;
2552
2553
2554 if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
2555 printk(MPT2SAS_ERR_FMT "doorbell is in use "
2556 " (line=%d)\n", ioc->name, __LINE__);
2557 return -EFAULT;
2558 }
2559
2560
2561 if (readl(&ioc->chip->HostInterruptStatus) &
2562 MPI2_HIS_IOC2SYS_DB_STATUS)
2563 writel(0, &ioc->chip->HostInterruptStatus);
2564
2565
2566 writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
2567 ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
2568 &ioc->chip->Doorbell);
2569
2570 if ((_base_wait_for_doorbell_int(ioc, 5, NO_SLEEP))) {
2571 printk(MPT2SAS_ERR_FMT "doorbell handshake "
2572 "int failed (line=%d)\n", ioc->name, __LINE__);
2573 return -EFAULT;
2574 }
2575 writel(0, &ioc->chip->HostInterruptStatus);
2576
2577 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) {
2578 printk(MPT2SAS_ERR_FMT "doorbell handshake "
2579 "ack failed (line=%d)\n", ioc->name, __LINE__);
2580 return -EFAULT;
2581 }
2582
2583
2584 for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
2585 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
2586 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag)))
2587 failed = 1;
2588 }
2589
2590 if (failed) {
2591 printk(MPT2SAS_ERR_FMT "doorbell handshake "
2592 "sending request failed (line=%d)\n", ioc->name, __LINE__);
2593 return -EFAULT;
2594 }
2595
2596
2597 if ((_base_wait_for_doorbell_int(ioc, timeout, sleep_flag))) {
2598 printk(MPT2SAS_ERR_FMT "doorbell handshake "
2599 "int failed (line=%d)\n", ioc->name, __LINE__);
2600 return -EFAULT;
2601 }
2602
2603
2604 reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
2605 & MPI2_DOORBELL_DATA_MASK);
2606 writel(0, &ioc->chip->HostInterruptStatus);
2607 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
2608 printk(MPT2SAS_ERR_FMT "doorbell handshake "
2609 "int failed (line=%d)\n", ioc->name, __LINE__);
2610 return -EFAULT;
2611 }
2612 reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
2613 & MPI2_DOORBELL_DATA_MASK);
2614 writel(0, &ioc->chip->HostInterruptStatus);
2615
2616 for (i = 2; i < default_reply->MsgLength * 2; i++) {
2617 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
2618 printk(MPT2SAS_ERR_FMT "doorbell "
2619 "handshake int failed (line=%d)\n", ioc->name,
2620 __LINE__);
2621 return -EFAULT;
2622 }
2623 if (i >= reply_bytes/2)
2624 dummy = readl(&ioc->chip->Doorbell);
2625 else
2626 reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
2627 & MPI2_DOORBELL_DATA_MASK);
2628 writel(0, &ioc->chip->HostInterruptStatus);
2629 }
2630
2631 _base_wait_for_doorbell_int(ioc, 5, sleep_flag);
2632 if (_base_wait_for_doorbell_not_used(ioc, 5, sleep_flag) != 0) {
2633 dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "doorbell is in use "
2634 " (line=%d)\n", ioc->name, __LINE__));
2635 }
2636 writel(0, &ioc->chip->HostInterruptStatus);
2637
2638 if (ioc->logging_level & MPT_DEBUG_INIT) {
2639 mfp = (u32 *)reply;
2640 printk(KERN_DEBUG "\toffset:data\n");
2641 for (i = 0; i < reply_bytes/4; i++)
2642 printk(KERN_DEBUG "\t[0x%02x]:%08x\n", i*4,
2643 le32_to_cpu(mfp[i]));
2644 }
2645 return 0;
2646}
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662int
2663mpt2sas_base_sas_iounit_control(struct MPT2SAS_ADAPTER *ioc,
2664 Mpi2SasIoUnitControlReply_t *mpi_reply,
2665 Mpi2SasIoUnitControlRequest_t *mpi_request)
2666{
2667 u16 smid;
2668 u32 ioc_state;
2669 unsigned long timeleft;
2670 u8 issue_reset;
2671 int rc;
2672 void *request;
2673 u16 wait_state_count;
2674
2675 dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
2676 __func__));
2677
2678 mutex_lock(&ioc->base_cmds.mutex);
2679
2680 if (ioc->base_cmds.status != MPT2_CMD_NOT_USED) {
2681 printk(MPT2SAS_ERR_FMT "%s: base_cmd in use\n",
2682 ioc->name, __func__);
2683 rc = -EAGAIN;
2684 goto out;
2685 }
2686
2687 wait_state_count = 0;
2688 ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
2689 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
2690 if (wait_state_count++ == 10) {
2691 printk(MPT2SAS_ERR_FMT
2692 "%s: failed due to ioc not operational\n",
2693 ioc->name, __func__);
2694 rc = -EFAULT;
2695 goto out;
2696 }
2697 ssleep(1);
2698 ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
2699 printk(MPT2SAS_INFO_FMT "%s: waiting for "
2700 "operational state(count=%d)\n", ioc->name,
2701 __func__, wait_state_count);
2702 }
2703
2704 smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
2705 if (!smid) {
2706 printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
2707 ioc->name, __func__);
2708 rc = -EAGAIN;
2709 goto out;
2710 }
2711
2712 rc = 0;
2713 ioc->base_cmds.status = MPT2_CMD_PENDING;
2714 request = mpt2sas_base_get_msg_frame(ioc, smid);
2715 ioc->base_cmds.smid = smid;
2716 memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
2717 if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
2718 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
2719 ioc->ioc_link_reset_in_progress = 1;
2720 mpt2sas_base_put_smid_default(ioc, smid);
2721 init_completion(&ioc->base_cmds.done);
2722 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
2723 msecs_to_jiffies(10000));
2724 if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
2725 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
2726 ioc->ioc_link_reset_in_progress)
2727 ioc->ioc_link_reset_in_progress = 0;
2728 if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
2729 printk(MPT2SAS_ERR_FMT "%s: timeout\n",
2730 ioc->name, __func__);
2731 _debug_dump_mf(mpi_request,
2732 sizeof(Mpi2SasIoUnitControlRequest_t)/4);
2733 if (!(ioc->base_cmds.status & MPT2_CMD_RESET))
2734 issue_reset = 1;
2735 goto issue_host_reset;
2736 }
2737 if (ioc->base_cmds.status & MPT2_CMD_REPLY_VALID)
2738 memcpy(mpi_reply, ioc->base_cmds.reply,
2739 sizeof(Mpi2SasIoUnitControlReply_t));
2740 else
2741 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
2742 ioc->base_cmds.status = MPT2_CMD_NOT_USED;
2743 goto out;
2744
2745 issue_host_reset:
2746 if (issue_reset)
2747 mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
2748 FORCE_BIG_HAMMER);
2749 ioc->base_cmds.status = MPT2_CMD_NOT_USED;
2750 rc = -EFAULT;
2751 out:
2752 mutex_unlock(&ioc->base_cmds.mutex);
2753 return rc;
2754}
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768int
2769mpt2sas_base_scsi_enclosure_processor(struct MPT2SAS_ADAPTER *ioc,
2770 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
2771{
2772 u16 smid;
2773 u32 ioc_state;
2774 unsigned long timeleft;
2775 u8 issue_reset;
2776 int rc;
2777 void *request;
2778 u16 wait_state_count;
2779
2780 dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
2781 __func__));
2782
2783 mutex_lock(&ioc->base_cmds.mutex);
2784
2785 if (ioc->base_cmds.status != MPT2_CMD_NOT_USED) {
2786 printk(MPT2SAS_ERR_FMT "%s: base_cmd in use\n",
2787 ioc->name, __func__);
2788 rc = -EAGAIN;
2789 goto out;
2790 }
2791
2792 wait_state_count = 0;
2793 ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
2794 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
2795 if (wait_state_count++ == 10) {
2796 printk(MPT2SAS_ERR_FMT
2797 "%s: failed due to ioc not operational\n",
2798 ioc->name, __func__);
2799 rc = -EFAULT;
2800 goto out;
2801 }
2802 ssleep(1);
2803 ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
2804 printk(MPT2SAS_INFO_FMT "%s: waiting for "
2805 "operational state(count=%d)\n", ioc->name,
2806 __func__, wait_state_count);
2807 }
2808
2809 smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
2810 if (!smid) {
2811 printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
2812 ioc->name, __func__);
2813 rc = -EAGAIN;
2814 goto out;
2815 }
2816
2817 rc = 0;
2818 ioc->base_cmds.status = MPT2_CMD_PENDING;
2819 request = mpt2sas_base_get_msg_frame(ioc, smid);
2820 ioc->base_cmds.smid = smid;
2821 memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
2822 mpt2sas_base_put_smid_default(ioc, smid);
2823 init_completion(&ioc->base_cmds.done);
2824 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
2825 msecs_to_jiffies(10000));
2826 if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
2827 printk(MPT2SAS_ERR_FMT "%s: timeout\n",
2828 ioc->name, __func__);
2829 _debug_dump_mf(mpi_request,
2830 sizeof(Mpi2SepRequest_t)/4);
2831 if (!(ioc->base_cmds.status & MPT2_CMD_RESET))
2832 issue_reset = 1;
2833 goto issue_host_reset;
2834 }
2835 if (ioc->base_cmds.status & MPT2_CMD_REPLY_VALID)
2836 memcpy(mpi_reply, ioc->base_cmds.reply,
2837 sizeof(Mpi2SepReply_t));
2838 else
2839 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
2840 ioc->base_cmds.status = MPT2_CMD_NOT_USED;
2841 goto out;
2842
2843 issue_host_reset:
2844 if (issue_reset)
2845 mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
2846 FORCE_BIG_HAMMER);
2847 ioc->base_cmds.status = MPT2_CMD_NOT_USED;
2848 rc = -EFAULT;
2849 out:
2850 mutex_unlock(&ioc->base_cmds.mutex);
2851 return rc;
2852}
2853
2854
2855
2856
2857
2858
2859
2860
2861static int
2862_base_get_port_facts(struct MPT2SAS_ADAPTER *ioc, int port, int sleep_flag)
2863{
2864 Mpi2PortFactsRequest_t mpi_request;
2865 Mpi2PortFactsReply_t mpi_reply, *pfacts;
2866 int mpi_reply_sz, mpi_request_sz, r;
2867
2868 dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
2869 __func__));
2870
2871 mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
2872 mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
2873 memset(&mpi_request, 0, mpi_request_sz);
2874 mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
2875 mpi_request.PortNumber = port;
2876 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
2877 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
2878
2879 if (r != 0) {
2880 printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
2881 ioc->name, __func__, r);
2882 return r;
2883 }
2884
2885 pfacts = &ioc->pfacts[port];
2886 memset(pfacts, 0, sizeof(Mpi2PortFactsReply_t));
2887 pfacts->PortNumber = mpi_reply.PortNumber;
2888 pfacts->VP_ID = mpi_reply.VP_ID;
2889 pfacts->VF_ID = mpi_reply.VF_ID;
2890 pfacts->MaxPostedCmdBuffers =
2891 le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
2892
2893 return 0;
2894}
2895
2896
2897
2898
2899
2900
2901
2902
2903static int
2904_base_get_ioc_facts(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
2905{
2906 Mpi2IOCFactsRequest_t mpi_request;
2907 Mpi2IOCFactsReply_t mpi_reply, *facts;
2908 int mpi_reply_sz, mpi_request_sz, r;
2909
2910 dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
2911 __func__));
2912
2913 mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
2914 mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
2915 memset(&mpi_request, 0, mpi_request_sz);
2916 mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
2917 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
2918 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
2919
2920 if (r != 0) {
2921 printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
2922 ioc->name, __func__, r);
2923 return r;
2924 }
2925
2926 facts = &ioc->facts;
2927 memset(facts, 0, sizeof(Mpi2IOCFactsReply_t));
2928 facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
2929 facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
2930 facts->VP_ID = mpi_reply.VP_ID;
2931 facts->VF_ID = mpi_reply.VF_ID;
2932 facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
2933 facts->MaxChainDepth = mpi_reply.MaxChainDepth;
2934 facts->WhoInit = mpi_reply.WhoInit;
2935 facts->NumberOfPorts = mpi_reply.NumberOfPorts;
2936 facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
2937 facts->MaxReplyDescriptorPostQueueDepth =
2938 le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
2939 facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
2940 facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
2941 if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
2942 ioc->ir_firmware = 1;
2943 facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
2944 facts->IOCRequestFrameSize =
2945 le16_to_cpu(mpi_reply.IOCRequestFrameSize);
2946 facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
2947 facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
2948 ioc->shost->max_id = -1;
2949 facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
2950 facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
2951 facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
2952 facts->HighPriorityCredit =
2953 le16_to_cpu(mpi_reply.HighPriorityCredit);
2954 facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
2955 facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
2956
2957 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "hba queue depth(%d), "
2958 "max chains per io(%d)\n", ioc->name, facts->RequestCredit,
2959 facts->MaxChainDepth));
2960 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request frame size(%d), "
2961 "reply frame size(%d)\n", ioc->name,
2962 facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
2963 return 0;
2964}
2965
2966
2967
2968
2969
2970
2971
2972
2973static int
2974_base_send_ioc_init(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
2975{
2976 Mpi2IOCInitRequest_t mpi_request;
2977 Mpi2IOCInitReply_t mpi_reply;
2978 int r;
2979 struct timeval current_time;
2980 u16 ioc_status;
2981
2982 dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
2983 __func__));
2984
2985 memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
2986 mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
2987 mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
2988 mpi_request.VF_ID = 0;
2989 mpi_request.VP_ID = 0;
2990 mpi_request.MsgVersion = cpu_to_le16(MPI2_VERSION);
2991 mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
2992
2993
2994
2995
2996
2997
2998 if ((ioc->facts.HeaderVersion >> 8) < 0xA) {
2999 mpi_request.Reserved7 = cpu_to_le16(ioc->reply_sz);
3000
3001
3002
3003 }
3004
3005 mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
3006 mpi_request.ReplyDescriptorPostQueueDepth =
3007 cpu_to_le16(ioc->reply_post_queue_depth);
3008 mpi_request.ReplyFreeQueueDepth =
3009 cpu_to_le16(ioc->reply_free_queue_depth);
3010
3011#if BITS_PER_LONG > 32
3012 mpi_request.SenseBufferAddressHigh =
3013 cpu_to_le32(ioc->sense_dma >> 32);
3014 mpi_request.SystemReplyAddressHigh =
3015 cpu_to_le32(ioc->reply_dma >> 32);
3016 mpi_request.SystemRequestFrameBaseAddress =
3017 cpu_to_le64(ioc->request_dma);
3018 mpi_request.ReplyFreeQueueAddress =
3019 cpu_to_le64(ioc->reply_free_dma);
3020 mpi_request.ReplyDescriptorPostQueueAddress =
3021 cpu_to_le64(ioc->reply_post_free_dma);
3022#else
3023 mpi_request.SystemRequestFrameBaseAddress =
3024 cpu_to_le32(ioc->request_dma);
3025 mpi_request.ReplyFreeQueueAddress =
3026 cpu_to_le32(ioc->reply_free_dma);
3027 mpi_request.ReplyDescriptorPostQueueAddress =
3028 cpu_to_le32(ioc->reply_post_free_dma);
3029#endif
3030
3031
3032
3033
3034 do_gettimeofday(¤t_time);
3035 mpi_request.TimeStamp = cpu_to_le64((u64)current_time.tv_sec * 1000 +
3036 (current_time.tv_usec / 1000));
3037
3038 if (ioc->logging_level & MPT_DEBUG_INIT) {
3039 u32 *mfp;
3040 int i;
3041
3042 mfp = (u32 *)&mpi_request;
3043 printk(KERN_DEBUG "\toffset:data\n");
3044 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
3045 printk(KERN_DEBUG "\t[0x%02x]:%08x\n", i*4,
3046 le32_to_cpu(mfp[i]));
3047 }
3048
3049 r = _base_handshake_req_reply_wait(ioc,
3050 sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
3051 sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10,
3052 sleep_flag);
3053
3054 if (r != 0) {
3055 printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
3056 ioc->name, __func__, r);
3057 return r;
3058 }
3059
3060 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
3061 if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
3062 mpi_reply.IOCLogInfo) {
3063 printk(MPT2SAS_ERR_FMT "%s: failed\n", ioc->name, __func__);
3064 r = -EIO;
3065 }
3066
3067 return 0;
3068}
3069
3070
3071
3072
3073
3074
3075
3076
3077static int
3078_base_send_port_enable(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
3079{
3080 Mpi2PortEnableRequest_t *mpi_request;
3081 u32 ioc_state;
3082 unsigned long timeleft;
3083 int r = 0;
3084 u16 smid;
3085
3086 printk(MPT2SAS_INFO_FMT "sending port enable !!\n", ioc->name);
3087
3088 if (ioc->base_cmds.status & MPT2_CMD_PENDING) {
3089 printk(MPT2SAS_ERR_FMT "%s: internal command already in use\n",
3090 ioc->name, __func__);
3091 return -EAGAIN;
3092 }
3093
3094 smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
3095 if (!smid) {
3096 printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
3097 ioc->name, __func__);
3098 return -EAGAIN;
3099 }
3100
3101 ioc->base_cmds.status = MPT2_CMD_PENDING;
3102 mpi_request = mpt2sas_base_get_msg_frame(ioc, smid);
3103 ioc->base_cmds.smid = smid;
3104 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
3105 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
3106 mpi_request->VF_ID = 0;
3107 mpi_request->VP_ID = 0;
3108
3109 mpt2sas_base_put_smid_default(ioc, smid);
3110 init_completion(&ioc->base_cmds.done);
3111 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
3112 300*HZ);
3113 if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
3114 printk(MPT2SAS_ERR_FMT "%s: timeout\n",
3115 ioc->name, __func__);
3116 _debug_dump_mf(mpi_request,
3117 sizeof(Mpi2PortEnableRequest_t)/4);
3118 if (ioc->base_cmds.status & MPT2_CMD_RESET)
3119 r = -EFAULT;
3120 else
3121 r = -ETIME;
3122 goto out;
3123 } else
3124 dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: complete\n",
3125 ioc->name, __func__));
3126
3127 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_OPERATIONAL,
3128 60, sleep_flag);
3129 if (ioc_state) {
3130 printk(MPT2SAS_ERR_FMT "%s: failed going to operational state "
3131 " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state);
3132 r = -EFAULT;
3133 }
3134 out:
3135 ioc->base_cmds.status = MPT2_CMD_NOT_USED;
3136 printk(MPT2SAS_INFO_FMT "port enable: %s\n",
3137 ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
3138 return r;
3139}
3140
3141
3142
3143
3144
3145
3146
3147
3148static void
3149_base_unmask_events(struct MPT2SAS_ADAPTER *ioc, u16 event)
3150{
3151 u32 desired_event;
3152
3153 if (event >= 128)
3154 return;
3155
3156 desired_event = (1 << (event % 32));
3157
3158 if (event < 32)
3159 ioc->event_masks[0] &= ~desired_event;
3160 else if (event < 64)
3161 ioc->event_masks[1] &= ~desired_event;
3162 else if (event < 96)
3163 ioc->event_masks[2] &= ~desired_event;
3164 else if (event < 128)
3165 ioc->event_masks[3] &= ~desired_event;
3166}
3167
3168
3169
3170
3171
3172
3173
3174
3175static int
3176_base_event_notification(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
3177{
3178 Mpi2EventNotificationRequest_t *mpi_request;
3179 unsigned long timeleft;
3180 u16 smid;
3181 int r = 0;
3182 int i;
3183
3184 dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
3185 __func__));
3186
3187 if (ioc->base_cmds.status & MPT2_CMD_PENDING) {
3188 printk(MPT2SAS_ERR_FMT "%s: internal command already in use\n",
3189 ioc->name, __func__);
3190 return -EAGAIN;
3191 }
3192
3193 smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
3194 if (!smid) {
3195 printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
3196 ioc->name, __func__);
3197 return -EAGAIN;
3198 }
3199 ioc->base_cmds.status = MPT2_CMD_PENDING;
3200 mpi_request = mpt2sas_base_get_msg_frame(ioc, smid);
3201 ioc->base_cmds.smid = smid;
3202 memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
3203 mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
3204 mpi_request->VF_ID = 0;
3205 mpi_request->VP_ID = 0;
3206 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3207 mpi_request->EventMasks[i] =
3208 cpu_to_le32(ioc->event_masks[i]);
3209 mpt2sas_base_put_smid_default(ioc, smid);
3210 init_completion(&ioc->base_cmds.done);
3211 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
3212 if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
3213 printk(MPT2SAS_ERR_FMT "%s: timeout\n",
3214 ioc->name, __func__);
3215 _debug_dump_mf(mpi_request,
3216 sizeof(Mpi2EventNotificationRequest_t)/4);
3217 if (ioc->base_cmds.status & MPT2_CMD_RESET)
3218 r = -EFAULT;
3219 else
3220 r = -ETIME;
3221 } else
3222 dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: complete\n",
3223 ioc->name, __func__));
3224 ioc->base_cmds.status = MPT2_CMD_NOT_USED;
3225 return r;
3226}
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236void
3237mpt2sas_base_validate_event_type(struct MPT2SAS_ADAPTER *ioc, u32 *event_type)
3238{
3239 int i, j;
3240 u32 event_mask, desired_event;
3241 u8 send_update_to_fw;
3242
3243 for (i = 0, send_update_to_fw = 0; i <
3244 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
3245 event_mask = ~event_type[i];
3246 desired_event = 1;
3247 for (j = 0; j < 32; j++) {
3248 if (!(event_mask & desired_event) &&
3249 (ioc->event_masks[i] & desired_event)) {
3250 ioc->event_masks[i] &= ~desired_event;
3251 send_update_to_fw = 1;
3252 }
3253 desired_event = (desired_event << 1);
3254 }
3255 }
3256
3257 if (!send_update_to_fw)
3258 return;
3259
3260 mutex_lock(&ioc->base_cmds.mutex);
3261 _base_event_notification(ioc, CAN_SLEEP);
3262 mutex_unlock(&ioc->base_cmds.mutex);
3263}
3264
3265
3266
3267
3268
3269
3270
3271
3272static int
3273_base_diag_reset(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
3274{
3275 u32 host_diagnostic;
3276 u32 ioc_state;
3277 u32 count;
3278 u32 hcb_size;
3279
3280 printk(MPT2SAS_INFO_FMT "sending diag reset !!\n", ioc->name);
3281
3282 _base_save_msix_table(ioc);
3283
3284 drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "clear interrupts\n",
3285 ioc->name));
3286
3287 count = 0;
3288 do {
3289
3290
3291
3292 drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "write magic "
3293 "sequence\n", ioc->name));
3294 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
3295 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
3296 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
3297 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
3298 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
3299 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
3300 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
3301
3302
3303 if (sleep_flag == CAN_SLEEP)
3304 msleep(100);
3305 else
3306 mdelay(100);
3307
3308 if (count++ > 20)
3309 goto out;
3310
3311 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
3312 drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "wrote magic "
3313 "sequence: count(%d), host_diagnostic(0x%08x)\n",
3314 ioc->name, count, host_diagnostic));
3315
3316 } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
3317
3318 hcb_size = readl(&ioc->chip->HCBSize);
3319
3320 drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "diag reset: issued\n",
3321 ioc->name));
3322 writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
3323 &ioc->chip->HostDiagnostic);
3324
3325
3326 msleep(50);
3327
3328
3329 for (count = 0; count < 3000000 ; count++) {
3330
3331 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
3332
3333 if (host_diagnostic == 0xFFFFFFFF)
3334 goto out;
3335 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
3336 break;
3337
3338
3339 if (sleep_flag == CAN_SLEEP)
3340 msleep(1);
3341 else
3342 mdelay(1);
3343 }
3344
3345 if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
3346
3347 drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "restart the adapter "
3348 "assuming the HCB Address points to good F/W\n",
3349 ioc->name));
3350 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
3351 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
3352 writel(host_diagnostic, &ioc->chip->HostDiagnostic);
3353
3354 drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT
3355 "re-enable the HCDW\n", ioc->name));
3356 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
3357 &ioc->chip->HCBSize);
3358 }
3359
3360 drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "restart the adapter\n",
3361 ioc->name));
3362 writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
3363 &ioc->chip->HostDiagnostic);
3364
3365 drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "disable writes to the "
3366 "diagnostic register\n", ioc->name));
3367 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
3368
3369 drsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "Wait for FW to go to the "
3370 "READY state\n", ioc->name));
3371 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20,
3372 sleep_flag);
3373 if (ioc_state) {
3374 printk(MPT2SAS_ERR_FMT "%s: failed going to ready state "
3375 " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state);
3376 goto out;
3377 }
3378
3379 _base_restore_msix_table(ioc);
3380 printk(MPT2SAS_INFO_FMT "diag reset: SUCCESS\n", ioc->name);
3381 return 0;
3382
3383 out:
3384 printk(MPT2SAS_ERR_FMT "diag reset: FAILED\n", ioc->name);
3385 return -EFAULT;
3386}
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396static int
3397_base_make_ioc_ready(struct MPT2SAS_ADAPTER *ioc, int sleep_flag,
3398 enum reset_type type)
3399{
3400 u32 ioc_state;
3401
3402 dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
3403 __func__));
3404
3405 ioc_state = mpt2sas_base_get_iocstate(ioc, 0);
3406 dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: ioc_state(0x%08x)\n",
3407 ioc->name, __func__, ioc_state));
3408
3409 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
3410 return 0;
3411
3412 if (ioc_state & MPI2_DOORBELL_USED) {
3413 dhsprintk(ioc, printk(MPT2SAS_DEBUG_FMT "unexpected doorbell "
3414 "active!\n", ioc->name));
3415 goto issue_diag_reset;
3416 }
3417
3418 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
3419 mpt2sas_base_fault_info(ioc, ioc_state &
3420 MPI2_DOORBELL_DATA_MASK);
3421 goto issue_diag_reset;
3422 }
3423
3424 if (type == FORCE_BIG_HAMMER)
3425 goto issue_diag_reset;
3426
3427 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
3428 if (!(_base_send_ioc_reset(ioc,
3429 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15, CAN_SLEEP)))
3430 return 0;
3431
3432 issue_diag_reset:
3433 return _base_diag_reset(ioc, CAN_SLEEP);
3434}
3435
3436
3437
3438
3439
3440
3441
3442
3443static int
3444_base_make_ioc_operational(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
3445{
3446 int r, i;
3447 unsigned long flags;
3448 u32 reply_address;
3449 u16 smid;
3450 struct _tr_list *delayed_tr, *delayed_tr_next;
3451
3452 dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
3453 __func__));
3454
3455
3456 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
3457 &ioc->delayed_tr_list, list) {
3458 list_del(&delayed_tr->list);
3459 kfree(delayed_tr);
3460 }
3461
3462
3463 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
3464 INIT_LIST_HEAD(&ioc->free_list);
3465 smid = 1;
3466 for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
3467 ioc->scsi_lookup[i].cb_idx = 0xFF;
3468 ioc->scsi_lookup[i].smid = smid;
3469 ioc->scsi_lookup[i].scmd = NULL;
3470 list_add_tail(&ioc->scsi_lookup[i].tracker_list,
3471 &ioc->free_list);
3472 }
3473
3474
3475 INIT_LIST_HEAD(&ioc->hpr_free_list);
3476 smid = ioc->hi_priority_smid;
3477 for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
3478 ioc->hpr_lookup[i].cb_idx = 0xFF;
3479 ioc->hpr_lookup[i].smid = smid;
3480 list_add_tail(&ioc->hpr_lookup[i].tracker_list,
3481 &ioc->hpr_free_list);
3482 }
3483
3484
3485 INIT_LIST_HEAD(&ioc->internal_free_list);
3486 smid = ioc->internal_smid;
3487 for (i = 0; i < ioc->internal_depth; i++, smid++) {
3488 ioc->internal_lookup[i].cb_idx = 0xFF;
3489 ioc->internal_lookup[i].smid = smid;
3490 list_add_tail(&ioc->internal_lookup[i].tracker_list,
3491 &ioc->internal_free_list);
3492 }
3493 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3494
3495
3496 for (i = 0, reply_address = (u32)ioc->reply_dma ;
3497 i < ioc->reply_free_queue_depth ; i++, reply_address +=
3498 ioc->reply_sz)
3499 ioc->reply_free[i] = cpu_to_le32(reply_address);
3500
3501
3502 for (i = 0; i < ioc->reply_post_queue_depth; i++)
3503 ioc->reply_post_free[i].Words = ULLONG_MAX;
3504
3505 r = _base_send_ioc_init(ioc, sleep_flag);
3506 if (r)
3507 return r;
3508
3509
3510 ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
3511 ioc->reply_post_host_index = 0;
3512 writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
3513 writel(0, &ioc->chip->ReplyPostHostIndex);
3514
3515 _base_unmask_interrupts(ioc);
3516 r = _base_event_notification(ioc, sleep_flag);
3517 if (r)
3518 return r;
3519
3520 if (sleep_flag == CAN_SLEEP)
3521 _base_static_config_pages(ioc);
3522
3523 r = _base_send_port_enable(ioc, sleep_flag);
3524 if (r)
3525 return r;
3526
3527 return r;
3528}
3529
3530
3531
3532
3533
3534
3535
3536void
3537mpt2sas_base_free_resources(struct MPT2SAS_ADAPTER *ioc)
3538{
3539 struct pci_dev *pdev = ioc->pdev;
3540
3541 dexitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
3542 __func__));
3543
3544 _base_mask_interrupts(ioc);
3545 ioc->shost_recovery = 1;
3546 _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
3547 ioc->shost_recovery = 0;
3548 if (ioc->pci_irq) {
3549 synchronize_irq(pdev->irq);
3550 free_irq(ioc->pci_irq, ioc);
3551 }
3552 _base_disable_msix(ioc);
3553 if (ioc->chip_phys)
3554 iounmap(ioc->chip);
3555 ioc->pci_irq = -1;
3556 ioc->chip_phys = 0;
3557 pci_release_selected_regions(ioc->pdev, ioc->bars);
3558 pci_disable_pcie_error_reporting(pdev);
3559 pci_disable_device(pdev);
3560 return;
3561}
3562
3563
3564
3565
3566
3567
3568
3569int
3570mpt2sas_base_attach(struct MPT2SAS_ADAPTER *ioc)
3571{
3572 int r, i;
3573
3574 dinitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
3575 __func__));
3576
3577 r = mpt2sas_base_map_resources(ioc);
3578 if (r)
3579 return r;
3580
3581 pci_set_drvdata(ioc->pdev, ioc->shost);
3582 r = _base_get_ioc_facts(ioc, CAN_SLEEP);
3583 if (r)
3584 goto out_free_resources;
3585
3586 r = _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
3587 if (r)
3588 goto out_free_resources;
3589
3590 ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
3591 sizeof(Mpi2PortFactsReply_t), GFP_KERNEL);
3592 if (!ioc->pfacts) {
3593 r = -ENOMEM;
3594 goto out_free_resources;
3595 }
3596
3597 for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
3598 r = _base_get_port_facts(ioc, i, CAN_SLEEP);
3599 if (r)
3600 goto out_free_resources;
3601 }
3602
3603 r = _base_allocate_memory_pools(ioc, CAN_SLEEP);
3604 if (r)
3605 goto out_free_resources;
3606
3607 init_waitqueue_head(&ioc->reset_wq);
3608
3609 ioc->fwfault_debug = mpt2sas_fwfault_debug;
3610
3611
3612 mutex_init(&ioc->base_cmds.mutex);
3613 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
3614 ioc->base_cmds.status = MPT2_CMD_NOT_USED;
3615
3616
3617 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
3618 ioc->transport_cmds.status = MPT2_CMD_NOT_USED;
3619 mutex_init(&ioc->transport_cmds.mutex);
3620
3621
3622 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
3623 ioc->scsih_cmds.status = MPT2_CMD_NOT_USED;
3624 mutex_init(&ioc->scsih_cmds.mutex);
3625
3626
3627 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
3628 ioc->tm_cmds.status = MPT2_CMD_NOT_USED;
3629 mutex_init(&ioc->tm_cmds.mutex);
3630
3631
3632 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
3633 ioc->config_cmds.status = MPT2_CMD_NOT_USED;
3634 mutex_init(&ioc->config_cmds.mutex);
3635
3636
3637 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
3638 ioc->ctl_cmds.status = MPT2_CMD_NOT_USED;
3639 mutex_init(&ioc->ctl_cmds.mutex);
3640
3641 if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
3642 !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
3643 !ioc->config_cmds.reply || !ioc->ctl_cmds.reply) {
3644 r = -ENOMEM;
3645 goto out_free_resources;
3646 }
3647
3648 init_completion(&ioc->shost_recovery_done);
3649
3650 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3651 ioc->event_masks[i] = -1;
3652
3653
3654 _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
3655 _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
3656 _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
3657 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
3658 _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
3659 _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
3660 _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
3661 _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
3662 _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
3663 _base_unmask_events(ioc, MPI2_EVENT_TASK_SET_FULL);
3664 _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
3665 r = _base_make_ioc_operational(ioc, CAN_SLEEP);
3666 if (r)
3667 goto out_free_resources;
3668
3669 mpt2sas_base_start_watchdog(ioc);
3670 if (diag_buffer_enable != 0)
3671 mpt2sas_enable_diag_buffer(ioc, diag_buffer_enable);
3672 return 0;
3673
3674 out_free_resources:
3675
3676 ioc->remove_host = 1;
3677 mpt2sas_base_free_resources(ioc);
3678 _base_release_memory_pools(ioc);
3679 pci_set_drvdata(ioc->pdev, NULL);
3680 kfree(ioc->tm_cmds.reply);
3681 kfree(ioc->transport_cmds.reply);
3682 kfree(ioc->scsih_cmds.reply);
3683 kfree(ioc->config_cmds.reply);
3684 kfree(ioc->base_cmds.reply);
3685 kfree(ioc->ctl_cmds.reply);
3686 kfree(ioc->pfacts);
3687 ioc->ctl_cmds.reply = NULL;
3688 ioc->base_cmds.reply = NULL;
3689 ioc->tm_cmds.reply = NULL;
3690 ioc->scsih_cmds.reply = NULL;
3691 ioc->transport_cmds.reply = NULL;
3692 ioc->config_cmds.reply = NULL;
3693 ioc->pfacts = NULL;
3694 return r;
3695}
3696
3697
3698
3699
3700
3701
3702
3703
3704void
3705mpt2sas_base_detach(struct MPT2SAS_ADAPTER *ioc)
3706{
3707
3708 dexitprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s\n", ioc->name,
3709 __func__));
3710
3711 mpt2sas_base_stop_watchdog(ioc);
3712 mpt2sas_base_free_resources(ioc);
3713 _base_release_memory_pools(ioc);
3714 pci_set_drvdata(ioc->pdev, NULL);
3715 kfree(ioc->pfacts);
3716 kfree(ioc->ctl_cmds.reply);
3717 kfree(ioc->base_cmds.reply);
3718 kfree(ioc->tm_cmds.reply);
3719 kfree(ioc->transport_cmds.reply);
3720 kfree(ioc->scsih_cmds.reply);
3721 kfree(ioc->config_cmds.reply);
3722}
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736static void
3737_base_reset_handler(struct MPT2SAS_ADAPTER *ioc, int reset_phase)
3738{
3739 switch (reset_phase) {
3740 case MPT2_IOC_PRE_RESET:
3741 dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
3742 "MPT2_IOC_PRE_RESET\n", ioc->name, __func__));
3743 break;
3744 case MPT2_IOC_AFTER_RESET:
3745 dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
3746 "MPT2_IOC_AFTER_RESET\n", ioc->name, __func__));
3747 if (ioc->transport_cmds.status & MPT2_CMD_PENDING) {
3748 ioc->transport_cmds.status |= MPT2_CMD_RESET;
3749 mpt2sas_base_free_smid(ioc, ioc->transport_cmds.smid);
3750 complete(&ioc->transport_cmds.done);
3751 }
3752 if (ioc->base_cmds.status & MPT2_CMD_PENDING) {
3753 ioc->base_cmds.status |= MPT2_CMD_RESET;
3754 mpt2sas_base_free_smid(ioc, ioc->base_cmds.smid);
3755 complete(&ioc->base_cmds.done);
3756 }
3757 if (ioc->config_cmds.status & MPT2_CMD_PENDING) {
3758 ioc->config_cmds.status |= MPT2_CMD_RESET;
3759 mpt2sas_base_free_smid(ioc, ioc->config_cmds.smid);
3760 ioc->config_cmds.smid = USHRT_MAX;
3761 complete(&ioc->config_cmds.done);
3762 }
3763 break;
3764 case MPT2_IOC_DONE_RESET:
3765 dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: "
3766 "MPT2_IOC_DONE_RESET\n", ioc->name, __func__));
3767 break;
3768 }
3769 mpt2sas_scsih_reset_handler(ioc, reset_phase);
3770 mpt2sas_ctl_reset_handler(ioc, reset_phase);
3771}
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781static void
3782_wait_for_commands_to_complete(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
3783{
3784 u32 ioc_state;
3785 unsigned long flags;
3786 u16 i;
3787
3788 ioc->pending_io_count = 0;
3789 if (sleep_flag != CAN_SLEEP)
3790 return;
3791
3792 ioc_state = mpt2sas_base_get_iocstate(ioc, 0);
3793 if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
3794 return;
3795
3796
3797 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
3798 for (i = 0; i < ioc->scsiio_depth; i++)
3799 if (ioc->scsi_lookup[i].cb_idx != 0xFF)
3800 ioc->pending_io_count++;
3801 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3802
3803 if (!ioc->pending_io_count)
3804 return;
3805
3806
3807 wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 3 * HZ);
3808}
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818int
3819mpt2sas_base_hard_reset_handler(struct MPT2SAS_ADAPTER *ioc, int sleep_flag,
3820 enum reset_type type)
3821{
3822 int r;
3823 unsigned long flags;
3824
3825 dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: enter\n", ioc->name,
3826 __func__));
3827
3828 if (mpt2sas_fwfault_debug)
3829 mpt2sas_halt_firmware(ioc);
3830
3831 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
3832 if (ioc->shost_recovery) {
3833 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
3834 printk(MPT2SAS_ERR_FMT "%s: busy\n",
3835 ioc->name, __func__);
3836 return -EBUSY;
3837 }
3838 ioc->shost_recovery = 1;
3839 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
3840
3841 _base_reset_handler(ioc, MPT2_IOC_PRE_RESET);
3842 _wait_for_commands_to_complete(ioc, sleep_flag);
3843 _base_mask_interrupts(ioc);
3844 r = _base_make_ioc_ready(ioc, sleep_flag, type);
3845 if (r)
3846 goto out;
3847 _base_reset_handler(ioc, MPT2_IOC_AFTER_RESET);
3848 r = _base_make_ioc_operational(ioc, sleep_flag);
3849 if (!r)
3850 _base_reset_handler(ioc, MPT2_IOC_DONE_RESET);
3851 out:
3852 dtmprintk(ioc, printk(MPT2SAS_DEBUG_FMT "%s: %s\n",
3853 ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
3854
3855 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
3856 ioc->shost_recovery = 0;
3857 complete(&ioc->shost_recovery_done);
3858 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
3859
3860 return r;
3861}
3862