1/* 2 * Header for MultiMediaCard (MMC) 3 * 4 * Copyright 2002 Hewlett-Packard Company 5 * 6 * Use consistent with the GNU GPL is permitted, 7 * provided that this copyright notice is 8 * preserved in its entirety in all copies and derived works. 9 * 10 * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, 11 * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS 12 * FITNESS FOR ANY PARTICULAR PURPOSE. 13 * 14 * Many thanks to Alessandro Rubini and Jonathan Corbet! 15 * 16 * Based strongly on code by: 17 * 18 * Author: Yong-iL Joh <tolkien@mizi.com> 19 * 20 * Author: Andrew Christian 21 * 15 May 2002 22 */ 23 24#ifndef MMC_MMC_H 25#define MMC_MMC_H 26 27/* Standard MMC commands (4.1) type argument response */ 28 /* class 1 */ 29#define MMC_GO_IDLE_STATE 0 /* bc */ 30#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */ 31#define MMC_ALL_SEND_CID 2 /* bcr R2 */ 32#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */ 33#define MMC_SET_DSR 4 /* bc [31:16] RCA */ 34#define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */ 35#define MMC_SWITCH 6 /* ac [31:0] See below R1b */ 36#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */ 37#define MMC_SEND_EXT_CSD 8 /* adtc R1 */ 38#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */ 39#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */ 40#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */ 41#define MMC_STOP_TRANSMISSION 12 /* ac R1b */ 42#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */ 43#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */ 44#define MMC_SPI_READ_OCR 58 /* spi spi_R3 */ 45#define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */ 46 47 /* class 2 */ 48#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */ 49#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ 50#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ 51 52 /* class 3 */ 53#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ 54 55 /* class 4 */ 56#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */ 57#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */ 58#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */ 59#define MMC_PROGRAM_CID 26 /* adtc R1 */ 60#define MMC_PROGRAM_CSD 27 /* adtc R1 */ 61 62 /* class 6 */ 63#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */ 64#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */ 65#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */ 66 67 /* class 5 */ 68#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */ 69#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */ 70#define MMC_ERASE 38 /* ac R1b */ 71 72 /* class 9 */ 73#define MMC_FAST_IO 39 /* ac <Complex> R4 */ 74#define MMC_GO_IRQ_STATE 40 /* bcr R5 */ 75 76 /* class 7 */ 77#define MMC_LOCK_UNLOCK 42 /* adtc R1b */ 78 79 /* class 8 */ 80#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ 81#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */ 82 83/* 84 * MMC_SWITCH argument format: 85 * 86 * [31:26] Always 0 87 * [25:24] Access Mode 88 * [23:16] Location of target Byte in EXT_CSD 89 * [15:08] Value Byte 90 * [07:03] Always 0 91 * [02:00] Command Set 92 */ 93 94/* 95 MMC status in R1, for native mode (SPI bits are different) 96 Type 97 e : error bit 98 s : status bit 99 r : detected and set for the actual command response 100 x : detected and set during command execution. the host must poll 101 the card by sending status command in order to read these bits. 102 Clear condition 103 a : according to the card state 104 b : always related to the previous command. Reception of 105 a valid command will clear it (with a delay of one command) 106 c : clear by read 107 */ 108 109#define R1_OUT_OF_RANGE (1 << 31) /* er, c */ 110#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */ 111#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */ 112#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */ 113#define R1_ERASE_PARAM (1 << 27) /* ex, c */ 114#define R1_WP_VIOLATION (1 << 26) /* erx, c */ 115#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */ 116#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */ 117#define R1_COM_CRC_ERROR (1 << 23) /* er, b */ 118#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */ 119#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */ 120#define R1_CC_ERROR (1 << 20) /* erx, c */ 121#define R1_ERROR (1 << 19) /* erx, c */ 122#define R1_UNDERRUN (1 << 18) /* ex, c */ 123#define R1_OVERRUN (1 << 17) /* ex, c */ 124#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */ 125#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */ 126#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */ 127#define R1_ERASE_RESET (1 << 13) /* sr, c */ 128#define R1_STATUS(x) (x & 0xFFFFE000) 129#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */ 130#define R1_READY_FOR_DATA (1 << 8) /* sx, a */ 131#define R1_SWITCH_ERROR (1 << 7) /* sx, c */ 132#define R1_APP_CMD (1 << 5) /* sr, c */ 133 134/* 135 * MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS 136 * R1 is the low order byte; R2 is the next highest byte, when present. 137 */ 138#define R1_SPI_IDLE (1 << 0) 139#define R1_SPI_ERASE_RESET (1 << 1) 140#define R1_SPI_ILLEGAL_COMMAND (1 << 2) 141#define R1_SPI_COM_CRC (1 << 3) 142#define R1_SPI_ERASE_SEQ (1 << 4) 143#define R1_SPI_ADDRESS (1 << 5) 144#define R1_SPI_PARAMETER (1 << 6) 145/* R1 bit 7 is always zero */ 146#define R2_SPI_CARD_LOCKED (1 << 8) 147#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */ 148#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP 149#define R2_SPI_ERROR (1 << 10) 150#define R2_SPI_CC_ERROR (1 << 11) 151#define R2_SPI_CARD_ECC_ERROR (1 << 12) 152#define R2_SPI_WP_VIOLATION (1 << 13) 153#define R2_SPI_ERASE_PARAM (1 << 14) 154#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */ 155#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE 156 157/* These are unpacked versions of the actual responses */ 158 159struct _mmc_csd { 160 u8 csd_structure; 161 u8 spec_vers; 162 u8 taac; 163 u8 nsac; 164 u8 tran_speed; 165 u16 ccc; 166 u8 read_bl_len; 167 u8 read_bl_partial; 168 u8 write_blk_misalign; 169 u8 read_blk_misalign; 170 u8 dsr_imp; 171 u16 c_size; 172 u8 vdd_r_curr_min; 173 u8 vdd_r_curr_max; 174 u8 vdd_w_curr_min; 175 u8 vdd_w_curr_max; 176 u8 c_size_mult; 177 union { 178 struct { /* MMC system specification version 3.1 */ 179 u8 erase_grp_size; 180 u8 erase_grp_mult; 181 } v31; 182 struct { /* MMC system specification version 2.2 */ 183 u8 sector_size; 184 u8 erase_grp_size; 185 } v22; 186 } erase; 187 u8 wp_grp_size; 188 u8 wp_grp_enable; 189 u8 default_ecc; 190 u8 r2w_factor; 191 u8 write_bl_len; 192 u8 write_bl_partial; 193 u8 file_format_grp; 194 u8 copy; 195 u8 perm_write_protect; 196 u8 tmp_write_protect; 197 u8 file_format; 198 u8 ecc; 199}; 200 201/* 202 * OCR bits are mostly in host.h 203 */ 204#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */ 205 206/* 207 * Card Command Classes (CCC) 208 */ 209#define CCC_BASIC (1<<0) /* (0) Basic protocol functions */ 210 /* (CMD0,1,2,3,4,7,9,10,12,13,15) */ 211 /* (and for SPI, CMD58,59) */ 212#define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */ 213 /* (CMD11) */ 214#define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */ 215 /* (CMD16,17,18) */ 216#define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */ 217 /* (CMD20) */ 218#define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */ 219 /* (CMD16,24,25,26,27) */ 220#define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */ 221 /* (CMD32,33,34,35,36,37,38,39) */ 222#define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */ 223 /* (CMD28,29,30) */ 224#define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */ 225 /* (CMD16,CMD42) */ 226#define CCC_APP_SPEC (1<<8) /* (8) Application specific */ 227 /* (CMD55,56,57,ACMD*) */ 228#define CCC_IO_MODE (1<<9) /* (9) I/O mode */ 229 /* (CMD5,39,40,52,53) */ 230#define CCC_SWITCH (1<<10) /* (10) High speed switch */ 231 /* (CMD6,34,35,36,37,50) */ 232 /* (11) Reserved */ 233 /* (CMD?) */ 234 235/* 236 * CSD field definitions 237 */ 238 239#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */ 240#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */ 241#define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */ 242#define CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */ 243 244#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */ 245#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */ 246#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */ 247#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */ 248#define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */ 249 250/* 251 * EXT_CSD fields 252 */ 253 254#define EXT_CSD_BUS_WIDTH 183 /* R/W */ 255#define EXT_CSD_HS_TIMING 185 /* R/W */ 256#define EXT_CSD_CARD_TYPE 196 /* RO */ 257#define EXT_CSD_REV 192 /* RO */ 258#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ 259#define EXT_CSD_S_A_TIMEOUT 217 260 261/* 262 * EXT_CSD field definitions 263 */ 264 265#define EXT_CSD_CMD_SET_NORMAL (1<<0) 266#define EXT_CSD_CMD_SET_SECURE (1<<1) 267#define EXT_CSD_CMD_SET_CPSECURE (1<<2) 268 269#define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */ 270#define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */ 271#define EXT_CSD_CARD_TYPE_MASK 0x3 /* Mask out reserved and DDR bits */ 272 273#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ 274#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ 275#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ 276 277/* 278 * MMC_SWITCH access modes 279 */ 280 281#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ 282#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */ 283#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */ 284#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */ 285 286#endif /* MMC_MMC_PROTOCOL_H */ 287 288