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12static const char serial_name[] = "MN10300 Serial driver";
13static const char serial_version[] = "mn10300_serial-1.0";
14static const char serial_revdate[] = "2007-11-06";
15
16#if defined(CONFIG_MN10300_TTYSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
17#define SUPPORT_SYSRQ
18#endif
19
20#include <linux/module.h>
21#include <linux/serial.h>
22#include <linux/circ_buf.h>
23#include <linux/errno.h>
24#include <linux/signal.h>
25#include <linux/sched.h>
26#include <linux/timer.h>
27#include <linux/interrupt.h>
28#include <linux/tty.h>
29#include <linux/tty_flip.h>
30#include <linux/major.h>
31#include <linux/string.h>
32#include <linux/ioport.h>
33#include <linux/mm.h>
34#include <linux/slab.h>
35#include <linux/init.h>
36#include <linux/console.h>
37#include <linux/sysrq.h>
38
39#include <asm/system.h>
40#include <asm/io.h>
41#include <asm/irq.h>
42#include <asm/bitops.h>
43#include <asm/serial-regs.h>
44#include <unit/timex.h>
45#include "mn10300-serial.h"
46
47static inline __attribute__((format(printf, 1, 2)))
48void no_printk(const char *fmt, ...)
49{
50}
51
52#define kenter(FMT, ...) \
53 printk(KERN_DEBUG "-->%s(" FMT ")\n", __func__, ##__VA_ARGS__)
54#define _enter(FMT, ...) \
55 no_printk(KERN_DEBUG "-->%s(" FMT ")\n", __func__, ##__VA_ARGS__)
56#define kdebug(FMT, ...) \
57 printk(KERN_DEBUG "--- " FMT "\n", ##__VA_ARGS__)
58#define _debug(FMT, ...) \
59 no_printk(KERN_DEBUG "--- " FMT "\n", ##__VA_ARGS__)
60#define kproto(FMT, ...) \
61 printk(KERN_DEBUG "### MNSERIAL " FMT " ###\n", ##__VA_ARGS__)
62#define _proto(FMT, ...) \
63 no_printk(KERN_DEBUG "### MNSERIAL " FMT " ###\n", ##__VA_ARGS__)
64
65#define NR_UARTS 3
66
67#ifdef CONFIG_MN10300_TTYSM_CONSOLE
68static void mn10300_serial_console_write(struct console *co,
69 const char *s, unsigned count);
70static int __init mn10300_serial_console_setup(struct console *co,
71 char *options);
72
73static struct uart_driver mn10300_serial_driver;
74static struct console mn10300_serial_console = {
75 .name = "ttySM",
76 .write = mn10300_serial_console_write,
77 .device = uart_console_device,
78 .setup = mn10300_serial_console_setup,
79 .flags = CON_PRINTBUFFER,
80 .index = -1,
81 .data = &mn10300_serial_driver,
82};
83#endif
84
85static struct uart_driver mn10300_serial_driver = {
86 .owner = NULL,
87 .driver_name = "mn10300-serial",
88 .dev_name = "ttySM",
89 .major = TTY_MAJOR,
90 .minor = 128,
91 .nr = NR_UARTS,
92#ifdef CONFIG_MN10300_TTYSM_CONSOLE
93 .cons = &mn10300_serial_console,
94#endif
95};
96
97static unsigned int mn10300_serial_tx_empty(struct uart_port *);
98static void mn10300_serial_set_mctrl(struct uart_port *, unsigned int mctrl);
99static unsigned int mn10300_serial_get_mctrl(struct uart_port *);
100static void mn10300_serial_stop_tx(struct uart_port *);
101static void mn10300_serial_start_tx(struct uart_port *);
102static void mn10300_serial_send_xchar(struct uart_port *, char ch);
103static void mn10300_serial_stop_rx(struct uart_port *);
104static void mn10300_serial_enable_ms(struct uart_port *);
105static void mn10300_serial_break_ctl(struct uart_port *, int ctl);
106static int mn10300_serial_startup(struct uart_port *);
107static void mn10300_serial_shutdown(struct uart_port *);
108static void mn10300_serial_set_termios(struct uart_port *,
109 struct ktermios *new,
110 struct ktermios *old);
111static const char *mn10300_serial_type(struct uart_port *);
112static void mn10300_serial_release_port(struct uart_port *);
113static int mn10300_serial_request_port(struct uart_port *);
114static void mn10300_serial_config_port(struct uart_port *, int);
115static int mn10300_serial_verify_port(struct uart_port *,
116 struct serial_struct *);
117
118static const struct uart_ops mn10300_serial_ops = {
119 .tx_empty = mn10300_serial_tx_empty,
120 .set_mctrl = mn10300_serial_set_mctrl,
121 .get_mctrl = mn10300_serial_get_mctrl,
122 .stop_tx = mn10300_serial_stop_tx,
123 .start_tx = mn10300_serial_start_tx,
124 .send_xchar = mn10300_serial_send_xchar,
125 .stop_rx = mn10300_serial_stop_rx,
126 .enable_ms = mn10300_serial_enable_ms,
127 .break_ctl = mn10300_serial_break_ctl,
128 .startup = mn10300_serial_startup,
129 .shutdown = mn10300_serial_shutdown,
130 .set_termios = mn10300_serial_set_termios,
131 .type = mn10300_serial_type,
132 .release_port = mn10300_serial_release_port,
133 .request_port = mn10300_serial_request_port,
134 .config_port = mn10300_serial_config_port,
135 .verify_port = mn10300_serial_verify_port,
136};
137
138static irqreturn_t mn10300_serial_interrupt(int irq, void *dev_id);
139
140
141
142
143#ifdef CONFIG_MN10300_TTYSM0
144struct mn10300_serial_port mn10300_serial_port_sif0 = {
145 .uart.ops = &mn10300_serial_ops,
146 .uart.membase = (void __iomem *) &SC0CTR,
147 .uart.mapbase = (unsigned long) &SC0CTR,
148 .uart.iotype = UPIO_MEM,
149 .uart.irq = 0,
150 .uart.uartclk = 0,
151 .uart.fifosize = 1,
152 .uart.flags = UPF_BOOT_AUTOCONF,
153 .uart.line = 0,
154 .uart.type = PORT_MN10300,
155 .uart.lock =
156 __SPIN_LOCK_UNLOCKED(mn10300_serial_port_sif0.uart.lock),
157 .name = "ttySM0",
158 ._iobase = &SC0CTR,
159 ._control = &SC0CTR,
160 ._status = (volatile u8 *) &SC0STR,
161 ._intr = &SC0ICR,
162 ._rxb = &SC0RXB,
163 ._txb = &SC0TXB,
164 .rx_name = "ttySM0/Rx",
165 .tx_name = "ttySM0/Tx",
166#ifdef CONFIG_MN10300_TTYSM0_TIMER8
167 .tm_name = "ttySM0/Timer8",
168 ._tmxmd = &TM8MD,
169 ._tmxbr = &TM8BR,
170 ._tmicr = &TM8ICR,
171 .tm_irq = TM8IRQ,
172 .div_timer = MNSCx_DIV_TIMER_16BIT,
173#else
174 .tm_name = "ttySM0/Timer2",
175 ._tmxmd = &TM2MD,
176 ._tmxbr = (volatile u16 *) &TM2BR,
177 ._tmicr = &TM2ICR,
178 .tm_irq = TM2IRQ,
179 .div_timer = MNSCx_DIV_TIMER_8BIT,
180#endif
181 .rx_irq = SC0RXIRQ,
182 .tx_irq = SC0TXIRQ,
183 .rx_icr = &GxICR(SC0RXIRQ),
184 .tx_icr = &GxICR(SC0TXIRQ),
185 .clock_src = MNSCx_CLOCK_SRC_IOCLK,
186 .options = 0,
187#ifdef CONFIG_GDBSTUB_ON_TTYSM0
188 .gdbstub = 1,
189#endif
190};
191#endif
192
193
194
195
196#ifdef CONFIG_MN10300_TTYSM1
197struct mn10300_serial_port mn10300_serial_port_sif1 = {
198 .uart.ops = &mn10300_serial_ops,
199 .uart.membase = (void __iomem *) &SC1CTR,
200 .uart.mapbase = (unsigned long) &SC1CTR,
201 .uart.iotype = UPIO_MEM,
202 .uart.irq = 0,
203 .uart.uartclk = 0,
204 .uart.fifosize = 1,
205 .uart.flags = UPF_BOOT_AUTOCONF,
206 .uart.line = 1,
207 .uart.type = PORT_MN10300,
208 .uart.lock =
209 __SPIN_LOCK_UNLOCKED(mn10300_serial_port_sif1.uart.lock),
210 .name = "ttySM1",
211 ._iobase = &SC1CTR,
212 ._control = &SC1CTR,
213 ._status = (volatile u8 *) &SC1STR,
214 ._intr = &SC1ICR,
215 ._rxb = &SC1RXB,
216 ._txb = &SC1TXB,
217 .rx_name = "ttySM1/Rx",
218 .tx_name = "ttySM1/Tx",
219#ifdef CONFIG_MN10300_TTYSM1_TIMER9
220 .tm_name = "ttySM1/Timer9",
221 ._tmxmd = &TM9MD,
222 ._tmxbr = &TM9BR,
223 ._tmicr = &TM9ICR,
224 .tm_irq = TM9IRQ,
225 .div_timer = MNSCx_DIV_TIMER_16BIT,
226#else
227 .tm_name = "ttySM1/Timer3",
228 ._tmxmd = &TM3MD,
229 ._tmxbr = (volatile u16 *) &TM3BR,
230 ._tmicr = &TM3ICR,
231 .tm_irq = TM3IRQ,
232 .div_timer = MNSCx_DIV_TIMER_8BIT,
233#endif
234 .rx_irq = SC1RXIRQ,
235 .tx_irq = SC1TXIRQ,
236 .rx_icr = &GxICR(SC1RXIRQ),
237 .tx_icr = &GxICR(SC1TXIRQ),
238 .clock_src = MNSCx_CLOCK_SRC_IOCLK,
239 .options = 0,
240#ifdef CONFIG_GDBSTUB_ON_TTYSM1
241 .gdbstub = 1,
242#endif
243};
244#endif
245
246
247
248
249#ifdef CONFIG_MN10300_TTYSM2
250struct mn10300_serial_port mn10300_serial_port_sif2 = {
251 .uart.ops = &mn10300_serial_ops,
252 .uart.membase = (void __iomem *) &SC2CTR,
253 .uart.mapbase = (unsigned long) &SC2CTR,
254 .uart.iotype = UPIO_MEM,
255 .uart.irq = 0,
256 .uart.uartclk = 0,
257 .uart.fifosize = 1,
258 .uart.flags = UPF_BOOT_AUTOCONF,
259 .uart.line = 2,
260#ifdef CONFIG_MN10300_TTYSM2_CTS
261 .uart.type = PORT_MN10300_CTS,
262#else
263 .uart.type = PORT_MN10300,
264#endif
265 .uart.lock =
266 __SPIN_LOCK_UNLOCKED(mn10300_serial_port_sif2.uart.lock),
267 .name = "ttySM2",
268 .rx_name = "ttySM2/Rx",
269 .tx_name = "ttySM2/Tx",
270 .tm_name = "ttySM2/Timer10",
271 ._iobase = &SC2CTR,
272 ._control = &SC2CTR,
273 ._status = &SC2STR,
274 ._intr = &SC2ICR,
275 ._rxb = &SC2RXB,
276 ._txb = &SC2TXB,
277 ._tmxmd = &TM10MD,
278 ._tmxbr = &TM10BR,
279 ._tmicr = &TM10ICR,
280 .tm_irq = TM10IRQ,
281 .div_timer = MNSCx_DIV_TIMER_16BIT,
282 .rx_irq = SC2RXIRQ,
283 .tx_irq = SC2TXIRQ,
284 .rx_icr = &GxICR(SC2RXIRQ),
285 .tx_icr = &GxICR(SC2TXIRQ),
286 .clock_src = MNSCx_CLOCK_SRC_IOCLK,
287#ifdef CONFIG_MN10300_TTYSM2_CTS
288 .options = MNSCx_OPT_CTS,
289#else
290 .options = 0,
291#endif
292#ifdef CONFIG_GDBSTUB_ON_TTYSM2
293 .gdbstub = 1,
294#endif
295};
296#endif
297
298
299
300
301
302struct mn10300_serial_port *mn10300_serial_ports[NR_UARTS + 1] = {
303#ifdef CONFIG_MN10300_TTYSM0
304 [0] = &mn10300_serial_port_sif0,
305#endif
306#ifdef CONFIG_MN10300_TTYSM1
307 [1] = &mn10300_serial_port_sif1,
308#endif
309#ifdef CONFIG_MN10300_TTYSM2
310 [2] = &mn10300_serial_port_sif2,
311#endif
312 [NR_UARTS] = NULL,
313};
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328static void mn10300_serial_mask_ack(unsigned int irq)
329{
330 u16 tmp;
331 GxICR(irq) = GxICR_LEVEL_6;
332 tmp = GxICR(irq);
333}
334
335static void mn10300_serial_nop(unsigned int irq)
336{
337}
338
339static struct irq_chip mn10300_serial_pic = {
340 .name = "mnserial",
341 .ack = mn10300_serial_mask_ack,
342 .mask = mn10300_serial_mask_ack,
343 .mask_ack = mn10300_serial_mask_ack,
344 .unmask = mn10300_serial_nop,
345 .end = mn10300_serial_nop,
346};
347
348
349
350
351
352struct mn10300_serial_int mn10300_serial_int_tbl[NR_IRQS];
353
354static void mn10300_serial_dis_tx_intr(struct mn10300_serial_port *port)
355{
356 u16 x;
357 *port->tx_icr = GxICR_LEVEL_1 | GxICR_DETECT;
358 x = *port->tx_icr;
359}
360
361static void mn10300_serial_en_tx_intr(struct mn10300_serial_port *port)
362{
363 u16 x;
364 *port->tx_icr = GxICR_LEVEL_1 | GxICR_ENABLE;
365 x = *port->tx_icr;
366}
367
368static void mn10300_serial_dis_rx_intr(struct mn10300_serial_port *port)
369{
370 u16 x;
371 *port->rx_icr = GxICR_LEVEL_1 | GxICR_DETECT;
372 x = *port->rx_icr;
373}
374
375
376
377
378static int mask_test_and_clear(volatile u8 *ptr, u8 mask)
379{
380 u32 epsw;
381 asm volatile(" bclr %1,(%2) \n"
382 " mov epsw,%0 \n"
383 : "=d"(epsw) : "d"(mask), "a"(ptr)
384 : "cc", "memory");
385 return !(epsw & EPSW_FLAG_Z);
386}
387
388
389
390
391
392static void mn10300_serial_receive_interrupt(struct mn10300_serial_port *port)
393{
394 struct uart_icount *icount = &port->uart.icount;
395 struct tty_struct *tty = port->uart.state->port.tty;
396 unsigned ix;
397 int count;
398 u8 st, ch, push, status, overrun;
399
400 _enter("%s", port->name);
401
402 push = 0;
403
404 count = CIRC_CNT(port->rx_inp, port->rx_outp, MNSC_BUFFER_SIZE);
405 count = tty_buffer_request_room(tty, count);
406 if (count == 0) {
407 if (!tty->low_latency)
408 tty_flip_buffer_push(tty);
409 return;
410 }
411
412try_again:
413
414 ix = port->rx_outp;
415 if (ix == port->rx_inp) {
416 if (push && !tty->low_latency)
417 tty_flip_buffer_push(tty);
418 return;
419 }
420
421 ch = port->rx_buffer[ix++];
422 st = port->rx_buffer[ix++];
423 smp_rmb();
424 port->rx_outp = ix & (MNSC_BUFFER_SIZE - 1);
425 port->uart.icount.rx++;
426
427 st &= SC01STR_FEF | SC01STR_PEF | SC01STR_OEF;
428 status = 0;
429 overrun = 0;
430
431
432
433
434
435
436
437 switch (port->rx_brk) {
438 case 0:
439
440 break;
441
442 case 1:
443 if (st & SC01STR_FEF && ch == 0) {
444 port->rx_brk = 2;
445 goto try_again;
446 }
447 goto not_break;
448
449 case 2:
450 if (st & SC01STR_FEF && ch == 0) {
451 port->rx_brk = 3;
452 _proto("Rx Break Detected");
453 icount->brk++;
454 if (uart_handle_break(&port->uart))
455 goto ignore_char;
456 status |= 1 << TTY_BREAK;
457 goto insert;
458 }
459 goto not_break;
460
461 default:
462 if (st & (SC01STR_FEF | SC01STR_PEF | SC01STR_OEF))
463 goto try_again;
464
465 port->rx_brk = 0;
466
467 switch (ch) {
468 case 0xFF:
469 case 0xFE:
470 case 0xFC:
471 case 0xF8:
472 case 0xF0:
473 case 0xE0:
474 case 0xC0:
475 case 0x80:
476 case 0x00:
477
478 goto try_again;
479 }
480 break;
481 }
482
483process_errors:
484
485 if (st & SC01STR_FEF) {
486 if (ch == 0) {
487
488 port->rx_brk = 1;
489 goto try_again;
490 }
491
492 _proto("Rx Framing Error");
493 icount->frame++;
494 status |= 1 << TTY_FRAME;
495 }
496
497
498 if (st & SC01STR_PEF) {
499 _proto("Rx Parity Error");
500 icount->parity++;
501 status = TTY_PARITY;
502 }
503
504
505 if (status == 0) {
506 if (uart_handle_sysrq_char(&port->uart, ch))
507 goto ignore_char;
508 status = (1 << TTY_NORMAL);
509 }
510
511
512 if (st & SC01STR_OEF) {
513 if (port->rx_brk)
514 goto try_again;
515
516 _proto("Rx Overrun Error");
517 icount->overrun++;
518 overrun = 1;
519 }
520
521insert:
522 status &= port->uart.read_status_mask;
523
524 if (!overrun && !(status & port->uart.ignore_status_mask)) {
525 int flag;
526
527 if (status & (1 << TTY_BREAK))
528 flag = TTY_BREAK;
529 else if (status & (1 << TTY_PARITY))
530 flag = TTY_PARITY;
531 else if (status & (1 << TTY_FRAME))
532 flag = TTY_FRAME;
533 else
534 flag = TTY_NORMAL;
535
536 tty_insert_flip_char(tty, ch, flag);
537 }
538
539
540
541
542 if (overrun)
543 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
544
545 count--;
546 if (count <= 0) {
547 if (!tty->low_latency)
548 tty_flip_buffer_push(tty);
549 return;
550 }
551
552ignore_char:
553 push = 1;
554 goto try_again;
555
556not_break:
557 port->rx_brk = 0;
558 goto process_errors;
559}
560
561
562
563
564
565
566static void mn10300_serial_transmit_interrupt(struct mn10300_serial_port *port)
567{
568 _enter("%s", port->name);
569
570 if (!port->uart.state || !port->uart.state->port.tty) {
571 mn10300_serial_dis_tx_intr(port);
572 return;
573 }
574
575 if (uart_tx_stopped(&port->uart) ||
576 uart_circ_empty(&port->uart.state->xmit))
577 mn10300_serial_dis_tx_intr(port);
578
579 if (uart_circ_chars_pending(&port->uart.state->xmit) < WAKEUP_CHARS)
580 uart_write_wakeup(&port->uart);
581}
582
583
584
585
586static void mn10300_serial_cts_changed(struct mn10300_serial_port *port, u8 st)
587{
588 u16 ctr;
589
590 port->tx_cts = st;
591 port->uart.icount.cts++;
592
593
594
595 ctr = *port->_control;
596 ctr ^= SC2CTR_TWS;
597 *port->_control = ctr;
598
599 uart_handle_cts_change(&port->uart, st & SC2STR_CTS);
600 wake_up_interruptible(&port->uart.state->port.delta_msr_wait);
601}
602
603
604
605
606
607static irqreturn_t mn10300_serial_interrupt(int irq, void *dev_id)
608{
609 struct mn10300_serial_port *port = dev_id;
610 u8 st;
611
612 spin_lock(&port->uart.lock);
613
614 if (port->intr_flags) {
615 _debug("INT %s: %x", port->name, port->intr_flags);
616
617 if (mask_test_and_clear(&port->intr_flags, MNSCx_RX_AVAIL))
618 mn10300_serial_receive_interrupt(port);
619
620 if (mask_test_and_clear(&port->intr_flags,
621 MNSCx_TX_SPACE | MNSCx_TX_EMPTY))
622 mn10300_serial_transmit_interrupt(port);
623 }
624
625
626
627 if (port->type == PORT_MN10300_CTS) {
628 st = *port->_status;
629 if ((port->tx_cts ^ st) & SC2STR_CTS)
630 mn10300_serial_cts_changed(port, st);
631 }
632
633 spin_unlock(&port->uart.lock);
634
635 return IRQ_HANDLED;
636}
637
638
639
640
641static unsigned int mn10300_serial_tx_empty(struct uart_port *_port)
642{
643 struct mn10300_serial_port *port =
644 container_of(_port, struct mn10300_serial_port, uart);
645
646 _enter("%s", port->name);
647
648 return (*port->_status & (SC01STR_TXF | SC01STR_TBF)) ?
649 0 : TIOCSER_TEMT;
650}
651
652
653
654
655static void mn10300_serial_set_mctrl(struct uart_port *_port,
656 unsigned int mctrl)
657{
658 struct mn10300_serial_port *port =
659 container_of(_port, struct mn10300_serial_port, uart);
660
661 _enter("%s,%x", port->name, mctrl);
662}
663
664
665
666
667static unsigned int mn10300_serial_get_mctrl(struct uart_port *_port)
668{
669 struct mn10300_serial_port *port =
670 container_of(_port, struct mn10300_serial_port, uart);
671
672 _enter("%s", port->name);
673
674 if (port->type == PORT_MN10300_CTS && !(*port->_status & SC2STR_CTS))
675 return TIOCM_CAR | TIOCM_DSR;
676
677 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
678}
679
680
681
682
683static void mn10300_serial_stop_tx(struct uart_port *_port)
684{
685 struct mn10300_serial_port *port =
686 container_of(_port, struct mn10300_serial_port, uart);
687
688 _enter("%s", port->name);
689
690
691 mn10300_serial_dis_tx_intr(port);
692}
693
694
695
696
697
698
699
700static void mn10300_serial_start_tx(struct uart_port *_port)
701{
702 struct mn10300_serial_port *port =
703 container_of(_port, struct mn10300_serial_port, uart);
704
705 u16 x;
706
707 _enter("%s{%lu}",
708 port->name,
709 CIRC_CNT(&port->uart.state->xmit.head,
710 &port->uart.state->xmit.tail,
711 UART_XMIT_SIZE));
712
713
714 x = *port->tx_icr;
715 x |= GxICR_ENABLE;
716
717 if (*port->_status & SC01STR_TBF)
718 x &= ~(GxICR_REQUEST | GxICR_DETECT);
719 else
720 x |= GxICR_REQUEST | GxICR_DETECT;
721
722 _debug("CTR=%04hx ICR=%02hx STR=%04x TMD=%02hx TBR=%04hx ICR=%04hx",
723 *port->_control, *port->_intr, *port->_status,
724 *port->_tmxmd, *port->_tmxbr, *port->tx_icr);
725
726 *port->tx_icr = x;
727 x = *port->tx_icr;
728}
729
730
731
732
733static void mn10300_serial_send_xchar(struct uart_port *_port, char ch)
734{
735 struct mn10300_serial_port *port =
736 container_of(_port, struct mn10300_serial_port, uart);
737
738 _enter("%s,%02x", port->name, ch);
739
740 if (likely(port->gdbstub)) {
741 port->tx_xchar = ch;
742 if (ch)
743 mn10300_serial_en_tx_intr(port);
744 }
745}
746
747
748
749
750
751static void mn10300_serial_stop_rx(struct uart_port *_port)
752{
753 struct mn10300_serial_port *port =
754 container_of(_port, struct mn10300_serial_port, uart);
755
756 u16 ctr;
757
758 _enter("%s", port->name);
759
760 ctr = *port->_control;
761 ctr &= ~SC01CTR_RXE;
762 *port->_control = ctr;
763
764 mn10300_serial_dis_rx_intr(port);
765}
766
767
768
769
770static void mn10300_serial_enable_ms(struct uart_port *_port)
771{
772 struct mn10300_serial_port *port =
773 container_of(_port, struct mn10300_serial_port, uart);
774
775 u16 ctr, cts;
776
777 _enter("%s", port->name);
778
779 if (port->type == PORT_MN10300_CTS) {
780
781
782
783 port->tx_cts = *port->_status;
784
785 cts = (port->tx_cts & SC2STR_CTS) ?
786 SC2CTR_TWE : SC2CTR_TWE | SC2CTR_TWS;
787
788 ctr = *port->_control;
789 ctr &= ~SC2CTR_TWS;
790 ctr |= cts;
791 *port->_control = ctr;
792
793 mn10300_serial_en_tx_intr(port);
794 }
795}
796
797
798
799
800static void mn10300_serial_break_ctl(struct uart_port *_port, int ctl)
801{
802 struct mn10300_serial_port *port =
803 container_of(_port, struct mn10300_serial_port, uart);
804
805 _enter("%s,%d", port->name, ctl);
806
807 if (ctl) {
808
809 port->tx_break = 1;
810 mn10300_serial_en_tx_intr(port);
811 } else {
812 port->tx_break = 0;
813 *port->_control &= ~SC01CTR_BKE;
814 mn10300_serial_en_tx_intr(port);
815 }
816}
817
818
819
820
821static int mn10300_serial_startup(struct uart_port *_port)
822{
823 struct mn10300_serial_port *port =
824 container_of(_port, struct mn10300_serial_port, uart);
825 struct mn10300_serial_int *pint;
826
827 _enter("%s{%d}", port->name, port->gdbstub);
828
829 if (unlikely(port->gdbstub))
830 return -EBUSY;
831
832
833 port->rx_buffer = kmalloc(MNSC_BUFFER_SIZE, GFP_KERNEL);
834 if (!port->rx_buffer)
835 return -ENOMEM;
836
837 port->rx_inp = port->rx_outp = 0;
838
839
840 *port->_intr = SC01ICR_TI;
841 *port->_control |= SC01CTR_TXE | SC01CTR_RXE;
842
843 pint = &mn10300_serial_int_tbl[port->rx_irq];
844 pint->port = port;
845 pint->vdma = mn10300_serial_vdma_rx_handler;
846 pint = &mn10300_serial_int_tbl[port->tx_irq];
847 pint->port = port;
848 pint->vdma = mn10300_serial_vdma_tx_handler;
849
850 set_intr_level(port->rx_irq, GxICR_LEVEL_1);
851 set_intr_level(port->tx_irq, GxICR_LEVEL_1);
852 set_irq_chip(port->tm_irq, &mn10300_serial_pic);
853
854 if (request_irq(port->rx_irq, mn10300_serial_interrupt,
855 IRQF_DISABLED, port->rx_name, port) < 0)
856 goto error;
857
858 if (request_irq(port->tx_irq, mn10300_serial_interrupt,
859 IRQF_DISABLED, port->tx_name, port) < 0)
860 goto error2;
861
862 if (request_irq(port->tm_irq, mn10300_serial_interrupt,
863 IRQF_DISABLED, port->tm_name, port) < 0)
864 goto error3;
865 mn10300_serial_mask_ack(port->tm_irq);
866
867 return 0;
868
869error3:
870 free_irq(port->tx_irq, port);
871error2:
872 free_irq(port->rx_irq, port);
873error:
874 kfree(port->rx_buffer);
875 port->rx_buffer = NULL;
876 return -EBUSY;
877}
878
879
880
881
882static void mn10300_serial_shutdown(struct uart_port *_port)
883{
884 struct mn10300_serial_port *port =
885 container_of(_port, struct mn10300_serial_port, uart);
886
887 _enter("%s", port->name);
888
889
890 port->tx_break = 0;
891 *port->_control &= ~(SC01CTR_TXE | SC01CTR_RXE | SC01CTR_BKE);
892 *port->_tmxmd = 0;
893
894 if (port->rx_buffer) {
895 void *buf = port->rx_buffer;
896 port->rx_buffer = NULL;
897 kfree(buf);
898 }
899
900
901 free_irq(port->tm_irq, port);
902 free_irq(port->rx_irq, port);
903 free_irq(port->tx_irq, port);
904
905 *port->rx_icr = GxICR_LEVEL_1;
906 *port->tx_icr = GxICR_LEVEL_1;
907}
908
909
910
911
912
913static void mn10300_serial_change_speed(struct mn10300_serial_port *port,
914 struct ktermios *new,
915 struct ktermios *old)
916{
917 unsigned long flags;
918 unsigned long ioclk = port->ioclk;
919 unsigned cflag;
920 int baud, bits, xdiv, tmp;
921 u16 tmxbr, scxctr;
922 u8 tmxmd, battempt;
923 u8 div_timer = port->div_timer;
924
925 _enter("%s{%lu}", port->name, ioclk);
926
927
928 cflag = new->c_cflag;
929 switch (cflag & CSIZE) {
930 case CS7: scxctr = SC01CTR_CLN_7BIT; bits = 9; break;
931 case CS8: scxctr = SC01CTR_CLN_8BIT; bits = 10; break;
932 default: scxctr = SC01CTR_CLN_8BIT; bits = 10; break;
933 }
934
935 if (cflag & CSTOPB) {
936 scxctr |= SC01CTR_STB_2BIT;
937 bits++;
938 }
939
940 if (cflag & PARENB) {
941 bits++;
942 if (cflag & PARODD)
943 scxctr |= SC01CTR_PB_ODD;
944#ifdef CMSPAR
945 else if (cflag & CMSPAR)
946 scxctr |= SC01CTR_PB_FIXED0;
947#endif
948 else
949 scxctr |= SC01CTR_PB_EVEN;
950 }
951
952
953 battempt = 0;
954
955 if (div_timer == MNSCx_DIV_TIMER_16BIT)
956 scxctr |= SC0CTR_CK_TM8UFLOW_8;
957
958 else if (div_timer == MNSCx_DIV_TIMER_8BIT)
959 scxctr |= SC0CTR_CK_TM2UFLOW_8;
960
961try_alternative:
962 baud = uart_get_baud_rate(&port->uart, new, old, 0,
963 port->ioclk / 8);
964
965 _debug("ALT %d [baud %d]", battempt, baud);
966
967 if (!baud)
968 baud = 9600;
969 xdiv = 1;
970 if (baud == 134) {
971 baud = 269;
972 xdiv = 2;
973 }
974
975 if (baud == 38400 &&
976 (port->uart.flags & UPF_SPD_MASK) == UPF_SPD_CUST
977 ) {
978 _debug("CUSTOM %u", port->uart.custom_divisor);
979
980 if (div_timer == MNSCx_DIV_TIMER_16BIT) {
981 if (port->uart.custom_divisor <= 65535) {
982 tmxmd = TM8MD_SRC_IOCLK;
983 tmxbr = port->uart.custom_divisor;
984 port->uart.uartclk = ioclk;
985 goto timer_okay;
986 }
987 if (port->uart.custom_divisor / 8 <= 65535) {
988 tmxmd = TM8MD_SRC_IOCLK_8;
989 tmxbr = port->uart.custom_divisor / 8;
990 port->uart.custom_divisor = tmxbr * 8;
991 port->uart.uartclk = ioclk / 8;
992 goto timer_okay;
993 }
994 if (port->uart.custom_divisor / 32 <= 65535) {
995 tmxmd = TM8MD_SRC_IOCLK_32;
996 tmxbr = port->uart.custom_divisor / 32;
997 port->uart.custom_divisor = tmxbr * 32;
998 port->uart.uartclk = ioclk / 32;
999 goto timer_okay;
1000 }
1001
1002 } else if (div_timer == MNSCx_DIV_TIMER_8BIT) {
1003 if (port->uart.custom_divisor <= 255) {
1004 tmxmd = TM2MD_SRC_IOCLK;
1005 tmxbr = port->uart.custom_divisor;
1006 port->uart.uartclk = ioclk;
1007 goto timer_okay;
1008 }
1009 if (port->uart.custom_divisor / 8 <= 255) {
1010 tmxmd = TM2MD_SRC_IOCLK_8;
1011 tmxbr = port->uart.custom_divisor / 8;
1012 port->uart.custom_divisor = tmxbr * 8;
1013 port->uart.uartclk = ioclk / 8;
1014 goto timer_okay;
1015 }
1016 if (port->uart.custom_divisor / 32 <= 255) {
1017 tmxmd = TM2MD_SRC_IOCLK_32;
1018 tmxbr = port->uart.custom_divisor / 32;
1019 port->uart.custom_divisor = tmxbr * 32;
1020 port->uart.uartclk = ioclk / 32;
1021 goto timer_okay;
1022 }
1023 }
1024 }
1025
1026 switch (div_timer) {
1027 case MNSCx_DIV_TIMER_16BIT:
1028 port->uart.uartclk = ioclk;
1029 tmxmd = TM8MD_SRC_IOCLK;
1030 tmxbr = tmp = (ioclk / (baud * xdiv) + 4) / 8 - 1;
1031 if (tmp > 0 && tmp <= 65535)
1032 goto timer_okay;
1033
1034 port->uart.uartclk = ioclk / 8;
1035 tmxmd = TM8MD_SRC_IOCLK_8;
1036 tmxbr = tmp = (ioclk / (baud * 8 * xdiv) + 4) / 8 - 1;
1037 if (tmp > 0 && tmp <= 65535)
1038 goto timer_okay;
1039
1040 port->uart.uartclk = ioclk / 32;
1041 tmxmd = TM8MD_SRC_IOCLK_32;
1042 tmxbr = tmp = (ioclk / (baud * 32 * xdiv) + 4) / 8 - 1;
1043 if (tmp > 0 && tmp <= 65535)
1044 goto timer_okay;
1045 break;
1046
1047 case MNSCx_DIV_TIMER_8BIT:
1048 port->uart.uartclk = ioclk;
1049 tmxmd = TM2MD_SRC_IOCLK;
1050 tmxbr = tmp = (ioclk / (baud * xdiv) + 4) / 8 - 1;
1051 if (tmp > 0 && tmp <= 255)
1052 goto timer_okay;
1053
1054 port->uart.uartclk = ioclk / 8;
1055 tmxmd = TM2MD_SRC_IOCLK_8;
1056 tmxbr = tmp = (ioclk / (baud * 8 * xdiv) + 4) / 8 - 1;
1057 if (tmp > 0 && tmp <= 255)
1058 goto timer_okay;
1059
1060 port->uart.uartclk = ioclk / 32;
1061 tmxmd = TM2MD_SRC_IOCLK_32;
1062 tmxbr = tmp = (ioclk / (baud * 32 * xdiv) + 4) / 8 - 1;
1063 if (tmp > 0 && tmp <= 255)
1064 goto timer_okay;
1065 break;
1066
1067 default:
1068 BUG();
1069 return;
1070 }
1071
1072
1073 _debug("CAN'T SUPPORT");
1074
1075 switch (battempt) {
1076 case 0:
1077 if (old) {
1078 new->c_cflag &= ~CBAUD;
1079 new->c_cflag |= (old->c_cflag & CBAUD);
1080 battempt = 1;
1081 goto try_alternative;
1082 }
1083
1084 case 1:
1085
1086
1087 new->c_cflag &= ~CBAUD;
1088 new->c_cflag |= B9600;
1089 battempt = 2;
1090 goto try_alternative;
1091
1092 default:
1093
1094
1095
1096
1097 new->c_cflag &= ~CBAUD;
1098 new->c_cflag |= B0;
1099
1100 if (div_timer == MNSCx_DIV_TIMER_16BIT)
1101 tmxmd = TM8MD_SRC_IOCLK_32;
1102 else if (div_timer == MNSCx_DIV_TIMER_8BIT)
1103 tmxmd = TM2MD_SRC_IOCLK_32;
1104 tmxbr = 1;
1105
1106 port->uart.uartclk = ioclk / 32;
1107 break;
1108 }
1109timer_okay:
1110
1111 _debug("UARTCLK: %u / %hu", port->uart.uartclk, tmxbr);
1112
1113
1114 spin_lock_irqsave(&port->uart.lock, flags);
1115
1116 uart_update_timeout(&port->uart, new->c_cflag, baud);
1117
1118
1119 switch (div_timer) {
1120 case MNSCx_DIV_TIMER_16BIT:
1121 *port->_tmxmd = 0;
1122 *port->_tmxbr = tmxbr;
1123 *port->_tmxmd = TM8MD_INIT_COUNTER;
1124 *port->_tmxmd = tmxmd | TM8MD_COUNT_ENABLE;
1125 break;
1126
1127 case MNSCx_DIV_TIMER_8BIT:
1128 *port->_tmxmd = 0;
1129 *(volatile u8 *) port->_tmxbr = (u8) tmxbr;
1130 *port->_tmxmd = TM2MD_INIT_COUNTER;
1131 *port->_tmxmd = tmxmd | TM2MD_COUNT_ENABLE;
1132 break;
1133 }
1134
1135
1136 scxctr &= ~(SC2CTR_TWE | SC2CTR_TWS);
1137
1138 if (port->type == PORT_MN10300_CTS && cflag & CRTSCTS) {
1139
1140
1141
1142 port->tx_cts = *port->_status;
1143
1144 if (port->tx_cts & SC2STR_CTS)
1145 scxctr |= SC2CTR_TWE;
1146 else
1147 scxctr |= SC2CTR_TWE | SC2CTR_TWS;
1148 }
1149
1150
1151 port->uart.read_status_mask = (1 << TTY_NORMAL) | (1 << TTY_OVERRUN);
1152 if (new->c_iflag & INPCK)
1153 port->uart.read_status_mask |=
1154 (1 << TTY_PARITY) | (1 << TTY_FRAME);
1155 if (new->c_iflag & (BRKINT | PARMRK))
1156 port->uart.read_status_mask |= (1 << TTY_BREAK);
1157
1158
1159 port->uart.ignore_status_mask = 0;
1160 if (new->c_iflag & IGNPAR)
1161 port->uart.ignore_status_mask |=
1162 (1 << TTY_PARITY) | (1 << TTY_FRAME);
1163 if (new->c_iflag & IGNBRK) {
1164 port->uart.ignore_status_mask |= (1 << TTY_BREAK);
1165
1166
1167
1168
1169 if (new->c_iflag & IGNPAR)
1170 port->uart.ignore_status_mask |= (1 << TTY_OVERRUN);
1171 }
1172
1173
1174 if ((new->c_cflag & CREAD) == 0)
1175 port->uart.ignore_status_mask |= (1 << TTY_NORMAL);
1176
1177 scxctr |= *port->_control & (SC01CTR_TXE | SC01CTR_RXE | SC01CTR_BKE);
1178 *port->_control = scxctr;
1179
1180 spin_unlock_irqrestore(&port->uart.lock, flags);
1181}
1182
1183
1184
1185
1186static void mn10300_serial_set_termios(struct uart_port *_port,
1187 struct ktermios *new,
1188 struct ktermios *old)
1189{
1190 struct mn10300_serial_port *port =
1191 container_of(_port, struct mn10300_serial_port, uart);
1192
1193 _enter("%s,%p,%p", port->name, new, old);
1194
1195 mn10300_serial_change_speed(port, new, old);
1196
1197
1198 if (!(new->c_cflag & CRTSCTS)) {
1199 u16 ctr = *port->_control;
1200 ctr &= ~SC2CTR_TWE;
1201 *port->_control = ctr;
1202 }
1203}
1204
1205
1206
1207
1208static const char *mn10300_serial_type(struct uart_port *_port)
1209{
1210 struct mn10300_serial_port *port =
1211 container_of(_port, struct mn10300_serial_port, uart);
1212
1213 if (port->uart.type == PORT_MN10300_CTS)
1214 return "MN10300 SIF_CTS";
1215
1216 return "MN10300 SIF";
1217}
1218
1219
1220
1221
1222static void mn10300_serial_release_port(struct uart_port *_port)
1223{
1224 struct mn10300_serial_port *port =
1225 container_of(_port, struct mn10300_serial_port, uart);
1226
1227 _enter("%s", port->name);
1228
1229 release_mem_region((unsigned long) port->_iobase, 16);
1230}
1231
1232
1233
1234
1235static int mn10300_serial_request_port(struct uart_port *_port)
1236{
1237 struct mn10300_serial_port *port =
1238 container_of(_port, struct mn10300_serial_port, uart);
1239
1240 _enter("%s", port->name);
1241
1242 request_mem_region((unsigned long) port->_iobase, 16, port->name);
1243 return 0;
1244}
1245
1246
1247
1248
1249static void mn10300_serial_config_port(struct uart_port *_port, int type)
1250{
1251 struct mn10300_serial_port *port =
1252 container_of(_port, struct mn10300_serial_port, uart);
1253
1254 _enter("%s", port->name);
1255
1256 port->uart.type = PORT_MN10300;
1257
1258 if (port->options & MNSCx_OPT_CTS)
1259 port->uart.type = PORT_MN10300_CTS;
1260
1261 mn10300_serial_request_port(_port);
1262}
1263
1264
1265
1266
1267static int mn10300_serial_verify_port(struct uart_port *_port,
1268 struct serial_struct *ss)
1269{
1270 struct mn10300_serial_port *port =
1271 container_of(_port, struct mn10300_serial_port, uart);
1272 void *mapbase = (void *) (unsigned long) port->uart.mapbase;
1273
1274 _enter("%s", port->name);
1275
1276
1277 if (ss->irq != port->uart.irq ||
1278 ss->port != port->uart.iobase ||
1279 ss->io_type != port->uart.iotype ||
1280 ss->iomem_base != mapbase ||
1281 ss->iomem_reg_shift != port->uart.regshift ||
1282 ss->hub6 != port->uart.hub6 ||
1283 ss->xmit_fifo_size != port->uart.fifosize)
1284 return -EINVAL;
1285
1286
1287 if (ss->type != port->uart.type) {
1288 if (!(port->options & MNSCx_OPT_CTS))
1289 return -EINVAL;
1290
1291 if (ss->type != PORT_MN10300 &&
1292 ss->type != PORT_MN10300_CTS)
1293 return -EINVAL;
1294 }
1295
1296 return 0;
1297}
1298
1299
1300
1301
1302static int __init mn10300_serial_init(void)
1303{
1304 struct mn10300_serial_port *port;
1305 int ret, i;
1306
1307 printk(KERN_INFO "%s version %s (%s)\n",
1308 serial_name, serial_version, serial_revdate);
1309
1310#ifdef CONFIG_MN10300_TTYSM2
1311 SC2TIM = 8;
1312#endif
1313
1314 set_intr_stub(EXCEP_IRQ_LEVEL1, mn10300_serial_vdma_interrupt);
1315
1316 ret = uart_register_driver(&mn10300_serial_driver);
1317 if (!ret) {
1318 for (i = 0 ; i < NR_PORTS ; i++) {
1319 port = mn10300_serial_ports[i];
1320 if (!port || port->gdbstub)
1321 continue;
1322
1323 switch (port->clock_src) {
1324 case MNSCx_CLOCK_SRC_IOCLK:
1325 port->ioclk = MN10300_IOCLK;
1326 break;
1327
1328#ifdef MN10300_IOBCLK
1329 case MNSCx_CLOCK_SRC_IOBCLK:
1330 port->ioclk = MN10300_IOBCLK;
1331 break;
1332#endif
1333 default:
1334 BUG();
1335 }
1336
1337 ret = uart_add_one_port(&mn10300_serial_driver,
1338 &port->uart);
1339
1340 if (ret < 0) {
1341 _debug("ERROR %d", -ret);
1342 break;
1343 }
1344 }
1345
1346 if (ret)
1347 uart_unregister_driver(&mn10300_serial_driver);
1348 }
1349
1350 return ret;
1351}
1352
1353__initcall(mn10300_serial_init);
1354
1355
1356#ifdef CONFIG_MN10300_TTYSM_CONSOLE
1357
1358
1359
1360
1361
1362
1363static void mn10300_serial_console_write(struct console *co,
1364 const char *s, unsigned count)
1365{
1366 struct mn10300_serial_port *port;
1367 unsigned i;
1368 u16 scxctr, txicr, tmp;
1369 u8 tmxmd;
1370
1371 port = mn10300_serial_ports[co->index];
1372
1373
1374 txicr = *port->tx_icr;
1375 *port->tx_icr = GxICR_LEVEL_1;
1376 tmp = *port->tx_icr;
1377
1378
1379 scxctr = *port->_control;
1380 if (!(scxctr & SC01CTR_TXE)) {
1381
1382 tmxmd = *port->_tmxmd;
1383
1384 switch (port->div_timer) {
1385 case MNSCx_DIV_TIMER_16BIT:
1386 *port->_tmxmd = 0;
1387 *port->_tmxmd = TM8MD_INIT_COUNTER;
1388 *port->_tmxmd = tmxmd | TM8MD_COUNT_ENABLE;
1389 break;
1390
1391 case MNSCx_DIV_TIMER_8BIT:
1392 *port->_tmxmd = 0;
1393 *port->_tmxmd = TM2MD_INIT_COUNTER;
1394 *port->_tmxmd = tmxmd | TM2MD_COUNT_ENABLE;
1395 break;
1396 }
1397
1398
1399 *port->_control = (scxctr & ~SC01CTR_BKE) | SC01CTR_TXE;
1400
1401 } else if (scxctr & SC01CTR_BKE) {
1402
1403 *port->_control = (scxctr & ~SC01CTR_BKE);
1404 }
1405
1406
1407 for (i = 0; i < count; i++) {
1408 char ch = *s++;
1409
1410 while (*port->_status & SC01STR_TBF)
1411 continue;
1412 *(u8 *) port->_txb = ch;
1413
1414 if (ch == 0x0a) {
1415 while (*port->_status & SC01STR_TBF)
1416 continue;
1417 *(u8 *) port->_txb = 0xd;
1418 }
1419 }
1420
1421
1422
1423 while (*port->_status & (SC01STR_TXF | SC01STR_TBF))
1424 continue;
1425
1426
1427 if (!(scxctr & SC01CTR_TXE))
1428 *port->_control = scxctr;
1429
1430 *port->tx_icr = txicr;
1431 tmp = *port->tx_icr;
1432}
1433
1434
1435
1436
1437
1438
1439
1440static int __init mn10300_serial_console_setup(struct console *co,
1441 char *options)
1442{
1443 struct mn10300_serial_port *port;
1444 int i, parity = 'n', baud = 9600, bits = 8, flow = 0;
1445
1446 for (i = 0 ; i < NR_PORTS ; i++) {
1447 port = mn10300_serial_ports[i];
1448 if (port && !port->gdbstub && port->uart.line == co->index)
1449 goto found_device;
1450 }
1451
1452 return -ENODEV;
1453
1454found_device:
1455 switch (port->clock_src) {
1456 case MNSCx_CLOCK_SRC_IOCLK:
1457 port->ioclk = MN10300_IOCLK;
1458 break;
1459
1460#ifdef MN10300_IOBCLK
1461 case MNSCx_CLOCK_SRC_IOBCLK:
1462 port->ioclk = MN10300_IOBCLK;
1463 break;
1464#endif
1465 default:
1466 BUG();
1467 }
1468
1469 if (options)
1470 uart_parse_options(options, &baud, &parity, &bits, &flow);
1471
1472 return uart_set_options(&port->uart, co, baud, parity, bits, flow);
1473}
1474
1475
1476
1477
1478static int __init mn10300_serial_console_init(void)
1479{
1480 register_console(&mn10300_serial_console);
1481 return 0;
1482}
1483
1484console_initcall(mn10300_serial_console_init);
1485#endif
1486