1
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5
6
7#include "qla_def.h"
8
9#include <linux/delay.h>
10#include <linux/slab.h>
11#include <linux/vmalloc.h>
12#include <asm/uaccess.h>
13
14
15
16
17
18
19
20
21
22static void
23qla2x00_lock_nvram_access(struct qla_hw_data *ha)
24{
25 uint16_t data;
26 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
27
28 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
29 data = RD_REG_WORD(®->nvram);
30 while (data & NVR_BUSY) {
31 udelay(100);
32 data = RD_REG_WORD(®->nvram);
33 }
34
35
36 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1);
37 RD_REG_WORD(®->u.isp2300.host_semaphore);
38 udelay(5);
39 data = RD_REG_WORD(®->u.isp2300.host_semaphore);
40 while ((data & BIT_0) == 0) {
41
42 udelay(100);
43 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1);
44 RD_REG_WORD(®->u.isp2300.host_semaphore);
45 udelay(5);
46 data = RD_REG_WORD(®->u.isp2300.host_semaphore);
47 }
48 }
49}
50
51
52
53
54
55static void
56qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
57{
58 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
59
60 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
61 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0);
62 RD_REG_WORD(®->u.isp2300.host_semaphore);
63 }
64}
65
66
67
68
69
70
71static void
72qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
73{
74 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
75
76 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
77 RD_REG_WORD(®->nvram);
78 NVRAM_DELAY();
79 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_CLOCK |
80 NVR_WRT_ENABLE);
81 RD_REG_WORD(®->nvram);
82 NVRAM_DELAY();
83 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
84 RD_REG_WORD(®->nvram);
85 NVRAM_DELAY();
86}
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103static uint16_t
104qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
105{
106 uint8_t cnt;
107 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
108 uint16_t data = 0;
109 uint16_t reg_data;
110
111
112 nv_cmd <<= 5;
113 for (cnt = 0; cnt < 11; cnt++) {
114 if (nv_cmd & BIT_31)
115 qla2x00_nv_write(ha, NVR_DATA_OUT);
116 else
117 qla2x00_nv_write(ha, 0);
118 nv_cmd <<= 1;
119 }
120
121
122 for (cnt = 0; cnt < 16; cnt++) {
123 WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK);
124 RD_REG_WORD(®->nvram);
125 NVRAM_DELAY();
126 data <<= 1;
127 reg_data = RD_REG_WORD(®->nvram);
128 if (reg_data & NVR_DATA_IN)
129 data |= BIT_0;
130 WRT_REG_WORD(®->nvram, NVR_SELECT);
131 RD_REG_WORD(®->nvram);
132 NVRAM_DELAY();
133 }
134
135
136 WRT_REG_WORD(®->nvram, NVR_DESELECT);
137 RD_REG_WORD(®->nvram);
138 NVRAM_DELAY();
139
140 return data;
141}
142
143
144
145
146
147
148
149
150
151
152static uint16_t
153qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
154{
155 uint16_t data;
156 uint32_t nv_cmd;
157
158 nv_cmd = addr << 16;
159 nv_cmd |= NV_READ_OP;
160 data = qla2x00_nvram_request(ha, nv_cmd);
161
162 return (data);
163}
164
165
166
167
168
169static void
170qla2x00_nv_deselect(struct qla_hw_data *ha)
171{
172 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
173
174 WRT_REG_WORD(®->nvram, NVR_DESELECT);
175 RD_REG_WORD(®->nvram);
176 NVRAM_DELAY();
177}
178
179
180
181
182
183
184
185static void
186qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
187{
188 int count;
189 uint16_t word;
190 uint32_t nv_cmd, wait_cnt;
191 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
192
193 qla2x00_nv_write(ha, NVR_DATA_OUT);
194 qla2x00_nv_write(ha, 0);
195 qla2x00_nv_write(ha, 0);
196
197 for (word = 0; word < 8; word++)
198 qla2x00_nv_write(ha, NVR_DATA_OUT);
199
200 qla2x00_nv_deselect(ha);
201
202
203 nv_cmd = (addr << 16) | NV_WRITE_OP;
204 nv_cmd |= data;
205 nv_cmd <<= 5;
206 for (count = 0; count < 27; count++) {
207 if (nv_cmd & BIT_31)
208 qla2x00_nv_write(ha, NVR_DATA_OUT);
209 else
210 qla2x00_nv_write(ha, 0);
211
212 nv_cmd <<= 1;
213 }
214
215 qla2x00_nv_deselect(ha);
216
217
218 WRT_REG_WORD(®->nvram, NVR_SELECT);
219 RD_REG_WORD(®->nvram);
220 wait_cnt = NVR_WAIT_CNT;
221 do {
222 if (!--wait_cnt) {
223 DEBUG9_10(qla_printk(KERN_WARNING, ha,
224 "NVRAM didn't go ready...\n"));
225 break;
226 }
227 NVRAM_DELAY();
228 word = RD_REG_WORD(®->nvram);
229 } while ((word & NVR_DATA_IN) == 0);
230
231 qla2x00_nv_deselect(ha);
232
233
234 qla2x00_nv_write(ha, NVR_DATA_OUT);
235 for (count = 0; count < 10; count++)
236 qla2x00_nv_write(ha, 0);
237
238 qla2x00_nv_deselect(ha);
239}
240
241static int
242qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
243 uint16_t data, uint32_t tmo)
244{
245 int ret, count;
246 uint16_t word;
247 uint32_t nv_cmd;
248 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
249
250 ret = QLA_SUCCESS;
251
252 qla2x00_nv_write(ha, NVR_DATA_OUT);
253 qla2x00_nv_write(ha, 0);
254 qla2x00_nv_write(ha, 0);
255
256 for (word = 0; word < 8; word++)
257 qla2x00_nv_write(ha, NVR_DATA_OUT);
258
259 qla2x00_nv_deselect(ha);
260
261
262 nv_cmd = (addr << 16) | NV_WRITE_OP;
263 nv_cmd |= data;
264 nv_cmd <<= 5;
265 for (count = 0; count < 27; count++) {
266 if (nv_cmd & BIT_31)
267 qla2x00_nv_write(ha, NVR_DATA_OUT);
268 else
269 qla2x00_nv_write(ha, 0);
270
271 nv_cmd <<= 1;
272 }
273
274 qla2x00_nv_deselect(ha);
275
276
277 WRT_REG_WORD(®->nvram, NVR_SELECT);
278 RD_REG_WORD(®->nvram);
279 do {
280 NVRAM_DELAY();
281 word = RD_REG_WORD(®->nvram);
282 if (!--tmo) {
283 ret = QLA_FUNCTION_FAILED;
284 break;
285 }
286 } while ((word & NVR_DATA_IN) == 0);
287
288 qla2x00_nv_deselect(ha);
289
290
291 qla2x00_nv_write(ha, NVR_DATA_OUT);
292 for (count = 0; count < 10; count++)
293 qla2x00_nv_write(ha, 0);
294
295 qla2x00_nv_deselect(ha);
296
297 return ret;
298}
299
300
301
302
303
304static int
305qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
306{
307 int ret, stat;
308 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
309 uint32_t word, wait_cnt;
310 uint16_t wprot, wprot_old;
311
312
313 ret = QLA_FUNCTION_FAILED;
314
315 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
316 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
317 __constant_cpu_to_le16(0x1234), 100000);
318 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
319 if (stat != QLA_SUCCESS || wprot != 0x1234) {
320
321 qla2x00_nv_write(ha, NVR_DATA_OUT);
322 qla2x00_nv_write(ha, 0);
323 qla2x00_nv_write(ha, 0);
324 for (word = 0; word < 8; word++)
325 qla2x00_nv_write(ha, NVR_DATA_OUT);
326
327 qla2x00_nv_deselect(ha);
328
329
330 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
331 qla2x00_nv_write(ha, NVR_PR_ENABLE);
332 qla2x00_nv_write(ha, NVR_PR_ENABLE);
333 for (word = 0; word < 8; word++)
334 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
335
336 qla2x00_nv_deselect(ha);
337
338
339 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
342 for (word = 0; word < 8; word++)
343 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
344
345 qla2x00_nv_deselect(ha);
346
347
348 WRT_REG_WORD(®->nvram, NVR_SELECT);
349 RD_REG_WORD(®->nvram);
350 wait_cnt = NVR_WAIT_CNT;
351 do {
352 if (!--wait_cnt) {
353 DEBUG9_10(qla_printk(KERN_WARNING, ha,
354 "NVRAM didn't go ready...\n"));
355 break;
356 }
357 NVRAM_DELAY();
358 word = RD_REG_WORD(®->nvram);
359 } while ((word & NVR_DATA_IN) == 0);
360
361 if (wait_cnt)
362 ret = QLA_SUCCESS;
363 } else
364 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
365
366 return ret;
367}
368
369static void
370qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
371{
372 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
373 uint32_t word, wait_cnt;
374
375 if (stat != QLA_SUCCESS)
376 return;
377
378
379
380 qla2x00_nv_write(ha, NVR_DATA_OUT);
381 qla2x00_nv_write(ha, 0);
382 qla2x00_nv_write(ha, 0);
383 for (word = 0; word < 8; word++)
384 qla2x00_nv_write(ha, NVR_DATA_OUT);
385
386 qla2x00_nv_deselect(ha);
387
388
389 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
390 qla2x00_nv_write(ha, NVR_PR_ENABLE);
391 qla2x00_nv_write(ha, NVR_PR_ENABLE);
392 for (word = 0; word < 8; word++)
393 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
394
395 qla2x00_nv_deselect(ha);
396
397
398 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
399 qla2x00_nv_write(ha, NVR_PR_ENABLE);
400 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
401 for (word = 0; word < 8; word++)
402 qla2x00_nv_write(ha, NVR_PR_ENABLE);
403
404 qla2x00_nv_deselect(ha);
405
406
407 WRT_REG_WORD(®->nvram, NVR_SELECT);
408 RD_REG_WORD(®->nvram);
409 wait_cnt = NVR_WAIT_CNT;
410 do {
411 if (!--wait_cnt) {
412 DEBUG9_10(qla_printk(KERN_WARNING, ha,
413 "NVRAM didn't go ready...\n"));
414 break;
415 }
416 NVRAM_DELAY();
417 word = RD_REG_WORD(®->nvram);
418 } while ((word & NVR_DATA_IN) == 0);
419}
420
421
422
423
424
425
426static inline uint32_t
427flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
428{
429 return ha->flash_conf_off | faddr;
430}
431
432static inline uint32_t
433flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
434{
435 return ha->flash_data_off | faddr;
436}
437
438static inline uint32_t
439nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
440{
441 return ha->nvram_conf_off | naddr;
442}
443
444static inline uint32_t
445nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
446{
447 return ha->nvram_data_off | naddr;
448}
449
450static uint32_t
451qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
452{
453 int rval;
454 uint32_t cnt, data;
455 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
456
457 WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG);
458
459 rval = QLA_SUCCESS;
460 for (cnt = 3000;
461 (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 &&
462 rval == QLA_SUCCESS; cnt--) {
463 if (cnt)
464 udelay(10);
465 else
466 rval = QLA_FUNCTION_TIMEOUT;
467 cond_resched();
468 }
469
470
471 data = 0xDEADDEAD;
472 if (rval == QLA_SUCCESS)
473 data = RD_REG_DWORD(®->flash_data);
474
475 return data;
476}
477
478uint32_t *
479qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
480 uint32_t dwords)
481{
482 uint32_t i;
483 struct qla_hw_data *ha = vha->hw;
484
485
486 for (i = 0; i < dwords; i++, faddr++)
487 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
488 flash_data_addr(ha, faddr)));
489
490 return dwptr;
491}
492
493static int
494qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
495{
496 int rval;
497 uint32_t cnt;
498 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
499
500 WRT_REG_DWORD(®->flash_data, data);
501 RD_REG_DWORD(®->flash_data);
502 WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG);
503
504 rval = QLA_SUCCESS;
505 for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) &&
506 rval == QLA_SUCCESS; cnt--) {
507 if (cnt)
508 udelay(10);
509 else
510 rval = QLA_FUNCTION_TIMEOUT;
511 cond_resched();
512 }
513 return rval;
514}
515
516static void
517qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
518 uint8_t *flash_id)
519{
520 uint32_t ids;
521
522 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
523 *man_id = LSB(ids);
524 *flash_id = MSB(ids);
525
526
527 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
528
529
530
531
532
533
534 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
535 *man_id = LSB(ids);
536 *flash_id = MSB(ids);
537 }
538}
539
540static int
541qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
542{
543 const char *loc, *locations[] = { "DEF", "PCI" };
544 uint32_t pcihdr, pcids;
545 uint32_t *dcode;
546 uint8_t *buf, *bcode, last_image;
547 uint16_t cnt, chksum, *wptr;
548 struct qla_flt_location *fltl;
549 struct qla_hw_data *ha = vha->hw;
550 struct req_que *req = ha->req_q_map[0];
551
552
553
554
555
556
557 loc = locations[0];
558 *start = 0;
559 if (IS_QLA24XX_TYPE(ha))
560 *start = FA_FLASH_LAYOUT_ADDR_24;
561 else if (IS_QLA25XX(ha))
562 *start = FA_FLASH_LAYOUT_ADDR;
563 else if (IS_QLA81XX(ha))
564 *start = FA_FLASH_LAYOUT_ADDR_81;
565 else if (IS_QLA82XX(ha)) {
566 *start = FA_FLASH_LAYOUT_ADDR_82;
567 goto end;
568 }
569
570 buf = (uint8_t *)req->ring;
571 dcode = (uint32_t *)req->ring;
572 pcihdr = 0;
573 last_image = 1;
574 do {
575
576 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
577 bcode = buf + (pcihdr % 4);
578 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
579 goto end;
580
581
582 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
583 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
584 bcode = buf + (pcihdr % 4);
585
586
587 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
588 bcode[0x2] != 'I' || bcode[0x3] != 'R')
589 goto end;
590
591 last_image = bcode[0x15] & BIT_7;
592
593
594 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
595 } while (!last_image);
596
597
598 fltl = (struct qla_flt_location *)req->ring;
599 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
600 sizeof(struct qla_flt_location) >> 2);
601 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
602 fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
603 goto end;
604
605 wptr = (uint16_t *)req->ring;
606 cnt = sizeof(struct qla_flt_location) >> 1;
607 for (chksum = 0; cnt; cnt--)
608 chksum += le16_to_cpu(*wptr++);
609 if (chksum) {
610 qla_printk(KERN_ERR, ha,
611 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
612 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location));
613 return QLA_FUNCTION_FAILED;
614 }
615
616
617 loc = locations[1];
618 *start = (le16_to_cpu(fltl->start_hi) << 16 |
619 le16_to_cpu(fltl->start_lo)) >> 2;
620end:
621 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
622 return QLA_SUCCESS;
623}
624
625static void
626qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
627{
628 const char *loc, *locations[] = { "DEF", "FLT" };
629 const uint32_t def_fw[] =
630 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
631 const uint32_t def_boot[] =
632 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
633 const uint32_t def_vpd_nvram[] =
634 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
635 const uint32_t def_vpd0[] =
636 { 0, 0, FA_VPD0_ADDR_81 };
637 const uint32_t def_vpd1[] =
638 { 0, 0, FA_VPD1_ADDR_81 };
639 const uint32_t def_nvram0[] =
640 { 0, 0, FA_NVRAM0_ADDR_81 };
641 const uint32_t def_nvram1[] =
642 { 0, 0, FA_NVRAM1_ADDR_81 };
643 const uint32_t def_fdt[] =
644 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
645 FA_FLASH_DESCR_ADDR_81 };
646 const uint32_t def_npiv_conf0[] =
647 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
648 FA_NPIV_CONF0_ADDR_81 };
649 const uint32_t def_npiv_conf1[] =
650 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
651 FA_NPIV_CONF1_ADDR_81 };
652 const uint32_t fcp_prio_cfg0[] =
653 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25,
654 0 };
655 const uint32_t fcp_prio_cfg1[] =
656 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25,
657 0 };
658 uint32_t def;
659 uint16_t *wptr;
660 uint16_t cnt, chksum;
661 uint32_t start;
662 struct qla_flt_header *flt;
663 struct qla_flt_region *region;
664 struct qla_hw_data *ha = vha->hw;
665 struct req_que *req = ha->req_q_map[0];
666
667 ha->flt_region_flt = flt_addr;
668 wptr = (uint16_t *)req->ring;
669 flt = (struct qla_flt_header *)req->ring;
670 region = (struct qla_flt_region *)&flt[1];
671 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
672 flt_addr << 2, OPTROM_BURST_SIZE);
673 if (*wptr == __constant_cpu_to_le16(0xffff))
674 goto no_flash_data;
675 if (flt->version != __constant_cpu_to_le16(1)) {
676 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: "
677 "version=0x%x length=0x%x checksum=0x%x.\n",
678 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
679 le16_to_cpu(flt->checksum)));
680 goto no_flash_data;
681 }
682
683 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
684 for (chksum = 0; cnt; cnt--)
685 chksum += le16_to_cpu(*wptr++);
686 if (chksum) {
687 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
688 "version=0x%x length=0x%x checksum=0x%x.\n",
689 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
690 chksum));
691 goto no_flash_data;
692 }
693
694 loc = locations[1];
695 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
696 for ( ; cnt; cnt--, region++) {
697
698 start = le32_to_cpu(region->start) >> 2;
699
700 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
701 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
702 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
703
704 switch (le32_to_cpu(region->code) & 0xff) {
705 case FLT_REG_FW:
706 ha->flt_region_fw = start;
707 break;
708 case FLT_REG_BOOT_CODE:
709 ha->flt_region_boot = start;
710 break;
711 case FLT_REG_VPD_0:
712 ha->flt_region_vpd_nvram = start;
713 if (IS_QLA82XX(ha))
714 break;
715 if (ha->flags.port0)
716 ha->flt_region_vpd = start;
717 break;
718 case FLT_REG_VPD_1:
719 if (IS_QLA82XX(ha))
720 break;
721 if (!ha->flags.port0)
722 ha->flt_region_vpd = start;
723 break;
724 case FLT_REG_NVRAM_0:
725 if (ha->flags.port0)
726 ha->flt_region_nvram = start;
727 break;
728 case FLT_REG_NVRAM_1:
729 if (!ha->flags.port0)
730 ha->flt_region_nvram = start;
731 break;
732 case FLT_REG_FDT:
733 ha->flt_region_fdt = start;
734 break;
735 case FLT_REG_NPIV_CONF_0:
736 if (ha->flags.port0)
737 ha->flt_region_npiv_conf = start;
738 break;
739 case FLT_REG_NPIV_CONF_1:
740 if (!ha->flags.port0)
741 ha->flt_region_npiv_conf = start;
742 break;
743 case FLT_REG_GOLD_FW:
744 ha->flt_region_gold_fw = start;
745 break;
746 case FLT_REG_FCP_PRIO_0:
747 if (ha->flags.port0)
748 ha->flt_region_fcp_prio = start;
749 break;
750 case FLT_REG_FCP_PRIO_1:
751 if (!ha->flags.port0)
752 ha->flt_region_fcp_prio = start;
753 break;
754 case FLT_REG_BOOT_CODE_82XX:
755 ha->flt_region_boot = start;
756 break;
757 case FLT_REG_FW_82XX:
758 ha->flt_region_fw = start;
759 break;
760 case FLT_REG_GOLD_FW_82XX:
761 ha->flt_region_gold_fw = start;
762 break;
763 case FLT_REG_BOOTLOAD_82XX:
764 ha->flt_region_bootload = start;
765 break;
766 case FLT_REG_VPD_82XX:
767 ha->flt_region_vpd = start;
768 break;
769 }
770 }
771 goto done;
772
773no_flash_data:
774
775 loc = locations[0];
776 def = 0;
777 if (IS_QLA24XX_TYPE(ha))
778 def = 0;
779 else if (IS_QLA25XX(ha))
780 def = 1;
781 else if (IS_QLA81XX(ha))
782 def = 2;
783 ha->flt_region_fw = def_fw[def];
784 ha->flt_region_boot = def_boot[def];
785 ha->flt_region_vpd_nvram = def_vpd_nvram[def];
786 ha->flt_region_vpd = ha->flags.port0 ?
787 def_vpd0[def] : def_vpd1[def];
788 ha->flt_region_nvram = ha->flags.port0 ?
789 def_nvram0[def] : def_nvram1[def];
790 ha->flt_region_fdt = def_fdt[def];
791 ha->flt_region_npiv_conf = ha->flags.port0 ?
792 def_npiv_conf0[def] : def_npiv_conf1[def];
793 ha->flt_region_fcp_prio = ha->flags.port0 ?
794 fcp_prio_cfg0[def] : fcp_prio_cfg1[def];
795done:
796 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x "
797 "vpd_nvram=0x%x vpd=0x%x nvram=0x%x fdt=0x%x flt=0x%x "
798 "npiv=0x%x.\n", loc, ha->flt_region_boot, ha->flt_region_fw,
799 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram,
800 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf));
801}
802
803static void
804qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
805{
806#define FLASH_BLK_SIZE_4K 0x1000
807#define FLASH_BLK_SIZE_32K 0x8000
808#define FLASH_BLK_SIZE_64K 0x10000
809 const char *loc, *locations[] = { "MID", "FDT" };
810 uint16_t cnt, chksum;
811 uint16_t *wptr;
812 struct qla_fdt_layout *fdt;
813 uint8_t man_id, flash_id;
814 uint16_t mid = 0, fid = 0;
815 struct qla_hw_data *ha = vha->hw;
816 struct req_que *req = ha->req_q_map[0];
817
818 wptr = (uint16_t *)req->ring;
819 fdt = (struct qla_fdt_layout *)req->ring;
820 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
821 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
822 if (*wptr == __constant_cpu_to_le16(0xffff))
823 goto no_flash_data;
824 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
825 fdt->sig[3] != 'D')
826 goto no_flash_data;
827
828 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
829 cnt++)
830 chksum += le16_to_cpu(*wptr++);
831 if (chksum) {
832 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
833 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
834 le16_to_cpu(fdt->version)));
835 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
836 goto no_flash_data;
837 }
838
839 loc = locations[1];
840 mid = le16_to_cpu(fdt->man_id);
841 fid = le16_to_cpu(fdt->id);
842 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
843 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
844 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
845 if (fdt->unprotect_sec_cmd) {
846 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
847 fdt->unprotect_sec_cmd);
848 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
849 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
850 flash_conf_addr(ha, 0x0336);
851 }
852 goto done;
853no_flash_data:
854 loc = locations[0];
855 if (IS_QLA82XX(ha)) {
856 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
857 goto done;
858 }
859 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
860 mid = man_id;
861 fid = flash_id;
862 ha->fdt_wrt_disable = 0x9c;
863 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
864 switch (man_id) {
865 case 0xbf:
866 if (flash_id == 0x8e)
867 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
868 else
869 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
870
871 if (flash_id == 0x80)
872 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
873 break;
874 case 0x13:
875 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
876 break;
877 case 0x1f:
878 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
879 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
880 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
881 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
882 break;
883 default:
884
885 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
886 break;
887 }
888done:
889 DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
890 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
891 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
892 ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable,
893 ha->fdt_block_size));
894}
895
896static void
897qla2xxx_get_idc_param(scsi_qla_host_t *vha)
898{
899#define QLA82XX_IDC_PARAM_ADDR 0x003e885c
900 uint32_t *wptr;
901 struct qla_hw_data *ha = vha->hw;
902 struct req_que *req = ha->req_q_map[0];
903
904 if (!IS_QLA82XX(ha))
905 return;
906
907 wptr = (uint32_t *)req->ring;
908 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
909 QLA82XX_IDC_PARAM_ADDR , 8);
910
911 if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
912 ha->nx_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT;
913 ha->nx_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT;
914 } else {
915 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
916 ha->nx_reset_timeout = le32_to_cpu(*wptr);
917 }
918 return;
919}
920
921int
922qla2xxx_get_flash_info(scsi_qla_host_t *vha)
923{
924 int ret;
925 uint32_t flt_addr;
926 struct qla_hw_data *ha = vha->hw;
927
928 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA8XXX_TYPE(ha))
929 return QLA_SUCCESS;
930
931 ret = qla2xxx_find_flt_start(vha, &flt_addr);
932 if (ret != QLA_SUCCESS)
933 return ret;
934
935 qla2xxx_get_flt_info(vha, flt_addr);
936 qla2xxx_get_fdt_info(vha);
937 qla2xxx_get_idc_param(vha);
938
939 return QLA_SUCCESS;
940}
941
942void
943qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
944{
945#define NPIV_CONFIG_SIZE (16*1024)
946 void *data;
947 uint16_t *wptr;
948 uint16_t cnt, chksum;
949 int i;
950 struct qla_npiv_header hdr;
951 struct qla_npiv_entry *entry;
952 struct qla_hw_data *ha = vha->hw;
953
954 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA8XXX_TYPE(ha))
955 return;
956
957 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
958 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
959 if (hdr.version == __constant_cpu_to_le16(0xffff))
960 return;
961 if (hdr.version != __constant_cpu_to_le16(1)) {
962 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config "
963 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
964 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
965 le16_to_cpu(hdr.checksum)));
966 return;
967 }
968
969 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
970 if (!data) {
971 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to "
972 "allocate memory.\n"));
973 return;
974 }
975
976 ha->isp_ops->read_optrom(vha, (uint8_t *)data,
977 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
978
979 cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
980 sizeof(struct qla_npiv_entry)) >> 1;
981 for (wptr = data, chksum = 0; cnt; cnt--)
982 chksum += le16_to_cpu(*wptr++);
983 if (chksum) {
984 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config "
985 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
986 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
987 chksum));
988 goto done;
989 }
990
991 entry = data + sizeof(struct qla_npiv_header);
992 cnt = le16_to_cpu(hdr.entries);
993 for (i = 0; cnt; cnt--, entry++, i++) {
994 uint16_t flags;
995 struct fc_vport_identifiers vid;
996 struct fc_vport *vport;
997
998 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
999
1000 flags = le16_to_cpu(entry->flags);
1001 if (flags == 0xffff)
1002 continue;
1003 if ((flags & BIT_0) == 0)
1004 continue;
1005
1006 memset(&vid, 0, sizeof(vid));
1007 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
1008 vid.vport_type = FC_PORTTYPE_NPIV;
1009 vid.disable = false;
1010 vid.port_name = wwn_to_u64(entry->port_name);
1011 vid.node_name = wwn_to_u64(entry->node_name);
1012
1013 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV[%02x]: wwpn=%llx "
1014 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
1015 (unsigned long long)vid.port_name,
1016 (unsigned long long)vid.node_name,
1017 le16_to_cpu(entry->vf_id),
1018 entry->q_qos, entry->f_qos));
1019
1020 if (i < QLA_PRECONFIG_VPORTS) {
1021 vport = fc_vport_create(vha->host, 0, &vid);
1022 if (!vport)
1023 qla_printk(KERN_INFO, ha,
1024 "NPIV-Config: Failed to create vport [%02x]: "
1025 "wwpn=%llx wwnn=%llx.\n", cnt,
1026 (unsigned long long)vid.port_name,
1027 (unsigned long long)vid.node_name);
1028 }
1029 }
1030done:
1031 kfree(data);
1032}
1033
1034static int
1035qla24xx_unprotect_flash(scsi_qla_host_t *vha)
1036{
1037 struct qla_hw_data *ha = vha->hw;
1038 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1039
1040 if (ha->flags.fac_supported)
1041 return qla81xx_fac_do_write_enable(vha, 1);
1042
1043
1044 WRT_REG_DWORD(®->ctrl_status,
1045 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE);
1046 RD_REG_DWORD(®->ctrl_status);
1047
1048 if (!ha->fdt_wrt_disable)
1049 goto done;
1050
1051
1052 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1053
1054 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1055done:
1056 return QLA_SUCCESS;
1057}
1058
1059static int
1060qla24xx_protect_flash(scsi_qla_host_t *vha)
1061{
1062 uint32_t cnt;
1063 struct qla_hw_data *ha = vha->hw;
1064 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1065
1066 if (ha->flags.fac_supported)
1067 return qla81xx_fac_do_write_enable(vha, 0);
1068
1069 if (!ha->fdt_wrt_disable)
1070 goto skip_wrt_protect;
1071
1072
1073 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
1074 ha->fdt_wrt_disable);
1075 for (cnt = 300; cnt &&
1076 qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
1077 cnt--) {
1078 udelay(10);
1079 }
1080
1081skip_wrt_protect:
1082
1083 WRT_REG_DWORD(®->ctrl_status,
1084 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
1085 RD_REG_DWORD(®->ctrl_status);
1086
1087 return QLA_SUCCESS;
1088}
1089
1090static int
1091qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1092{
1093 struct qla_hw_data *ha = vha->hw;
1094 uint32_t start, finish;
1095
1096 if (ha->flags.fac_supported) {
1097 start = fdata >> 2;
1098 finish = start + (ha->fdt_block_size >> 2) - 1;
1099 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1100 start), flash_data_addr(ha, finish));
1101 }
1102
1103 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1104 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1105 ((fdata >> 16) & 0xff));
1106}
1107
1108static int
1109qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
1110 uint32_t dwords)
1111{
1112 int ret;
1113 uint32_t liter;
1114 uint32_t sec_mask, rest_addr;
1115 uint32_t fdata;
1116 dma_addr_t optrom_dma;
1117 void *optrom = NULL;
1118 struct qla_hw_data *ha = vha->hw;
1119
1120
1121 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && !(faddr & 0xfff) &&
1122 dwords > OPTROM_BURST_DWORDS) {
1123 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1124 &optrom_dma, GFP_KERNEL);
1125 if (!optrom) {
1126 qla_printk(KERN_DEBUG, ha,
1127 "Unable to allocate memory for optrom burst write "
1128 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
1129 }
1130 }
1131
1132 rest_addr = (ha->fdt_block_size >> 2) - 1;
1133 sec_mask = ~rest_addr;
1134
1135 ret = qla24xx_unprotect_flash(vha);
1136 if (ret != QLA_SUCCESS) {
1137 qla_printk(KERN_WARNING, ha,
1138 "Unable to unprotect flash for update.\n");
1139 goto done;
1140 }
1141
1142 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1143 fdata = (faddr & sec_mask) << 2;
1144
1145
1146 if ((faddr & rest_addr) == 0) {
1147
1148 if (ha->fdt_unprotect_sec_cmd)
1149 qla24xx_write_flash_dword(ha,
1150 ha->fdt_unprotect_sec_cmd,
1151 (fdata & 0xff00) | ((fdata << 16) &
1152 0xff0000) | ((fdata >> 16) & 0xff));
1153 ret = qla24xx_erase_sector(vha, fdata);
1154 if (ret != QLA_SUCCESS) {
1155 DEBUG9(qla_printk(KERN_WARNING, ha,
1156 "Unable to erase sector: address=%x.\n",
1157 faddr));
1158 break;
1159 }
1160 }
1161
1162
1163 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1164
1165 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
1166
1167 ret = qla2x00_load_ram(vha, optrom_dma,
1168 flash_data_addr(ha, faddr),
1169 OPTROM_BURST_DWORDS);
1170 if (ret != QLA_SUCCESS) {
1171 qla_printk(KERN_WARNING, ha,
1172 "Unable to burst-write optrom segment "
1173 "(%x/%x/%llx).\n", ret,
1174 flash_data_addr(ha, faddr),
1175 (unsigned long long)optrom_dma);
1176 qla_printk(KERN_WARNING, ha,
1177 "Reverting to slow-write.\n");
1178
1179 dma_free_coherent(&ha->pdev->dev,
1180 OPTROM_BURST_SIZE, optrom, optrom_dma);
1181 optrom = NULL;
1182 } else {
1183 liter += OPTROM_BURST_DWORDS - 1;
1184 faddr += OPTROM_BURST_DWORDS - 1;
1185 dwptr += OPTROM_BURST_DWORDS - 1;
1186 continue;
1187 }
1188 }
1189
1190 ret = qla24xx_write_flash_dword(ha,
1191 flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
1192 if (ret != QLA_SUCCESS) {
1193 DEBUG9(printk("%s(%ld) Unable to program flash "
1194 "address=%x data=%x.\n", __func__,
1195 vha->host_no, faddr, *dwptr));
1196 break;
1197 }
1198
1199
1200 if (ha->fdt_unprotect_sec_cmd &&
1201 ((faddr & rest_addr) == rest_addr))
1202 qla24xx_write_flash_dword(ha,
1203 ha->fdt_protect_sec_cmd,
1204 (fdata & 0xff00) | ((fdata << 16) &
1205 0xff0000) | ((fdata >> 16) & 0xff));
1206 }
1207
1208 ret = qla24xx_protect_flash(vha);
1209 if (ret != QLA_SUCCESS)
1210 qla_printk(KERN_WARNING, ha,
1211 "Unable to protect flash after update.\n");
1212done:
1213 if (optrom)
1214 dma_free_coherent(&ha->pdev->dev,
1215 OPTROM_BURST_SIZE, optrom, optrom_dma);
1216
1217 return ret;
1218}
1219
1220uint8_t *
1221qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1222 uint32_t bytes)
1223{
1224 uint32_t i;
1225 uint16_t *wptr;
1226 struct qla_hw_data *ha = vha->hw;
1227
1228
1229 wptr = (uint16_t *)buf;
1230 qla2x00_lock_nvram_access(ha);
1231 for (i = 0; i < bytes >> 1; i++, naddr++)
1232 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1233 naddr));
1234 qla2x00_unlock_nvram_access(ha);
1235
1236 return buf;
1237}
1238
1239uint8_t *
1240qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1241 uint32_t bytes)
1242{
1243 uint32_t i;
1244 uint32_t *dwptr;
1245 struct qla_hw_data *ha = vha->hw;
1246
1247 if (IS_QLA82XX(ha))
1248 return buf;
1249
1250
1251 dwptr = (uint32_t *)buf;
1252 for (i = 0; i < bytes >> 2; i++, naddr++)
1253 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1254 nvram_data_addr(ha, naddr)));
1255
1256 return buf;
1257}
1258
1259int
1260qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1261 uint32_t bytes)
1262{
1263 int ret, stat;
1264 uint32_t i;
1265 uint16_t *wptr;
1266 unsigned long flags;
1267 struct qla_hw_data *ha = vha->hw;
1268
1269 ret = QLA_SUCCESS;
1270
1271 spin_lock_irqsave(&ha->hardware_lock, flags);
1272 qla2x00_lock_nvram_access(ha);
1273
1274
1275 stat = qla2x00_clear_nvram_protection(ha);
1276
1277 wptr = (uint16_t *)buf;
1278 for (i = 0; i < bytes >> 1; i++, naddr++) {
1279 qla2x00_write_nvram_word(ha, naddr,
1280 cpu_to_le16(*wptr));
1281 wptr++;
1282 }
1283
1284
1285 qla2x00_set_nvram_protection(ha, stat);
1286
1287 qla2x00_unlock_nvram_access(ha);
1288 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1289
1290 return ret;
1291}
1292
1293int
1294qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1295 uint32_t bytes)
1296{
1297 int ret;
1298 uint32_t i;
1299 uint32_t *dwptr;
1300 struct qla_hw_data *ha = vha->hw;
1301 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1302
1303 ret = QLA_SUCCESS;
1304
1305 if (IS_QLA82XX(ha))
1306 return ret;
1307
1308
1309 WRT_REG_DWORD(®->ctrl_status,
1310 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE);
1311 RD_REG_DWORD(®->ctrl_status);
1312
1313
1314 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1315 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1316
1317
1318 dwptr = (uint32_t *)buf;
1319 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1320 ret = qla24xx_write_flash_dword(ha,
1321 nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
1322 if (ret != QLA_SUCCESS) {
1323 DEBUG9(qla_printk(KERN_WARNING, ha,
1324 "Unable to program nvram address=%x data=%x.\n",
1325 naddr, *dwptr));
1326 break;
1327 }
1328 }
1329
1330
1331 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1332
1333
1334 WRT_REG_DWORD(®->ctrl_status,
1335 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
1336 RD_REG_DWORD(®->ctrl_status);
1337
1338 return ret;
1339}
1340
1341uint8_t *
1342qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1343 uint32_t bytes)
1344{
1345 uint32_t i;
1346 uint32_t *dwptr;
1347 struct qla_hw_data *ha = vha->hw;
1348
1349
1350 dwptr = (uint32_t *)buf;
1351 for (i = 0; i < bytes >> 2; i++, naddr++)
1352 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1353 flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
1354
1355 return buf;
1356}
1357
1358int
1359qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1360 uint32_t bytes)
1361{
1362 struct qla_hw_data *ha = vha->hw;
1363#define RMW_BUFFER_SIZE (64 * 1024)
1364 uint8_t *dbuf;
1365
1366 dbuf = vmalloc(RMW_BUFFER_SIZE);
1367 if (!dbuf)
1368 return QLA_MEMORY_ALLOC_FAILED;
1369 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1370 RMW_BUFFER_SIZE);
1371 memcpy(dbuf + (naddr << 2), buf, bytes);
1372 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1373 RMW_BUFFER_SIZE);
1374 vfree(dbuf);
1375
1376 return QLA_SUCCESS;
1377}
1378
1379static inline void
1380qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1381{
1382 if (IS_QLA2322(ha)) {
1383
1384 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1385
1386 ha->beacon_color_state = 0;
1387 *pflags = GPIO_LED_ALL_OFF;
1388 } else {
1389
1390 ha->beacon_color_state = QLA_LED_ALL_ON;
1391 *pflags = GPIO_LED_RGA_ON;
1392 }
1393 } else {
1394
1395 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1396
1397 ha->beacon_color_state = 0;
1398 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1399 } else {
1400
1401 ha->beacon_color_state = QLA_LED_GRN_ON;
1402 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1403 }
1404 }
1405}
1406
1407#define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1408
1409void
1410qla2x00_beacon_blink(struct scsi_qla_host *vha)
1411{
1412 uint16_t gpio_enable;
1413 uint16_t gpio_data;
1414 uint16_t led_color = 0;
1415 unsigned long flags;
1416 struct qla_hw_data *ha = vha->hw;
1417 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1418
1419 if (IS_QLA82XX(ha))
1420 return;
1421
1422 spin_lock_irqsave(&ha->hardware_lock, flags);
1423
1424
1425 if (ha->pio_address) {
1426 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1427 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1428 } else {
1429 gpio_enable = RD_REG_WORD(®->gpioe);
1430 gpio_data = RD_REG_WORD(®->gpiod);
1431 }
1432
1433
1434 gpio_enable |= GPIO_LED_MASK;
1435
1436 if (ha->pio_address) {
1437 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1438 } else {
1439 WRT_REG_WORD(®->gpioe, gpio_enable);
1440 RD_REG_WORD(®->gpioe);
1441 }
1442
1443 qla2x00_flip_colors(ha, &led_color);
1444
1445
1446 gpio_data &= ~GPIO_LED_MASK;
1447
1448
1449 gpio_data |= led_color;
1450
1451
1452 if (ha->pio_address) {
1453 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1454 } else {
1455 WRT_REG_WORD(®->gpiod, gpio_data);
1456 RD_REG_WORD(®->gpiod);
1457 }
1458
1459 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1460}
1461
1462int
1463qla2x00_beacon_on(struct scsi_qla_host *vha)
1464{
1465 uint16_t gpio_enable;
1466 uint16_t gpio_data;
1467 unsigned long flags;
1468 struct qla_hw_data *ha = vha->hw;
1469 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1470
1471 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1472 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1473
1474 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1475 qla_printk(KERN_WARNING, ha,
1476 "Unable to update fw options (beacon on).\n");
1477 return QLA_FUNCTION_FAILED;
1478 }
1479
1480
1481 spin_lock_irqsave(&ha->hardware_lock, flags);
1482 if (ha->pio_address) {
1483 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1484 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1485 } else {
1486 gpio_enable = RD_REG_WORD(®->gpioe);
1487 gpio_data = RD_REG_WORD(®->gpiod);
1488 }
1489 gpio_enable |= GPIO_LED_MASK;
1490
1491
1492 if (ha->pio_address) {
1493 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1494 } else {
1495 WRT_REG_WORD(®->gpioe, gpio_enable);
1496 RD_REG_WORD(®->gpioe);
1497 }
1498
1499
1500 gpio_data &= ~GPIO_LED_MASK;
1501 if (ha->pio_address) {
1502 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1503 } else {
1504 WRT_REG_WORD(®->gpiod, gpio_data);
1505 RD_REG_WORD(®->gpiod);
1506 }
1507 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1508
1509
1510
1511
1512
1513 ha->beacon_blink_led = 1;
1514 ha->beacon_color_state = 0;
1515
1516 return QLA_SUCCESS;
1517}
1518
1519int
1520qla2x00_beacon_off(struct scsi_qla_host *vha)
1521{
1522 int rval = QLA_SUCCESS;
1523 struct qla_hw_data *ha = vha->hw;
1524
1525 ha->beacon_blink_led = 0;
1526
1527
1528 if (IS_QLA2322(ha))
1529 ha->beacon_color_state = QLA_LED_ALL_ON;
1530 else
1531 ha->beacon_color_state = QLA_LED_GRN_ON;
1532
1533 ha->isp_ops->beacon_blink(vha);
1534
1535 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1536 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1537
1538 rval = qla2x00_set_fw_options(vha, ha->fw_options);
1539 if (rval != QLA_SUCCESS)
1540 qla_printk(KERN_WARNING, ha,
1541 "Unable to update fw options (beacon off).\n");
1542 return rval;
1543}
1544
1545
1546static inline void
1547qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1548{
1549
1550 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1551
1552 ha->beacon_color_state = 0;
1553 *pflags = 0;
1554 } else {
1555
1556 ha->beacon_color_state = QLA_LED_ALL_ON;
1557 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1558 }
1559}
1560
1561void
1562qla24xx_beacon_blink(struct scsi_qla_host *vha)
1563{
1564 uint16_t led_color = 0;
1565 uint32_t gpio_data;
1566 unsigned long flags;
1567 struct qla_hw_data *ha = vha->hw;
1568 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1569
1570
1571 spin_lock_irqsave(&ha->hardware_lock, flags);
1572 gpio_data = RD_REG_DWORD(®->gpiod);
1573
1574
1575 gpio_data |= GPDX_LED_UPDATE_MASK;
1576
1577 WRT_REG_DWORD(®->gpiod, gpio_data);
1578 gpio_data = RD_REG_DWORD(®->gpiod);
1579
1580
1581 qla24xx_flip_colors(ha, &led_color);
1582
1583
1584 gpio_data &= ~GPDX_LED_COLOR_MASK;
1585
1586
1587 gpio_data |= led_color;
1588
1589
1590 WRT_REG_DWORD(®->gpiod, gpio_data);
1591 gpio_data = RD_REG_DWORD(®->gpiod);
1592 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1593}
1594
1595int
1596qla24xx_beacon_on(struct scsi_qla_host *vha)
1597{
1598 uint32_t gpio_data;
1599 unsigned long flags;
1600 struct qla_hw_data *ha = vha->hw;
1601 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1602
1603 if (IS_QLA82XX(ha))
1604 return QLA_SUCCESS;
1605
1606 if (ha->beacon_blink_led == 0) {
1607
1608 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1609
1610 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1611 return QLA_FUNCTION_FAILED;
1612
1613 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1614 QLA_SUCCESS) {
1615 qla_printk(KERN_WARNING, ha,
1616 "Unable to update fw options (beacon on).\n");
1617 return QLA_FUNCTION_FAILED;
1618 }
1619
1620 spin_lock_irqsave(&ha->hardware_lock, flags);
1621 gpio_data = RD_REG_DWORD(®->gpiod);
1622
1623
1624 gpio_data |= GPDX_LED_UPDATE_MASK;
1625 WRT_REG_DWORD(®->gpiod, gpio_data);
1626 RD_REG_DWORD(®->gpiod);
1627
1628 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1629 }
1630
1631
1632 ha->beacon_color_state = 0;
1633
1634
1635 ha->beacon_blink_led = 1;
1636
1637 return QLA_SUCCESS;
1638}
1639
1640int
1641qla24xx_beacon_off(struct scsi_qla_host *vha)
1642{
1643 uint32_t gpio_data;
1644 unsigned long flags;
1645 struct qla_hw_data *ha = vha->hw;
1646 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1647
1648 if (IS_QLA82XX(ha))
1649 return QLA_SUCCESS;
1650
1651 ha->beacon_blink_led = 0;
1652 ha->beacon_color_state = QLA_LED_ALL_ON;
1653
1654 ha->isp_ops->beacon_blink(vha);
1655
1656
1657 spin_lock_irqsave(&ha->hardware_lock, flags);
1658 gpio_data = RD_REG_DWORD(®->gpiod);
1659
1660
1661 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1662 WRT_REG_DWORD(®->gpiod, gpio_data);
1663 RD_REG_DWORD(®->gpiod);
1664 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1665
1666 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1667
1668 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1669 qla_printk(KERN_WARNING, ha,
1670 "Unable to update fw options (beacon off).\n");
1671 return QLA_FUNCTION_FAILED;
1672 }
1673
1674 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1675 qla_printk(KERN_WARNING, ha,
1676 "Unable to get fw options (beacon off).\n");
1677 return QLA_FUNCTION_FAILED;
1678 }
1679
1680 return QLA_SUCCESS;
1681}
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692static void
1693qla2x00_flash_enable(struct qla_hw_data *ha)
1694{
1695 uint16_t data;
1696 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1697
1698 data = RD_REG_WORD(®->ctrl_status);
1699 data |= CSR_FLASH_ENABLE;
1700 WRT_REG_WORD(®->ctrl_status, data);
1701 RD_REG_WORD(®->ctrl_status);
1702}
1703
1704
1705
1706
1707
1708static void
1709qla2x00_flash_disable(struct qla_hw_data *ha)
1710{
1711 uint16_t data;
1712 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1713
1714 data = RD_REG_WORD(®->ctrl_status);
1715 data &= ~(CSR_FLASH_ENABLE);
1716 WRT_REG_WORD(®->ctrl_status, data);
1717 RD_REG_WORD(®->ctrl_status);
1718}
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729static uint8_t
1730qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
1731{
1732 uint16_t data;
1733 uint16_t bank_select;
1734 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1735
1736 bank_select = RD_REG_WORD(®->ctrl_status);
1737
1738 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1739
1740
1741 bank_select &= ~0xf8;
1742 bank_select |= addr >> 12 & 0xf0;
1743 bank_select |= CSR_FLASH_64K_BANK;
1744 WRT_REG_WORD(®->ctrl_status, bank_select);
1745 RD_REG_WORD(®->ctrl_status);
1746
1747 WRT_REG_WORD(®->flash_address, (uint16_t)addr);
1748 data = RD_REG_WORD(®->flash_data);
1749
1750 return (uint8_t)data;
1751 }
1752
1753
1754 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1755 bank_select |= CSR_FLASH_64K_BANK;
1756 WRT_REG_WORD(®->ctrl_status, bank_select);
1757 RD_REG_WORD(®->ctrl_status);
1758 } else if (((addr & BIT_16) == 0) &&
1759 (bank_select & CSR_FLASH_64K_BANK)) {
1760 bank_select &= ~(CSR_FLASH_64K_BANK);
1761 WRT_REG_WORD(®->ctrl_status, bank_select);
1762 RD_REG_WORD(®->ctrl_status);
1763 }
1764
1765
1766 if (ha->pio_address) {
1767 uint16_t data2;
1768
1769 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1770 do {
1771 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1772 barrier();
1773 cpu_relax();
1774 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1775 } while (data != data2);
1776 } else {
1777 WRT_REG_WORD(®->flash_address, (uint16_t)addr);
1778 data = qla2x00_debounce_register(®->flash_data);
1779 }
1780
1781 return (uint8_t)data;
1782}
1783
1784
1785
1786
1787
1788
1789
1790static void
1791qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
1792{
1793 uint16_t bank_select;
1794 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1795
1796 bank_select = RD_REG_WORD(®->ctrl_status);
1797 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1798
1799
1800 bank_select &= ~0xf8;
1801 bank_select |= addr >> 12 & 0xf0;
1802 bank_select |= CSR_FLASH_64K_BANK;
1803 WRT_REG_WORD(®->ctrl_status, bank_select);
1804 RD_REG_WORD(®->ctrl_status);
1805
1806 WRT_REG_WORD(®->flash_address, (uint16_t)addr);
1807 RD_REG_WORD(®->ctrl_status);
1808 WRT_REG_WORD(®->flash_data, (uint16_t)data);
1809 RD_REG_WORD(®->ctrl_status);
1810
1811 return;
1812 }
1813
1814
1815 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1816 bank_select |= CSR_FLASH_64K_BANK;
1817 WRT_REG_WORD(®->ctrl_status, bank_select);
1818 RD_REG_WORD(®->ctrl_status);
1819 } else if (((addr & BIT_16) == 0) &&
1820 (bank_select & CSR_FLASH_64K_BANK)) {
1821 bank_select &= ~(CSR_FLASH_64K_BANK);
1822 WRT_REG_WORD(®->ctrl_status, bank_select);
1823 RD_REG_WORD(®->ctrl_status);
1824 }
1825
1826
1827 if (ha->pio_address) {
1828 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1829 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1830 } else {
1831 WRT_REG_WORD(®->flash_address, (uint16_t)addr);
1832 RD_REG_WORD(®->ctrl_status);
1833 WRT_REG_WORD(®->flash_data, (uint16_t)data);
1834 RD_REG_WORD(®->ctrl_status);
1835 }
1836}
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853static int
1854qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
1855 uint8_t man_id, uint8_t flash_id)
1856{
1857 int status;
1858 uint8_t flash_data;
1859 uint32_t cnt;
1860
1861 status = 1;
1862
1863
1864 poll_data &= BIT_7;
1865 for (cnt = 3000000; cnt; cnt--) {
1866 flash_data = qla2x00_read_flash_byte(ha, addr);
1867 if ((flash_data & BIT_7) == poll_data) {
1868 status = 0;
1869 break;
1870 }
1871
1872 if (man_id != 0x40 && man_id != 0xda) {
1873 if ((flash_data & BIT_5) && cnt > 2)
1874 cnt = 2;
1875 }
1876 udelay(10);
1877 barrier();
1878 cond_resched();
1879 }
1880 return status;
1881}
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893static int
1894qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
1895 uint8_t data, uint8_t man_id, uint8_t flash_id)
1896{
1897
1898 if (IS_OEM_001(ha)) {
1899 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1900 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1901 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1902 qla2x00_write_flash_byte(ha, addr, data);
1903 } else {
1904 if (man_id == 0xda && flash_id == 0xc1) {
1905 qla2x00_write_flash_byte(ha, addr, data);
1906 if (addr & 0x7e)
1907 return 0;
1908 } else {
1909 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1910 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1911 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1912 qla2x00_write_flash_byte(ha, addr, data);
1913 }
1914 }
1915
1916 udelay(150);
1917
1918
1919 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1920}
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930static int
1931qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
1932{
1933
1934 if (IS_OEM_001(ha)) {
1935 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1936 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1937 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1938 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1939 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1940 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1941 } else {
1942 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1943 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1944 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1945 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1946 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1947 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1948 }
1949
1950 udelay(150);
1951
1952
1953 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1954}
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966static int
1967qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
1968 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1969{
1970
1971 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1972 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1973 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1974 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1975 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1976 if (man_id == 0x1f && flash_id == 0x13)
1977 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1978 else
1979 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1980
1981 udelay(150);
1982
1983
1984 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1985}
1986
1987
1988
1989
1990
1991
1992static void
1993qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
1994 uint8_t *flash_id)
1995{
1996 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1997 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1998 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1999 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
2000 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
2001 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2002 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2003 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
2004}
2005
2006static void
2007qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
2008 uint32_t saddr, uint32_t length)
2009{
2010 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2011 uint32_t midpoint, ilength;
2012 uint8_t data;
2013
2014 midpoint = length / 2;
2015
2016 WRT_REG_WORD(®->nvram, 0);
2017 RD_REG_WORD(®->nvram);
2018 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
2019 if (ilength == midpoint) {
2020 WRT_REG_WORD(®->nvram, NVR_SELECT);
2021 RD_REG_WORD(®->nvram);
2022 }
2023 data = qla2x00_read_flash_byte(ha, saddr);
2024 if (saddr % 100)
2025 udelay(10);
2026 *tmp_buf = data;
2027 cond_resched();
2028 }
2029}
2030
2031static inline void
2032qla2x00_suspend_hba(struct scsi_qla_host *vha)
2033{
2034 int cnt;
2035 unsigned long flags;
2036 struct qla_hw_data *ha = vha->hw;
2037 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2038
2039
2040 scsi_block_requests(vha->host);
2041 ha->isp_ops->disable_intrs(ha);
2042 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2043
2044
2045 spin_lock_irqsave(&ha->hardware_lock, flags);
2046 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
2047 RD_REG_WORD(®->hccr);
2048 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2049 for (cnt = 0; cnt < 30000; cnt++) {
2050 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0)
2051 break;
2052 udelay(100);
2053 }
2054 } else {
2055 udelay(10);
2056 }
2057 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2058}
2059
2060static inline void
2061qla2x00_resume_hba(struct scsi_qla_host *vha)
2062{
2063 struct qla_hw_data *ha = vha->hw;
2064
2065
2066 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2067 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2068 qla2xxx_wake_dpc(vha);
2069 qla2x00_wait_for_chip_reset(vha);
2070 scsi_unblock_requests(vha->host);
2071}
2072
2073uint8_t *
2074qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2075 uint32_t offset, uint32_t length)
2076{
2077 uint32_t addr, midpoint;
2078 uint8_t *data;
2079 struct qla_hw_data *ha = vha->hw;
2080 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2081
2082
2083 qla2x00_suspend_hba(vha);
2084
2085
2086 midpoint = ha->optrom_size / 2;
2087
2088 qla2x00_flash_enable(ha);
2089 WRT_REG_WORD(®->nvram, 0);
2090 RD_REG_WORD(®->nvram);
2091 for (addr = offset, data = buf; addr < length; addr++, data++) {
2092 if (addr == midpoint) {
2093 WRT_REG_WORD(®->nvram, NVR_SELECT);
2094 RD_REG_WORD(®->nvram);
2095 }
2096
2097 *data = qla2x00_read_flash_byte(ha, addr);
2098 }
2099 qla2x00_flash_disable(ha);
2100
2101
2102 qla2x00_resume_hba(vha);
2103
2104 return buf;
2105}
2106
2107int
2108qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2109 uint32_t offset, uint32_t length)
2110{
2111
2112 int rval;
2113 uint8_t man_id, flash_id, sec_number, data;
2114 uint16_t wd;
2115 uint32_t addr, liter, sec_mask, rest_addr;
2116 struct qla_hw_data *ha = vha->hw;
2117 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2118
2119
2120 qla2x00_suspend_hba(vha);
2121
2122 rval = QLA_SUCCESS;
2123 sec_number = 0;
2124
2125
2126 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
2127 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2128
2129
2130 qla2x00_flash_enable(ha);
2131 do {
2132
2133 if (IS_OEM_001(ha)) {
2134
2135 man_id = flash_id = 0;
2136 rest_addr = 0xffff;
2137 sec_mask = 0x10000;
2138 goto update_flash;
2139 }
2140 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2141 switch (man_id) {
2142 case 0x20:
2143 if (flash_id == 0xd2 || flash_id == 0xe3) {
2144
2145
2146
2147
2148
2149 rest_addr = 0xffff;
2150 sec_mask = 0x10000;
2151 break;
2152 }
2153
2154
2155
2156
2157 rest_addr = 0x3fff;
2158 sec_mask = 0x1c000;
2159 break;
2160 case 0x40:
2161
2162 rest_addr = 0x1ff;
2163 sec_mask = 0x1fe00;
2164 break;
2165 case 0xbf:
2166
2167 rest_addr = 0xfff;
2168 sec_mask = 0x1f000;
2169 break;
2170 case 0xda:
2171
2172 rest_addr = 0x7f;
2173 sec_mask = 0x1ff80;
2174 break;
2175 case 0xc2:
2176
2177 if (flash_id == 0x38 || flash_id == 0x4f) {
2178 rest_addr = 0xffff;
2179 sec_mask = 0x10000;
2180 break;
2181 }
2182
2183
2184 case 0x1f:
2185
2186 if (flash_id == 0x13) {
2187 rest_addr = 0x7fffffff;
2188 sec_mask = 0x80000000;
2189 break;
2190 }
2191
2192
2193 case 0x01:
2194 if (flash_id == 0x38 || flash_id == 0x40 ||
2195 flash_id == 0x4f) {
2196
2197
2198 rest_addr = 0xffff;
2199 sec_mask = 0x10000;
2200 break;
2201 } else if (flash_id == 0x3e) {
2202
2203
2204
2205
2206
2207 rest_addr = 0xffff;
2208 sec_mask = 0x10000;
2209 break;
2210 } else if (flash_id == 0x20 || flash_id == 0x6e) {
2211
2212
2213
2214
2215 rest_addr = 0x3fff;
2216 sec_mask = 0x1c000;
2217 break;
2218 } else if (flash_id == 0x6d) {
2219
2220 rest_addr = 0x1fff;
2221 sec_mask = 0x1e000;
2222 break;
2223 }
2224 default:
2225
2226 rest_addr = 0x3fff;
2227 sec_mask = 0x1c000;
2228 break;
2229 }
2230
2231update_flash:
2232 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2233 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2234 rval = QLA_FUNCTION_FAILED;
2235 break;
2236 }
2237 }
2238
2239 for (addr = offset, liter = 0; liter < length; liter++,
2240 addr++) {
2241 data = buf[liter];
2242
2243 if ((addr & rest_addr) == 0) {
2244 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2245 if (addr >= 0x10000UL) {
2246 if (((addr >> 12) & 0xf0) &&
2247 ((man_id == 0x01 &&
2248 flash_id == 0x3e) ||
2249 (man_id == 0x20 &&
2250 flash_id == 0xd2))) {
2251 sec_number++;
2252 if (sec_number == 1) {
2253 rest_addr =
2254 0x7fff;
2255 sec_mask =
2256 0x18000;
2257 } else if (
2258 sec_number == 2 ||
2259 sec_number == 3) {
2260 rest_addr =
2261 0x1fff;
2262 sec_mask =
2263 0x1e000;
2264 } else if (
2265 sec_number == 4) {
2266 rest_addr =
2267 0x3fff;
2268 sec_mask =
2269 0x1c000;
2270 }
2271 }
2272 }
2273 } else if (addr == ha->optrom_size / 2) {
2274 WRT_REG_WORD(®->nvram, NVR_SELECT);
2275 RD_REG_WORD(®->nvram);
2276 }
2277
2278 if (flash_id == 0xda && man_id == 0xc1) {
2279 qla2x00_write_flash_byte(ha, 0x5555,
2280 0xaa);
2281 qla2x00_write_flash_byte(ha, 0x2aaa,
2282 0x55);
2283 qla2x00_write_flash_byte(ha, 0x5555,
2284 0xa0);
2285 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2286
2287 if (qla2x00_erase_flash_sector(ha,
2288 addr, sec_mask, man_id,
2289 flash_id)) {
2290 rval = QLA_FUNCTION_FAILED;
2291 break;
2292 }
2293 if (man_id == 0x01 && flash_id == 0x6d)
2294 sec_number++;
2295 }
2296 }
2297
2298 if (man_id == 0x01 && flash_id == 0x6d) {
2299 if (sec_number == 1 &&
2300 addr == (rest_addr - 1)) {
2301 rest_addr = 0x0fff;
2302 sec_mask = 0x1f000;
2303 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2304 rest_addr = 0x3fff;
2305 sec_mask = 0x1c000;
2306 }
2307 }
2308
2309 if (qla2x00_program_flash_address(ha, addr, data,
2310 man_id, flash_id)) {
2311 rval = QLA_FUNCTION_FAILED;
2312 break;
2313 }
2314 cond_resched();
2315 }
2316 } while (0);
2317 qla2x00_flash_disable(ha);
2318
2319
2320 qla2x00_resume_hba(vha);
2321
2322 return rval;
2323}
2324
2325uint8_t *
2326qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2327 uint32_t offset, uint32_t length)
2328{
2329 struct qla_hw_data *ha = vha->hw;
2330
2331
2332 scsi_block_requests(vha->host);
2333 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2334
2335
2336 qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
2337
2338
2339 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2340 scsi_unblock_requests(vha->host);
2341
2342 return buf;
2343}
2344
2345int
2346qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2347 uint32_t offset, uint32_t length)
2348{
2349 int rval;
2350 struct qla_hw_data *ha = vha->hw;
2351
2352
2353 scsi_block_requests(vha->host);
2354 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2355
2356
2357 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2358 length >> 2);
2359
2360 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2361 scsi_unblock_requests(vha->host);
2362
2363 return rval;
2364}
2365
2366uint8_t *
2367qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2368 uint32_t offset, uint32_t length)
2369{
2370 int rval;
2371 dma_addr_t optrom_dma;
2372 void *optrom;
2373 uint8_t *pbuf;
2374 uint32_t faddr, left, burst;
2375 struct qla_hw_data *ha = vha->hw;
2376
2377 if (IS_QLA25XX(ha) || IS_QLA81XX(ha))
2378 goto try_fast;
2379 if (offset & 0xfff)
2380 goto slow_read;
2381 if (length < OPTROM_BURST_SIZE)
2382 goto slow_read;
2383
2384try_fast:
2385 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2386 &optrom_dma, GFP_KERNEL);
2387 if (!optrom) {
2388 qla_printk(KERN_DEBUG, ha,
2389 "Unable to allocate memory for optrom burst read "
2390 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
2391
2392 goto slow_read;
2393 }
2394
2395 pbuf = buf;
2396 faddr = offset >> 2;
2397 left = length >> 2;
2398 burst = OPTROM_BURST_DWORDS;
2399 while (left != 0) {
2400 if (burst > left)
2401 burst = left;
2402
2403 rval = qla2x00_dump_ram(vha, optrom_dma,
2404 flash_data_addr(ha, faddr), burst);
2405 if (rval) {
2406 qla_printk(KERN_WARNING, ha,
2407 "Unable to burst-read optrom segment "
2408 "(%x/%x/%llx).\n", rval,
2409 flash_data_addr(ha, faddr),
2410 (unsigned long long)optrom_dma);
2411 qla_printk(KERN_WARNING, ha,
2412 "Reverting to slow-read.\n");
2413
2414 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2415 optrom, optrom_dma);
2416 goto slow_read;
2417 }
2418
2419 memcpy(pbuf, optrom, burst * 4);
2420
2421 left -= burst;
2422 faddr += burst;
2423 pbuf += burst * 4;
2424 }
2425
2426 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2427 optrom_dma);
2428
2429 return buf;
2430
2431slow_read:
2432 return qla24xx_read_optrom_data(vha, buf, offset, length);
2433}
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453static void
2454qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
2455{
2456 int ret = QLA_FUNCTION_FAILED;
2457 uint32_t istart, iend, iter, vend;
2458 uint8_t do_next, rbyte, *vbyte;
2459
2460 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2461
2462
2463 istart = pcids +
2464 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2465 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2466 iend = istart + 0x100;
2467 do {
2468
2469 do_next = 0;
2470 iter = istart;
2471 while ((iter < iend) && !do_next) {
2472 iter++;
2473 if (qla2x00_read_flash_byte(ha, iter) == '/') {
2474 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2475 '/')
2476 do_next++;
2477 else if (qla2x00_read_flash_byte(ha,
2478 iter + 3) == '/')
2479 do_next++;
2480 }
2481 }
2482 if (!do_next)
2483 break;
2484
2485
2486 do_next = 0;
2487 while ((iter > istart) && !do_next) {
2488 iter--;
2489 if (qla2x00_read_flash_byte(ha, iter) == ' ')
2490 do_next++;
2491 }
2492 if (!do_next)
2493 break;
2494
2495
2496
2497
2498
2499 vend = iter - 1;
2500 do_next = 0;
2501 while ((iter > istart) && !do_next) {
2502 iter--;
2503 rbyte = qla2x00_read_flash_byte(ha, iter);
2504 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2505 do_next++;
2506 }
2507 if (!do_next)
2508 break;
2509
2510
2511 iter++;
2512 if ((vend - iter) &&
2513 ((vend - iter) < sizeof(ha->fcode_revision))) {
2514 vbyte = ha->fcode_revision;
2515 while (iter <= vend) {
2516 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2517 iter++;
2518 }
2519 ret = QLA_SUCCESS;
2520 }
2521 } while (0);
2522
2523 if (ret != QLA_SUCCESS)
2524 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2525}
2526
2527int
2528qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2529{
2530 int ret = QLA_SUCCESS;
2531 uint8_t code_type, last_image;
2532 uint32_t pcihdr, pcids;
2533 uint8_t *dbyte;
2534 uint16_t *dcode;
2535 struct qla_hw_data *ha = vha->hw;
2536
2537 if (!ha->pio_address || !mbuf)
2538 return QLA_FUNCTION_FAILED;
2539
2540 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2541 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2542 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2543 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2544
2545 qla2x00_flash_enable(ha);
2546
2547
2548 pcihdr = 0;
2549 last_image = 1;
2550 do {
2551
2552 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2553 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2554
2555 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2556 "signature.\n"));
2557 ret = QLA_FUNCTION_FAILED;
2558 break;
2559 }
2560
2561
2562 pcids = pcihdr +
2563 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2564 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2565
2566
2567 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2568 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2569 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2570 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2571
2572 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2573 "found pcir_adr=%x.\n", pcids));
2574 ret = QLA_FUNCTION_FAILED;
2575 break;
2576 }
2577
2578
2579 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2580 switch (code_type) {
2581 case ROM_CODE_TYPE_BIOS:
2582
2583 ha->bios_revision[0] =
2584 qla2x00_read_flash_byte(ha, pcids + 0x12);
2585 ha->bios_revision[1] =
2586 qla2x00_read_flash_byte(ha, pcids + 0x13);
2587 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2588 ha->bios_revision[1], ha->bios_revision[0]));
2589 break;
2590 case ROM_CODE_TYPE_FCODE:
2591
2592
2593 qla2x00_get_fcode_version(ha, pcids);
2594 break;
2595 case ROM_CODE_TYPE_EFI:
2596
2597 ha->efi_revision[0] =
2598 qla2x00_read_flash_byte(ha, pcids + 0x12);
2599 ha->efi_revision[1] =
2600 qla2x00_read_flash_byte(ha, pcids + 0x13);
2601 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2602 ha->efi_revision[1], ha->efi_revision[0]));
2603 break;
2604 default:
2605 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2606 "type %x at pcids %x.\n", code_type, pcids));
2607 break;
2608 }
2609
2610 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2611
2612
2613 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2614 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2615 } while (!last_image);
2616
2617 if (IS_QLA2322(ha)) {
2618
2619 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2620 dbyte = mbuf;
2621 memset(dbyte, 0, 8);
2622 dcode = (uint16_t *)dbyte;
2623
2624 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2625 8);
2626 DEBUG3(qla_printk(KERN_DEBUG, ha, "dumping fw ver from "
2627 "flash:\n"));
2628 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2629
2630 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2631 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2632 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2633 dcode[3] == 0)) {
2634 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2635 "revision at %x.\n", ha->flt_region_fw * 4));
2636 } else {
2637
2638 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2639 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2640 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2641 }
2642 }
2643
2644 qla2x00_flash_disable(ha);
2645
2646 return ret;
2647}
2648
2649int
2650qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2651{
2652 int ret = QLA_SUCCESS;
2653 uint32_t pcihdr, pcids;
2654 uint32_t *dcode;
2655 uint8_t *bcode;
2656 uint8_t code_type, last_image;
2657 int i;
2658 struct qla_hw_data *ha = vha->hw;
2659
2660 if (IS_QLA82XX(ha))
2661 return ret;
2662
2663 if (!mbuf)
2664 return QLA_FUNCTION_FAILED;
2665
2666 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2667 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2668 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2669 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2670
2671 dcode = mbuf;
2672
2673
2674 pcihdr = ha->flt_region_boot << 2;
2675 last_image = 1;
2676 do {
2677
2678 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
2679 bcode = mbuf + (pcihdr % 4);
2680 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2681
2682 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2683 "signature.\n"));
2684 ret = QLA_FUNCTION_FAILED;
2685 break;
2686 }
2687
2688
2689 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2690
2691 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
2692 bcode = mbuf + (pcihdr % 4);
2693
2694
2695 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2696 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2697
2698 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2699 "found pcir_adr=%x.\n", pcids));
2700 ret = QLA_FUNCTION_FAILED;
2701 break;
2702 }
2703
2704
2705 code_type = bcode[0x14];
2706 switch (code_type) {
2707 case ROM_CODE_TYPE_BIOS:
2708
2709 ha->bios_revision[0] = bcode[0x12];
2710 ha->bios_revision[1] = bcode[0x13];
2711 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2712 ha->bios_revision[1], ha->bios_revision[0]));
2713 break;
2714 case ROM_CODE_TYPE_FCODE:
2715
2716 ha->fcode_revision[0] = bcode[0x12];
2717 ha->fcode_revision[1] = bcode[0x13];
2718 DEBUG3(qla_printk(KERN_DEBUG, ha, "read FCODE %d.%d.\n",
2719 ha->fcode_revision[1], ha->fcode_revision[0]));
2720 break;
2721 case ROM_CODE_TYPE_EFI:
2722
2723 ha->efi_revision[0] = bcode[0x12];
2724 ha->efi_revision[1] = bcode[0x13];
2725 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2726 ha->efi_revision[1], ha->efi_revision[0]));
2727 break;
2728 default:
2729 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2730 "type %x at pcids %x.\n", code_type, pcids));
2731 break;
2732 }
2733
2734 last_image = bcode[0x15] & BIT_7;
2735
2736
2737 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2738 } while (!last_image);
2739
2740
2741 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2742 dcode = mbuf;
2743
2744 qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
2745 for (i = 0; i < 4; i++)
2746 dcode[i] = be32_to_cpu(dcode[i]);
2747
2748 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2749 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2750 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2751 dcode[3] == 0)) {
2752 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2753 "revision at %x.\n", ha->flt_region_fw * 4));
2754 } else {
2755 ha->fw_revision[0] = dcode[0];
2756 ha->fw_revision[1] = dcode[1];
2757 ha->fw_revision[2] = dcode[2];
2758 ha->fw_revision[3] = dcode[3];
2759 }
2760
2761 return ret;
2762}
2763
2764static int
2765qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2766{
2767 if (pos >= end || *pos != 0x82)
2768 return 0;
2769
2770 pos += 3 + pos[1];
2771 if (pos >= end || *pos != 0x90)
2772 return 0;
2773
2774 pos += 3 + pos[1];
2775 if (pos >= end || *pos != 0x78)
2776 return 0;
2777
2778 return 1;
2779}
2780
2781int
2782qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
2783{
2784 struct qla_hw_data *ha = vha->hw;
2785 uint8_t *pos = ha->vpd;
2786 uint8_t *end = pos + ha->vpd_size;
2787 int len = 0;
2788
2789 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2790 return 0;
2791
2792 while (pos < end && *pos != 0x78) {
2793 len = (*pos == 0x82) ? pos[1] : pos[2];
2794
2795 if (!strncmp(pos, key, strlen(key)))
2796 break;
2797
2798 if (*pos != 0x90 && *pos != 0x91)
2799 pos += len;
2800
2801 pos += 3;
2802 }
2803
2804 if (pos < end - len && *pos != 0x78)
2805 return snprintf(str, size, "%.*s", len, pos + 3);
2806
2807 return 0;
2808}
2809
2810int
2811qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha)
2812{
2813 int len, max_len;
2814 uint32_t fcp_prio_addr;
2815 struct qla_hw_data *ha = vha->hw;
2816
2817 if (!ha->fcp_prio_cfg) {
2818 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE);
2819 if (!ha->fcp_prio_cfg) {
2820 qla_printk(KERN_WARNING, ha,
2821 "Unable to allocate memory for fcp priority data "
2822 "(%x).\n", FCP_PRIO_CFG_SIZE);
2823 return QLA_FUNCTION_FAILED;
2824 }
2825 }
2826 memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE);
2827
2828 fcp_prio_addr = ha->flt_region_fcp_prio;
2829
2830
2831 ha->isp_ops->read_optrom(vha, (uint8_t *)ha->fcp_prio_cfg,
2832 fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE);
2833
2834 if (!qla24xx_fcp_prio_cfg_valid(ha->fcp_prio_cfg, 0))
2835 goto fail;
2836
2837
2838 fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2);
2839 len = ha->fcp_prio_cfg->num_entries * FCP_PRIO_CFG_ENTRY_SIZE;
2840 max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE;
2841
2842 ha->isp_ops->read_optrom(vha, (uint8_t *)&ha->fcp_prio_cfg->entry[0],
2843 fcp_prio_addr << 2, (len < max_len ? len : max_len));
2844
2845
2846 if (!qla24xx_fcp_prio_cfg_valid(ha->fcp_prio_cfg, 1))
2847 goto fail;
2848
2849 ha->flags.fcp_prio_enabled = 1;
2850 return QLA_SUCCESS;
2851fail:
2852 vfree(ha->fcp_prio_cfg);
2853 ha->fcp_prio_cfg = NULL;
2854 return QLA_FUNCTION_FAILED;
2855}
2856
