linux/drivers/net/wireless/b43/b43.h
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   1#ifndef B43_H_
   2#define B43_H_
   3
   4#include <linux/kernel.h>
   5#include <linux/spinlock.h>
   6#include <linux/interrupt.h>
   7#include <linux/hw_random.h>
   8#include <linux/ssb/ssb.h>
   9#include <net/mac80211.h>
  10
  11#include "debugfs.h"
  12#include "leds.h"
  13#include "rfkill.h"
  14#include "lo.h"
  15#include "phy_common.h"
  16
  17
  18/* The unique identifier of the firmware that's officially supported by
  19 * this driver version. */
  20#define B43_SUPPORTED_FIRMWARE_ID       "FW13"
  21
  22
  23#ifdef CONFIG_B43_DEBUG
  24# define B43_DEBUG      1
  25#else
  26# define B43_DEBUG      0
  27#endif
  28
  29/* MMIO offsets */
  30#define B43_MMIO_DMA0_REASON            0x20
  31#define B43_MMIO_DMA0_IRQ_MASK          0x24
  32#define B43_MMIO_DMA1_REASON            0x28
  33#define B43_MMIO_DMA1_IRQ_MASK          0x2C
  34#define B43_MMIO_DMA2_REASON            0x30
  35#define B43_MMIO_DMA2_IRQ_MASK          0x34
  36#define B43_MMIO_DMA3_REASON            0x38
  37#define B43_MMIO_DMA3_IRQ_MASK          0x3C
  38#define B43_MMIO_DMA4_REASON            0x40
  39#define B43_MMIO_DMA4_IRQ_MASK          0x44
  40#define B43_MMIO_DMA5_REASON            0x48
  41#define B43_MMIO_DMA5_IRQ_MASK          0x4C
  42#define B43_MMIO_MACCTL                 0x120   /* MAC control */
  43#define B43_MMIO_MACCMD                 0x124   /* MAC command */
  44#define B43_MMIO_GEN_IRQ_REASON         0x128
  45#define B43_MMIO_GEN_IRQ_MASK           0x12C
  46#define B43_MMIO_RAM_CONTROL            0x130
  47#define B43_MMIO_RAM_DATA               0x134
  48#define B43_MMIO_PS_STATUS              0x140
  49#define B43_MMIO_RADIO_HWENABLED_HI     0x158
  50#define B43_MMIO_SHM_CONTROL            0x160
  51#define B43_MMIO_SHM_DATA               0x164
  52#define B43_MMIO_SHM_DATA_UNALIGNED     0x166
  53#define B43_MMIO_XMITSTAT_0             0x170
  54#define B43_MMIO_XMITSTAT_1             0x174
  55#define B43_MMIO_REV3PLUS_TSF_LOW       0x180   /* core rev >= 3 only */
  56#define B43_MMIO_REV3PLUS_TSF_HIGH      0x184   /* core rev >= 3 only */
  57#define B43_MMIO_TSF_CFP_REP            0x188
  58#define B43_MMIO_TSF_CFP_START          0x18C
  59#define B43_MMIO_TSF_CFP_MAXDUR         0x190
  60
  61/* 32-bit DMA */
  62#define B43_MMIO_DMA32_BASE0            0x200
  63#define B43_MMIO_DMA32_BASE1            0x220
  64#define B43_MMIO_DMA32_BASE2            0x240
  65#define B43_MMIO_DMA32_BASE3            0x260
  66#define B43_MMIO_DMA32_BASE4            0x280
  67#define B43_MMIO_DMA32_BASE5            0x2A0
  68/* 64-bit DMA */
  69#define B43_MMIO_DMA64_BASE0            0x200
  70#define B43_MMIO_DMA64_BASE1            0x240
  71#define B43_MMIO_DMA64_BASE2            0x280
  72#define B43_MMIO_DMA64_BASE3            0x2C0
  73#define B43_MMIO_DMA64_BASE4            0x300
  74#define B43_MMIO_DMA64_BASE5            0x340
  75
  76/* PIO on core rev < 11 */
  77#define B43_MMIO_PIO_BASE0              0x300
  78#define B43_MMIO_PIO_BASE1              0x310
  79#define B43_MMIO_PIO_BASE2              0x320
  80#define B43_MMIO_PIO_BASE3              0x330
  81#define B43_MMIO_PIO_BASE4              0x340
  82#define B43_MMIO_PIO_BASE5              0x350
  83#define B43_MMIO_PIO_BASE6              0x360
  84#define B43_MMIO_PIO_BASE7              0x370
  85/* PIO on core rev >= 11 */
  86#define B43_MMIO_PIO11_BASE0            0x200
  87#define B43_MMIO_PIO11_BASE1            0x240
  88#define B43_MMIO_PIO11_BASE2            0x280
  89#define B43_MMIO_PIO11_BASE3            0x2C0
  90#define B43_MMIO_PIO11_BASE4            0x300
  91#define B43_MMIO_PIO11_BASE5            0x340
  92
  93#define B43_MMIO_PHY_VER                0x3E0
  94#define B43_MMIO_PHY_RADIO              0x3E2
  95#define B43_MMIO_PHY0                   0x3E6
  96#define B43_MMIO_ANTENNA                0x3E8
  97#define B43_MMIO_CHANNEL                0x3F0
  98#define B43_MMIO_CHANNEL_EXT            0x3F4
  99#define B43_MMIO_RADIO_CONTROL          0x3F6
 100#define B43_MMIO_RADIO_DATA_HIGH        0x3F8
 101#define B43_MMIO_RADIO_DATA_LOW         0x3FA
 102#define B43_MMIO_PHY_CONTROL            0x3FC
 103#define B43_MMIO_PHY_DATA               0x3FE
 104#define B43_MMIO_MACFILTER_CONTROL      0x420
 105#define B43_MMIO_MACFILTER_DATA         0x422
 106#define B43_MMIO_RCMTA_COUNT            0x43C
 107#define B43_MMIO_PSM_PHY_HDR            0x492
 108#define B43_MMIO_RADIO_HWENABLED_LO     0x49A
 109#define B43_MMIO_GPIO_CONTROL           0x49C
 110#define B43_MMIO_GPIO_MASK              0x49E
 111#define B43_MMIO_TSF_CFP_START_LOW      0x604
 112#define B43_MMIO_TSF_CFP_START_HIGH     0x606
 113#define B43_MMIO_TSF_CFP_PRETBTT        0x612
 114#define B43_MMIO_TSF_0                  0x632   /* core rev < 3 only */
 115#define B43_MMIO_TSF_1                  0x634   /* core rev < 3 only */
 116#define B43_MMIO_TSF_2                  0x636   /* core rev < 3 only */
 117#define B43_MMIO_TSF_3                  0x638   /* core rev < 3 only */
 118#define B43_MMIO_RNG                    0x65A
 119#define B43_MMIO_IFSSLOT                0x684   /* Interframe slot time */
 120#define B43_MMIO_IFSCTL                 0x688 /* Interframe space control */
 121#define  B43_MMIO_IFSCTL_USE_EDCF       0x0004
 122#define B43_MMIO_POWERUP_DELAY          0x6A8
 123#define B43_MMIO_BTCOEX_CTL             0x6B4 /* Bluetooth Coexistence Control */
 124#define B43_MMIO_BTCOEX_STAT            0x6B6 /* Bluetooth Coexistence Status */
 125#define B43_MMIO_BTCOEX_TXCTL           0x6B8 /* Bluetooth Coexistence Transmit Control */
 126
 127/* SPROM boardflags_lo values */
 128#define B43_BFL_BTCOEXIST               0x0001  /* implements Bluetooth coexistance */
 129#define B43_BFL_PACTRL                  0x0002  /* GPIO 9 controlling the PA */
 130#define B43_BFL_AIRLINEMODE             0x0004  /* implements GPIO 13 radio disable indication */
 131#define B43_BFL_RSSI                    0x0008  /* software calculates nrssi slope. */
 132#define B43_BFL_ENETSPI                 0x0010  /* has ephy roboswitch spi */
 133#define B43_BFL_XTAL_NOSLOW             0x0020  /* no slow clock available */
 134#define B43_BFL_CCKHIPWR                0x0040  /* can do high power CCK transmission */
 135#define B43_BFL_ENETADM                 0x0080  /* has ADMtek switch */
 136#define B43_BFL_ENETVLAN                0x0100  /* can do vlan */
 137#define B43_BFL_AFTERBURNER             0x0200  /* supports Afterburner mode */
 138#define B43_BFL_NOPCI                   0x0400  /* leaves PCI floating */
 139#define B43_BFL_FEM                     0x0800  /* supports the Front End Module */
 140#define B43_BFL_EXTLNA                  0x1000  /* has an external LNA */
 141#define B43_BFL_HGPA                    0x2000  /* had high gain PA */
 142#define B43_BFL_BTCMOD                  0x4000  /* BFL_BTCOEXIST is given in alternate GPIOs */
 143#define B43_BFL_ALTIQ                   0x8000  /* alternate I/Q settings */
 144
 145/* SPROM boardflags_hi values */
 146#define B43_BFH_NOPA                    0x0001  /* has no PA */
 147#define B43_BFH_RSSIINV                 0x0002  /* RSSI uses positive slope (not TSSI) */
 148#define B43_BFH_PAREF                   0x0004  /* uses the PARef LDO */
 149#define B43_BFH_3TSWITCH                0x0008  /* uses a triple throw switch shared
 150                                                 * with bluetooth */
 151#define B43_BFH_PHASESHIFT              0x0010  /* can support phase shifter */
 152#define B43_BFH_BUCKBOOST               0x0020  /* has buck/booster */
 153#define B43_BFH_FEM_BT                  0x0040  /* has FEM and switch to share antenna
 154                                                 * with bluetooth */
 155
 156/* GPIO register offset, in both ChipCommon and PCI core. */
 157#define B43_GPIO_CONTROL                0x6c
 158
 159/* SHM Routing */
 160enum {
 161        B43_SHM_UCODE,          /* Microcode memory */
 162        B43_SHM_SHARED,         /* Shared memory */
 163        B43_SHM_SCRATCH,        /* Scratch memory */
 164        B43_SHM_HW,             /* Internal hardware register */
 165        B43_SHM_RCMTA,          /* Receive match transmitter address (rev >= 5 only) */
 166};
 167/* SHM Routing modifiers */
 168#define B43_SHM_AUTOINC_R               0x0200  /* Auto-increment address on read */
 169#define B43_SHM_AUTOINC_W               0x0100  /* Auto-increment address on write */
 170#define B43_SHM_AUTOINC_RW              (B43_SHM_AUTOINC_R | \
 171                                         B43_SHM_AUTOINC_W)
 172
 173/* Misc SHM_SHARED offsets */
 174#define B43_SHM_SH_WLCOREREV            0x0016  /* 802.11 core revision */
 175#define B43_SHM_SH_PCTLWDPOS            0x0008
 176#define B43_SHM_SH_RXPADOFF             0x0034  /* RX Padding data offset (PIO only) */
 177#define B43_SHM_SH_FWCAPA               0x0042  /* Firmware capabilities (Opensource firmware only) */
 178#define B43_SHM_SH_PHYVER               0x0050  /* PHY version */
 179#define B43_SHM_SH_PHYTYPE              0x0052  /* PHY type */
 180#define B43_SHM_SH_ANTSWAP              0x005C  /* Antenna swap threshold */
 181#define B43_SHM_SH_HOSTFLO              0x005E  /* Hostflags for ucode options (low) */
 182#define B43_SHM_SH_HOSTFMI              0x0060  /* Hostflags for ucode options (middle) */
 183#define B43_SHM_SH_HOSTFHI              0x0062  /* Hostflags for ucode options (high) */
 184#define B43_SHM_SH_RFATT                0x0064  /* Current radio attenuation value */
 185#define B43_SHM_SH_RADAR                0x0066  /* Radar register */
 186#define B43_SHM_SH_PHYTXNOI             0x006E  /* PHY noise directly after TX (lower 8bit only) */
 187#define B43_SHM_SH_RFRXSP1              0x0072  /* RF RX SP Register 1 */
 188#define B43_SHM_SH_CHAN                 0x00A0  /* Current channel (low 8bit only) */
 189#define  B43_SHM_SH_CHAN_5GHZ           0x0100  /* Bit set, if 5Ghz channel */
 190#define B43_SHM_SH_BCMCFIFOID           0x0108  /* Last posted cookie to the bcast/mcast FIFO */
 191/* TSSI information */
 192#define B43_SHM_SH_TSSI_CCK             0x0058  /* TSSI for last 4 CCK frames (32bit) */
 193#define B43_SHM_SH_TSSI_OFDM_A          0x0068  /* TSSI for last 4 OFDM frames (32bit) */
 194#define B43_SHM_SH_TSSI_OFDM_G          0x0070  /* TSSI for last 4 OFDM frames (32bit) */
 195#define  B43_TSSI_MAX                   0x7F    /* Max value for one TSSI value */
 196/* SHM_SHARED TX FIFO variables */
 197#define B43_SHM_SH_SIZE01               0x0098  /* TX FIFO size for FIFO 0 (low) and 1 (high) */
 198#define B43_SHM_SH_SIZE23               0x009A  /* TX FIFO size for FIFO 2 and 3 */
 199#define B43_SHM_SH_SIZE45               0x009C  /* TX FIFO size for FIFO 4 and 5 */
 200#define B43_SHM_SH_SIZE67               0x009E  /* TX FIFO size for FIFO 6 and 7 */
 201/* SHM_SHARED background noise */
 202#define B43_SHM_SH_JSSI0                0x0088  /* Measure JSSI 0 */
 203#define B43_SHM_SH_JSSI1                0x008A  /* Measure JSSI 1 */
 204#define B43_SHM_SH_JSSIAUX              0x008C  /* Measure JSSI AUX */
 205/* SHM_SHARED crypto engine */
 206#define B43_SHM_SH_DEFAULTIV            0x003C  /* Default IV location */
 207#define B43_SHM_SH_NRRXTRANS            0x003E  /* # of soft RX transmitter addresses (max 8) */
 208#define B43_SHM_SH_KTP                  0x0056  /* Key table pointer */
 209#define B43_SHM_SH_TKIPTSCTTAK          0x0318
 210#define B43_SHM_SH_KEYIDXBLOCK          0x05D4  /* Key index/algorithm block (v4 firmware) */
 211#define B43_SHM_SH_PSM                  0x05F4  /* PSM transmitter address match block (rev < 5) */
 212/* SHM_SHARED WME variables */
 213#define B43_SHM_SH_EDCFSTAT             0x000E  /* EDCF status */
 214#define B43_SHM_SH_TXFCUR               0x0030  /* TXF current index */
 215#define B43_SHM_SH_EDCFQ                0x0240  /* EDCF Q info */
 216/* SHM_SHARED powersave mode related */
 217#define B43_SHM_SH_SLOTT                0x0010  /* Slot time */
 218#define B43_SHM_SH_DTIMPER              0x0012  /* DTIM period */
 219#define B43_SHM_SH_NOSLPZNATDTIM        0x004C  /* NOSLPZNAT DTIM */
 220/* SHM_SHARED beacon/AP variables */
 221#define B43_SHM_SH_BTL0                 0x0018  /* Beacon template length 0 */
 222#define B43_SHM_SH_BTL1                 0x001A  /* Beacon template length 1 */
 223#define B43_SHM_SH_BTSFOFF              0x001C  /* Beacon TSF offset */
 224#define B43_SHM_SH_TIMBPOS              0x001E  /* TIM B position in beacon */
 225#define B43_SHM_SH_DTIMP                0x0012  /* DTIP period */
 226#define B43_SHM_SH_MCASTCOOKIE          0x00A8  /* Last bcast/mcast frame ID */
 227#define B43_SHM_SH_SFFBLIM              0x0044  /* Short frame fallback retry limit */
 228#define B43_SHM_SH_LFFBLIM              0x0046  /* Long frame fallback retry limit */
 229#define B43_SHM_SH_BEACPHYCTL           0x0054  /* Beacon PHY TX control word (see PHY TX control) */
 230#define B43_SHM_SH_EXTNPHYCTL           0x00B0  /* Extended bytes for beacon PHY control (N) */
 231/* SHM_SHARED ACK/CTS control */
 232#define B43_SHM_SH_ACKCTSPHYCTL         0x0022  /* ACK/CTS PHY control word (see PHY TX control) */
 233/* SHM_SHARED probe response variables */
 234#define B43_SHM_SH_PRSSID               0x0160  /* Probe Response SSID */
 235#define B43_SHM_SH_PRSSIDLEN            0x0048  /* Probe Response SSID length */
 236#define B43_SHM_SH_PRTLEN               0x004A  /* Probe Response template length */
 237#define B43_SHM_SH_PRMAXTIME            0x0074  /* Probe Response max time */
 238#define B43_SHM_SH_PRPHYCTL             0x0188  /* Probe Response PHY TX control word */
 239/* SHM_SHARED rate tables */
 240#define B43_SHM_SH_OFDMDIRECT           0x01C0  /* Pointer to OFDM direct map */
 241#define B43_SHM_SH_OFDMBASIC            0x01E0  /* Pointer to OFDM basic rate map */
 242#define B43_SHM_SH_CCKDIRECT            0x0200  /* Pointer to CCK direct map */
 243#define B43_SHM_SH_CCKBASIC             0x0220  /* Pointer to CCK basic rate map */
 244/* SHM_SHARED microcode soft registers */
 245#define B43_SHM_SH_UCODEREV             0x0000  /* Microcode revision */
 246#define B43_SHM_SH_UCODEPATCH           0x0002  /* Microcode patchlevel */
 247#define B43_SHM_SH_UCODEDATE            0x0004  /* Microcode date */
 248#define B43_SHM_SH_UCODETIME            0x0006  /* Microcode time */
 249#define B43_SHM_SH_UCODESTAT            0x0040  /* Microcode debug status code */
 250#define  B43_SHM_SH_UCODESTAT_INVALID   0
 251#define  B43_SHM_SH_UCODESTAT_INIT      1
 252#define  B43_SHM_SH_UCODESTAT_ACTIVE    2
 253#define  B43_SHM_SH_UCODESTAT_SUSP      3       /* suspended */
 254#define  B43_SHM_SH_UCODESTAT_SLEEP     4       /* asleep (PS) */
 255#define B43_SHM_SH_MAXBFRAMES           0x0080  /* Maximum number of frames in a burst */
 256#define B43_SHM_SH_SPUWKUP              0x0094  /* pre-wakeup for synth PU in us */
 257#define B43_SHM_SH_PRETBTT              0x0096  /* pre-TBTT in us */
 258/* SHM_SHARED tx iq workarounds */
 259#define B43_SHM_SH_NPHY_TXIQW0          0x0700
 260#define B43_SHM_SH_NPHY_TXIQW1          0x0702
 261#define B43_SHM_SH_NPHY_TXIQW2          0x0704
 262#define B43_SHM_SH_NPHY_TXIQW3          0x0706
 263/* SHM_SHARED tx pwr ctrl */
 264#define B43_SHM_SH_NPHY_TXPWR_INDX0     0x0708
 265#define B43_SHM_SH_NPHY_TXPWR_INDX1     0x070E
 266
 267/* SHM_SCRATCH offsets */
 268#define B43_SHM_SC_MINCONT              0x0003  /* Minimum contention window */
 269#define B43_SHM_SC_MAXCONT              0x0004  /* Maximum contention window */
 270#define B43_SHM_SC_CURCONT              0x0005  /* Current contention window */
 271#define B43_SHM_SC_SRLIMIT              0x0006  /* Short retry count limit */
 272#define B43_SHM_SC_LRLIMIT              0x0007  /* Long retry count limit */
 273#define B43_SHM_SC_DTIMC                0x0008  /* Current DTIM count */
 274#define B43_SHM_SC_BTL0LEN              0x0015  /* Beacon 0 template length */
 275#define B43_SHM_SC_BTL1LEN              0x0016  /* Beacon 1 template length */
 276#define B43_SHM_SC_SCFB                 0x0017  /* Short frame transmit count threshold for rate fallback */
 277#define B43_SHM_SC_LCFB                 0x0018  /* Long frame transmit count threshold for rate fallback */
 278
 279/* Hardware Radio Enable masks */
 280#define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
 281#define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
 282
 283/* HostFlags. See b43_hf_read/write() */
 284#define B43_HF_ANTDIVHELP       0x000000000001ULL /* ucode antenna div helper */
 285#define B43_HF_SYMW             0x000000000002ULL /* G-PHY SYM workaround */
 286#define B43_HF_RXPULLW          0x000000000004ULL /* RX pullup workaround */
 287#define B43_HF_CCKBOOST         0x000000000008ULL /* 4dB CCK power boost (exclusive with OFDM boost) */
 288#define B43_HF_BTCOEX           0x000000000010ULL /* Bluetooth coexistance */
 289#define B43_HF_GDCW             0x000000000020ULL /* G-PHY DC canceller filter bw workaround */
 290#define B43_HF_OFDMPABOOST      0x000000000040ULL /* Enable PA gain boost for OFDM */
 291#define B43_HF_ACPR             0x000000000080ULL /* Disable for Japan, channel 14 */
 292#define B43_HF_EDCF             0x000000000100ULL /* on if WME and MAC suspended */
 293#define B43_HF_TSSIRPSMW        0x000000000200ULL /* TSSI reset PSM ucode workaround */
 294#define B43_HF_20IN40IQW        0x000000000200ULL /* 20 in 40 MHz I/Q workaround (rev >= 13 only) */
 295#define B43_HF_DSCRQ            0x000000000400ULL /* Disable slow clock request in ucode */
 296#define B43_HF_ACIW             0x000000000800ULL /* ACI workaround: shift bits by 2 on PHY CRS */
 297#define B43_HF_2060W            0x000000001000ULL /* 2060 radio workaround */
 298#define B43_HF_RADARW           0x000000002000ULL /* Radar workaround */
 299#define B43_HF_USEDEFKEYS       0x000000004000ULL /* Enable use of default keys */
 300#define B43_HF_AFTERBURNER      0x000000008000ULL /* Afterburner enabled */
 301#define B43_HF_BT4PRIOCOEX      0x000000010000ULL /* Bluetooth 4-priority coexistance */
 302#define B43_HF_FWKUP            0x000000020000ULL /* Fast wake-up ucode */
 303#define B43_HF_VCORECALC        0x000000040000ULL /* Force VCO recalculation when powering up synthpu */
 304#define B43_HF_PCISCW           0x000000080000ULL /* PCI slow clock workaround */
 305#define B43_HF_4318TSSI         0x000000200000ULL /* 4318 TSSI */
 306#define B43_HF_FBCMCFIFO        0x000000400000ULL /* Flush bcast/mcast FIFO immediately */
 307#define B43_HF_HWPCTL           0x000000800000ULL /* Enable hardwarre power control */
 308#define B43_HF_BTCOEXALT        0x000001000000ULL /* Bluetooth coexistance in alternate pins */
 309#define B43_HF_TXBTCHECK        0x000002000000ULL /* Bluetooth check during transmission */
 310#define B43_HF_SKCFPUP          0x000004000000ULL /* Skip CFP update */
 311#define B43_HF_N40W             0x000008000000ULL /* N PHY 40 MHz workaround (rev >= 13 only) */
 312#define B43_HF_ANTSEL           0x000020000000ULL /* Antenna selection (for testing antenna div.) */
 313#define B43_HF_BT3COEXT         0x000020000000ULL /* Bluetooth 3-wire coexistence (rev >= 13 only) */
 314#define B43_HF_BTCANT           0x000040000000ULL /* Bluetooth coexistence (antenna mode) (rev >= 13 only) */
 315#define B43_HF_ANTSELEN         0x000100000000ULL /* Antenna selection enabled (rev >= 13 only) */
 316#define B43_HF_ANTSELMODE       0x000200000000ULL /* Antenna selection mode (rev >= 13 only) */
 317#define B43_HF_MLADVW           0x001000000000ULL /* N PHY ML ADV workaround (rev >= 13 only) */
 318#define B43_HF_PR45960W         0x080000000000ULL /* PR 45960 workaround (rev >= 13 only) */
 319
 320/* Firmware capabilities field in SHM (Opensource firmware only) */
 321#define B43_FWCAPA_HWCRYPTO     0x0001
 322#define B43_FWCAPA_QOS          0x0002
 323
 324/* MacFilter offsets. */
 325#define B43_MACFILTER_SELF              0x0000
 326#define B43_MACFILTER_BSSID             0x0003
 327
 328/* PowerControl */
 329#define B43_PCTL_IN                     0xB0
 330#define B43_PCTL_OUT                    0xB4
 331#define B43_PCTL_OUTENABLE              0xB8
 332#define B43_PCTL_XTAL_POWERUP           0x40
 333#define B43_PCTL_PLL_POWERDOWN          0x80
 334
 335/* PowerControl Clock Modes */
 336#define B43_PCTL_CLK_FAST               0x00
 337#define B43_PCTL_CLK_SLOW               0x01
 338#define B43_PCTL_CLK_DYNAMIC            0x02
 339
 340#define B43_PCTL_FORCE_SLOW             0x0800
 341#define B43_PCTL_FORCE_PLL              0x1000
 342#define B43_PCTL_DYN_XTAL               0x2000
 343
 344/* PHYVersioning */
 345#define B43_PHYTYPE_A                   0x00
 346#define B43_PHYTYPE_B                   0x01
 347#define B43_PHYTYPE_G                   0x02
 348#define B43_PHYTYPE_N                   0x04
 349#define B43_PHYTYPE_LP                  0x05
 350
 351/* PHYRegisters */
 352#define B43_PHY_ILT_A_CTRL              0x0072
 353#define B43_PHY_ILT_A_DATA1             0x0073
 354#define B43_PHY_ILT_A_DATA2             0x0074
 355#define B43_PHY_G_LO_CONTROL            0x0810
 356#define B43_PHY_ILT_G_CTRL              0x0472
 357#define B43_PHY_ILT_G_DATA1             0x0473
 358#define B43_PHY_ILT_G_DATA2             0x0474
 359#define B43_PHY_A_PCTL                  0x007B
 360#define B43_PHY_G_PCTL                  0x0029
 361#define B43_PHY_A_CRS                   0x0029
 362#define B43_PHY_RADIO_BITFIELD          0x0401
 363#define B43_PHY_G_CRS                   0x0429
 364#define B43_PHY_NRSSILT_CTRL            0x0803
 365#define B43_PHY_NRSSILT_DATA            0x0804
 366
 367/* RadioRegisters */
 368#define B43_RADIOCTL_ID                 0x01
 369
 370/* MAC Control bitfield */
 371#define B43_MACCTL_ENABLED              0x00000001      /* MAC Enabled */
 372#define B43_MACCTL_PSM_RUN              0x00000002      /* Run Microcode */
 373#define B43_MACCTL_PSM_JMP0             0x00000004      /* Microcode jump to 0 */
 374#define B43_MACCTL_SHM_ENABLED          0x00000100      /* SHM Enabled */
 375#define B43_MACCTL_SHM_UPPER            0x00000200      /* SHM Upper */
 376#define B43_MACCTL_IHR_ENABLED          0x00000400      /* IHR Region Enabled */
 377#define B43_MACCTL_PSM_DBG              0x00002000      /* Microcode debugging enabled */
 378#define B43_MACCTL_GPOUTSMSK            0x0000C000      /* GPOUT Select Mask */
 379#define B43_MACCTL_BE                   0x00010000      /* Big Endian mode */
 380#define B43_MACCTL_INFRA                0x00020000      /* Infrastructure mode */
 381#define B43_MACCTL_AP                   0x00040000      /* AccessPoint mode */
 382#define B43_MACCTL_RADIOLOCK            0x00080000      /* Radio lock */
 383#define B43_MACCTL_BEACPROMISC          0x00100000      /* Beacon Promiscuous */
 384#define B43_MACCTL_KEEP_BADPLCP         0x00200000      /* Keep frames with bad PLCP */
 385#define B43_MACCTL_KEEP_CTL             0x00400000      /* Keep control frames */
 386#define B43_MACCTL_KEEP_BAD             0x00800000      /* Keep bad frames (FCS) */
 387#define B43_MACCTL_PROMISC              0x01000000      /* Promiscuous mode */
 388#define B43_MACCTL_HWPS                 0x02000000      /* Hardware Power Saving */
 389#define B43_MACCTL_AWAKE                0x04000000      /* Device is awake */
 390#define B43_MACCTL_CLOSEDNET            0x08000000      /* Closed net (no SSID bcast) */
 391#define B43_MACCTL_TBTTHOLD             0x10000000      /* TBTT Hold */
 392#define B43_MACCTL_DISCTXSTAT           0x20000000      /* Discard TX status */
 393#define B43_MACCTL_DISCPMQ              0x40000000      /* Discard Power Management Queue */
 394#define B43_MACCTL_GMODE                0x80000000      /* G Mode */
 395
 396/* MAC Command bitfield */
 397#define B43_MACCMD_BEACON0_VALID        0x00000001      /* Beacon 0 in template RAM is busy/valid */
 398#define B43_MACCMD_BEACON1_VALID        0x00000002      /* Beacon 1 in template RAM is busy/valid */
 399#define B43_MACCMD_DFQ_VALID            0x00000004      /* Directed frame queue valid (IBSS PS mode, ATIM) */
 400#define B43_MACCMD_CCA                  0x00000008      /* Clear channel assessment */
 401#define B43_MACCMD_BGNOISE              0x00000010      /* Background noise */
 402
 403/* 802.11 core specific TM State Low (SSB_TMSLOW) flags */
 404#define B43_TMSLOW_GMODE                0x20000000      /* G Mode Enable */
 405#define B43_TMSLOW_PHYCLKSPEED          0x00C00000      /* PHY clock speed mask (N-PHY only) */
 406#define  B43_TMSLOW_PHYCLKSPEED_40MHZ   0x00000000      /* 40 MHz PHY */
 407#define  B43_TMSLOW_PHYCLKSPEED_80MHZ   0x00400000      /* 80 MHz PHY */
 408#define  B43_TMSLOW_PHYCLKSPEED_160MHZ  0x00800000      /* 160 MHz PHY */
 409#define B43_TMSLOW_PLLREFSEL            0x00200000      /* PLL Frequency Reference Select (rev >= 5) */
 410#define B43_TMSLOW_MACPHYCLKEN          0x00100000      /* MAC PHY Clock Control Enable (rev >= 5) */
 411#define B43_TMSLOW_PHYRESET             0x00080000      /* PHY Reset */
 412#define B43_TMSLOW_PHYCLKEN             0x00040000      /* PHY Clock Enable */
 413
 414/* 802.11 core specific TM State High (SSB_TMSHIGH) flags */
 415#define B43_TMSHIGH_DUALBAND_PHY        0x00080000      /* Dualband PHY available */
 416#define B43_TMSHIGH_FCLOCK              0x00040000      /* Fast Clock Available (rev >= 5) */
 417#define B43_TMSHIGH_HAVE_5GHZ_PHY       0x00020000      /* 5 GHz PHY available (rev >= 5) */
 418#define B43_TMSHIGH_HAVE_2GHZ_PHY       0x00010000      /* 2.4 GHz PHY available (rev >= 5) */
 419
 420/* Generic-Interrupt reasons. */
 421#define B43_IRQ_MAC_SUSPENDED           0x00000001
 422#define B43_IRQ_BEACON                  0x00000002
 423#define B43_IRQ_TBTT_INDI               0x00000004
 424#define B43_IRQ_BEACON_TX_OK            0x00000008
 425#define B43_IRQ_BEACON_CANCEL           0x00000010
 426#define B43_IRQ_ATIM_END                0x00000020
 427#define B43_IRQ_PMQ                     0x00000040
 428#define B43_IRQ_PIO_WORKAROUND          0x00000100
 429#define B43_IRQ_MAC_TXERR               0x00000200
 430#define B43_IRQ_PHY_TXERR               0x00000800
 431#define B43_IRQ_PMEVENT                 0x00001000
 432#define B43_IRQ_TIMER0                  0x00002000
 433#define B43_IRQ_TIMER1                  0x00004000
 434#define B43_IRQ_DMA                     0x00008000
 435#define B43_IRQ_TXFIFO_FLUSH_OK         0x00010000
 436#define B43_IRQ_CCA_MEASURE_OK          0x00020000
 437#define B43_IRQ_NOISESAMPLE_OK          0x00040000
 438#define B43_IRQ_UCODE_DEBUG             0x08000000
 439#define B43_IRQ_RFKILL                  0x10000000
 440#define B43_IRQ_TX_OK                   0x20000000
 441#define B43_IRQ_PHY_G_CHANGED           0x40000000
 442#define B43_IRQ_TIMEOUT                 0x80000000
 443
 444#define B43_IRQ_ALL                     0xFFFFFFFF
 445#define B43_IRQ_MASKTEMPLATE            (B43_IRQ_TBTT_INDI | \
 446                                         B43_IRQ_ATIM_END | \
 447                                         B43_IRQ_PMQ | \
 448                                         B43_IRQ_MAC_TXERR | \
 449                                         B43_IRQ_PHY_TXERR | \
 450                                         B43_IRQ_DMA | \
 451                                         B43_IRQ_TXFIFO_FLUSH_OK | \
 452                                         B43_IRQ_NOISESAMPLE_OK | \
 453                                         B43_IRQ_UCODE_DEBUG | \
 454                                         B43_IRQ_RFKILL | \
 455                                         B43_IRQ_TX_OK)
 456
 457/* The firmware register to fetch the debug-IRQ reason from. */
 458#define B43_DEBUGIRQ_REASON_REG         63
 459/* Debug-IRQ reasons. */
 460#define B43_DEBUGIRQ_PANIC              0       /* The firmware panic'ed */
 461#define B43_DEBUGIRQ_DUMP_SHM           1       /* Dump shared SHM */
 462#define B43_DEBUGIRQ_DUMP_REGS          2       /* Dump the microcode registers */
 463#define B43_DEBUGIRQ_MARKER             3       /* A "marker" was thrown by the firmware. */
 464#define B43_DEBUGIRQ_ACK                0xFFFF  /* The host writes that to ACK the IRQ */
 465
 466/* The firmware register that contains the "marker" line. */
 467#define B43_MARKER_ID_REG               2
 468#define B43_MARKER_LINE_REG             3
 469
 470/* The firmware register to fetch the panic reason from. */
 471#define B43_FWPANIC_REASON_REG          3
 472/* Firmware panic reason codes */
 473#define B43_FWPANIC_DIE                 0 /* Firmware died. Don't auto-restart it. */
 474#define B43_FWPANIC_RESTART             1 /* Firmware died. Schedule a controller reset. */
 475
 476/* The firmware register that contains the watchdog counter. */
 477#define B43_WATCHDOG_REG                1
 478
 479/* Device specific rate values.
 480 * The actual values defined here are (rate_in_mbps * 2).
 481 * Some code depends on this. Don't change it. */
 482#define B43_CCK_RATE_1MB                0x02
 483#define B43_CCK_RATE_2MB                0x04
 484#define B43_CCK_RATE_5MB                0x0B
 485#define B43_CCK_RATE_11MB               0x16
 486#define B43_OFDM_RATE_6MB               0x0C
 487#define B43_OFDM_RATE_9MB               0x12
 488#define B43_OFDM_RATE_12MB              0x18
 489#define B43_OFDM_RATE_18MB              0x24
 490#define B43_OFDM_RATE_24MB              0x30
 491#define B43_OFDM_RATE_36MB              0x48
 492#define B43_OFDM_RATE_48MB              0x60
 493#define B43_OFDM_RATE_54MB              0x6C
 494/* Convert a b43 rate value to a rate in 100kbps */
 495#define B43_RATE_TO_BASE100KBPS(rate)   (((rate) * 10) / 2)
 496
 497#define B43_DEFAULT_SHORT_RETRY_LIMIT   7
 498#define B43_DEFAULT_LONG_RETRY_LIMIT    4
 499
 500#define B43_PHY_TX_BADNESS_LIMIT        1000
 501
 502/* Max size of a security key */
 503#define B43_SEC_KEYSIZE                 16
 504/* Max number of group keys */
 505#define B43_NR_GROUP_KEYS               4
 506/* Max number of pairwise keys */
 507#define B43_NR_PAIRWISE_KEYS            50
 508/* Security algorithms. */
 509enum {
 510        B43_SEC_ALGO_NONE = 0,  /* unencrypted, as of TX header. */
 511        B43_SEC_ALGO_WEP40,
 512        B43_SEC_ALGO_TKIP,
 513        B43_SEC_ALGO_AES,
 514        B43_SEC_ALGO_WEP104,
 515        B43_SEC_ALGO_AES_LEGACY,
 516};
 517
 518struct b43_dmaring;
 519
 520/* The firmware file header */
 521#define B43_FW_TYPE_UCODE       'u'
 522#define B43_FW_TYPE_PCM         'p'
 523#define B43_FW_TYPE_IV          'i'
 524struct b43_fw_header {
 525        /* File type */
 526        u8 type;
 527        /* File format version */
 528        u8 ver;
 529        u8 __padding[2];
 530        /* Size of the data. For ucode and PCM this is in bytes.
 531         * For IV this is number-of-ivs. */
 532        __be32 size;
 533} __attribute__((__packed__));
 534
 535/* Initial Value file format */
 536#define B43_IV_OFFSET_MASK      0x7FFF
 537#define B43_IV_32BIT            0x8000
 538struct b43_iv {
 539        __be16 offset_size;
 540        union {
 541                __be16 d16;
 542                __be32 d32;
 543        } data __attribute__((__packed__));
 544} __attribute__((__packed__));
 545
 546
 547/* Data structures for DMA transmission, per 80211 core. */
 548struct b43_dma {
 549        struct b43_dmaring *tx_ring_AC_BK; /* Background */
 550        struct b43_dmaring *tx_ring_AC_BE; /* Best Effort */
 551        struct b43_dmaring *tx_ring_AC_VI; /* Video */
 552        struct b43_dmaring *tx_ring_AC_VO; /* Voice */
 553        struct b43_dmaring *tx_ring_mcast; /* Multicast */
 554
 555        struct b43_dmaring *rx_ring;
 556};
 557
 558struct b43_pio_txqueue;
 559struct b43_pio_rxqueue;
 560
 561/* Data structures for PIO transmission, per 80211 core. */
 562struct b43_pio {
 563        struct b43_pio_txqueue *tx_queue_AC_BK; /* Background */
 564        struct b43_pio_txqueue *tx_queue_AC_BE; /* Best Effort */
 565        struct b43_pio_txqueue *tx_queue_AC_VI; /* Video */
 566        struct b43_pio_txqueue *tx_queue_AC_VO; /* Voice */
 567        struct b43_pio_txqueue *tx_queue_mcast; /* Multicast */
 568
 569        struct b43_pio_rxqueue *rx_queue;
 570};
 571
 572/* Context information for a noise calculation (Link Quality). */
 573struct b43_noise_calculation {
 574        bool calculation_running;
 575        u8 nr_samples;
 576        s8 samples[8][4];
 577};
 578
 579struct b43_stats {
 580        u8 link_noise;
 581};
 582
 583struct b43_key {
 584        /* If keyconf is NULL, this key is disabled.
 585         * keyconf is a cookie. Don't derefenrence it outside of the set_key
 586         * path, because b43 doesn't own it. */
 587        struct ieee80211_key_conf *keyconf;
 588        u8 algorithm;
 589};
 590
 591/* SHM offsets to the QOS data structures for the 4 different queues. */
 592#define B43_QOS_PARAMS(queue)   (B43_SHM_SH_EDCFQ + \
 593                                 (B43_NR_QOSPARAMS * sizeof(u16) * (queue)))
 594#define B43_QOS_BACKGROUND      B43_QOS_PARAMS(0)
 595#define B43_QOS_BESTEFFORT      B43_QOS_PARAMS(1)
 596#define B43_QOS_VIDEO           B43_QOS_PARAMS(2)
 597#define B43_QOS_VOICE           B43_QOS_PARAMS(3)
 598
 599/* QOS parameter hardware data structure offsets. */
 600#define B43_NR_QOSPARAMS        16
 601enum {
 602        B43_QOSPARAM_TXOP = 0,
 603        B43_QOSPARAM_CWMIN,
 604        B43_QOSPARAM_CWMAX,
 605        B43_QOSPARAM_CWCUR,
 606        B43_QOSPARAM_AIFS,
 607        B43_QOSPARAM_BSLOTS,
 608        B43_QOSPARAM_REGGAP,
 609        B43_QOSPARAM_STATUS,
 610};
 611
 612/* QOS parameters for a queue. */
 613struct b43_qos_params {
 614        /* The QOS parameters */
 615        struct ieee80211_tx_queue_params p;
 616};
 617
 618struct b43_wl;
 619
 620/* The type of the firmware file. */
 621enum b43_firmware_file_type {
 622        B43_FWTYPE_PROPRIETARY,
 623        B43_FWTYPE_OPENSOURCE,
 624        B43_NR_FWTYPES,
 625};
 626
 627/* Context data for fetching firmware. */
 628struct b43_request_fw_context {
 629        /* The device we are requesting the fw for. */
 630        struct b43_wldev *dev;
 631        /* The type of firmware to request. */
 632        enum b43_firmware_file_type req_type;
 633        /* Error messages for each firmware type. */
 634        char errors[B43_NR_FWTYPES][128];
 635        /* Temporary buffer for storing the firmware name. */
 636        char fwname[64];
 637        /* A fatal error occured while requesting. Firmware reqest
 638         * can not continue, as any other reqest will also fail. */
 639        int fatal_failure;
 640};
 641
 642/* In-memory representation of a cached microcode file. */
 643struct b43_firmware_file {
 644        const char *filename;
 645        const struct firmware *data;
 646        /* Type of the firmware file name. Note that this does only indicate
 647         * the type by the firmware name. NOT the file contents.
 648         * If you want to check for proprietary vs opensource, use (struct b43_firmware)->opensource
 649         * instead! The (struct b43_firmware)->opensource flag is derived from the actual firmware
 650         * binary code, not just the filename.
 651         */
 652        enum b43_firmware_file_type type;
 653};
 654
 655/* Pointers to the firmware data and meta information about it. */
 656struct b43_firmware {
 657        /* Microcode */
 658        struct b43_firmware_file ucode;
 659        /* PCM code */
 660        struct b43_firmware_file pcm;
 661        /* Initial MMIO values for the firmware */
 662        struct b43_firmware_file initvals;
 663        /* Initial MMIO values for the firmware, band-specific */
 664        struct b43_firmware_file initvals_band;
 665
 666        /* Firmware revision */
 667        u16 rev;
 668        /* Firmware patchlevel */
 669        u16 patch;
 670
 671        /* Set to true, if we are using an opensource firmware.
 672         * Use this to check for proprietary vs opensource. */
 673        bool opensource;
 674        /* Set to true, if the core needs a PCM firmware, but
 675         * we failed to load one. This is always false for
 676         * core rev > 10, as these don't need PCM firmware. */
 677        bool pcm_request_failed;
 678};
 679
 680/* Device (802.11 core) initialization status. */
 681enum {
 682        B43_STAT_UNINIT = 0,    /* Uninitialized. */
 683        B43_STAT_INITIALIZED = 1,       /* Initialized, but not started, yet. */
 684        B43_STAT_STARTED = 2,   /* Up and running. */
 685};
 686#define b43_status(wldev)               atomic_read(&(wldev)->__init_status)
 687#define b43_set_status(wldev, stat)     do {                    \
 688                atomic_set(&(wldev)->__init_status, (stat));    \
 689                smp_wmb();                                      \
 690                                        } while (0)
 691
 692/* Data structure for one wireless device (802.11 core) */
 693struct b43_wldev {
 694        struct ssb_device *dev;
 695        struct b43_wl *wl;
 696
 697        /* The device initialization status.
 698         * Use b43_status() to query. */
 699        atomic_t __init_status;
 700
 701        bool bad_frames_preempt;        /* Use "Bad Frames Preemption" (default off) */
 702        bool dfq_valid;         /* Directed frame queue valid (IBSS PS mode, ATIM) */
 703        bool radio_hw_enable;   /* saved state of radio hardware enabled state */
 704        bool qos_enabled;               /* TRUE, if QoS is used. */
 705        bool hwcrypto_enabled;          /* TRUE, if HW crypto acceleration is enabled. */
 706        bool use_pio;                   /* TRUE if next init should use PIO */
 707
 708        /* PHY/Radio device. */
 709        struct b43_phy phy;
 710
 711        union {
 712                /* DMA engines. */
 713                struct b43_dma dma;
 714                /* PIO engines. */
 715                struct b43_pio pio;
 716        };
 717        /* Use b43_using_pio_transfers() to check whether we are using
 718         * DMA or PIO data transfers. */
 719        bool __using_pio_transfers;
 720
 721        /* Various statistics about the physical device. */
 722        struct b43_stats stats;
 723
 724        /* Reason code of the last interrupt. */
 725        u32 irq_reason;
 726        u32 dma_reason[6];
 727        /* The currently active generic-interrupt mask. */
 728        u32 irq_mask;
 729
 730        /* Link Quality calculation context. */
 731        struct b43_noise_calculation noisecalc;
 732        /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
 733        int mac_suspended;
 734
 735        /* Periodic tasks */
 736        struct delayed_work periodic_work;
 737        unsigned int periodic_state;
 738
 739        struct work_struct restart_work;
 740
 741        /* encryption/decryption */
 742        u16 ktp;                /* Key table pointer */
 743        struct b43_key key[B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS];
 744
 745        /* Firmware data */
 746        struct b43_firmware fw;
 747
 748        /* Devicelist in struct b43_wl (all 802.11 cores) */
 749        struct list_head list;
 750
 751        /* Debugging stuff follows. */
 752#ifdef CONFIG_B43_DEBUG
 753        struct b43_dfsentry *dfsentry;
 754        unsigned int irq_count;
 755        unsigned int irq_bit_count[32];
 756        unsigned int tx_count;
 757        unsigned int rx_count;
 758#endif
 759};
 760
 761/* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */
 762struct b43_wl {
 763        /* Pointer to the active wireless device on this chip */
 764        struct b43_wldev *current_dev;
 765        /* Pointer to the ieee80211 hardware data structure */
 766        struct ieee80211_hw *hw;
 767
 768        /* Global driver mutex. Every operation must run with this mutex locked. */
 769        struct mutex mutex;
 770        /* Hard-IRQ spinlock. This lock protects things used in the hard-IRQ
 771         * handler, only. This basically is just the IRQ mask register. */
 772        spinlock_t hardirq_lock;
 773
 774        /* The number of queues that were registered with the mac80211 subsystem
 775         * initially. This is a backup copy of hw->queues in case hw->queues has
 776         * to be dynamically lowered at runtime (Firmware does not support QoS).
 777         * hw->queues has to be restored to the original value before unregistering
 778         * from the mac80211 subsystem. */
 779        u16 mac80211_initially_registered_queues;
 780
 781        /* We can only have one operating interface (802.11 core)
 782         * at a time. General information about this interface follows.
 783         */
 784
 785        struct ieee80211_vif *vif;
 786        /* The MAC address of the operating interface. */
 787        u8 mac_addr[ETH_ALEN];
 788        /* Current BSSID */
 789        u8 bssid[ETH_ALEN];
 790        /* Interface type. (NL80211_IFTYPE_XXX) */
 791        int if_type;
 792        /* Is the card operating in AP, STA or IBSS mode? */
 793        bool operating;
 794        /* filter flags */
 795        unsigned int filter_flags;
 796        /* Stats about the wireless interface */
 797        struct ieee80211_low_level_stats ieee_stats;
 798
 799#ifdef CONFIG_B43_HWRNG
 800        struct hwrng rng;
 801        bool rng_initialized;
 802        char rng_name[30 + 1];
 803#endif /* CONFIG_B43_HWRNG */
 804
 805        /* List of all wireless devices on this chip */
 806        struct list_head devlist;
 807        u8 nr_devs;
 808
 809        bool radiotap_enabled;
 810        bool radio_enabled;
 811
 812        /* The beacon we are currently using (AP or IBSS mode). */
 813        struct sk_buff *current_beacon;
 814        bool beacon0_uploaded;
 815        bool beacon1_uploaded;
 816        bool beacon_templates_virgin; /* Never wrote the templates? */
 817        struct work_struct beacon_update_trigger;
 818
 819        /* The current QOS parameters for the 4 queues. */
 820        struct b43_qos_params qos_params[4];
 821
 822        /* Work for adjustment of the transmission power.
 823         * This is scheduled when we determine that the actual TX output
 824         * power doesn't match what we want. */
 825        struct work_struct txpower_adjust_work;
 826
 827        /* Packet transmit work */
 828        struct work_struct tx_work;
 829        /* Queue of packets to be transmitted. */
 830        struct sk_buff_head tx_queue;
 831
 832        /* The device LEDs. */
 833        struct b43_leds leds;
 834
 835        /* Kmalloc'ed scratch space for PIO TX/RX. Protected by wl->mutex. */
 836        u8 pio_scratchspace[110] __attribute__((__aligned__(8)));
 837        u8 pio_tailspace[4] __attribute__((__aligned__(8)));
 838};
 839
 840static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw)
 841{
 842        return hw->priv;
 843}
 844
 845static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev)
 846{
 847        struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
 848        return ssb_get_drvdata(ssb_dev);
 849}
 850
 851/* Is the device operating in a specified mode (NL80211_IFTYPE_XXX). */
 852static inline int b43_is_mode(struct b43_wl *wl, int type)
 853{
 854        return (wl->operating && wl->if_type == type);
 855}
 856
 857/**
 858 * b43_current_band - Returns the currently used band.
 859 * Returns one of IEEE80211_BAND_2GHZ and IEEE80211_BAND_5GHZ.
 860 */
 861static inline enum ieee80211_band b43_current_band(struct b43_wl *wl)
 862{
 863        return wl->hw->conf.channel->band;
 864}
 865
 866static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
 867{
 868        return ssb_read16(dev->dev, offset);
 869}
 870
 871static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
 872{
 873        ssb_write16(dev->dev, offset, value);
 874}
 875
 876static inline u32 b43_read32(struct b43_wldev *dev, u16 offset)
 877{
 878        return ssb_read32(dev->dev, offset);
 879}
 880
 881static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
 882{
 883        ssb_write32(dev->dev, offset, value);
 884}
 885
 886static inline bool b43_using_pio_transfers(struct b43_wldev *dev)
 887{
 888        return dev->__using_pio_transfers;
 889}
 890
 891#ifdef CONFIG_B43_FORCE_PIO
 892# define B43_PIO_DEFAULT 1
 893#else
 894# define B43_PIO_DEFAULT 0
 895#endif
 896
 897/* Message printing */
 898void b43info(struct b43_wl *wl, const char *fmt, ...)
 899    __attribute__ ((format(printf, 2, 3)));
 900void b43err(struct b43_wl *wl, const char *fmt, ...)
 901    __attribute__ ((format(printf, 2, 3)));
 902void b43warn(struct b43_wl *wl, const char *fmt, ...)
 903    __attribute__ ((format(printf, 2, 3)));
 904void b43dbg(struct b43_wl *wl, const char *fmt, ...)
 905    __attribute__ ((format(printf, 2, 3)));
 906
 907
 908/* A WARN_ON variant that vanishes when b43 debugging is disabled.
 909 * This _also_ evaluates the arg with debugging disabled. */
 910#if B43_DEBUG
 911# define B43_WARN_ON(x) WARN_ON(x)
 912#else
 913static inline bool __b43_warn_on_dummy(bool x) { return x; }
 914# define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x)))
 915#endif
 916
 917/* Convert an integer to a Q5.2 value */
 918#define INT_TO_Q52(i)   ((i) << 2)
 919/* Convert a Q5.2 value to an integer (precision loss!) */
 920#define Q52_TO_INT(q52) ((q52) >> 2)
 921/* Macros for printing a value in Q5.2 format */
 922#define Q52_FMT         "%u.%u"
 923#define Q52_ARG(q52)    Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4)
 924
 925#endif /* B43_H_ */
 926
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