linux/drivers/gpu/drm/nouveau/nouveau_drv.h
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   1/*
   2 * Copyright 2005 Stephane Marchesin.
   3 * All Rights Reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice (including the next
  13 * paragraph) shall be included in all copies or substantial portions of the
  14 * Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22 * OTHER DEALINGS IN THE SOFTWARE.
  23 */
  24
  25#ifndef __NOUVEAU_DRV_H__
  26#define __NOUVEAU_DRV_H__
  27
  28#define DRIVER_AUTHOR           "Stephane Marchesin"
  29#define DRIVER_EMAIL            "dri-devel@lists.sourceforge.net"
  30
  31#define DRIVER_NAME             "nouveau"
  32#define DRIVER_DESC             "nVidia Riva/TNT/GeForce"
  33#define DRIVER_DATE             "20090420"
  34
  35#define DRIVER_MAJOR            0
  36#define DRIVER_MINOR            0
  37#define DRIVER_PATCHLEVEL       16
  38
  39#define NOUVEAU_FAMILY   0x0000FFFF
  40#define NOUVEAU_FLAGS    0xFFFF0000
  41
  42#include "ttm/ttm_bo_api.h"
  43#include "ttm/ttm_bo_driver.h"
  44#include "ttm/ttm_placement.h"
  45#include "ttm/ttm_memory.h"
  46#include "ttm/ttm_module.h"
  47
  48struct nouveau_fpriv {
  49        struct ttm_object_file *tfile;
  50};
  51
  52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  53
  54#include "nouveau_drm.h"
  55#include "nouveau_reg.h"
  56#include "nouveau_bios.h"
  57struct nouveau_grctx;
  58
  59#define MAX_NUM_DCB_ENTRIES 16
  60
  61#define NOUVEAU_MAX_CHANNEL_NR 128
  62#define NOUVEAU_MAX_TILE_NR 15
  63
  64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
  65#define NV50_VM_BLOCK    (512*1024*1024ULL)
  66#define NV50_VM_VRAM_NR  (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
  67
  68struct nouveau_tile_reg {
  69        struct nouveau_fence *fence;
  70        uint32_t addr;
  71        uint32_t size;
  72        bool used;
  73};
  74
  75struct nouveau_bo {
  76        struct ttm_buffer_object bo;
  77        struct ttm_placement placement;
  78        u32 placements[3];
  79        u32 busy_placements[3];
  80        struct ttm_bo_kmap_obj kmap;
  81        struct list_head head;
  82
  83        /* protected by ttm_bo_reserve() */
  84        struct drm_file *reserved_by;
  85        struct list_head entry;
  86        int pbbo_index;
  87        bool validate_mapped;
  88
  89        struct nouveau_channel *channel;
  90
  91        bool mappable;
  92        bool no_vm;
  93
  94        uint32_t tile_mode;
  95        uint32_t tile_flags;
  96        struct nouveau_tile_reg *tile;
  97
  98        struct drm_gem_object *gem;
  99        struct drm_file *cpu_filp;
 100        int pin_refcnt;
 101};
 102
 103static inline struct nouveau_bo *
 104nouveau_bo(struct ttm_buffer_object *bo)
 105{
 106        return container_of(bo, struct nouveau_bo, bo);
 107}
 108
 109static inline struct nouveau_bo *
 110nouveau_gem_object(struct drm_gem_object *gem)
 111{
 112        return gem ? gem->driver_private : NULL;
 113}
 114
 115/* TODO: submit equivalent to TTM generic API upstream? */
 116static inline void __iomem *
 117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
 118{
 119        bool is_iomem;
 120        void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
 121                                                &nvbo->kmap, &is_iomem);
 122        WARN_ON_ONCE(ioptr && !is_iomem);
 123        return ioptr;
 124}
 125
 126struct mem_block {
 127        struct mem_block *next;
 128        struct mem_block *prev;
 129        uint64_t start;
 130        uint64_t size;
 131        struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
 132};
 133
 134enum nouveau_flags {
 135        NV_NFORCE   = 0x10000000,
 136        NV_NFORCE2  = 0x20000000
 137};
 138
 139#define NVOBJ_ENGINE_SW         0
 140#define NVOBJ_ENGINE_GR         1
 141#define NVOBJ_ENGINE_DISPLAY    2
 142#define NVOBJ_ENGINE_INT        0xdeadbeef
 143
 144#define NVOBJ_FLAG_ALLOW_NO_REFS        (1 << 0)
 145#define NVOBJ_FLAG_ZERO_ALLOC           (1 << 1)
 146#define NVOBJ_FLAG_ZERO_FREE            (1 << 2)
 147#define NVOBJ_FLAG_FAKE                 (1 << 3)
 148struct nouveau_gpuobj {
 149        struct list_head list;
 150
 151        struct nouveau_channel *im_channel;
 152        struct mem_block *im_pramin;
 153        struct nouveau_bo *im_backing;
 154        uint32_t im_backing_start;
 155        uint32_t *im_backing_suspend;
 156        int im_bound;
 157
 158        uint32_t flags;
 159        int refcount;
 160
 161        uint32_t engine;
 162        uint32_t class;
 163
 164        void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
 165        void *priv;
 166};
 167
 168struct nouveau_gpuobj_ref {
 169        struct list_head list;
 170
 171        struct nouveau_gpuobj *gpuobj;
 172        uint32_t instance;
 173
 174        struct nouveau_channel *channel;
 175        int handle;
 176};
 177
 178struct nouveau_channel {
 179        struct drm_device *dev;
 180        int id;
 181
 182        /* owner of this fifo */
 183        struct drm_file *file_priv;
 184        /* mapping of the fifo itself */
 185        struct drm_local_map *map;
 186
 187        /* mapping of the regs controling the fifo */
 188        void __iomem *user;
 189        uint32_t user_get;
 190        uint32_t user_put;
 191
 192        /* Fencing */
 193        struct {
 194                /* lock protects the pending list only */
 195                spinlock_t lock;
 196                struct list_head pending;
 197                uint32_t sequence;
 198                uint32_t sequence_ack;
 199                uint32_t last_sequence_irq;
 200        } fence;
 201
 202        /* DMA push buffer */
 203        struct nouveau_gpuobj_ref *pushbuf;
 204        struct nouveau_bo         *pushbuf_bo;
 205        uint32_t                   pushbuf_base;
 206
 207        /* Notifier memory */
 208        struct nouveau_bo *notifier_bo;
 209        struct mem_block *notifier_heap;
 210
 211        /* PFIFO context */
 212        struct nouveau_gpuobj_ref *ramfc;
 213        struct nouveau_gpuobj_ref *cache;
 214
 215        /* PGRAPH context */
 216        /* XXX may be merge 2 pointers as private data ??? */
 217        struct nouveau_gpuobj_ref *ramin_grctx;
 218        void *pgraph_ctx;
 219
 220        /* NV50 VM */
 221        struct nouveau_gpuobj     *vm_pd;
 222        struct nouveau_gpuobj_ref *vm_gart_pt;
 223        struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR];
 224
 225        /* Objects */
 226        struct nouveau_gpuobj_ref *ramin; /* Private instmem */
 227        struct mem_block          *ramin_heap; /* Private PRAMIN heap */
 228        struct nouveau_gpuobj_ref *ramht; /* Hash table */
 229        struct list_head           ramht_refs; /* Objects referenced by RAMHT */
 230
 231        /* GPU object info for stuff used in-kernel (mm_enabled) */
 232        uint32_t m2mf_ntfy;
 233        uint32_t vram_handle;
 234        uint32_t gart_handle;
 235        bool accel_done;
 236
 237        /* Push buffer state (only for drm's channel on !mm_enabled) */
 238        struct {
 239                int max;
 240                int free;
 241                int cur;
 242                int put;
 243                /* access via pushbuf_bo */
 244
 245                int ib_base;
 246                int ib_max;
 247                int ib_free;
 248                int ib_put;
 249        } dma;
 250
 251        uint32_t sw_subchannel[8];
 252
 253        struct {
 254                struct nouveau_gpuobj *vblsem;
 255                uint32_t vblsem_offset;
 256                uint32_t vblsem_rval;
 257                struct list_head vbl_wait;
 258        } nvsw;
 259
 260        struct {
 261                bool active;
 262                char name[32];
 263                struct drm_info_list info;
 264        } debugfs;
 265};
 266
 267struct nouveau_instmem_engine {
 268        void    *priv;
 269
 270        int     (*init)(struct drm_device *dev);
 271        void    (*takedown)(struct drm_device *dev);
 272        int     (*suspend)(struct drm_device *dev);
 273        void    (*resume)(struct drm_device *dev);
 274
 275        int     (*populate)(struct drm_device *, struct nouveau_gpuobj *,
 276                            uint32_t *size);
 277        void    (*clear)(struct drm_device *, struct nouveau_gpuobj *);
 278        int     (*bind)(struct drm_device *, struct nouveau_gpuobj *);
 279        int     (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
 280        void    (*prepare_access)(struct drm_device *, bool write);
 281        void    (*finish_access)(struct drm_device *);
 282};
 283
 284struct nouveau_mc_engine {
 285        int  (*init)(struct drm_device *dev);
 286        void (*takedown)(struct drm_device *dev);
 287};
 288
 289struct nouveau_timer_engine {
 290        int      (*init)(struct drm_device *dev);
 291        void     (*takedown)(struct drm_device *dev);
 292        uint64_t (*read)(struct drm_device *dev);
 293};
 294
 295struct nouveau_fb_engine {
 296        int num_tiles;
 297
 298        int  (*init)(struct drm_device *dev);
 299        void (*takedown)(struct drm_device *dev);
 300
 301        void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
 302                                 uint32_t size, uint32_t pitch);
 303};
 304
 305struct nouveau_fifo_engine {
 306        void *priv;
 307
 308        int  channels;
 309
 310        int  (*init)(struct drm_device *);
 311        void (*takedown)(struct drm_device *);
 312
 313        void (*disable)(struct drm_device *);
 314        void (*enable)(struct drm_device *);
 315        bool (*reassign)(struct drm_device *, bool enable);
 316        bool (*cache_flush)(struct drm_device *dev);
 317        bool (*cache_pull)(struct drm_device *dev, bool enable);
 318
 319        int  (*channel_id)(struct drm_device *);
 320
 321        int  (*create_context)(struct nouveau_channel *);
 322        void (*destroy_context)(struct nouveau_channel *);
 323        int  (*load_context)(struct nouveau_channel *);
 324        int  (*unload_context)(struct drm_device *);
 325};
 326
 327struct nouveau_pgraph_object_method {
 328        int id;
 329        int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
 330                      uint32_t data);
 331};
 332
 333struct nouveau_pgraph_object_class {
 334        int id;
 335        bool software;
 336        struct nouveau_pgraph_object_method *methods;
 337};
 338
 339struct nouveau_pgraph_engine {
 340        struct nouveau_pgraph_object_class *grclass;
 341        bool accel_blocked;
 342        void *ctxprog;
 343        void *ctxvals;
 344        int grctx_size;
 345
 346        int  (*init)(struct drm_device *);
 347        void (*takedown)(struct drm_device *);
 348
 349        void (*fifo_access)(struct drm_device *, bool);
 350
 351        struct nouveau_channel *(*channel)(struct drm_device *);
 352        int  (*create_context)(struct nouveau_channel *);
 353        void (*destroy_context)(struct nouveau_channel *);
 354        int  (*load_context)(struct nouveau_channel *);
 355        int  (*unload_context)(struct drm_device *);
 356
 357        void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
 358                                  uint32_t size, uint32_t pitch);
 359};
 360
 361struct nouveau_engine {
 362        struct nouveau_instmem_engine instmem;
 363        struct nouveau_mc_engine      mc;
 364        struct nouveau_timer_engine   timer;
 365        struct nouveau_fb_engine      fb;
 366        struct nouveau_pgraph_engine  graph;
 367        struct nouveau_fifo_engine    fifo;
 368};
 369
 370struct nouveau_pll_vals {
 371        union {
 372                struct {
 373#ifdef __BIG_ENDIAN
 374                        uint8_t N1, M1, N2, M2;
 375#else
 376                        uint8_t M1, N1, M2, N2;
 377#endif
 378                };
 379                struct {
 380                        uint16_t NM1, NM2;
 381                } __attribute__((packed));
 382        };
 383        int log2P;
 384
 385        int refclk;
 386};
 387
 388enum nv04_fp_display_regs {
 389        FP_DISPLAY_END,
 390        FP_TOTAL,
 391        FP_CRTC,
 392        FP_SYNC_START,
 393        FP_SYNC_END,
 394        FP_VALID_START,
 395        FP_VALID_END
 396};
 397
 398struct nv04_crtc_reg {
 399        unsigned char MiscOutReg;     /* */
 400        uint8_t CRTC[0x9f];
 401        uint8_t CR58[0x10];
 402        uint8_t Sequencer[5];
 403        uint8_t Graphics[9];
 404        uint8_t Attribute[21];
 405        unsigned char DAC[768];       /* Internal Colorlookuptable */
 406
 407        /* PCRTC regs */
 408        uint32_t fb_start;
 409        uint32_t crtc_cfg;
 410        uint32_t cursor_cfg;
 411        uint32_t gpio_ext;
 412        uint32_t crtc_830;
 413        uint32_t crtc_834;
 414        uint32_t crtc_850;
 415        uint32_t crtc_eng_ctrl;
 416
 417        /* PRAMDAC regs */
 418        uint32_t nv10_cursync;
 419        struct nouveau_pll_vals pllvals;
 420        uint32_t ramdac_gen_ctrl;
 421        uint32_t ramdac_630;
 422        uint32_t ramdac_634;
 423        uint32_t tv_setup;
 424        uint32_t tv_vtotal;
 425        uint32_t tv_vskew;
 426        uint32_t tv_vsync_delay;
 427        uint32_t tv_htotal;
 428        uint32_t tv_hskew;
 429        uint32_t tv_hsync_delay;
 430        uint32_t tv_hsync_delay2;
 431        uint32_t fp_horiz_regs[7];
 432        uint32_t fp_vert_regs[7];
 433        uint32_t dither;
 434        uint32_t fp_control;
 435        uint32_t dither_regs[6];
 436        uint32_t fp_debug_0;
 437        uint32_t fp_debug_1;
 438        uint32_t fp_debug_2;
 439        uint32_t fp_margin_color;
 440        uint32_t ramdac_8c0;
 441        uint32_t ramdac_a20;
 442        uint32_t ramdac_a24;
 443        uint32_t ramdac_a34;
 444        uint32_t ctv_regs[38];
 445};
 446
 447struct nv04_output_reg {
 448        uint32_t output;
 449        int head;
 450};
 451
 452struct nv04_mode_state {
 453        uint32_t bpp;
 454        uint32_t width;
 455        uint32_t height;
 456        uint32_t interlace;
 457        uint32_t repaint0;
 458        uint32_t repaint1;
 459        uint32_t screen;
 460        uint32_t scale;
 461        uint32_t dither;
 462        uint32_t extra;
 463        uint32_t fifo;
 464        uint32_t pixel;
 465        uint32_t horiz;
 466        int arbitration0;
 467        int arbitration1;
 468        uint32_t pll;
 469        uint32_t pllB;
 470        uint32_t vpll;
 471        uint32_t vpll2;
 472        uint32_t vpllB;
 473        uint32_t vpll2B;
 474        uint32_t pllsel;
 475        uint32_t sel_clk;
 476        uint32_t general;
 477        uint32_t crtcOwner;
 478        uint32_t head;
 479        uint32_t head2;
 480        uint32_t cursorConfig;
 481        uint32_t cursor0;
 482        uint32_t cursor1;
 483        uint32_t cursor2;
 484        uint32_t timingH;
 485        uint32_t timingV;
 486        uint32_t displayV;
 487        uint32_t crtcSync;
 488
 489        struct nv04_crtc_reg crtc_reg[2];
 490};
 491
 492enum nouveau_card_type {
 493        NV_04      = 0x00,
 494        NV_10      = 0x10,
 495        NV_20      = 0x20,
 496        NV_30      = 0x30,
 497        NV_40      = 0x40,
 498        NV_50      = 0x50,
 499};
 500
 501struct drm_nouveau_private {
 502        struct drm_device *dev;
 503        enum {
 504                NOUVEAU_CARD_INIT_DOWN,
 505                NOUVEAU_CARD_INIT_DONE,
 506                NOUVEAU_CARD_INIT_FAILED
 507        } init_state;
 508
 509        /* the card type, takes NV_* as values */
 510        enum nouveau_card_type card_type;
 511        /* exact chipset, derived from NV_PMC_BOOT_0 */
 512        int chipset;
 513        int flags;
 514
 515        void __iomem *mmio;
 516        void __iomem *ramin;
 517        uint32_t ramin_size;
 518
 519        struct nouveau_bo *vga_ram;
 520
 521        struct workqueue_struct *wq;
 522        struct work_struct irq_work;
 523        struct work_struct hpd_work;
 524
 525        struct list_head vbl_waiting;
 526
 527        struct {
 528                struct ttm_global_reference mem_global_ref;
 529                struct ttm_bo_global_ref bo_global_ref;
 530                struct ttm_bo_device bdev;
 531                spinlock_t bo_list_lock;
 532                struct list_head bo_list;
 533                atomic_t validate_sequence;
 534        } ttm;
 535
 536        struct fb_info *fbdev_info;
 537
 538        int fifo_alloc_count;
 539        struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
 540
 541        struct nouveau_engine engine;
 542        struct nouveau_channel *channel;
 543
 544        /* For PFIFO and PGRAPH. */
 545        spinlock_t context_switch_lock;
 546
 547        /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
 548        struct nouveau_gpuobj *ramht;
 549        uint32_t ramin_rsvd_vram;
 550        uint32_t ramht_offset;
 551        uint32_t ramht_size;
 552        uint32_t ramht_bits;
 553        uint32_t ramfc_offset;
 554        uint32_t ramfc_size;
 555        uint32_t ramro_offset;
 556        uint32_t ramro_size;
 557
 558        struct {
 559                enum {
 560                        NOUVEAU_GART_NONE = 0,
 561                        NOUVEAU_GART_AGP,
 562                        NOUVEAU_GART_SGDMA
 563                } type;
 564                uint64_t aper_base;
 565                uint64_t aper_size;
 566                uint64_t aper_free;
 567
 568                struct nouveau_gpuobj *sg_ctxdma;
 569                struct page *sg_dummy_page;
 570                dma_addr_t sg_dummy_bus;
 571        } gart_info;
 572
 573        /* nv10-nv40 tiling regions */
 574        struct {
 575                struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
 576                spinlock_t lock;
 577        } tile;
 578
 579        /* VRAM/fb configuration */
 580        uint64_t vram_size;
 581        uint64_t vram_sys_base;
 582
 583        uint64_t fb_phys;
 584        uint64_t fb_available_size;
 585        uint64_t fb_mappable_pages;
 586        uint64_t fb_aper_free;
 587        int fb_mtrr;
 588
 589        /* G8x/G9x virtual address space */
 590        uint64_t vm_gart_base;
 591        uint64_t vm_gart_size;
 592        uint64_t vm_vram_base;
 593        uint64_t vm_vram_size;
 594        uint64_t vm_end;
 595        struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
 596        int vm_vram_pt_nr;
 597
 598        struct mem_block *ramin_heap;
 599
 600        /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
 601        uint32_t ctx_table_size;
 602        struct nouveau_gpuobj_ref *ctx_table;
 603
 604        struct list_head gpuobj_list;
 605
 606        struct nvbios vbios;
 607
 608        struct nv04_mode_state mode_reg;
 609        struct nv04_mode_state saved_reg;
 610        uint32_t saved_vga_font[4][16384];
 611        uint32_t crtc_owner;
 612        uint32_t dac_users[4];
 613
 614        struct nouveau_suspend_resume {
 615                uint32_t *ramin_copy;
 616        } susres;
 617
 618        struct backlight_device *backlight;
 619
 620        struct nouveau_channel *evo;
 621
 622        struct {
 623                struct dentry *channel_root;
 624        } debugfs;
 625
 626        struct nouveau_fbdev *nfbdev;
 627        struct apertures_struct *apertures;
 628};
 629
 630static inline struct drm_nouveau_private *
 631nouveau_bdev(struct ttm_bo_device *bd)
 632{
 633        return container_of(bd, struct drm_nouveau_private, ttm.bdev);
 634}
 635
 636static inline int
 637nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
 638{
 639        struct nouveau_bo *prev;
 640
 641        if (!pnvbo)
 642                return -EINVAL;
 643        prev = *pnvbo;
 644
 645        *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
 646        if (prev) {
 647                struct ttm_buffer_object *bo = &prev->bo;
 648
 649                ttm_bo_unref(&bo);
 650        }
 651
 652        return 0;
 653}
 654
 655#define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do {            \
 656        struct drm_nouveau_private *nv = dev->dev_private;    \
 657        if (nv->init_state != NOUVEAU_CARD_INIT_DONE) {       \
 658                NV_ERROR(dev, "called without init\n");       \
 659                return -EINVAL;                               \
 660        }                                                     \
 661} while (0)
 662
 663#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do {    \
 664        struct drm_nouveau_private *nv = dev->dev_private;       \
 665        if (!nouveau_channel_owner(dev, (cl), (id))) {           \
 666                NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
 667                         DRM_CURRENTPID, (id));                  \
 668                return -EPERM;                                   \
 669        }                                                        \
 670        (ch) = nv->fifos[(id)];                                  \
 671} while (0)
 672
 673/* nouveau_drv.c */
 674extern int nouveau_noagp;
 675extern int nouveau_duallink;
 676extern int nouveau_uscript_lvds;
 677extern int nouveau_uscript_tmds;
 678extern int nouveau_vram_pushbuf;
 679extern int nouveau_vram_notify;
 680extern int nouveau_fbpercrtc;
 681extern int nouveau_tv_disable;
 682extern char *nouveau_tv_norm;
 683extern int nouveau_reg_debug;
 684extern char *nouveau_vbios;
 685extern int nouveau_ctxfw;
 686extern int nouveau_ignorelid;
 687extern int nouveau_nofbaccel;
 688extern int nouveau_noaccel;
 689extern int nouveau_override_conntype;
 690
 691extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
 692extern int nouveau_pci_resume(struct pci_dev *pdev);
 693
 694/* nouveau_state.c */
 695extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
 696extern int  nouveau_load(struct drm_device *, unsigned long flags);
 697extern int  nouveau_firstopen(struct drm_device *);
 698extern void nouveau_lastclose(struct drm_device *);
 699extern int  nouveau_unload(struct drm_device *);
 700extern int  nouveau_ioctl_getparam(struct drm_device *, void *data,
 701                                   struct drm_file *);
 702extern int  nouveau_ioctl_setparam(struct drm_device *, void *data,
 703                                   struct drm_file *);
 704extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
 705                               uint32_t reg, uint32_t mask, uint32_t val);
 706extern bool nouveau_wait_for_idle(struct drm_device *);
 707extern int  nouveau_card_init(struct drm_device *);
 708
 709/* nouveau_mem.c */
 710extern int  nouveau_mem_init_heap(struct mem_block **, uint64_t start,
 711                                 uint64_t size);
 712extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
 713                                                 uint64_t size, int align2,
 714                                                 struct drm_file *, int tail);
 715extern void nouveau_mem_takedown(struct mem_block **heap);
 716extern void nouveau_mem_free_block(struct mem_block *);
 717extern int  nouveau_mem_detect(struct drm_device *dev);
 718extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
 719extern int  nouveau_mem_init(struct drm_device *);
 720extern int  nouveau_mem_init_agp(struct drm_device *);
 721extern void nouveau_mem_close(struct drm_device *);
 722extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
 723                                                    uint32_t addr,
 724                                                    uint32_t size,
 725                                                    uint32_t pitch);
 726extern void nv10_mem_expire_tiling(struct drm_device *dev,
 727                                   struct nouveau_tile_reg *tile,
 728                                   struct nouveau_fence *fence);
 729extern int  nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
 730                                    uint32_t size, uint32_t flags,
 731                                    uint64_t phys);
 732extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
 733                               uint32_t size);
 734
 735/* nouveau_notifier.c */
 736extern int  nouveau_notifier_init_channel(struct nouveau_channel *);
 737extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
 738extern int  nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
 739                                   int cout, uint32_t *offset);
 740extern int  nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
 741extern int  nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
 742                                         struct drm_file *);
 743extern int  nouveau_ioctl_notifier_free(struct drm_device *, void *data,
 744                                        struct drm_file *);
 745
 746/* nouveau_channel.c */
 747extern struct drm_ioctl_desc nouveau_ioctls[];
 748extern int nouveau_max_ioctl;
 749extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
 750extern int  nouveau_channel_owner(struct drm_device *, struct drm_file *,
 751                                  int channel);
 752extern int  nouveau_channel_alloc(struct drm_device *dev,
 753                                  struct nouveau_channel **chan,
 754                                  struct drm_file *file_priv,
 755                                  uint32_t fb_ctxdma, uint32_t tt_ctxdma);
 756extern void nouveau_channel_free(struct nouveau_channel *);
 757
 758/* nouveau_object.c */
 759extern int  nouveau_gpuobj_early_init(struct drm_device *);
 760extern int  nouveau_gpuobj_init(struct drm_device *);
 761extern void nouveau_gpuobj_takedown(struct drm_device *);
 762extern void nouveau_gpuobj_late_takedown(struct drm_device *);
 763extern int  nouveau_gpuobj_suspend(struct drm_device *dev);
 764extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
 765extern void nouveau_gpuobj_resume(struct drm_device *dev);
 766extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
 767                                       uint32_t vram_h, uint32_t tt_h);
 768extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
 769extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
 770                              uint32_t size, int align, uint32_t flags,
 771                              struct nouveau_gpuobj **);
 772extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
 773extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
 774                                  uint32_t handle, struct nouveau_gpuobj *,
 775                                  struct nouveau_gpuobj_ref **);
 776extern int nouveau_gpuobj_ref_del(struct drm_device *,
 777                                  struct nouveau_gpuobj_ref **);
 778extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
 779                                   struct nouveau_gpuobj_ref **ref_ret);
 780extern int nouveau_gpuobj_new_ref(struct drm_device *,
 781                                  struct nouveau_channel *alloc_chan,
 782                                  struct nouveau_channel *ref_chan,
 783                                  uint32_t handle, uint32_t size, int align,
 784                                  uint32_t flags, struct nouveau_gpuobj_ref **);
 785extern int nouveau_gpuobj_new_fake(struct drm_device *,
 786                                   uint32_t p_offset, uint32_t b_offset,
 787                                   uint32_t size, uint32_t flags,
 788                                   struct nouveau_gpuobj **,
 789                                   struct nouveau_gpuobj_ref**);
 790extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
 791                                  uint64_t offset, uint64_t size, int access,
 792                                  int target, struct nouveau_gpuobj **);
 793extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
 794                                       uint64_t offset, uint64_t size,
 795                                       int access, struct nouveau_gpuobj **,
 796                                       uint32_t *o_ret);
 797extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
 798                                 struct nouveau_gpuobj **);
 799extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
 800                                 struct nouveau_gpuobj **);
 801extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
 802                                     struct drm_file *);
 803extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
 804                                     struct drm_file *);
 805
 806/* nouveau_irq.c */
 807extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
 808extern void        nouveau_irq_preinstall(struct drm_device *);
 809extern int         nouveau_irq_postinstall(struct drm_device *);
 810extern void        nouveau_irq_uninstall(struct drm_device *);
 811
 812/* nouveau_sgdma.c */
 813extern int nouveau_sgdma_init(struct drm_device *);
 814extern void nouveau_sgdma_takedown(struct drm_device *);
 815extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
 816                                  uint32_t *page);
 817extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
 818
 819/* nouveau_debugfs.c */
 820#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
 821extern int  nouveau_debugfs_init(struct drm_minor *);
 822extern void nouveau_debugfs_takedown(struct drm_minor *);
 823extern int  nouveau_debugfs_channel_init(struct nouveau_channel *);
 824extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
 825#else
 826static inline int
 827nouveau_debugfs_init(struct drm_minor *minor)
 828{
 829        return 0;
 830}
 831
 832static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
 833{
 834}
 835
 836static inline int
 837nouveau_debugfs_channel_init(struct nouveau_channel *chan)
 838{
 839        return 0;
 840}
 841
 842static inline void
 843nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
 844{
 845}
 846#endif
 847
 848/* nouveau_dma.c */
 849extern void nouveau_dma_pre_init(struct nouveau_channel *);
 850extern int  nouveau_dma_init(struct nouveau_channel *);
 851extern int  nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
 852
 853/* nouveau_acpi.c */
 854#define ROM_BIOS_PAGE 4096
 855#if defined(CONFIG_ACPI)
 856void nouveau_register_dsm_handler(void);
 857void nouveau_unregister_dsm_handler(void);
 858int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
 859bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
 860#else
 861static inline void nouveau_register_dsm_handler(void) {}
 862static inline void nouveau_unregister_dsm_handler(void) {}
 863static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
 864static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
 865#endif
 866
 867/* nouveau_backlight.c */
 868#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
 869extern int nouveau_backlight_init(struct drm_device *);
 870extern void nouveau_backlight_exit(struct drm_device *);
 871#else
 872static inline int nouveau_backlight_init(struct drm_device *dev)
 873{
 874        return 0;
 875}
 876
 877static inline void nouveau_backlight_exit(struct drm_device *dev) { }
 878#endif
 879
 880/* nouveau_bios.c */
 881extern int nouveau_bios_init(struct drm_device *);
 882extern void nouveau_bios_takedown(struct drm_device *dev);
 883extern int nouveau_run_vbios_init(struct drm_device *);
 884extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
 885                                        struct dcb_entry *);
 886extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
 887                                                      enum dcb_gpio_tag);
 888extern struct dcb_connector_table_entry *
 889nouveau_bios_connector_entry(struct drm_device *, int index);
 890extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
 891                          struct pll_lims *);
 892extern int nouveau_bios_run_display_table(struct drm_device *,
 893                                          struct dcb_entry *,
 894                                          uint32_t script, int pxclk);
 895extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
 896                                   int *length);
 897extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
 898extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
 899extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
 900                                         bool *dl, bool *if_is_24bit);
 901extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
 902                          int head, int pxclk);
 903extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
 904                            enum LVDS_script, int pxclk);
 905
 906/* nouveau_ttm.c */
 907int nouveau_ttm_global_init(struct drm_nouveau_private *);
 908void nouveau_ttm_global_release(struct drm_nouveau_private *);
 909int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
 910
 911/* nouveau_dp.c */
 912int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
 913                     uint8_t *data, int data_nr);
 914bool nouveau_dp_detect(struct drm_encoder *);
 915bool nouveau_dp_link_train(struct drm_encoder *);
 916
 917/* nv04_fb.c */
 918extern int  nv04_fb_init(struct drm_device *);
 919extern void nv04_fb_takedown(struct drm_device *);
 920
 921/* nv10_fb.c */
 922extern int  nv10_fb_init(struct drm_device *);
 923extern void nv10_fb_takedown(struct drm_device *);
 924extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
 925                                      uint32_t, uint32_t);
 926
 927/* nv40_fb.c */
 928extern int  nv40_fb_init(struct drm_device *);
 929extern void nv40_fb_takedown(struct drm_device *);
 930extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
 931                                      uint32_t, uint32_t);
 932
 933/* nv50_fb.c */
 934extern int  nv50_fb_init(struct drm_device *);
 935extern void nv50_fb_takedown(struct drm_device *);
 936
 937/* nv04_fifo.c */
 938extern int  nv04_fifo_init(struct drm_device *);
 939extern void nv04_fifo_disable(struct drm_device *);
 940extern void nv04_fifo_enable(struct drm_device *);
 941extern bool nv04_fifo_reassign(struct drm_device *, bool);
 942extern bool nv04_fifo_cache_flush(struct drm_device *);
 943extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
 944extern int  nv04_fifo_channel_id(struct drm_device *);
 945extern int  nv04_fifo_create_context(struct nouveau_channel *);
 946extern void nv04_fifo_destroy_context(struct nouveau_channel *);
 947extern int  nv04_fifo_load_context(struct nouveau_channel *);
 948extern int  nv04_fifo_unload_context(struct drm_device *);
 949
 950/* nv10_fifo.c */
 951extern int  nv10_fifo_init(struct drm_device *);
 952extern int  nv10_fifo_channel_id(struct drm_device *);
 953extern int  nv10_fifo_create_context(struct nouveau_channel *);
 954extern void nv10_fifo_destroy_context(struct nouveau_channel *);
 955extern int  nv10_fifo_load_context(struct nouveau_channel *);
 956extern int  nv10_fifo_unload_context(struct drm_device *);
 957
 958/* nv40_fifo.c */
 959extern int  nv40_fifo_init(struct drm_device *);
 960extern int  nv40_fifo_create_context(struct nouveau_channel *);
 961extern void nv40_fifo_destroy_context(struct nouveau_channel *);
 962extern int  nv40_fifo_load_context(struct nouveau_channel *);
 963extern int  nv40_fifo_unload_context(struct drm_device *);
 964
 965/* nv50_fifo.c */
 966extern int  nv50_fifo_init(struct drm_device *);
 967extern void nv50_fifo_takedown(struct drm_device *);
 968extern int  nv50_fifo_channel_id(struct drm_device *);
 969extern int  nv50_fifo_create_context(struct nouveau_channel *);
 970extern void nv50_fifo_destroy_context(struct nouveau_channel *);
 971extern int  nv50_fifo_load_context(struct nouveau_channel *);
 972extern int  nv50_fifo_unload_context(struct drm_device *);
 973
 974/* nv04_graph.c */
 975extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
 976extern int  nv04_graph_init(struct drm_device *);
 977extern void nv04_graph_takedown(struct drm_device *);
 978extern void nv04_graph_fifo_access(struct drm_device *, bool);
 979extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
 980extern int  nv04_graph_create_context(struct nouveau_channel *);
 981extern void nv04_graph_destroy_context(struct nouveau_channel *);
 982extern int  nv04_graph_load_context(struct nouveau_channel *);
 983extern int  nv04_graph_unload_context(struct drm_device *);
 984extern void nv04_graph_context_switch(struct drm_device *);
 985
 986/* nv10_graph.c */
 987extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
 988extern int  nv10_graph_init(struct drm_device *);
 989extern void nv10_graph_takedown(struct drm_device *);
 990extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
 991extern int  nv10_graph_create_context(struct nouveau_channel *);
 992extern void nv10_graph_destroy_context(struct nouveau_channel *);
 993extern int  nv10_graph_load_context(struct nouveau_channel *);
 994extern int  nv10_graph_unload_context(struct drm_device *);
 995extern void nv10_graph_context_switch(struct drm_device *);
 996extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
 997                                         uint32_t, uint32_t);
 998
 999/* nv20_graph.c */
1000extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
1001extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
1002extern int  nv20_graph_create_context(struct nouveau_channel *);
1003extern void nv20_graph_destroy_context(struct nouveau_channel *);
1004extern int  nv20_graph_load_context(struct nouveau_channel *);
1005extern int  nv20_graph_unload_context(struct drm_device *);
1006extern int  nv20_graph_init(struct drm_device *);
1007extern void nv20_graph_takedown(struct drm_device *);
1008extern int  nv30_graph_init(struct drm_device *);
1009extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1010                                         uint32_t, uint32_t);
1011
1012/* nv40_graph.c */
1013extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1014extern int  nv40_graph_init(struct drm_device *);
1015extern void nv40_graph_takedown(struct drm_device *);
1016extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1017extern int  nv40_graph_create_context(struct nouveau_channel *);
1018extern void nv40_graph_destroy_context(struct nouveau_channel *);
1019extern int  nv40_graph_load_context(struct nouveau_channel *);
1020extern int  nv40_graph_unload_context(struct drm_device *);
1021extern void nv40_grctx_init(struct nouveau_grctx *);
1022extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1023                                         uint32_t, uint32_t);
1024
1025/* nv50_graph.c */
1026extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1027extern int  nv50_graph_init(struct drm_device *);
1028extern void nv50_graph_takedown(struct drm_device *);
1029extern void nv50_graph_fifo_access(struct drm_device *, bool);
1030extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1031extern int  nv50_graph_create_context(struct nouveau_channel *);
1032extern void nv50_graph_destroy_context(struct nouveau_channel *);
1033extern int  nv50_graph_load_context(struct nouveau_channel *);
1034extern int  nv50_graph_unload_context(struct drm_device *);
1035extern void nv50_graph_context_switch(struct drm_device *);
1036extern int  nv50_grctx_init(struct nouveau_grctx *);
1037
1038/* nouveau_grctx.c */
1039extern int  nouveau_grctx_prog_load(struct drm_device *);
1040extern void nouveau_grctx_vals_load(struct drm_device *,
1041                                    struct nouveau_gpuobj *);
1042extern void nouveau_grctx_fini(struct drm_device *);
1043
1044/* nv04_instmem.c */
1045extern int  nv04_instmem_init(struct drm_device *);
1046extern void nv04_instmem_takedown(struct drm_device *);
1047extern int  nv04_instmem_suspend(struct drm_device *);
1048extern void nv04_instmem_resume(struct drm_device *);
1049extern int  nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1050                                  uint32_t *size);
1051extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1052extern int  nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1053extern int  nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1054extern void nv04_instmem_prepare_access(struct drm_device *, bool write);
1055extern void nv04_instmem_finish_access(struct drm_device *);
1056
1057/* nv50_instmem.c */
1058extern int  nv50_instmem_init(struct drm_device *);
1059extern void nv50_instmem_takedown(struct drm_device *);
1060extern int  nv50_instmem_suspend(struct drm_device *);
1061extern void nv50_instmem_resume(struct drm_device *);
1062extern int  nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1063                                  uint32_t *size);
1064extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1065extern int  nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1066extern int  nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1067extern void nv50_instmem_prepare_access(struct drm_device *, bool write);
1068extern void nv50_instmem_finish_access(struct drm_device *);
1069
1070/* nv04_mc.c */
1071extern int  nv04_mc_init(struct drm_device *);
1072extern void nv04_mc_takedown(struct drm_device *);
1073
1074/* nv40_mc.c */
1075extern int  nv40_mc_init(struct drm_device *);
1076extern void nv40_mc_takedown(struct drm_device *);
1077
1078/* nv50_mc.c */
1079extern int  nv50_mc_init(struct drm_device *);
1080extern void nv50_mc_takedown(struct drm_device *);
1081
1082/* nv04_timer.c */
1083extern int  nv04_timer_init(struct drm_device *);
1084extern uint64_t nv04_timer_read(struct drm_device *);
1085extern void nv04_timer_takedown(struct drm_device *);
1086
1087extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1088                                 unsigned long arg);
1089
1090/* nv04_dac.c */
1091extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry);
1092extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1093extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1094extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1095
1096/* nv04_dfp.c */
1097extern int nv04_dfp_create(struct drm_device *dev, struct dcb_entry *entry);
1098extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1099extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1100                               int head, bool dl);
1101extern void nv04_dfp_disable(struct drm_device *dev, int head);
1102extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1103
1104/* nv04_tv.c */
1105extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1106extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1107
1108/* nv17_tv.c */
1109extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1110
1111/* nv04_display.c */
1112extern int nv04_display_create(struct drm_device *);
1113extern void nv04_display_destroy(struct drm_device *);
1114extern void nv04_display_restore(struct drm_device *);
1115
1116/* nv04_crtc.c */
1117extern int nv04_crtc_create(struct drm_device *, int index);
1118
1119/* nouveau_bo.c */
1120extern struct ttm_bo_driver nouveau_bo_driver;
1121extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1122                          int size, int align, uint32_t flags,
1123                          uint32_t tile_mode, uint32_t tile_flags,
1124                          bool no_vm, bool mappable, struct nouveau_bo **);
1125extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1126extern int nouveau_bo_unpin(struct nouveau_bo *);
1127extern int nouveau_bo_map(struct nouveau_bo *);
1128extern void nouveau_bo_unmap(struct nouveau_bo *);
1129extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1130                                     uint32_t busy);
1131extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1132extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1133extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1134extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1135
1136/* nouveau_fence.c */
1137struct nouveau_fence;
1138extern int nouveau_fence_init(struct nouveau_channel *);
1139extern void nouveau_fence_fini(struct nouveau_channel *);
1140extern void nouveau_fence_update(struct nouveau_channel *);
1141extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1142                             bool emit);
1143extern int nouveau_fence_emit(struct nouveau_fence *);
1144struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1145extern bool nouveau_fence_signalled(void *obj, void *arg);
1146extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1147extern int nouveau_fence_flush(void *obj, void *arg);
1148extern void nouveau_fence_unref(void **obj);
1149extern void *nouveau_fence_ref(void *obj);
1150extern void nouveau_fence_handler(struct drm_device *dev, int channel);
1151
1152/* nouveau_gem.c */
1153extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1154                           int size, int align, uint32_t flags,
1155                           uint32_t tile_mode, uint32_t tile_flags,
1156                           bool no_vm, bool mappable, struct nouveau_bo **);
1157extern int nouveau_gem_object_new(struct drm_gem_object *);
1158extern void nouveau_gem_object_del(struct drm_gem_object *);
1159extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1160                                 struct drm_file *);
1161extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1162                                     struct drm_file *);
1163extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1164                                      struct drm_file *);
1165extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1166                                      struct drm_file *);
1167extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1168                                  struct drm_file *);
1169
1170/* nv17_gpio.c */
1171int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1172int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1173
1174/* nv50_gpio.c */
1175int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1176int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1177
1178/* nv50_calc. */
1179int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1180                  int *N1, int *M1, int *N2, int *M2, int *P);
1181int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1182                   int clk, int *N, int *fN, int *M, int *P);
1183
1184#ifndef ioread32_native
1185#ifdef __BIG_ENDIAN
1186#define ioread16_native ioread16be
1187#define iowrite16_native iowrite16be
1188#define ioread32_native  ioread32be
1189#define iowrite32_native iowrite32be
1190#else /* def __BIG_ENDIAN */
1191#define ioread16_native ioread16
1192#define iowrite16_native iowrite16
1193#define ioread32_native  ioread32
1194#define iowrite32_native iowrite32
1195#endif /* def __BIG_ENDIAN else */
1196#endif /* !ioread32_native */
1197
1198/* channel control reg access */
1199static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1200{
1201        return ioread32_native(chan->user + reg);
1202}
1203
1204static inline void nvchan_wr32(struct nouveau_channel *chan,
1205                                                        unsigned reg, u32 val)
1206{
1207        iowrite32_native(val, chan->user + reg);
1208}
1209
1210/* register access */
1211static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1212{
1213        struct drm_nouveau_private *dev_priv = dev->dev_private;
1214        return ioread32_native(dev_priv->mmio + reg);
1215}
1216
1217static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1218{
1219        struct drm_nouveau_private *dev_priv = dev->dev_private;
1220        iowrite32_native(val, dev_priv->mmio + reg);
1221}
1222
1223static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1224{
1225        struct drm_nouveau_private *dev_priv = dev->dev_private;
1226        return ioread8(dev_priv->mmio + reg);
1227}
1228
1229static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1230{
1231        struct drm_nouveau_private *dev_priv = dev->dev_private;
1232        iowrite8(val, dev_priv->mmio + reg);
1233}
1234
1235#define nv_wait(reg, mask, val) \
1236        nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1237
1238/* PRAMIN access */
1239static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1240{
1241        struct drm_nouveau_private *dev_priv = dev->dev_private;
1242        return ioread32_native(dev_priv->ramin + offset);
1243}
1244
1245static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1246{
1247        struct drm_nouveau_private *dev_priv = dev->dev_private;
1248        iowrite32_native(val, dev_priv->ramin + offset);
1249}
1250
1251/* object access */
1252static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1253                                unsigned index)
1254{
1255        return nv_ri32(dev, obj->im_pramin->start + index * 4);
1256}
1257
1258static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1259                                unsigned index, u32 val)
1260{
1261        nv_wi32(dev, obj->im_pramin->start + index * 4, val);
1262}
1263
1264/*
1265 * Logging
1266 * Argument d is (struct drm_device *).
1267 */
1268#define NV_PRINTK(level, d, fmt, arg...) \
1269        printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1270                                        pci_name(d->pdev), ##arg)
1271#ifndef NV_DEBUG_NOTRACE
1272#define NV_DEBUG(d, fmt, arg...) do {                                          \
1273        if (drm_debug & DRM_UT_DRIVER) {                                       \
1274                NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__,             \
1275                          __LINE__, ##arg);                                    \
1276        }                                                                      \
1277} while (0)
1278#define NV_DEBUG_KMS(d, fmt, arg...) do {                                      \
1279        if (drm_debug & DRM_UT_KMS) {                                          \
1280                NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__,             \
1281                          __LINE__, ##arg);                                    \
1282        }                                                                      \
1283} while (0)
1284#else
1285#define NV_DEBUG(d, fmt, arg...) do {                                          \
1286        if (drm_debug & DRM_UT_DRIVER)                                         \
1287                NV_PRINTK(KERN_DEBUG, d, fmt, ##arg);                          \
1288} while (0)
1289#define NV_DEBUG_KMS(d, fmt, arg...) do {                                      \
1290        if (drm_debug & DRM_UT_KMS)                                            \
1291                NV_PRINTK(KERN_DEBUG, d, fmt, ##arg);                          \
1292} while (0)
1293#endif
1294#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1295#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1296#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1297#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1298#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1299
1300/* nouveau_reg_debug bitmask */
1301enum {
1302        NOUVEAU_REG_DEBUG_MC             = 0x1,
1303        NOUVEAU_REG_DEBUG_VIDEO          = 0x2,
1304        NOUVEAU_REG_DEBUG_FB             = 0x4,
1305        NOUVEAU_REG_DEBUG_EXTDEV         = 0x8,
1306        NOUVEAU_REG_DEBUG_CRTC           = 0x10,
1307        NOUVEAU_REG_DEBUG_RAMDAC         = 0x20,
1308        NOUVEAU_REG_DEBUG_VGACRTC        = 0x40,
1309        NOUVEAU_REG_DEBUG_RMVIO          = 0x80,
1310        NOUVEAU_REG_DEBUG_VGAATTR        = 0x100,
1311        NOUVEAU_REG_DEBUG_EVO            = 0x200,
1312};
1313
1314#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1315        if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1316                NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1317} while (0)
1318
1319static inline bool
1320nv_two_heads(struct drm_device *dev)
1321{
1322        struct drm_nouveau_private *dev_priv = dev->dev_private;
1323        const int impl = dev->pci_device & 0x0ff0;
1324
1325        if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1326            impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1327                return true;
1328
1329        return false;
1330}
1331
1332static inline bool
1333nv_gf4_disp_arch(struct drm_device *dev)
1334{
1335        return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1336}
1337
1338static inline bool
1339nv_two_reg_pll(struct drm_device *dev)
1340{
1341        struct drm_nouveau_private *dev_priv = dev->dev_private;
1342        const int impl = dev->pci_device & 0x0ff0;
1343
1344        if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1345                return true;
1346        return false;
1347}
1348
1349#define NV_SW                                                        0x0000506e
1350#define NV_SW_DMA_SEMAPHORE                                          0x00000060
1351#define NV_SW_SEMAPHORE_OFFSET                                       0x00000064
1352#define NV_SW_SEMAPHORE_ACQUIRE                                      0x00000068
1353#define NV_SW_SEMAPHORE_RELEASE                                      0x0000006c
1354#define NV_SW_DMA_VBLSEM                                             0x0000018c
1355#define NV_SW_VBLSEM_OFFSET                                          0x00000400
1356#define NV_SW_VBLSEM_RELEASE_VALUE                                   0x00000404
1357#define NV_SW_VBLSEM_RELEASE                                         0x00000408
1358
1359#endif /* __NOUVEAU_DRV_H__ */
1360
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