LXR linux/drivers/net/r8169.c

   1/*
   2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3 *
   4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6 * Copyright (c) a lot of people too. Please respect their work.
   7 *
   8 * See MAINTAINERS file for support contact information.
   9 */
  10
  11#include <linux/module.h>
  12#include <linux/moduleparam.h>
  13#include <linux/pci.h>
  14#include <linux/netdevice.h>
  15#include <linux/etherdevice.h>
  16#include <linux/delay.h>
  17#include <linux/ethtool.h>
  18#include <linux/mii.h>
  19#include <linux/if_vlan.h>
  20#include <linux/crc32.h>
  21#include <linux/in.h>
  22#include <linux/ip.h>
  23#include <linux/tcp.h>
  24#include <linux/init.h>
  25#include <linux/dma-mapping.h>
  26#include <linux/pci-aspm.h>
  27
  28#include <asm/system.h>
  29#include <asm/io.h>
  30#include <asm/irq.h>
  31
  32#define RTL8169_VERSION "2.3LK-NAPI"
  33#define MODULENAME "r8169"
  34#define PFX MODULENAME ": "
  35
  36#ifdef RTL8169_DEBUG
  37#define assert(expr) \
  38        if (!(expr)) {                                  \
  39                printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  40                #expr,__FILE__,__func__,__LINE__);              \
  41        }
  42#define dprintk(fmt, args...) \
  43        do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  44#else
  45#define assert(expr) do {} while (0)
  46#define dprintk(fmt, args...)   do {} while (0)
  47#endif /* RTL8169_DEBUG */
  48
  49#define R8169_MSG_DEFAULT \
  50        (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  51
  52#define TX_BUFFS_AVAIL(tp) \
  53        (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  54
  55/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  56   The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  57static const int multicast_filter_limit = 32;
  58
  59/* MAC address length */
  60#define MAC_ADDR_LEN    6
  61
  62#define MAX_READ_REQUEST_SHIFT  12
  63#define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  64#define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  65#define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  66#define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  67#define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  68#define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  69
  70#define R8169_REGS_SIZE         256
  71#define R8169_NAPI_WEIGHT       64
  72#define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  73#define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  74#define RX_BUF_SIZE     1536    /* Rx Buffer size */
  75#define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  76#define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  77
  78#define RTL8169_TX_TIMEOUT      (6*HZ)
  79#define RTL8169_PHY_TIMEOUT     (10*HZ)
  80
  81#define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  82#define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  83#define RTL_EEPROM_SIG_ADDR     0x0000
  84
  85/* write/read MMIO register */
  86#define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  87#define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  88#define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  89#define RTL_R8(reg)             readb (ioaddr + (reg))
  90#define RTL_R16(reg)            readw (ioaddr + (reg))
  91#define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
  92
  93enum mac_version {
  94        RTL_GIGA_MAC_NONE   = 0x00,
  95        RTL_GIGA_MAC_VER_01 = 0x01, // 8169
  96        RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
  97        RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
  98        RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
  99        RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
 100        RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 101        RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
 102        RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
 103        RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
 104        RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
 105        RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 106        RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
 107        RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
 108        RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
 109        RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
 110        RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
 111        RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
 112        RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
 113        RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
 114        RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
 115        RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
 116        RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
 117        RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
 118        RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
 119        RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
 120        RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
 121        RTL_GIGA_MAC_VER_27 = 0x1b  // 8168DP
 122};
 123
 124#define _R(NAME,MAC,MASK) \
 125        { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 126
 127static const struct {
 128        const char *name;
 129        u8 mac_version;
 130        u32 RxConfigMask;       /* Clears the bits supported by this chip */
 131} rtl_chip_info[] = {
 132        _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 133        _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 134        _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 135        _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 136        _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 137        _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 138        _R("RTL8102e",          RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
 139        _R("RTL8102e",          RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
 140        _R("RTL8102e",          RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
 141        _R("RTL8101e",          RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
 142        _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 143        _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 144        _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 145        _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 146        _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
 147        _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
 148        _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
 149        _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
 150        _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
 151        _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
 152        _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
 153        _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
 154        _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
 155        _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
 156        _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
 157        _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
 158        _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_27, 0xff7e1880)  // PCI-E
 159};
 160#undef _R
 161
 162enum cfg_version {
 163        RTL_CFG_0 = 0x00,
 164        RTL_CFG_1,
 165        RTL_CFG_2
 166};
 167
 168static void rtl_hw_start_8169(struct net_device *);
 169static void rtl_hw_start_8168(struct net_device *);
 170static void rtl_hw_start_8101(struct net_device *);
 171
 172static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 173        { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 174        { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 175        { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 176        { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 177        { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 178        { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 179        { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 180        { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 181        { PCI_VENDOR_ID_LINKSYS,                0x1032,
 182                PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 183        { 0x0001,                               0x8168,
 184                PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 185        {0,},
 186};
 187
 188MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 189
 190/*
 191 * we set our copybreak very high so that we don't have
 192 * to allocate 16k frames all the time (see note in
 193 * rtl8169_open()
 194 */
 195static int rx_copybreak = 16383;
 196static int use_dac;
 197static struct {
 198        u32 msg_enable;
 199} debug = { -1 };
 200
 201enum rtl_registers {
 202        MAC0            = 0,    /* Ethernet hardware address. */
 203        MAC4            = 4,
 204        MAR0            = 8,    /* Multicast filter. */
 205        CounterAddrLow          = 0x10,
 206        CounterAddrHigh         = 0x14,
 207        TxDescStartAddrLow      = 0x20,
 208        TxDescStartAddrHigh     = 0x24,
 209        TxHDescStartAddrLow     = 0x28,
 210        TxHDescStartAddrHigh    = 0x2c,
 211        FLASH           = 0x30,
 212        ERSR            = 0x36,
 213        ChipCmd         = 0x37,
 214        TxPoll          = 0x38,
 215        IntrMask        = 0x3c,
 216        IntrStatus      = 0x3e,
 217        TxConfig        = 0x40,
 218        RxConfig        = 0x44,
 219        RxMissed        = 0x4c,
 220        Cfg9346         = 0x50,
 221        Config0         = 0x51,
 222        Config1         = 0x52,
 223        Config2         = 0x53,
 224        Config3         = 0x54,
 225        Config4         = 0x55,
 226        Config5         = 0x56,
 227        MultiIntr       = 0x5c,
 228        PHYAR           = 0x60,
 229        PHYstatus       = 0x6c,
 230        RxMaxSize       = 0xda,
 231        CPlusCmd        = 0xe0,
 232        IntrMitigate    = 0xe2,
 233        RxDescAddrLow   = 0xe4,
 234        RxDescAddrHigh  = 0xe8,
 235        EarlyTxThres    = 0xec,
 236        FuncEvent       = 0xf0,
 237        FuncEventMask   = 0xf4,
 238        FuncPresetState = 0xf8,
 239        FuncForceEvent  = 0xfc,
 240};
 241
 242enum rtl8110_registers {
 243        TBICSR                  = 0x64,
 244        TBI_ANAR                = 0x68,
 245        TBI_LPAR                = 0x6a,
 246};
 247
 248enum rtl8168_8101_registers {
 249        CSIDR                   = 0x64,
 250        CSIAR                   = 0x68,
 251#define CSIAR_FLAG                      0x80000000
 252#define CSIAR_WRITE_CMD                 0x80000000
 253#define CSIAR_BYTE_ENABLE               0x0f
 254#define CSIAR_BYTE_ENABLE_SHIFT         12
 255#define CSIAR_ADDR_MASK                 0x0fff
 256
 257        EPHYAR                  = 0x80,
 258#define EPHYAR_FLAG                     0x80000000
 259#define EPHYAR_WRITE_CMD                0x80000000
 260#define EPHYAR_REG_MASK                 0x1f
 261#define EPHYAR_REG_SHIFT                16
 262#define EPHYAR_DATA_MASK                0xffff
 263        DBG_REG                 = 0xd1,
 264#define FIX_NAK_1                       (1 << 4)
 265#define FIX_NAK_2                       (1 << 3)
 266        EFUSEAR                 = 0xdc,
 267#define EFUSEAR_FLAG                    0x80000000
 268#define EFUSEAR_WRITE_CMD               0x80000000
 269#define EFUSEAR_READ_CMD                0x00000000
 270#define EFUSEAR_REG_MASK                0x03ff
 271#define EFUSEAR_REG_SHIFT               8
 272#define EFUSEAR_DATA_MASK               0xff
 273};
 274
 275enum rtl_register_content {
 276        /* InterruptStatusBits */
 277        SYSErr          = 0x8000,
 278        PCSTimeout      = 0x4000,
 279        SWInt           = 0x0100,
 280        TxDescUnavail   = 0x0080,
 281        RxFIFOOver      = 0x0040,
 282        LinkChg         = 0x0020,
 283        RxOverflow      = 0x0010,
 284        TxErr           = 0x0008,
 285        TxOK            = 0x0004,
 286        RxErr           = 0x0002,
 287        RxOK            = 0x0001,
 288
 289        /* RxStatusDesc */
 290        RxFOVF  = (1 << 23),
 291        RxRWT   = (1 << 22),
 292        RxRES   = (1 << 21),
 293        RxRUNT  = (1 << 20),
 294        RxCRC   = (1 << 19),
 295
 296        /* ChipCmdBits */
 297        CmdReset        = 0x10,
 298        CmdRxEnb        = 0x08,
 299        CmdTxEnb        = 0x04,
 300        RxBufEmpty      = 0x01,
 301
 302        /* TXPoll register p.5 */
 303        HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 304        NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 305        FSWInt          = 0x01,         /* Forced software interrupt */
 306
 307        /* Cfg9346Bits */
 308        Cfg9346_Lock    = 0x00,
 309        Cfg9346_Unlock  = 0xc0,
 310
 311        /* rx_mode_bits */
 312        AcceptErr       = 0x20,
 313        AcceptRunt      = 0x10,
 314        AcceptBroadcast = 0x08,
 315        AcceptMulticast = 0x04,
 316        AcceptMyPhys    = 0x02,
 317        AcceptAllPhys   = 0x01,
 318
 319        /* RxConfigBits */
 320        RxCfgFIFOShift  = 13,
 321        RxCfgDMAShift   =  8,
 322
 323        /* TxConfigBits */
 324        TxInterFrameGapShift = 24,
 325        TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 326
 327        /* Config1 register p.24 */
 328        LEDS1           = (1 << 7),
 329        LEDS0           = (1 << 6),
 330        MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 331        Speed_down      = (1 << 4),
 332        MEMMAP          = (1 << 3),
 333        IOMAP           = (1 << 2),
 334        VPD             = (1 << 1),
 335        PMEnable        = (1 << 0),     /* Power Management Enable */
 336
 337        /* Config2 register p. 25 */
 338        PCI_Clock_66MHz = 0x01,
 339        PCI_Clock_33MHz = 0x00,
 340
 341        /* Config3 register p.25 */
 342        MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 343        LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 344        Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 345
 346        /* Config5 register p.27 */
 347        BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 348        MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 349        UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 350        LanWake         = (1 << 1),     /* LanWake enable/disable */
 351        PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 352
 353        /* TBICSR p.28 */
 354        TBIReset        = 0x80000000,
 355        TBILoopback     = 0x40000000,
 356        TBINwEnable     = 0x20000000,
 357        TBINwRestart    = 0x10000000,
 358        TBILinkOk       = 0x02000000,
 359        TBINwComplete   = 0x01000000,
 360
 361        /* CPlusCmd p.31 */
 362        EnableBist      = (1 << 15),    // 8168 8101
 363        Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 364        Normal_mode     = (1 << 13),    // unused
 365        Force_half_dup  = (1 << 12),    // 8168 8101
 366        Force_rxflow_en = (1 << 11),    // 8168 8101
 367        Force_txflow_en = (1 << 10),    // 8168 8101
 368        Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 369        ASF             = (1 << 8),     // 8168 8101
 370        PktCntrDisable  = (1 << 7),     // 8168 8101
 371        Mac_dbgo_sel    = 0x001c,       // 8168
 372        RxVlan          = (1 << 6),
 373        RxChkSum        = (1 << 5),
 374        PCIDAC          = (1 << 4),
 375        PCIMulRW        = (1 << 3),
 376        INTT_0          = 0x0000,       // 8168
 377        INTT_1          = 0x0001,       // 8168
 378        INTT_2          = 0x0002,       // 8168
 379        INTT_3          = 0x0003,       // 8168
 380
 381        /* rtl8169_PHYstatus */
 382        TBI_Enable      = 0x80,
 383        TxFlowCtrl      = 0x40,
 384        RxFlowCtrl      = 0x20,
 385        _1000bpsF       = 0x10,
 386        _100bps         = 0x08,
 387        _10bps          = 0x04,
 388        LinkStatus      = 0x02,
 389        FullDup         = 0x01,
 390
 391        /* _TBICSRBit */
 392        TBILinkOK       = 0x02000000,
 393
 394        /* DumpCounterCommand */
 395        CounterDump     = 0x8,
 396};
 397
 398enum desc_status_bit {
 399        DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 400        RingEnd         = (1 << 30), /* End of descriptor ring */
 401        FirstFrag       = (1 << 29), /* First segment of a packet */
 402        LastFrag        = (1 << 28), /* Final segment of a packet */
 403
 404        /* Tx private */
 405        LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 406        MSSShift        = 16,        /* MSS value position */
 407        MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 408        IPCS            = (1 << 18), /* Calculate IP checksum */
 409        UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 410        TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 411        TxVlanTag       = (1 << 17), /* Add VLAN tag */
 412
 413        /* Rx private */
 414        PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 415        PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 416
 417#define RxProtoUDP      (PID1)
 418#define RxProtoTCP      (PID0)
 419#define RxProtoIP       (PID1 | PID0)
 420#define RxProtoMask     RxProtoIP
 421
 422        IPFail          = (1 << 16), /* IP checksum failed */
 423        UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 424        TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 425        RxVlanTag       = (1 << 16), /* VLAN tag available */
 426};
 427
 428#define RsvdMask        0x3fffc000
 429
 430struct TxDesc {
 431        __le32 opts1;
 432        __le32 opts2;
 433        __le64 addr;
 434};
 435
 436struct RxDesc {
 437        __le32 opts1;
 438        __le32 opts2;
 439        __le64 addr;
 440};
 441
 442struct ring_info {
 443        struct sk_buff  *skb;
 444        u32             len;
 445        u8              __pad[sizeof(void *) - sizeof(u32)];
 446};
 447
 448enum features {
 449        RTL_FEATURE_WOL         = (1 << 0),
 450        RTL_FEATURE_MSI         = (1 << 1),
 451        RTL_FEATURE_GMII        = (1 << 2),
 452};
 453
 454struct rtl8169_counters {
 455        __le64  tx_packets;
 456        __le64  rx_packets;
 457        __le64  tx_errors;
 458        __le32  rx_errors;
 459        __le16  rx_missed;
 460        __le16  align_errors;
 461        __le32  tx_one_collision;
 462        __le32  tx_multi_collision;
 463        __le64  rx_unicast;
 464        __le64  rx_broadcast;
 465        __le32  rx_multicast;
 466        __le16  tx_aborted;
 467        __le16  tx_underun;
 468};
 469
 470struct rtl8169_private {
 471        void __iomem *mmio_addr;        /* memory map physical address */
 472        struct pci_dev *pci_dev;        /* Index of PCI device */
 473        struct net_device *dev;
 474        struct napi_struct napi;
 475        spinlock_t lock;                /* spin lock flag */
 476        u32 msg_enable;
 477        int chipset;
 478        int mac_version;
 479        u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 480        u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 481        u32 dirty_rx;
 482        u32 dirty_tx;
 483        struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 484        struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 485        dma_addr_t TxPhyAddr;
 486        dma_addr_t RxPhyAddr;
 487        struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
 488        struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 489        unsigned align;
 490        unsigned rx_buf_sz;
 491        struct timer_list timer;
 492        u16 cp_cmd;
 493        u16 intr_event;
 494        u16 napi_event;
 495        u16 intr_mask;
 496        int phy_1000_ctrl_reg;
 497#ifdef CONFIG_R8169_VLAN
 498        struct vlan_group *vlgrp;
 499#endif
 500        int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 501        int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 502        void (*phy_reset_enable)(void __iomem *);
 503        void (*hw_start)(struct net_device *);
 504        unsigned int (*phy_reset_pending)(void __iomem *);
 505        unsigned int (*link_ok)(void __iomem *);
 506        int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 507        int pcie_cap;
 508        struct delayed_work task;
 509        unsigned features;
 510
 511        struct mii_if_info mii;
 512        struct rtl8169_counters counters;
 513};
 514
 515MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 516MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 517module_param(rx_copybreak, int, 0);
 518MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
 519module_param(use_dac, int, 0);
 520MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 521module_param_named(debug, debug.msg_enable, int, 0);
 522MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 523MODULE_LICENSE("GPL");
 524MODULE_VERSION(RTL8169_VERSION);
 525
 526static int rtl8169_open(struct net_device *dev);
 527static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 528                                      struct net_device *dev);
 529static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 530static int rtl8169_init_ring(struct net_device *dev);
 531static void rtl_hw_start(struct net_device *dev);
 532static int rtl8169_close(struct net_device *dev);
 533static void rtl_set_rx_mode(struct net_device *dev);
 534static void rtl8169_tx_timeout(struct net_device *dev);
 535static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 536static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 537                                void __iomem *, u32 budget);
 538static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 539static void rtl8169_down(struct net_device *dev);
 540static void rtl8169_rx_clear(struct rtl8169_private *tp);
 541static int rtl8169_poll(struct napi_struct *napi, int budget);
 542
 543static const unsigned int rtl8169_rx_config =
 544        (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 545
 546static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 547{
 548        int i;
 549
 550        RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 551
 552        for (i = 20; i > 0; i--) {
 553                /*
 554                 * Check if the RTL8169 has completed writing to the specified
 555                 * MII register.
 556                 */
 557                if (!(RTL_R32(PHYAR) & 0x80000000))
 558                        break;
 559                udelay(25);
 560        }
 561        /*
 562         * According to hardware specs a 20us delay is required after write
 563         * complete indication, but before sending next command.
 564         */
 565        udelay(20);
 566}
 567
 568static int mdio_read(void __iomem *ioaddr, int reg_addr)
 569{
 570        int i, value = -1;
 571
 572        RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 573
 574        for (i = 20; i > 0; i--) {
 575                /*
 576                 * Check if the RTL8169 has completed retrieving data from
 577                 * the specified MII register.
 578                 */
 579                if (RTL_R32(PHYAR) & 0x80000000) {
 580                        value = RTL_R32(PHYAR) & 0xffff;
 581                        break;
 582                }
 583                udelay(25);
 584        }
 585        /*
 586         * According to hardware specs a 20us delay is required after read
 587         * complete indication, but before sending next command.
 588         */
 589        udelay(20);
 590
 591        return value;
 592}
 593
 594static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
 595{
 596        mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
 597}
 598
 599static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
 600{
 601        int val;
 602
 603        val = mdio_read(ioaddr, reg_addr);
 604        mdio_write(ioaddr, reg_addr, (val | p) & ~m);
 605}
 606
 607static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 608                           int val)
 609{
 610        struct rtl8169_private *tp = netdev_priv(dev);
 611        void __iomem *ioaddr = tp->mmio_addr;
 612
 613        mdio_write(ioaddr, location, val);
 614}
 615
 616static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 617{
 618        struct rtl8169_private *tp = netdev_priv(dev);
 619        void __iomem *ioaddr = tp->mmio_addr;
 620
 621        return mdio_read(ioaddr, location);
 622}
 623
 624static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 625{
 626        unsigned int i;
 627
 628        RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 629                (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 630
 631        for (i = 0; i < 100; i++) {
 632                if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 633                        break;
 634                udelay(10);
 635        }
 636}
 637
 638static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
 639{
 640        u16 value = 0xffff;
 641        unsigned int i;
 642
 643        RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 644
 645        for (i = 0; i < 100; i++) {
 646                if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
 647                        value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
 648                        break;
 649                }
 650                udelay(10);
 651        }
 652
 653        return value;
 654}
 655
 656static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
 657{
 658        unsigned int i;
 659
 660        RTL_W32(CSIDR, value);
 661        RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
 662                CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 663
 664        for (i = 0; i < 100; i++) {
 665                if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
 666                        break;
 667                udelay(10);
 668        }
 669}
 670
 671static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
 672{
 673        u32 value = ~0x00;
 674        unsigned int i;
 675
 676        RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
 677                CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 678
 679        for (i = 0; i < 100; i++) {
 680                if (RTL_R32(CSIAR) & CSIAR_FLAG) {
 681                        value = RTL_R32(CSIDR);
 682                        break;
 683                }
 684                udelay(10);
 685        }
 686
 687        return value;
 688}
 689
 690static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
 691{
 692        u8 value = 0xff;
 693        unsigned int i;
 694
 695        RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
 696
 697        for (i = 0; i < 300; i++) {
 698                if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
 699                        value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
 700                        break;
 701                }
 702                udelay(100);
 703        }
 704
 705        return value;
 706}
 707
 708static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 709{
 710        RTL_W16(IntrMask, 0x0000);
 711
 712        RTL_W16(IntrStatus, 0xffff);
 713}
 714
 715static void rtl8169_asic_down(void __iomem *ioaddr)
 716{
 717        RTL_W8(ChipCmd, 0x00);
 718        rtl8169_irq_mask_and_ack(ioaddr);
 719        RTL_R16(CPlusCmd);
 720}
 721
 722static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
 723{
 724        return RTL_R32(TBICSR) & TBIReset;
 725}
 726
 727static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
 728{
 729        return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
 730}
 731
 732static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 733{
 734        return RTL_R32(TBICSR) & TBILinkOk;
 735}
 736
 737static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 738{
 739        return RTL_R8(PHYstatus) & LinkStatus;
 740}
 741
 742static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
 743{
 744        RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 745}
 746
 747static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
 748{
 749        unsigned int val;
 750
 751        val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
 752        mdio_write(ioaddr, MII_BMCR, val & 0xffff);
 753}
 754
 755static void rtl8169_check_link_status(struct net_device *dev,
 756                                      struct rtl8169_private *tp,
 757                                      void __iomem *ioaddr)
 758{
 759        unsigned long flags;
 760
 761        spin_lock_irqsave(&tp->lock, flags);
 762        if (tp->link_ok(ioaddr)) {
 763                netif_carrier_on(dev);
 764                netif_info(tp, ifup, dev, "link up\n");
 765        } else {
 766                netif_carrier_off(dev);
 767                netif_info(tp, ifdown, dev, "link down\n");
 768        }
 769        spin_unlock_irqrestore(&tp->lock, flags);
 770}
 771
 772static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 773{
 774        struct rtl8169_private *tp = netdev_priv(dev);
 775        void __iomem *ioaddr = tp->mmio_addr;
 776        u8 options;
 777
 778        wol->wolopts = 0;
 779
 780#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 781        wol->supported = WAKE_ANY;
 782
 783        spin_lock_irq(&tp->lock);
 784
 785        options = RTL_R8(Config1);
 786        if (!(options & PMEnable))
 787                goto out_unlock;
 788
 789        options = RTL_R8(Config3);
 790        if (options & LinkUp)
 791                wol->wolopts |= WAKE_PHY;
 792        if (options & MagicPacket)
 793                wol->wolopts |= WAKE_MAGIC;
 794
 795        options = RTL_R8(Config5);
 796        if (options & UWF)
 797                wol->wolopts |= WAKE_UCAST;
 798        if (options & BWF)
 799                wol->wolopts |= WAKE_BCAST;
 800        if (options & MWF)
 801                wol->wolopts |= WAKE_MCAST;
 802
 803out_unlock:
 804        spin_unlock_irq(&tp->lock);
 805}
 806
 807static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 808{
 809        struct rtl8169_private *tp = netdev_priv(dev);
 810        void __iomem *ioaddr = tp->mmio_addr;
 811        unsigned int i;
 812        static const struct {
 813                u32 opt;
 814                u16 reg;
 815                u8  mask;
 816        } cfg[] = {
 817                { WAKE_ANY,   Config1, PMEnable },
 818                { WAKE_PHY,   Config3, LinkUp },
 819                { WAKE_MAGIC, Config3, MagicPacket },
 820                { WAKE_UCAST, Config5, UWF },
 821                { WAKE_BCAST, Config5, BWF },
 822                { WAKE_MCAST, Config5, MWF },
 823                { WAKE_ANY,   Config5, LanWake }
 824        };
 825
 826        spin_lock_irq(&tp->lock);
 827
 828        RTL_W8(Cfg9346, Cfg9346_Unlock);
 829
 830        for (i = 0; i < ARRAY_SIZE(cfg); i++) {
 831                u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
 832                if (wol->wolopts & cfg[i].opt)
 833                        options |= cfg[i].mask;
 834                RTL_W8(cfg[i].reg, options);
 835        }
 836
 837        RTL_W8(Cfg9346, Cfg9346_Lock);
 838
 839        if (wol->wolopts)
 840                tp->features |= RTL_FEATURE_WOL;
 841        else
 842                tp->features &= ~RTL_FEATURE_WOL;
 843        device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
 844
 845        spin_unlock_irq(&tp->lock);
 846
 847        return 0;
 848}
 849
 850static void rtl8169_get_drvinfo(struct net_device *dev,
 851                                struct ethtool_drvinfo *info)
 852{
 853        struct rtl8169_private *tp = netdev_priv(dev);
 854
 855        strcpy(info->driver, MODULENAME);
 856        strcpy(info->version, RTL8169_VERSION);
 857        strcpy(info->bus_info, pci_name(tp->pci_dev));
 858}
 859
 860static int rtl8169_get_regs_len(struct net_device *dev)
 861{
 862        return R8169_REGS_SIZE;
 863}
 864
 865static int rtl8169_set_speed_tbi(struct net_device *dev,
 866                                 u8 autoneg, u16 speed, u8 duplex)
 867{
 868        struct rtl8169_private *tp = netdev_priv(dev);
 869        void __iomem *ioaddr = tp->mmio_addr;
 870        int ret = 0;
 871        u32 reg;
 872
 873        reg = RTL_R32(TBICSR);
 874        if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
 875            (duplex == DUPLEX_FULL)) {
 876                RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
 877        } else if (autoneg == AUTONEG_ENABLE)
 878                RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
 879        else {
 880                netif_warn(tp, link, dev,
 881                           "incorrect speed setting refused in TBI mode\n");
 882                ret = -EOPNOTSUPP;
 883        }
 884
 885        return ret;
 886}
 887
 888static int rtl8169_set_speed_xmii(struct net_device *dev,
 889                                  u8 autoneg, u16 speed, u8 duplex)
 890{
 891        struct rtl8169_private *tp = netdev_priv(dev);
 892        void __iomem *ioaddr = tp->mmio_addr;
 893        int giga_ctrl, bmcr;
 894
 895        if (autoneg == AUTONEG_ENABLE) {
 896                int auto_nego;
 897
 898                auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
 899                auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
 900                              ADVERTISE_100HALF | ADVERTISE_100FULL);
 901                auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 902
 903                giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
 904                giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 905
 906                /* The 8100e/8101e/8102e do Fast Ethernet only. */
 907                if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
 908                    (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
 909                    (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
 910                    (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
 911                    (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
 912                    (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
 913                    (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
 914                    (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
 915                        giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 916                } else {
 917                        netif_info(tp, link, dev,
 918                                   "PHY does not support 1000Mbps\n");
 919                }
 920
 921                bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
 922
 923                if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
 924                    (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
 925                    (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
 926                        /*
 927                         * Wake up the PHY.
 928                         * Vendor specific (0x1f) and reserved (0x0e) MII
 929                         * registers.
 930                         */
 931                        mdio_write(ioaddr, 0x1f, 0x0000);
 932                        mdio_write(ioaddr, 0x0e, 0x0000);
 933                }
 934
 935                mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
 936                mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
 937        } else {
 938                giga_ctrl = 0;
 939
 940                if (speed == SPEED_10)
 941                        bmcr = 0;
 942                else if (speed == SPEED_100)
 943                        bmcr = BMCR_SPEED100;
 944                else
 945                        return -EINVAL;
 946
 947                if (duplex == DUPLEX_FULL)
 948                        bmcr |= BMCR_FULLDPLX;
 949
 950                mdio_write(ioaddr, 0x1f, 0x0000);
 951        }
 952
 953        tp->phy_1000_ctrl_reg = giga_ctrl;
 954
 955        mdio_write(ioaddr, MII_BMCR, bmcr);
 956
 957        if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
 958            (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
 959                if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
 960                        mdio_write(ioaddr, 0x17, 0x2138);
 961                        mdio_write(ioaddr, 0x0e, 0x0260);
 962                } else {
 963                        mdio_write(ioaddr, 0x17, 0x2108);
 964                        mdio_write(ioaddr, 0x0e, 0x0000);
 965                }
 966        }
 967
 968        return 0;
 969}
 970
 971static int rtl8169_set_speed(struct net_device *dev,
 972                             u8 autoneg, u16 speed, u8 duplex)
 973{
 974        struct rtl8169_private *tp = netdev_priv(dev);
 975        int ret;
 976
 977        ret = tp->set_speed(dev, autoneg, speed, duplex);
 978
 979        if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
 980                mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
 981
 982        return ret;
 983}
 984
 985static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 986{
 987        struct rtl8169_private *tp = netdev_priv(dev);
 988        unsigned long flags;
 989        int ret;
 990
 991        spin_lock_irqsave(&tp->lock, flags);
 992        ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
 993        spin_unlock_irqrestore(&tp->lock, flags);
 994
 995        return ret;
 996}
 997
 998static u32 rtl8169_get_rx_csum(struct net_device *dev)
 999{
1000        struct rtl8169_private *tp = netdev_priv(dev);

1001
1002        return tp->cp_cmd & RxChkSum;
1003}
1004
1005static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1006{
1007        struct rtl8169_private *tp = netdev_priv(dev);
1008        void __iomem *ioaddr = tp->mmio_addr;
1009        unsigned long flags;
1010
1011        spin_lock_irqsave(&tp->lock, flags);
1012
1013        if (data)
1014                tp->cp_cmd |= RxChkSum;
1015        else
1016                tp->cp_cmd &= ~RxChkSum;
1017
1018        RTL_W16(CPlusCmd, tp->cp_cmd);
1019        RTL_R16(CPlusCmd);
1020
1021        spin_unlock_irqrestore(&tp->lock, flags);
1022
1023        return 0;
1024}
1025
1026#ifdef CONFIG_R8169_VLAN
1027
1028static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1029                                      struct sk_buff *skb)
1030{
1031        return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
1032                TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1033}
1034
1035static void rtl8169_vlan_rx_register(struct net_device *dev,
1036                                     struct vlan_group *grp)
1037{
1038        struct rtl8169_private *tp = netdev_priv(dev);
1039        void __iomem *ioaddr = tp->mmio_addr;
1040        unsigned long flags;
1041
1042        spin_lock_irqsave(&tp->lock, flags);
1043        tp->vlgrp = grp;
1044        /*
1045         * Do not disable RxVlan on 8110SCd.
1046         */
1047        if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1048                tp->cp_cmd |= RxVlan;
1049        else
1050                tp->cp_cmd &= ~RxVlan;
1051        RTL_W16(CPlusCmd, tp->cp_cmd);
1052        RTL_R16(CPlusCmd);
1053        spin_unlock_irqrestore(&tp->lock, flags);
1054}
1055
1056static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1057                               struct sk_buff *skb, int polling)
1058{
1059        u32 opts2 = le32_to_cpu(desc->opts2);
1060        struct vlan_group *vlgrp = tp->vlgrp;
1061        int ret;
1062
1063        if (vlgrp && (opts2 & RxVlanTag)) {
1064                __vlan_hwaccel_rx(skb, vlgrp, swab16(opts2 & 0xffff), polling);
1065                ret = 0;
1066        } else
1067                ret = -1;
1068        desc->opts2 = 0;
1069        return ret;
1070}
1071
1072#else /* !CONFIG_R8169_VLAN */
1073
1074static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1075                                      struct sk_buff *skb)
1076{
1077        return 0;
1078}
1079
1080static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1081                               struct sk_buff *skb, int polling)
1082{
1083        return -1;
1084}
1085
1086#endif
1087
1088static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1089{
1090        struct rtl8169_private *tp = netdev_priv(dev);
1091        void __iomem *ioaddr = tp->mmio_addr;
1092        u32 status;
1093
1094        cmd->supported =
1095                SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1096        cmd->port = PORT_FIBRE;
1097        cmd->transceiver = XCVR_INTERNAL;
1098
1099        status = RTL_R32(TBICSR);
1100        cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1101        cmd->autoneg = !!(status & TBINwEnable);
1102
1103        cmd->speed = SPEED_1000;
1104        cmd->duplex = DUPLEX_FULL; /* Always set */
1105
1106        return 0;
1107}
1108
1109static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1110{
1111        struct rtl8169_private *tp = netdev_priv(dev);
1112
1113        return mii_ethtool_gset(&tp->mii, cmd);
1114}
1115
1116static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1117{
1118        struct rtl8169_private *tp = netdev_priv(dev);
1119        unsigned long flags;
1120        int rc;
1121
1122        spin_lock_irqsave(&tp->lock, flags);
1123
1124        rc = tp->get_settings(dev, cmd);
1125
1126        spin_unlock_irqrestore(&tp->lock, flags);
1127        return rc;
1128}
1129
1130static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1131                             void *p)
1132{
1133        struct rtl8169_private *tp = netdev_priv(dev);
1134        unsigned long flags;
1135
1136        if (regs->len > R8169_REGS_SIZE)
1137                regs->len = R8169_REGS_SIZE;
1138
1139        spin_lock_irqsave(&tp->lock, flags);
1140        memcpy_fromio(p, tp->mmio_addr, regs->len);
1141        spin_unlock_irqrestore(&tp->lock, flags);
1142}
1143
1144static u32 rtl8169_get_msglevel(struct net_device *dev)
1145{
1146        struct rtl8169_private *tp = netdev_priv(dev);
1147
1148        return tp->msg_enable;
1149}
1150
1151static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1152{
1153        struct rtl8169_private *tp = netdev_priv(dev);
1154
1155        tp->msg_enable = value;
1156}
1157
1158static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1159        "tx_packets",
1160        "rx_packets",
1161        "tx_errors",
1162        "rx_errors",
1163        "rx_missed",
1164        "align_errors",
1165        "tx_single_collisions",
1166        "tx_multi_collisions",
1167        "unicast",
1168        "broadcast",
1169        "multicast",
1170        "tx_aborted",
1171        "tx_underrun",
1172};
1173
1174static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1175{
1176        switch (sset) {
1177        case ETH_SS_STATS:
1178                return ARRAY_SIZE(rtl8169_gstrings);
1179        default:
1180                return -EOPNOTSUPP;
1181        }
1182}
1183
1184static void rtl8169_update_counters(struct net_device *dev)
1185{
1186        struct rtl8169_private *tp = netdev_priv(dev);
1187        void __iomem *ioaddr = tp->mmio_addr;
1188        struct rtl8169_counters *counters;
1189        dma_addr_t paddr;
1190        u32 cmd;
1191        int wait = 1000;
1192
1193        /*
1194         * Some chips are unable to dump tally counters when the receiver
1195         * is disabled.
1196         */
1197        if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1198                return;
1199
1200        counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1201        if (!counters)
1202                return;
1203
1204        RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1205        cmd = (u64)paddr & DMA_BIT_MASK(32);
1206        RTL_W32(CounterAddrLow, cmd);
1207        RTL_W32(CounterAddrLow, cmd | CounterDump);
1208
1209        while (wait--) {
1210                if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1211                        /* copy updated counters */
1212                        memcpy(&tp->counters, counters, sizeof(*counters));
1213                        break;
1214                }
1215                udelay(10);
1216        }
1217
1218        RTL_W32(CounterAddrLow, 0);
1219        RTL_W32(CounterAddrHigh, 0);
1220
1221        pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1222}
1223
1224static void rtl8169_get_ethtool_stats(struct net_device *dev,
1225                                      struct ethtool_stats *stats, u64 *data)
1226{
1227        struct rtl8169_private *tp = netdev_priv(dev);
1228
1229        ASSERT_RTNL();
1230
1231        rtl8169_update_counters(dev);
1232
1233        data[0] = le64_to_cpu(tp->counters.tx_packets);
1234        data[1] = le64_to_cpu(tp->counters.rx_packets);
1235        data[2] = le64_to_cpu(tp->counters.tx_errors);
1236        data[3] = le32_to_cpu(tp->counters.rx_errors);
1237        data[4] = le16_to_cpu(tp->counters.rx_missed);
1238        data[5] = le16_to_cpu(tp->counters.align_errors);
1239        data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1240        data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1241        data[8] = le64_to_cpu(tp->counters.rx_unicast);
1242        data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1243        data[10] = le32_to_cpu(tp->counters.rx_multicast);
1244        data[11] = le16_to_cpu(tp->counters.tx_aborted);
1245        data[12] = le16_to_cpu(tp->counters.tx_underun);
1246}
1247
1248static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1249{
1250        switch(stringset) {
1251        case ETH_SS_STATS:
1252                memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1253                break;
1254        }
1255}
1256
1257static const struct ethtool_ops rtl8169_ethtool_ops = {
1258        .get_drvinfo            = rtl8169_get_drvinfo,
1259        .get_regs_len           = rtl8169_get_regs_len,
1260        .get_link               = ethtool_op_get_link,
1261        .get_settings           = rtl8169_get_settings,
1262        .set_settings           = rtl8169_set_settings,
1263        .get_msglevel           = rtl8169_get_msglevel,
1264        .set_msglevel           = rtl8169_set_msglevel,
1265        .get_rx_csum            = rtl8169_get_rx_csum,
1266        .set_rx_csum            = rtl8169_set_rx_csum,
1267        .set_tx_csum            = ethtool_op_set_tx_csum,
1268        .set_sg                 = ethtool_op_set_sg,
1269        .set_tso                = ethtool_op_set_tso,
1270        .get_regs               = rtl8169_get_regs,
1271        .get_wol                = rtl8169_get_wol,
1272        .set_wol                = rtl8169_set_wol,
1273        .get_strings            = rtl8169_get_strings,
1274        .get_sset_count         = rtl8169_get_sset_count,
1275        .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1276};
1277
1278static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1279                                    void __iomem *ioaddr)
1280{
1281        /*
1282         * The driver currently handles the 8168Bf and the 8168Be identically
1283         * but they can be identified more specifically through the test below
1284         * if needed:
1285         *
1286         * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1287         *
1288         * Same thing for the 8101Eb and the 8101Ec:
1289         *
1290         * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1291         */
1292        static const struct {
1293                u32 mask;
1294                u32 val;
1295                int mac_version;
1296        } mac_info[] = {
1297                /* 8168D family. */
1298                { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1299                { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1300                { 0x7c800000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1301                { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1302
1303                /* 8168C family. */
1304                { 0x7cf00000, 0x3ca00000,       RTL_GIGA_MAC_VER_24 },
1305                { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1306                { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1307                { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1308                { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1309                { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1310                { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1311                { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1312                { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1313
1314                /* 8168B family. */
1315                { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1316                { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1317                { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1318                { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1319
1320                /* 8101 family. */
1321                { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1322                { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1323                { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1324                { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1325                { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1326                { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1327                { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1328                { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1329                { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1330                { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1331                { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1332                { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1333                /* FIXME: where did these entries come from ? -- FR */
1334                { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1335                { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1336
1337                /* 8110 family. */
1338                { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1339                { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1340                { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1341                { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1342                { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1343                { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1344
1345                /* Catch-all */
1346                { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1347        }, *p = mac_info;
1348        u32 reg;
1349
1350        reg = RTL_R32(TxConfig);
1351        while ((reg & p->mask) != p->val)
1352                p++;
1353        tp->mac_version = p->mac_version;
1354}
1355
1356static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1357{
1358        dprintk("mac_version = 0x%02x\n", tp->mac_version);
1359}
1360
1361struct phy_reg {
1362        u16 reg;
1363        u16 val;
1364};
1365
1366static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len)
1367{
1368        while (len-- > 0) {
1369                mdio_write(ioaddr, regs->reg, regs->val);
1370                regs++;
1371        }
1372}
1373
1374static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1375{
1376        static const struct phy_reg phy_reg_init[] = {
1377                { 0x1f, 0x0001 },
1378                { 0x06, 0x006e },
1379                { 0x08, 0x0708 },
1380                { 0x15, 0x4000 },
1381                { 0x18, 0x65c7 },
1382
1383                { 0x1f, 0x0001 },
1384                { 0x03, 0x00a1 },
1385                { 0x02, 0x0008 },
1386                { 0x01, 0x0120 },
1387                { 0x00, 0x1000 },
1388                { 0x04, 0x0800 },
1389                { 0x04, 0x0000 },
1390
1391                { 0x03, 0xff41 },
1392                { 0x02, 0xdf60 },
1393                { 0x01, 0x0140 },
1394                { 0x00, 0x0077 },
1395                { 0x04, 0x7800 },
1396                { 0x04, 0x7000 },
1397
1398                { 0x03, 0x802f },
1399                { 0x02, 0x4f02 },
1400                { 0x01, 0x0409 },
1401                { 0x00, 0xf0f9 },
1402                { 0x04, 0x9800 },
1403                { 0x04, 0x9000 },
1404
1405                { 0x03, 0xdf01 },
1406                { 0x02, 0xdf20 },
1407                { 0x01, 0xff95 },
1408                { 0x00, 0xba00 },
1409                { 0x04, 0xa800 },
1410                { 0x04, 0xa000 },
1411
1412                { 0x03, 0xff41 },
1413                { 0x02, 0xdf20 },
1414                { 0x01, 0x0140 },
1415                { 0x00, 0x00bb },
1416                { 0x04, 0xb800 },
1417                { 0x04, 0xb000 },
1418
1419                { 0x03, 0xdf41 },
1420                { 0x02, 0xdc60 },
1421                { 0x01, 0x6340 },
1422                { 0x00, 0x007d },
1423                { 0x04, 0xd800 },
1424                { 0x04, 0xd000 },
1425
1426                { 0x03, 0xdf01 },
1427                { 0x02, 0xdf20 },
1428                { 0x01, 0x100a },
1429                { 0x00, 0xa0ff },
1430                { 0x04, 0xf800 },
1431                { 0x04, 0xf000 },
1432
1433                { 0x1f, 0x0000 },
1434                { 0x0b, 0x0000 },
1435                { 0x00, 0x9200 }
1436        };
1437
1438        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1439}
1440
1441static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1442{
1443        static const struct phy_reg phy_reg_init[] = {
1444                { 0x1f, 0x0002 },
1445                { 0x01, 0x90d0 },
1446                { 0x1f, 0x0000 }
1447        };
1448
1449        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1450}
1451
1452static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1453                                           void __iomem *ioaddr)
1454{
1455        struct pci_dev *pdev = tp->pci_dev;
1456        u16 vendor_id, device_id;
1457
1458        pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1459        pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1460
1461        if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1462                return;
1463
1464        mdio_write(ioaddr, 0x1f, 0x0001);
1465        mdio_write(ioaddr, 0x10, 0xf01b);
1466        mdio_write(ioaddr, 0x1f, 0x0000);
1467}
1468
1469static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1470                                     void __iomem *ioaddr)
1471{
1472        static const struct phy_reg phy_reg_init[] = {
1473                { 0x1f, 0x0001 },
1474                { 0x04, 0x0000 },
1475                { 0x03, 0x00a1 },
1476                { 0x02, 0x0008 },
1477                { 0x01, 0x0120 },
1478                { 0x00, 0x1000 },
1479                { 0x04, 0x0800 },
1480                { 0x04, 0x9000 },
1481                { 0x03, 0x802f },
1482                { 0x02, 0x4f02 },
1483                { 0x01, 0x0409 },
1484                { 0x00, 0xf099 },
1485                { 0x04, 0x9800 },
1486                { 0x04, 0xa000 },
1487                { 0x03, 0xdf01 },
1488                { 0x02, 0xdf20 },
1489                { 0x01, 0xff95 },
1490                { 0x00, 0xba00 },
1491                { 0x04, 0xa800 },
1492                { 0x04, 0xf000 },
1493                { 0x03, 0xdf01 },
1494                { 0x02, 0xdf20 },
1495                { 0x01, 0x101a },
1496                { 0x00, 0xa0ff },
1497                { 0x04, 0xf800 },
1498                { 0x04, 0x0000 },
1499                { 0x1f, 0x0000 },
1500
1501                { 0x1f, 0x0001 },
1502                { 0x10, 0xf41b },
1503                { 0x14, 0xfb54 },
1504                { 0x18, 0xf5c7 },
1505                { 0x1f, 0x0000 },
1506
1507                { 0x1f, 0x0001 },
1508                { 0x17, 0x0cc0 },
1509                { 0x1f, 0x0000 }
1510        };
1511
1512        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1513
1514        rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1515}
1516
1517static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1518{
1519        static const struct phy_reg phy_reg_init[] = {
1520                { 0x1f, 0x0001 },
1521                { 0x04, 0x0000 },
1522                { 0x03, 0x00a1 },
1523                { 0x02, 0x0008 },
1524                { 0x01, 0x0120 },
1525                { 0x00, 0x1000 },
1526                { 0x04, 0x0800 },
1527                { 0x04, 0x9000 },
1528                { 0x03, 0x802f },
1529                { 0x02, 0x4f02 },
1530                { 0x01, 0x0409 },
1531                { 0x00, 0xf099 },
1532                { 0x04, 0x9800 },
1533                { 0x04, 0xa000 },
1534                { 0x03, 0xdf01 },
1535                { 0x02, 0xdf20 },
1536                { 0x01, 0xff95 },
1537                { 0x00, 0xba00 },
1538                { 0x04, 0xa800 },
1539                { 0x04, 0xf000 },
1540                { 0x03, 0xdf01 },
1541                { 0x02, 0xdf20 },
1542                { 0x01, 0x101a },
1543                { 0x00, 0xa0ff },
1544                { 0x04, 0xf800 },
1545                { 0x04, 0x0000 },
1546                { 0x1f, 0x0000 },
1547
1548                { 0x1f, 0x0001 },
1549                { 0x0b, 0x8480 },
1550                { 0x1f, 0x0000 },
1551
1552                { 0x1f, 0x0001 },
1553                { 0x18, 0x67c7 },
1554                { 0x04, 0x2000 },
1555                { 0x03, 0x002f },
1556                { 0x02, 0x4360 },
1557                { 0x01, 0x0109 },
1558                { 0x00, 0x3022 },
1559                { 0x04, 0x2800 },
1560                { 0x1f, 0x0000 },
1561
1562                { 0x1f, 0x0001 },
1563                { 0x17, 0x0cc0 },
1564                { 0x1f, 0x0000 }
1565        };
1566
1567        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1568}
1569
1570static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1571{
1572        static const struct phy_reg phy_reg_init[] = {
1573                { 0x10, 0xf41b },
1574                { 0x1f, 0x0000 }
1575        };
1576
1577        mdio_write(ioaddr, 0x1f, 0x0001);
1578        mdio_patch(ioaddr, 0x16, 1 << 0);
1579
1580        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1581}
1582
1583static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1584{
1585        static const struct phy_reg phy_reg_init[] = {
1586                { 0x1f, 0x0001 },
1587                { 0x10, 0xf41b },
1588                { 0x1f, 0x0000 }
1589        };
1590
1591        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1592}
1593
1594static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1595{
1596        static const struct phy_reg phy_reg_init[] = {
1597                { 0x1f, 0x0000 },
1598                { 0x1d, 0x0f00 },
1599                { 0x1f, 0x0002 },
1600                { 0x0c, 0x1ec8 },
1601                { 0x1f, 0x0000 }
1602        };
1603
1604        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1605}
1606
1607static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1608{
1609        static const struct phy_reg phy_reg_init[] = {
1610                { 0x1f, 0x0001 },
1611                { 0x1d, 0x3d98 },
1612                { 0x1f, 0x0000 }
1613        };
1614
1615        mdio_write(ioaddr, 0x1f, 0x0000);
1616        mdio_patch(ioaddr, 0x14, 1 << 5);
1617        mdio_patch(ioaddr, 0x0d, 1 << 5);
1618
1619        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1620}
1621
1622static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1623{
1624        static const struct phy_reg phy_reg_init[] = {
1625                { 0x1f, 0x0001 },
1626                { 0x12, 0x2300 },
1627                { 0x1f, 0x0002 },
1628                { 0x00, 0x88d4 },
1629                { 0x01, 0x82b1 },
1630                { 0x03, 0x7002 },
1631                { 0x08, 0x9e30 },
1632                { 0x09, 0x01f0 },
1633                { 0x0a, 0x5500 },
1634                { 0x0c, 0x00c8 },
1635                { 0x1f, 0x0003 },
1636                { 0x12, 0xc096 },
1637                { 0x16, 0x000a },
1638                { 0x1f, 0x0000 },
1639                { 0x1f, 0x0000 },
1640                { 0x09, 0x2000 },
1641                { 0x09, 0x0000 }
1642        };
1643
1644        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1645
1646        mdio_patch(ioaddr, 0x14, 1 << 5);
1647        mdio_patch(ioaddr, 0x0d, 1 << 5);
1648        mdio_write(ioaddr, 0x1f, 0x0000);
1649}
1650
1651static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1652{
1653        static const struct phy_reg phy_reg_init[] = {
1654                { 0x1f, 0x0001 },
1655                { 0x12, 0x2300 },
1656                { 0x03, 0x802f },
1657                { 0x02, 0x4f02 },
1658                { 0x01, 0x0409 },
1659                { 0x00, 0xf099 },
1660                { 0x04, 0x9800 },
1661                { 0x04, 0x9000 },
1662                { 0x1d, 0x3d98 },
1663                { 0x1f, 0x0002 },
1664                { 0x0c, 0x7eb8 },
1665                { 0x06, 0x0761 },
1666                { 0x1f, 0x0003 },
1667                { 0x16, 0x0f0a },
1668                { 0x1f, 0x0000 }
1669        };
1670
1671        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1672
1673        mdio_patch(ioaddr, 0x16, 1 << 0);
1674        mdio_patch(ioaddr, 0x14, 1 << 5);
1675        mdio_patch(ioaddr, 0x0d, 1 << 5);
1676        mdio_write(ioaddr, 0x1f, 0x0000);
1677}
1678
1679static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1680{
1681        static const struct phy_reg phy_reg_init[] = {
1682                { 0x1f, 0x0001 },
1683                { 0x12, 0x2300 },
1684                { 0x1d, 0x3d98 },
1685                { 0x1f, 0x0002 },
1686                { 0x0c, 0x7eb8 },
1687                { 0x06, 0x5461 },
1688                { 0x1f, 0x0003 },
1689                { 0x16, 0x0f0a },
1690                { 0x1f, 0x0000 }
1691        };
1692
1693        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1694
1695        mdio_patch(ioaddr, 0x16, 1 << 0);
1696        mdio_patch(ioaddr, 0x14, 1 << 5);
1697        mdio_patch(ioaddr, 0x0d, 1 << 5);
1698        mdio_write(ioaddr, 0x1f, 0x0000);
1699}
1700
1701static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1702{
1703        rtl8168c_3_hw_phy_config(ioaddr);
1704}
1705
1706static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
1707{
1708        static const struct phy_reg phy_reg_init_0[] = {
1709                { 0x1f, 0x0001 },
1710                { 0x06, 0x4064 },
1711                { 0x07, 0x2863 },
1712                { 0x08, 0x059c },
1713                { 0x09, 0x26b4 },
1714                { 0x0a, 0x6a19 },
1715                { 0x0b, 0xdcc8 },
1716                { 0x10, 0xf06d },
1717                { 0x14, 0x7f68 },
1718                { 0x18, 0x7fd9 },
1719                { 0x1c, 0xf0ff },
1720                { 0x1d, 0x3d9c },
1721                { 0x1f, 0x0003 },
1722                { 0x12, 0xf49f },
1723                { 0x13, 0x070b },
1724                { 0x1a, 0x05ad },
1725                { 0x14, 0x94c0 }
1726        };
1727        static const struct phy_reg phy_reg_init_1[] = {
1728                { 0x1f, 0x0002 },
1729                { 0x06, 0x5561 },
1730                { 0x1f, 0x0005 },
1731                { 0x05, 0x8332 },
1732                { 0x06, 0x5561 }
1733        };
1734        static const struct phy_reg phy_reg_init_2[] = {
1735                { 0x1f, 0x0005 },
1736                { 0x05, 0xffc2 },
1737                { 0x1f, 0x0005 },
1738                { 0x05, 0x8000 },
1739                { 0x06, 0xf8f9 },
1740                { 0x06, 0xfaef },
1741                { 0x06, 0x59ee },
1742                { 0x06, 0xf8ea },
1743                { 0x06, 0x00ee },
1744                { 0x06, 0xf8eb },
1745                { 0x06, 0x00e0 },
1746                { 0x06, 0xf87c },
1747                { 0x06, 0xe1f8 },
1748                { 0x06, 0x7d59 },
1749                { 0x06, 0x0fef },
1750                { 0x06, 0x0139 },
1751                { 0x06, 0x029e },
1752                { 0x06, 0x06ef },
1753                { 0x06, 0x1039 },
1754                { 0x06, 0x089f },
1755                { 0x06, 0x2aee },
1756                { 0x06, 0xf8ea },
1757                { 0x06, 0x00ee },
1758                { 0x06, 0xf8eb },
1759                { 0x06, 0x01e0 },
1760                { 0x06, 0xf87c },
1761                { 0x06, 0xe1f8 },
1762                { 0x06, 0x7d58 },
1763                { 0x06, 0x409e },
1764                { 0x06, 0x0f39 },
1765                { 0x06, 0x46aa },
1766                { 0x06, 0x0bbf },
1767                { 0x06, 0x8290 },
1768                { 0x06, 0xd682 },
1769                { 0x06, 0x9802 },
1770                { 0x06, 0x014f },
1771                { 0x06, 0xae09 },
1772                { 0x06, 0xbf82 },
1773                { 0x06, 0x98d6 },
1774                { 0x06, 0x82a0 },
1775                { 0x06, 0x0201 },
1776                { 0x06, 0x4fef },
1777                { 0x06, 0x95fe },
1778                { 0x06, 0xfdfc },
1779                { 0x06, 0x05f8 },
1780                { 0x06, 0xf9fa },
1781                { 0x06, 0xeef8 },
1782                { 0x06, 0xea00 },
1783                { 0x06, 0xeef8 },
1784                { 0x06, 0xeb00 },
1785                { 0x06, 0xe2f8 },
1786                { 0x06, 0x7ce3 },
1787                { 0x06, 0xf87d },
1788                { 0x06, 0xa511 },
1789                { 0x06, 0x1112 },
1790                { 0x06, 0xd240 },
1791                { 0x06, 0xd644 },
1792                { 0x06, 0x4402 },
1793                { 0x06, 0x8217 },
1794                { 0x06, 0xd2a0 },
1795                { 0x06, 0xd6aa },
1796                { 0x06, 0xaa02 },
1797                { 0x06, 0x8217 },
1798                { 0x06, 0xae0f },
1799                { 0x06, 0xa544 },
1800                { 0x06, 0x4402 },
1801                { 0x06, 0xae4d },
1802                { 0x06, 0xa5aa },
1803                { 0x06, 0xaa02 },
1804                { 0x06, 0xae47 },
1805                { 0x06, 0xaf82 },
1806                { 0x06, 0x13ee },
1807                { 0x06, 0x834e },
1808                { 0x06, 0x00ee },
1809                { 0x06, 0x834d },
1810                { 0x06, 0x0fee },
1811                { 0x06, 0x834c },
1812                { 0x06, 0x0fee },
1813                { 0x06, 0x834f },
1814                { 0x06, 0x00ee },
1815                { 0x06, 0x8351 },
1816                { 0x06, 0x00ee },
1817                { 0x06, 0x834a },
1818                { 0x06, 0xffee },
1819                { 0x06, 0x834b },
1820                { 0x06, 0xffe0 },
1821                { 0x06, 0x8330 },
1822                { 0x06, 0xe183 },
1823                { 0x06, 0x3158 },
1824                { 0x06, 0xfee4 },
1825                { 0x06, 0xf88a },
1826                { 0x06, 0xe5f8 },
1827                { 0x06, 0x8be0 },
1828                { 0x06, 0x8332 },
1829                { 0x06, 0xe183 },
1830                { 0x06, 0x3359 },
1831                { 0x06, 0x0fe2 },
1832                { 0x06, 0x834d },
1833                { 0x06, 0x0c24 },
1834                { 0x06, 0x5af0 },
1835                { 0x06, 0x1e12 },
1836                { 0x06, 0xe4f8 },
1837                { 0x06, 0x8ce5 },
1838                { 0x06, 0xf88d },
1839                { 0x06, 0xaf82 },
1840                { 0x06, 0x13e0 },
1841                { 0x06, 0x834f },
1842                { 0x06, 0x10e4 },
1843                { 0x06, 0x834f },
1844                { 0x06, 0xe083 },
1845                { 0x06, 0x4e78 },
1846                { 0x06, 0x009f },
1847                { 0x06, 0x0ae0 },
1848                { 0x06, 0x834f },
1849                { 0x06, 0xa010 },
1850                { 0x06, 0xa5ee },
1851                { 0x06, 0x834e },
1852                { 0x06, 0x01e0 },
1853                { 0x06, 0x834e },
1854                { 0x06, 0x7805 },
1855                { 0x06, 0x9e9a },
1856                { 0x06, 0xe083 },
1857                { 0x06, 0x4e78 },
1858                { 0x06, 0x049e },
1859                { 0x06, 0x10e0 },
1860                { 0x06, 0x834e },
1861                { 0x06, 0x7803 },
1862                { 0x06, 0x9e0f },
1863                { 0x06, 0xe083 },
1864                { 0x06, 0x4e78 },
1865                { 0x06, 0x019e },
1866                { 0x06, 0x05ae },
1867                { 0x06, 0x0caf },
1868                { 0x06, 0x81f8 },
1869                { 0x06, 0xaf81 },
1870                { 0x06, 0xa3af },
1871                { 0x06, 0x81dc },
1872                { 0x06, 0xaf82 },
1873                { 0x06, 0x13ee },
1874                { 0x06, 0x8348 },
1875                { 0x06, 0x00ee },
1876                { 0x06, 0x8349 },
1877                { 0x06, 0x00e0 },
1878                { 0x06, 0x8351 },
1879                { 0x06, 0x10e4 },
1880                { 0x06, 0x8351 },
1881                { 0x06, 0x5801 },
1882                { 0x06, 0x9fea },
1883                { 0x06, 0xd000 },
1884                { 0x06, 0xd180 },
1885                { 0x06, 0x1f66 },
1886                { 0x06, 0xe2f8 },
1887                { 0x06, 0xeae3 },
1888                { 0x06, 0xf8eb },
1889                { 0x06, 0x5af8 },
1890                { 0x06, 0x1e20 },
1891                { 0x06, 0xe6f8 },
1892                { 0x06, 0xeae5 },
1893                { 0x06, 0xf8eb },
1894                { 0x06, 0xd302 },
1895                { 0x06, 0xb3fe },
1896                { 0x06, 0xe2f8 },
1897                { 0x06, 0x7cef },
1898                { 0x06, 0x325b },
1899                { 0x06, 0x80e3 },
1900                { 0x06, 0xf87d },
1901                { 0x06, 0x9e03 },
1902                { 0x06, 0x7dff },
1903                { 0x06, 0xff0d },
1904                { 0x06, 0x581c },
1905                { 0x06, 0x551a },
1906                { 0x06, 0x6511 },
1907                { 0x06, 0xa190 },
1908                { 0x06, 0xd3e2 },
1909                { 0x06, 0x8348 },
1910                { 0x06, 0xe383 },
1911                { 0x06, 0x491b },
1912                { 0x06, 0x56ab },
1913                { 0x06, 0x08ef },
1914                { 0x06, 0x56e6 },
1915                { 0x06, 0x8348 },
1916                { 0x06, 0xe783 },
1917                { 0x06, 0x4910 },
1918                { 0x06, 0xd180 },
1919                { 0x06, 0x1f66 },
1920                { 0x06, 0xa004 },
1921                { 0x06, 0xb9e2 },
1922                { 0x06, 0x8348 },
1923                { 0x06, 0xe383 },
1924                { 0x06, 0x49ef },
1925                { 0x06, 0x65e2 },
1926                { 0x06, 0x834a },
1927                { 0x06, 0xe383 },
1928                { 0x06, 0x4b1b },
1929                { 0x06, 0x56aa },
1930                { 0x06, 0x0eef },
1931                { 0x06, 0x56e6 },
1932                { 0x06, 0x834a },
1933                { 0x06, 0xe783 },
1934                { 0x06, 0x4be2 },
1935                { 0x06, 0x834d },
1936                { 0x06, 0xe683 },
1937                { 0x06, 0x4ce0 },
1938                { 0x06, 0x834d },
1939                { 0x06, 0xa000 },
1940                { 0x06, 0x0caf },
1941                { 0x06, 0x81dc },
1942                { 0x06, 0xe083 },
1943                { 0x06, 0x4d10 },
1944                { 0x06, 0xe483 },
1945                { 0x06, 0x4dae },
1946                { 0x06, 0x0480 },
1947                { 0x06, 0xe483 },
1948                { 0x06, 0x4de0 },
1949                { 0x06, 0x834e },
1950                { 0x06, 0x7803 },
1951                { 0x06, 0x9e0b },
1952                { 0x06, 0xe083 },
1953                { 0x06, 0x4e78 },
1954                { 0x06, 0x049e },
1955                { 0x06, 0x04ee },
1956                { 0x06, 0x834e },
1957                { 0x06, 0x02e0 },
1958                { 0x06, 0x8332 },
1959                { 0x06, 0xe183 },
1960                { 0x06, 0x3359 },
1961                { 0x06, 0x0fe2 },
1962                { 0x06, 0x834d },
1963                { 0x06, 0x0c24 },
1964                { 0x06, 0x5af0 },
1965                { 0x06, 0x1e12 },
1966                { 0x06, 0xe4f8 },
1967                { 0x06, 0x8ce5 },
1968                { 0x06, 0xf88d },
1969                { 0x06, 0xe083 },
1970                { 0x06, 0x30e1 },
1971                { 0x06, 0x8331 },
1972                { 0x06, 0x6801 },
1973                { 0x06, 0xe4f8 },
1974                { 0x06, 0x8ae5 },
1975                { 0x06, 0xf88b },
1976                { 0x06, 0xae37 },
1977                { 0x06, 0xee83 },
1978                { 0x06, 0x4e03 },
1979                { 0x06, 0xe083 },
1980                { 0x06, 0x4ce1 },
1981                { 0x06, 0x834d },
1982                { 0x06, 0x1b01 },
1983                { 0x06, 0x9e04 },
1984                { 0x06, 0xaaa1 },
1985                { 0x06, 0xaea8 },
1986                { 0x06, 0xee83 },
1987                { 0x06, 0x4e04 },
1988                { 0x06, 0xee83 },
1989                { 0x06, 0x4f00 },
1990                { 0x06, 0xaeab },
1991                { 0x06, 0xe083 },
1992                { 0x06, 0x4f78 },
1993                { 0x06, 0x039f },
1994                { 0x06, 0x14ee },
1995                { 0x06, 0x834e },
1996                { 0x06, 0x05d2 },
1997                { 0x06, 0x40d6 },
1998                { 0x06, 0x5554 },
1999                { 0x06, 0x0282 },
2000                { 0x06, 0x17d2 },

2001                { 0x06, 0xa0d6 },
2002                { 0x06, 0xba00 },
2003                { 0x06, 0x0282 },
2004                { 0x06, 0x17fe },
2005                { 0x06, 0xfdfc },
2006                { 0x06, 0x05f8 },
2007                { 0x06, 0xe0f8 },
2008                { 0x06, 0x60e1 },
2009                { 0x06, 0xf861 },
2010                { 0x06, 0x6802 },
2011                { 0x06, 0xe4f8 },
2012                { 0x06, 0x60e5 },
2013                { 0x06, 0xf861 },
2014                { 0x06, 0xe0f8 },
2015                { 0x06, 0x48e1 },
2016                { 0x06, 0xf849 },
2017                { 0x06, 0x580f },
2018                { 0x06, 0x1e02 },
2019                { 0x06, 0xe4f8 },
2020                { 0x06, 0x48e5 },
2021                { 0x06, 0xf849 },
2022                { 0x06, 0xd000 },
2023                { 0x06, 0x0282 },
2024                { 0x06, 0x5bbf },
2025                { 0x06, 0x8350 },
2026                { 0x06, 0xef46 },
2027                { 0x06, 0xdc19 },
2028                { 0x06, 0xddd0 },
2029                { 0x06, 0x0102 },
2030                { 0x06, 0x825b },
2031                { 0x06, 0x0282 },
2032                { 0x06, 0x77e0 },
2033                { 0x06, 0xf860 },
2034                { 0x06, 0xe1f8 },
2035                { 0x06, 0x6158 },
2036                { 0x06, 0xfde4 },
2037                { 0x06, 0xf860 },
2038                { 0x06, 0xe5f8 },
2039                { 0x06, 0x61fc },
2040                { 0x06, 0x04f9 },
2041                { 0x06, 0xfafb },
2042                { 0x06, 0xc6bf },
2043                { 0x06, 0xf840 },
2044                { 0x06, 0xbe83 },
2045                { 0x06, 0x50a0 },
2046                { 0x06, 0x0101 },
2047                { 0x06, 0x071b },
2048                { 0x06, 0x89cf },
2049                { 0x06, 0xd208 },
2050                { 0x06, 0xebdb },
2051                { 0x06, 0x19b2 },
2052                { 0x06, 0xfbff },
2053                { 0x06, 0xfefd },
2054                { 0x06, 0x04f8 },
2055                { 0x06, 0xe0f8 },
2056                { 0x06, 0x48e1 },
2057                { 0x06, 0xf849 },
2058                { 0x06, 0x6808 },
2059                { 0x06, 0xe4f8 },
2060                { 0x06, 0x48e5 },
2061                { 0x06, 0xf849 },
2062                { 0x06, 0x58f7 },
2063                { 0x06, 0xe4f8 },
2064                { 0x06, 0x48e5 },
2065                { 0x06, 0xf849 },
2066                { 0x06, 0xfc04 },
2067                { 0x06, 0x4d20 },
2068                { 0x06, 0x0002 },
2069                { 0x06, 0x4e22 },
2070                { 0x06, 0x0002 },
2071                { 0x06, 0x4ddf },
2072                { 0x06, 0xff01 },
2073                { 0x06, 0x4edd },
2074                { 0x06, 0xff01 },
2075                { 0x05, 0x83d4 },
2076                { 0x06, 0x8000 },
2077                { 0x05, 0x83d8 },
2078                { 0x06, 0x8051 },
2079                { 0x02, 0x6010 },
2080                { 0x03, 0xdc00 },
2081                { 0x05, 0xfff6 },
2082                { 0x06, 0x00fc },
2083                { 0x1f, 0x0000 },
2084
2085                { 0x1f, 0x0000 },
2086                { 0x0d, 0xf880 },
2087                { 0x1f, 0x0000 }
2088        };
2089
2090        rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2091
2092        mdio_write(ioaddr, 0x1f, 0x0002);
2093        mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
2094        mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
2095
2096        rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2097
2098        if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2099                static const struct phy_reg phy_reg_init[] = {
2100                        { 0x1f, 0x0002 },
2101                        { 0x05, 0x669a },
2102                        { 0x1f, 0x0005 },
2103                        { 0x05, 0x8330 },
2104                        { 0x06, 0x669a },
2105                        { 0x1f, 0x0002 }
2106                };
2107                int val;
2108
2109                rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2110
2111                val = mdio_read(ioaddr, 0x0d);
2112
2113                if ((val & 0x00ff) != 0x006c) {
2114                        static const u32 set[] = {
2115                                0x0065, 0x0066, 0x0067, 0x0068,
2116                                0x0069, 0x006a, 0x006b, 0x006c
2117                        };
2118                        int i;
2119
2120                        mdio_write(ioaddr, 0x1f, 0x0002);
2121
2122                        val &= 0xff00;
2123                        for (i = 0; i < ARRAY_SIZE(set); i++)
2124                                mdio_write(ioaddr, 0x0d, val | set[i]);
2125                }
2126        } else {
2127                static const struct phy_reg phy_reg_init[] = {
2128                        { 0x1f, 0x0002 },
2129                        { 0x05, 0x6662 },
2130                        { 0x1f, 0x0005 },
2131                        { 0x05, 0x8330 },
2132                        { 0x06, 0x6662 }
2133                };
2134
2135                rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2136        }
2137
2138        mdio_write(ioaddr, 0x1f, 0x0002);
2139        mdio_patch(ioaddr, 0x0d, 0x0300);
2140        mdio_patch(ioaddr, 0x0f, 0x0010);
2141
2142        mdio_write(ioaddr, 0x1f, 0x0002);
2143        mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2144        mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2145
2146        rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
2147}
2148
2149static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2150{
2151        static const struct phy_reg phy_reg_init_0[] = {
2152                { 0x1f, 0x0001 },
2153                { 0x06, 0x4064 },
2154                { 0x07, 0x2863 },
2155                { 0x08, 0x059c },
2156                { 0x09, 0x26b4 },
2157                { 0x0a, 0x6a19 },
2158                { 0x0b, 0xdcc8 },
2159                { 0x10, 0xf06d },
2160                { 0x14, 0x7f68 },
2161                { 0x18, 0x7fd9 },
2162                { 0x1c, 0xf0ff },
2163                { 0x1d, 0x3d9c },
2164                { 0x1f, 0x0003 },
2165                { 0x12, 0xf49f },
2166                { 0x13, 0x070b },
2167                { 0x1a, 0x05ad },
2168                { 0x14, 0x94c0 },
2169
2170                { 0x1f, 0x0002 },
2171                { 0x06, 0x5561 },
2172                { 0x1f, 0x0005 },
2173                { 0x05, 0x8332 },
2174                { 0x06, 0x5561 }
2175        };
2176        static const struct phy_reg phy_reg_init_1[] = {
2177                { 0x1f, 0x0005 },
2178                { 0x05, 0xffc2 },
2179                { 0x1f, 0x0005 },
2180                { 0x05, 0x8000 },
2181                { 0x06, 0xf8f9 },
2182                { 0x06, 0xfaee },
2183                { 0x06, 0xf8ea },
2184                { 0x06, 0x00ee },
2185                { 0x06, 0xf8eb },
2186                { 0x06, 0x00e2 },
2187                { 0x06, 0xf87c },
2188                { 0x06, 0xe3f8 },
2189                { 0x06, 0x7da5 },
2190                { 0x06, 0x1111 },
2191                { 0x06, 0x12d2 },
2192                { 0x06, 0x40d6 },
2193                { 0x06, 0x4444 },
2194                { 0x06, 0x0281 },
2195                { 0x06, 0xc6d2 },
2196                { 0x06, 0xa0d6 },
2197                { 0x06, 0xaaaa },
2198                { 0x06, 0x0281 },
2199                { 0x06, 0xc6ae },
2200                { 0x06, 0x0fa5 },
2201                { 0x06, 0x4444 },
2202                { 0x06, 0x02ae },
2203                { 0x06, 0x4da5 },
2204                { 0x06, 0xaaaa },
2205                { 0x06, 0x02ae },
2206                { 0x06, 0x47af },
2207                { 0x06, 0x81c2 },
2208                { 0x06, 0xee83 },
2209                { 0x06, 0x4e00 },
2210                { 0x06, 0xee83 },
2211                { 0x06, 0x4d0f },
2212                { 0x06, 0xee83 },
2213                { 0x06, 0x4c0f },
2214                { 0x06, 0xee83 },
2215                { 0x06, 0x4f00 },
2216                { 0x06, 0xee83 },
2217                { 0x06, 0x5100 },
2218                { 0x06, 0xee83 },
2219                { 0x06, 0x4aff },
2220                { 0x06, 0xee83 },
2221                { 0x06, 0x4bff },
2222                { 0x06, 0xe083 },
2223                { 0x06, 0x30e1 },
2224                { 0x06, 0x8331 },
2225                { 0x06, 0x58fe },
2226                { 0x06, 0xe4f8 },
2227                { 0x06, 0x8ae5 },
2228                { 0x06, 0xf88b },
2229                { 0x06, 0xe083 },
2230                { 0x06, 0x32e1 },
2231                { 0x06, 0x8333 },
2232                { 0x06, 0x590f },
2233                { 0x06, 0xe283 },
2234                { 0x06, 0x4d0c },
2235                { 0x06, 0x245a },
2236                { 0x06, 0xf01e },
2237                { 0x06, 0x12e4 },
2238                { 0x06, 0xf88c },
2239                { 0x06, 0xe5f8 },
2240                { 0x06, 0x8daf },
2241                { 0x06, 0x81c2 },
2242                { 0x06, 0xe083 },
2243                { 0x06, 0x4f10 },
2244                { 0x06, 0xe483 },
2245                { 0x06, 0x4fe0 },
2246                { 0x06, 0x834e },
2247                { 0x06, 0x7800 },
2248                { 0x06, 0x9f0a },
2249                { 0x06, 0xe083 },
2250                { 0x06, 0x4fa0 },
2251                { 0x06, 0x10a5 },
2252                { 0x06, 0xee83 },
2253                { 0x06, 0x4e01 },
2254                { 0x06, 0xe083 },
2255                { 0x06, 0x4e78 },
2256                { 0x06, 0x059e },
2257                { 0x06, 0x9ae0 },
2258                { 0x06, 0x834e },
2259                { 0x06, 0x7804 },
2260                { 0x06, 0x9e10 },
2261                { 0x06, 0xe083 },
2262                { 0x06, 0x4e78 },
2263                { 0x06, 0x039e },
2264                { 0x06, 0x0fe0 },
2265                { 0x06, 0x834e },
2266                { 0x06, 0x7801 },
2267                { 0x06, 0x9e05 },
2268                { 0x06, 0xae0c },
2269                { 0x06, 0xaf81 },
2270                { 0x06, 0xa7af },
2271                { 0x06, 0x8152 },
2272                { 0x06, 0xaf81 },
2273                { 0x06, 0x8baf },
2274                { 0x06, 0x81c2 },
2275                { 0x06, 0xee83 },
2276                { 0x06, 0x4800 },
2277                { 0x06, 0xee83 },
2278                { 0x06, 0x4900 },
2279                { 0x06, 0xe083 },
2280                { 0x06, 0x5110 },
2281                { 0x06, 0xe483 },
2282                { 0x06, 0x5158 },
2283                { 0x06, 0x019f },
2284                { 0x06, 0xead0 },
2285                { 0x06, 0x00d1 },
2286                { 0x06, 0x801f },
2287                { 0x06, 0x66e2 },
2288                { 0x06, 0xf8ea },
2289                { 0x06, 0xe3f8 },
2290                { 0x06, 0xeb5a },
2291                { 0x06, 0xf81e },
2292                { 0x06, 0x20e6 },
2293                { 0x06, 0xf8ea },
2294                { 0x06, 0xe5f8 },
2295                { 0x06, 0xebd3 },
2296                { 0x06, 0x02b3 },
2297                { 0x06, 0xfee2 },
2298                { 0x06, 0xf87c },
2299                { 0x06, 0xef32 },
2300                { 0x06, 0x5b80 },
2301                { 0x06, 0xe3f8 },
2302                { 0x06, 0x7d9e },
2303                { 0x06, 0x037d },
2304                { 0x06, 0xffff },
2305                { 0x06, 0x0d58 },
2306                { 0x06, 0x1c55 },
2307                { 0x06, 0x1a65 },
2308                { 0x06, 0x11a1 },
2309                { 0x06, 0x90d3 },
2310                { 0x06, 0xe283 },
2311                { 0x06, 0x48e3 },
2312                { 0x06, 0x8349 },
2313                { 0x06, 0x1b56 },
2314                { 0x06, 0xab08 },
2315                { 0x06, 0xef56 },
2316                { 0x06, 0xe683 },
2317                { 0x06, 0x48e7 },
2318                { 0x06, 0x8349 },
2319                { 0x06, 0x10d1 },
2320                { 0x06, 0x801f },
2321                { 0x06, 0x66a0 },
2322                { 0x06, 0x04b9 },
2323                { 0x06, 0xe283 },
2324                { 0x06, 0x48e3 },
2325                { 0x06, 0x8349 },
2326                { 0x06, 0xef65 },
2327                { 0x06, 0xe283 },
2328                { 0x06, 0x4ae3 },
2329                { 0x06, 0x834b },
2330                { 0x06, 0x1b56 },
2331                { 0x06, 0xaa0e },
2332                { 0x06, 0xef56 },
2333                { 0x06, 0xe683 },
2334                { 0x06, 0x4ae7 },
2335                { 0x06, 0x834b },
2336                { 0x06, 0xe283 },
2337                { 0x06, 0x4de6 },
2338                { 0x06, 0x834c },
2339                { 0x06, 0xe083 },
2340                { 0x06, 0x4da0 },
2341                { 0x06, 0x000c },
2342                { 0x06, 0xaf81 },
2343                { 0x06, 0x8be0 },
2344                { 0x06, 0x834d },
2345                { 0x06, 0x10e4 },
2346                { 0x06, 0x834d },
2347                { 0x06, 0xae04 },
2348                { 0x06, 0x80e4 },
2349                { 0x06, 0x834d },
2350                { 0x06, 0xe083 },
2351                { 0x06, 0x4e78 },
2352                { 0x06, 0x039e },
2353                { 0x06, 0x0be0 },
2354                { 0x06, 0x834e },
2355                { 0x06, 0x7804 },
2356                { 0x06, 0x9e04 },
2357                { 0x06, 0xee83 },
2358                { 0x06, 0x4e02 },
2359                { 0x06, 0xe083 },
2360                { 0x06, 0x32e1 },
2361                { 0x06, 0x8333 },
2362                { 0x06, 0x590f },
2363                { 0x06, 0xe283 },
2364                { 0x06, 0x4d0c },
2365                { 0x06, 0x245a },
2366                { 0x06, 0xf01e },
2367                { 0x06, 0x12e4 },
2368                { 0x06, 0xf88c },
2369                { 0x06, 0xe5f8 },
2370                { 0x06, 0x8de0 },
2371                { 0x06, 0x8330 },
2372                { 0x06, 0xe183 },
2373                { 0x06, 0x3168 },
2374                { 0x06, 0x01e4 },
2375                { 0x06, 0xf88a },
2376                { 0x06, 0xe5f8 },
2377                { 0x06, 0x8bae },
2378                { 0x06, 0x37ee },
2379                { 0x06, 0x834e },
2380                { 0x06, 0x03e0 },
2381                { 0x06, 0x834c },
2382                { 0x06, 0xe183 },
2383                { 0x06, 0x4d1b },
2384                { 0x06, 0x019e },
2385                { 0x06, 0x04aa },
2386                { 0x06, 0xa1ae },
2387                { 0x06, 0xa8ee },
2388                { 0x06, 0x834e },
2389                { 0x06, 0x04ee },
2390                { 0x06, 0x834f },
2391                { 0x06, 0x00ae },
2392                { 0x06, 0xabe0 },
2393                { 0x06, 0x834f },
2394                { 0x06, 0x7803 },
2395                { 0x06, 0x9f14 },
2396                { 0x06, 0xee83 },
2397                { 0x06, 0x4e05 },
2398                { 0x06, 0xd240 },
2399                { 0x06, 0xd655 },
2400                { 0x06, 0x5402 },
2401                { 0x06, 0x81c6 },
2402                { 0x06, 0xd2a0 },
2403                { 0x06, 0xd6ba },
2404                { 0x06, 0x0002 },
2405                { 0x06, 0x81c6 },
2406                { 0x06, 0xfefd },
2407                { 0x06, 0xfc05 },
2408                { 0x06, 0xf8e0 },
2409                { 0x06, 0xf860 },
2410                { 0x06, 0xe1f8 },
2411                { 0x06, 0x6168 },
2412                { 0x06, 0x02e4 },
2413                { 0x06, 0xf860 },
2414                { 0x06, 0xe5f8 },
2415                { 0x06, 0x61e0 },
2416                { 0x06, 0xf848 },
2417                { 0x06, 0xe1f8 },
2418                { 0x06, 0x4958 },
2419                { 0x06, 0x0f1e },
2420                { 0x06, 0x02e4 },
2421                { 0x06, 0xf848 },
2422                { 0x06, 0xe5f8 },
2423                { 0x06, 0x49d0 },
2424                { 0x06, 0x0002 },
2425                { 0x06, 0x820a },
2426                { 0x06, 0xbf83 },
2427                { 0x06, 0x50ef },
2428                { 0x06, 0x46dc },
2429                { 0x06, 0x19dd },
2430                { 0x06, 0xd001 },
2431                { 0x06, 0x0282 },
2432                { 0x06, 0x0a02 },
2433                { 0x06, 0x8226 },
2434                { 0x06, 0xe0f8 },
2435                { 0x06, 0x60e1 },
2436                { 0x06, 0xf861 },
2437                { 0x06, 0x58fd },
2438                { 0x06, 0xe4f8 },
2439                { 0x06, 0x60e5 },
2440                { 0x06, 0xf861 },
2441                { 0x06, 0xfc04 },
2442                { 0x06, 0xf9fa },
2443                { 0x06, 0xfbc6 },
2444                { 0x06, 0xbff8 },
2445                { 0x06, 0x40be },
2446                { 0x06, 0x8350 },
2447                { 0x06, 0xa001 },
2448                { 0x06, 0x0107 },
2449                { 0x06, 0x1b89 },
2450                { 0x06, 0xcfd2 },
2451                { 0x06, 0x08eb },
2452                { 0x06, 0xdb19 },
2453                { 0x06, 0xb2fb },
2454                { 0x06, 0xfffe },
2455                { 0x06, 0xfd04 },
2456                { 0x06, 0xf8e0 },
2457                { 0x06, 0xf848 },
2458                { 0x06, 0xe1f8 },
2459                { 0x06, 0x4968 },
2460                { 0x06, 0x08e4 },
2461                { 0x06, 0xf848 },
2462                { 0x06, 0xe5f8 },
2463                { 0x06, 0x4958 },
2464                { 0x06, 0xf7e4 },
2465                { 0x06, 0xf848 },
2466                { 0x06, 0xe5f8 },
2467                { 0x06, 0x49fc },
2468                { 0x06, 0x044d },
2469                { 0x06, 0x2000 },
2470                { 0x06, 0x024e },
2471                { 0x06, 0x2200 },
2472                { 0x06, 0x024d },
2473                { 0x06, 0xdfff },
2474                { 0x06, 0x014e },
2475                { 0x06, 0xddff },
2476                { 0x06, 0x0100 },
2477                { 0x05, 0x83d8 },
2478                { 0x06, 0x8000 },
2479                { 0x03, 0xdc00 },
2480                { 0x05, 0xfff6 },
2481                { 0x06, 0x00fc },
2482                { 0x1f, 0x0000 },
2483
2484                { 0x1f, 0x0000 },
2485                { 0x0d, 0xf880 },
2486                { 0x1f, 0x0000 }
2487        };
2488
2489        rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2490
2491        if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2492                static const struct phy_reg phy_reg_init[] = {
2493                        { 0x1f, 0x0002 },
2494                        { 0x05, 0x669a },
2495                        { 0x1f, 0x0005 },
2496                        { 0x05, 0x8330 },
2497                        { 0x06, 0x669a },
2498
2499                        { 0x1f, 0x0002 }
2500                };
2501                int val;
2502
2503                rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2504
2505                val = mdio_read(ioaddr, 0x0d);
2506                if ((val & 0x00ff) != 0x006c) {
2507                        u32 set[] = {
2508                                0x0065, 0x0066, 0x0067, 0x0068,
2509                                0x0069, 0x006a, 0x006b, 0x006c
2510                        };
2511                        int i;
2512
2513                        mdio_write(ioaddr, 0x1f, 0x0002);
2514
2515                        val &= 0xff00;
2516                        for (i = 0; i < ARRAY_SIZE(set); i++)
2517                                mdio_write(ioaddr, 0x0d, val | set[i]);
2518                }
2519        } else {
2520                static const struct phy_reg phy_reg_init[] = {
2521                        { 0x1f, 0x0002 },
2522                        { 0x05, 0x2642 },
2523                        { 0x1f, 0x0005 },
2524                        { 0x05, 0x8330 },
2525                        { 0x06, 0x2642 }
2526                };
2527
2528                rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2529        }
2530
2531        mdio_write(ioaddr, 0x1f, 0x0002);
2532        mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2533        mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2534
2535        mdio_write(ioaddr, 0x1f, 0x0001);
2536        mdio_write(ioaddr, 0x17, 0x0cc0);
2537
2538        mdio_write(ioaddr, 0x1f, 0x0002);
2539        mdio_patch(ioaddr, 0x0f, 0x0017);
2540
2541        rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2542}
2543
2544static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2545{
2546        static const struct phy_reg phy_reg_init[] = {
2547                { 0x1f, 0x0002 },
2548                { 0x10, 0x0008 },
2549                { 0x0d, 0x006c },
2550
2551                { 0x1f, 0x0000 },
2552                { 0x0d, 0xf880 },
2553
2554                { 0x1f, 0x0001 },
2555                { 0x17, 0x0cc0 },
2556
2557                { 0x1f, 0x0001 },
2558                { 0x0b, 0xa4d8 },
2559                { 0x09, 0x281c },
2560                { 0x07, 0x2883 },
2561                { 0x0a, 0x6b35 },
2562                { 0x1d, 0x3da4 },
2563                { 0x1c, 0xeffd },
2564                { 0x14, 0x7f52 },
2565                { 0x18, 0x7fc6 },
2566                { 0x08, 0x0601 },
2567                { 0x06, 0x4063 },
2568                { 0x10, 0xf074 },
2569                { 0x1f, 0x0003 },
2570                { 0x13, 0x0789 },
2571                { 0x12, 0xf4bd },
2572                { 0x1a, 0x04fd },
2573                { 0x14, 0x84b0 },
2574                { 0x1f, 0x0000 },
2575                { 0x00, 0x9200 },
2576
2577                { 0x1f, 0x0005 },
2578                { 0x01, 0x0340 },
2579                { 0x1f, 0x0001 },
2580                { 0x04, 0x4000 },
2581                { 0x03, 0x1d21 },
2582                { 0x02, 0x0c32 },
2583                { 0x01, 0x0200 },
2584                { 0x00, 0x5554 },
2585                { 0x04, 0x4800 },
2586                { 0x04, 0x4000 },
2587                { 0x04, 0xf000 },
2588                { 0x03, 0xdf01 },
2589                { 0x02, 0xdf20 },
2590                { 0x01, 0x101a },
2591                { 0x00, 0xa0ff },
2592                { 0x04, 0xf800 },
2593                { 0x04, 0xf000 },
2594                { 0x1f, 0x0000 },
2595
2596                { 0x1f, 0x0007 },
2597                { 0x1e, 0x0023 },
2598                { 0x16, 0x0000 },
2599                { 0x1f, 0x0000 }
2600        };
2601
2602        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2603}
2604
2605static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2606{
2607        static const struct phy_reg phy_reg_init[] = {
2608                { 0x1f, 0x0003 },
2609                { 0x08, 0x441d },
2610                { 0x01, 0x9100 },
2611                { 0x1f, 0x0000 }
2612        };
2613
2614        mdio_write(ioaddr, 0x1f, 0x0000);
2615        mdio_patch(ioaddr, 0x11, 1 << 12);
2616        mdio_patch(ioaddr, 0x19, 1 << 13);
2617        mdio_patch(ioaddr, 0x10, 1 << 15);
2618
2619        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2620}
2621
2622static void rtl_hw_phy_config(struct net_device *dev)
2623{
2624        struct rtl8169_private *tp = netdev_priv(dev);
2625        void __iomem *ioaddr = tp->mmio_addr;
2626
2627        rtl8169_print_mac_version(tp);
2628
2629        switch (tp->mac_version) {
2630        case RTL_GIGA_MAC_VER_01:
2631                break;
2632        case RTL_GIGA_MAC_VER_02:
2633        case RTL_GIGA_MAC_VER_03:
2634                rtl8169s_hw_phy_config(ioaddr);
2635                break;
2636        case RTL_GIGA_MAC_VER_04:
2637                rtl8169sb_hw_phy_config(ioaddr);
2638                break;
2639        case RTL_GIGA_MAC_VER_05:
2640                rtl8169scd_hw_phy_config(tp, ioaddr);
2641                break;
2642        case RTL_GIGA_MAC_VER_06:
2643                rtl8169sce_hw_phy_config(ioaddr);
2644                break;
2645        case RTL_GIGA_MAC_VER_07:
2646        case RTL_GIGA_MAC_VER_08:
2647        case RTL_GIGA_MAC_VER_09:
2648                rtl8102e_hw_phy_config(ioaddr);
2649                break;
2650        case RTL_GIGA_MAC_VER_11:
2651                rtl8168bb_hw_phy_config(ioaddr);
2652                break;
2653        case RTL_GIGA_MAC_VER_12:
2654                rtl8168bef_hw_phy_config(ioaddr);
2655                break;
2656        case RTL_GIGA_MAC_VER_17:
2657                rtl8168bef_hw_phy_config(ioaddr);
2658                break;
2659        case RTL_GIGA_MAC_VER_18:
2660                rtl8168cp_1_hw_phy_config(ioaddr);
2661                break;
2662        case RTL_GIGA_MAC_VER_19:
2663                rtl8168c_1_hw_phy_config(ioaddr);
2664                break;
2665        case RTL_GIGA_MAC_VER_20:
2666                rtl8168c_2_hw_phy_config(ioaddr);
2667                break;
2668        case RTL_GIGA_MAC_VER_21:
2669                rtl8168c_3_hw_phy_config(ioaddr);
2670                break;
2671        case RTL_GIGA_MAC_VER_22:
2672                rtl8168c_4_hw_phy_config(ioaddr);
2673                break;
2674        case RTL_GIGA_MAC_VER_23:
2675        case RTL_GIGA_MAC_VER_24:
2676                rtl8168cp_2_hw_phy_config(ioaddr);
2677                break;
2678        case RTL_GIGA_MAC_VER_25:
2679                rtl8168d_1_hw_phy_config(ioaddr);
2680                break;
2681        case RTL_GIGA_MAC_VER_26:
2682                rtl8168d_2_hw_phy_config(ioaddr);
2683                break;
2684        case RTL_GIGA_MAC_VER_27:
2685                rtl8168d_3_hw_phy_config(ioaddr);
2686                break;
2687
2688        default:
2689                break;
2690        }
2691}
2692
2693static void rtl8169_phy_timer(unsigned long __opaque)
2694{
2695        struct net_device *dev = (struct net_device *)__opaque;
2696        struct rtl8169_private *tp = netdev_priv(dev);
2697        struct timer_list *timer = &tp->timer;
2698        void __iomem *ioaddr = tp->mmio_addr;
2699        unsigned long timeout = RTL8169_PHY_TIMEOUT;
2700
2701        assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2702
2703        if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2704                return;
2705
2706        spin_lock_irq(&tp->lock);
2707
2708        if (tp->phy_reset_pending(ioaddr)) {
2709                /*
2710                 * A busy loop could burn quite a few cycles on nowadays CPU.
2711                 * Let's delay the execution of the timer for a few ticks.
2712                 */
2713                timeout = HZ/10;
2714                goto out_mod_timer;
2715        }
2716
2717        if (tp->link_ok(ioaddr))
2718                goto out_unlock;
2719
2720        netif_warn(tp, link, dev, "PHY reset until link up\n");
2721
2722        tp->phy_reset_enable(ioaddr);
2723
2724out_mod_timer:
2725        mod_timer(timer, jiffies + timeout);
2726out_unlock:
2727        spin_unlock_irq(&tp->lock);
2728}
2729
2730static inline void rtl8169_delete_timer(struct net_device *dev)
2731{
2732        struct rtl8169_private *tp = netdev_priv(dev);
2733        struct timer_list *timer = &tp->timer;
2734
2735        if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2736                return;
2737
2738        del_timer_sync(timer);
2739}
2740
2741static inline void rtl8169_request_timer(struct net_device *dev)
2742{
2743        struct rtl8169_private *tp = netdev_priv(dev);
2744        struct timer_list *timer = &tp->timer;
2745
2746        if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2747                return;
2748
2749        mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2750}
2751
2752#ifdef CONFIG_NET_POLL_CONTROLLER
2753/*
2754 * Polling 'interrupt' - used by things like netconsole to send skbs
2755 * without having to re-enable interrupts. It's not called while
2756 * the interrupt routine is executing.
2757 */
2758static void rtl8169_netpoll(struct net_device *dev)
2759{
2760        struct rtl8169_private *tp = netdev_priv(dev);
2761        struct pci_dev *pdev = tp->pci_dev;
2762
2763        disable_irq(pdev->irq);
2764        rtl8169_interrupt(pdev->irq, dev);
2765        enable_irq(pdev->irq);
2766}
2767#endif
2768
2769static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2770                                  void __iomem *ioaddr)
2771{
2772        iounmap(ioaddr);
2773        pci_release_regions(pdev);
2774        pci_clear_mwi(pdev);
2775        pci_disable_device(pdev);
2776        free_netdev(dev);
2777}
2778
2779static void rtl8169_phy_reset(struct net_device *dev,
2780                              struct rtl8169_private *tp)
2781{
2782        void __iomem *ioaddr = tp->mmio_addr;
2783        unsigned int i;
2784
2785        tp->phy_reset_enable(ioaddr);
2786        for (i = 0; i < 100; i++) {
2787                if (!tp->phy_reset_pending(ioaddr))
2788                        return;
2789                msleep(1);
2790        }
2791        netif_err(tp, link, dev, "PHY reset failed\n");
2792}
2793
2794static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2795{
2796        void __iomem *ioaddr = tp->mmio_addr;
2797
2798        rtl_hw_phy_config(dev);
2799
2800        if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2801                dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2802                RTL_W8(0x82, 0x01);
2803        }
2804
2805        pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2806
2807        if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2808                pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2809
2810        if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2811                dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2812                RTL_W8(0x82, 0x01);
2813                dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2814                mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2815        }
2816
2817        rtl8169_phy_reset(dev, tp);
2818
2819        /*
2820         * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2821         * only 8101. Don't panic.
2822         */
2823        rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2824
2825        if (RTL_R8(PHYstatus) & TBI_Enable)
2826                netif_info(tp, link, dev, "TBI auto-negotiating\n");
2827}
2828
2829static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2830{
2831        void __iomem *ioaddr = tp->mmio_addr;
2832        u32 high;
2833        u32 low;
2834
2835        low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2836        high = addr[4] | (addr[5] << 8);
2837
2838        spin_lock_irq(&tp->lock);
2839
2840        RTL_W8(Cfg9346, Cfg9346_Unlock);
2841
2842        RTL_W32(MAC4, high);
2843        RTL_R32(MAC4);
2844
2845        RTL_W32(MAC0, low);
2846        RTL_R32(MAC0);
2847
2848        RTL_W8(Cfg9346, Cfg9346_Lock);
2849
2850        spin_unlock_irq(&tp->lock);
2851}
2852
2853static int rtl_set_mac_address(struct net_device *dev, void *p)
2854{
2855        struct rtl8169_private *tp = netdev_priv(dev);
2856        struct sockaddr *addr = p;
2857
2858        if (!is_valid_ether_addr(addr->sa_data))
2859                return -EADDRNOTAVAIL;
2860
2861        memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2862
2863        rtl_rar_set(tp, dev->dev_addr);
2864
2865        return 0;
2866}
2867
2868static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2869{
2870        struct rtl8169_private *tp = netdev_priv(dev);
2871        struct mii_ioctl_data *data = if_mii(ifr);
2872
2873        return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2874}
2875
2876static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2877{
2878        switch (cmd) {
2879        case SIOCGMIIPHY:
2880                data->phy_id = 32; /* Internal PHY */
2881                return 0;
2882
2883        case SIOCGMIIREG:
2884                data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2885                return 0;
2886
2887        case SIOCSMIIREG:
2888                mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2889                return 0;
2890        }
2891        return -EOPNOTSUPP;
2892}
2893
2894static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2895{
2896        return -EOPNOTSUPP;
2897}
2898
2899static const struct rtl_cfg_info {
2900        void (*hw_start)(struct net_device *);
2901        unsigned int region;
2902        unsigned int align;
2903        u16 intr_event;
2904        u16 napi_event;
2905        unsigned features;
2906        u8 default_ver;
2907} rtl_cfg_infos [] = {
2908        [RTL_CFG_0] = {
2909                .hw_start       = rtl_hw_start_8169,
2910                .region         = 1,
2911                .align          = 0,
2912                .intr_event     = SYSErr | LinkChg | RxOverflow |
2913                                  RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2914                .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2915                .features       = RTL_FEATURE_GMII,
2916                .default_ver    = RTL_GIGA_MAC_VER_01,
2917        },
2918        [RTL_CFG_1] = {
2919                .hw_start       = rtl_hw_start_8168,
2920                .region         = 2,
2921                .align          = 8,
2922                .intr_event     = SYSErr | LinkChg | RxOverflow |
2923                                  TxErr | TxOK | RxOK | RxErr,
2924                .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
2925                .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2926                .default_ver    = RTL_GIGA_MAC_VER_11,
2927        },
2928        [RTL_CFG_2] = {
2929                .hw_start       = rtl_hw_start_8101,
2930                .region         = 2,
2931                .align          = 8,
2932                .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2933                                  RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2934                .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2935                .features       = RTL_FEATURE_MSI,
2936                .default_ver    = RTL_GIGA_MAC_VER_13,
2937        }
2938};
2939
2940/* Cfg9346_Unlock assumed. */
2941static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2942                            const struct rtl_cfg_info *cfg)
2943{
2944        unsigned msi = 0;
2945        u8 cfg2;
2946
2947        cfg2 = RTL_R8(Config2) & ~MSIEnable;
2948        if (cfg->features & RTL_FEATURE_MSI) {
2949                if (pci_enable_msi(pdev)) {
2950                        dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2951                } else {
2952                        cfg2 |= MSIEnable;
2953                        msi = RTL_FEATURE_MSI;
2954                }
2955        }
2956        RTL_W8(Config2, cfg2);
2957        return msi;
2958}
2959
2960static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2961{
2962        if (tp->features & RTL_FEATURE_MSI) {
2963                pci_disable_msi(pdev);
2964                tp->features &= ~RTL_FEATURE_MSI;
2965        }
2966}
2967
2968static const struct net_device_ops rtl8169_netdev_ops = {
2969        .ndo_open               = rtl8169_open,
2970        .ndo_stop               = rtl8169_close,
2971        .ndo_get_stats          = rtl8169_get_stats,
2972        .ndo_start_xmit         = rtl8169_start_xmit,
2973        .ndo_tx_timeout         = rtl8169_tx_timeout,
2974        .ndo_validate_addr      = eth_validate_addr,
2975        .ndo_change_mtu         = rtl8169_change_mtu,
2976        .ndo_set_mac_address    = rtl_set_mac_address,
2977        .ndo_do_ioctl           = rtl8169_ioctl,
2978        .ndo_set_multicast_list = rtl_set_rx_mode,
2979#ifdef CONFIG_R8169_VLAN
2980        .ndo_vlan_rx_register   = rtl8169_vlan_rx_register,
2981#endif
2982#ifdef CONFIG_NET_POLL_CONTROLLER
2983        .ndo_poll_controller    = rtl8169_netpoll,
2984#endif
2985
2986};
2987
2988static int __devinit
2989rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2990{
2991        const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2992        const unsigned int region = cfg->region;
2993        struct rtl8169_private *tp;
2994        struct mii_if_info *mii;
2995        struct net_device *dev;
2996        void __iomem *ioaddr;
2997        unsigned int i;
2998        int rc;
2999
3000        if (netif_msg_drv(&debug)) {

3001                printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3002                       MODULENAME, RTL8169_VERSION);
3003        }
3004
3005        dev = alloc_etherdev(sizeof (*tp));
3006        if (!dev) {
3007                if (netif_msg_drv(&debug))
3008                        dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3009                rc = -ENOMEM;
3010                goto out;
3011        }
3012
3013        SET_NETDEV_DEV(dev, &pdev->dev);
3014        dev->netdev_ops = &rtl8169_netdev_ops;
3015        tp = netdev_priv(dev);
3016        tp->dev = dev;
3017        tp->pci_dev = pdev;
3018        tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3019
3020        mii = &tp->mii;
3021        mii->dev = dev;
3022        mii->mdio_read = rtl_mdio_read;
3023        mii->mdio_write = rtl_mdio_write;
3024        mii->phy_id_mask = 0x1f;
3025        mii->reg_num_mask = 0x1f;
3026        mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3027
3028        /* disable ASPM completely as that cause random device stop working
3029         * problems as well as full system hangs for some PCIe devices users */
3030        pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3031                                     PCIE_LINK_STATE_CLKPM);
3032
3033        /* enable device (incl. PCI PM wakeup and hotplug setup) */
3034        rc = pci_enable_device(pdev);
3035        if (rc < 0) {
3036                netif_err(tp, probe, dev, "enable failure\n");
3037                goto err_out_free_dev_1;
3038        }
3039
3040        if (pci_set_mwi(pdev) < 0)
3041                netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3042
3043        /* make sure PCI base addr 1 is MMIO */
3044        if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3045                netif_err(tp, probe, dev,
3046                          "region #%d not an MMIO resource, aborting\n",
3047                          region);
3048                rc = -ENODEV;
3049                goto err_out_mwi_2;
3050        }
3051
3052        /* check for weird/broken PCI region reporting */
3053        if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3054                netif_err(tp, probe, dev,
3055                          "Invalid PCI region size(s), aborting\n");
3056                rc = -ENODEV;
3057                goto err_out_mwi_2;
3058        }
3059
3060        rc = pci_request_regions(pdev, MODULENAME);
3061        if (rc < 0) {
3062                netif_err(tp, probe, dev, "could not request regions\n");
3063                goto err_out_mwi_2;
3064        }
3065
3066        tp->cp_cmd = PCIMulRW | RxChkSum;
3067
3068        if ((sizeof(dma_addr_t) > 4) &&
3069            !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3070                tp->cp_cmd |= PCIDAC;
3071                dev->features |= NETIF_F_HIGHDMA;
3072        } else {
3073                rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3074                if (rc < 0) {
3075                        netif_err(tp, probe, dev, "DMA configuration failed\n");
3076                        goto err_out_free_res_3;
3077                }
3078        }
3079
3080        /* ioremap MMIO region */
3081        ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3082        if (!ioaddr) {
3083                netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3084                rc = -EIO;
3085                goto err_out_free_res_3;
3086        }
3087
3088        tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3089        if (!tp->pcie_cap)
3090                netif_info(tp, probe, dev, "no PCI Express capability\n");
3091
3092        RTL_W16(IntrMask, 0x0000);
3093
3094        /* Soft reset the chip. */
3095        RTL_W8(ChipCmd, CmdReset);
3096
3097        /* Check that the chip has finished the reset. */
3098        for (i = 0; i < 100; i++) {
3099                if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3100                        break;
3101                msleep_interruptible(1);
3102        }
3103
3104        RTL_W16(IntrStatus, 0xffff);
3105
3106        pci_set_master(pdev);
3107
3108        /* Identify chip attached to board */
3109        rtl8169_get_mac_version(tp, ioaddr);
3110
3111        /* Use appropriate default if unknown */
3112        if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3113                netif_notice(tp, probe, dev,
3114                             "unknown MAC, using family default\n");
3115                tp->mac_version = cfg->default_ver;
3116        }
3117
3118        rtl8169_print_mac_version(tp);
3119
3120        for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3121                if (tp->mac_version == rtl_chip_info[i].mac_version)
3122                        break;
3123        }
3124        if (i == ARRAY_SIZE(rtl_chip_info)) {
3125                dev_err(&pdev->dev,
3126                        "driver bug, MAC version not found in rtl_chip_info\n");
3127                goto err_out_msi_4;
3128        }
3129        tp->chipset = i;
3130
3131        RTL_W8(Cfg9346, Cfg9346_Unlock);
3132        RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3133        RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3134        if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3135                tp->features |= RTL_FEATURE_WOL;
3136        if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3137                tp->features |= RTL_FEATURE_WOL;
3138        tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3139        RTL_W8(Cfg9346, Cfg9346_Lock);
3140
3141        if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3142            (RTL_R8(PHYstatus) & TBI_Enable)) {
3143                tp->set_speed = rtl8169_set_speed_tbi;
3144                tp->get_settings = rtl8169_gset_tbi;
3145                tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3146                tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3147                tp->link_ok = rtl8169_tbi_link_ok;
3148                tp->do_ioctl = rtl_tbi_ioctl;
3149
3150                tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3151        } else {
3152                tp->set_speed = rtl8169_set_speed_xmii;
3153                tp->get_settings = rtl8169_gset_xmii;
3154                tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3155                tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3156                tp->link_ok = rtl8169_xmii_link_ok;
3157                tp->do_ioctl = rtl_xmii_ioctl;
3158        }
3159
3160        spin_lock_init(&tp->lock);
3161
3162        tp->mmio_addr = ioaddr;
3163
3164        /* Get MAC address */
3165        for (i = 0; i < MAC_ADDR_LEN; i++)
3166                dev->dev_addr[i] = RTL_R8(MAC0 + i);
3167        memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3168
3169        SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3170        dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3171        dev->irq = pdev->irq;
3172        dev->base_addr = (unsigned long) ioaddr;
3173
3174        netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3175
3176#ifdef CONFIG_R8169_VLAN
3177        dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3178#endif
3179
3180        tp->intr_mask = 0xffff;
3181        tp->align = cfg->align;
3182        tp->hw_start = cfg->hw_start;
3183        tp->intr_event = cfg->intr_event;
3184        tp->napi_event = cfg->napi_event;
3185
3186        init_timer(&tp->timer);
3187        tp->timer.data = (unsigned long) dev;
3188        tp->timer.function = rtl8169_phy_timer;
3189
3190        rc = register_netdev(dev);
3191        if (rc < 0)
3192                goto err_out_msi_4;
3193
3194        pci_set_drvdata(pdev, dev);
3195
3196        netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3197                   rtl_chip_info[tp->chipset].name,
3198                   dev->base_addr, dev->dev_addr,
3199                   (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3200
3201        rtl8169_init_phy(dev, tp);
3202
3203        /*
3204         * Pretend we are using VLANs; This bypasses a nasty bug where
3205         * Interrupts stop flowing on high load on 8110SCd controllers.
3206         */
3207        if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3208                RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3209
3210        device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3211
3212out:
3213        return rc;
3214
3215err_out_msi_4:
3216        rtl_disable_msi(pdev, tp);
3217        iounmap(ioaddr);
3218err_out_free_res_3:
3219        pci_release_regions(pdev);
3220err_out_mwi_2:
3221        pci_clear_mwi(pdev);
3222        pci_disable_device(pdev);
3223err_out_free_dev_1:
3224        free_netdev(dev);
3225        goto out;
3226}
3227
3228static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3229{
3230        struct net_device *dev = pci_get_drvdata(pdev);
3231        struct rtl8169_private *tp = netdev_priv(dev);
3232
3233        flush_scheduled_work();
3234
3235        unregister_netdev(dev);
3236
3237        /* restore original MAC address */
3238        rtl_rar_set(tp, dev->perm_addr);
3239
3240        rtl_disable_msi(pdev, tp);
3241        rtl8169_release_board(pdev, dev, tp->mmio_addr);
3242        pci_set_drvdata(pdev, NULL);
3243}
3244
3245static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
3246                                  unsigned int mtu)
3247{
3248        unsigned int max_frame = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3249
3250        if (max_frame != 16383)
3251                printk(KERN_WARNING PFX "WARNING! Changing of MTU on this "
3252                        "NIC may lead to frame reception errors!\n");
3253
3254        tp->rx_buf_sz = (max_frame > RX_BUF_SIZE) ? max_frame : RX_BUF_SIZE;
3255}
3256
3257static int rtl8169_open(struct net_device *dev)
3258{
3259        struct rtl8169_private *tp = netdev_priv(dev);
3260        struct pci_dev *pdev = tp->pci_dev;
3261        int retval = -ENOMEM;
3262
3263
3264        /*
3265         * Note that we use a magic value here, its wierd I know
3266         * its done because, some subset of rtl8169 hardware suffers from
3267         * a problem in which frames received that are longer than
3268         * the size set in RxMaxSize register return garbage sizes
3269         * when received.  To avoid this we need to turn off filtering,
3270         * which is done by setting a value of 16383 in the RxMaxSize register
3271         * and allocating 16k frames to handle the largest possible rx value
3272         * thats what the magic math below does.
3273         */
3274        rtl8169_set_rxbufsize(tp, 16383 - VLAN_ETH_HLEN - ETH_FCS_LEN);
3275
3276        /*
3277         * Rx and Tx desscriptors needs 256 bytes alignment.
3278         * pci_alloc_consistent provides more.
3279         */
3280        tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
3281                                               &tp->TxPhyAddr);
3282        if (!tp->TxDescArray)
3283                goto out;
3284
3285        tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
3286                                               &tp->RxPhyAddr);
3287        if (!tp->RxDescArray)
3288                goto err_free_tx_0;
3289
3290        retval = rtl8169_init_ring(dev);
3291        if (retval < 0)
3292                goto err_free_rx_1;
3293
3294        INIT_DELAYED_WORK(&tp->task, NULL);
3295
3296        smp_mb();
3297
3298        retval = request_irq(dev->irq, rtl8169_interrupt,
3299                             (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3300                             dev->name, dev);
3301        if (retval < 0)
3302                goto err_release_ring_2;
3303
3304        napi_enable(&tp->napi);
3305
3306        rtl_hw_start(dev);
3307
3308        rtl8169_request_timer(dev);
3309
3310        rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3311out:
3312        return retval;
3313
3314err_release_ring_2:
3315        rtl8169_rx_clear(tp);
3316err_free_rx_1:
3317        pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3318                            tp->RxPhyAddr);
3319err_free_tx_0:
3320        pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3321                            tp->TxPhyAddr);
3322        goto out;
3323}
3324
3325static void rtl8169_hw_reset(void __iomem *ioaddr)
3326{
3327        /* Disable interrupts */
3328        rtl8169_irq_mask_and_ack(ioaddr);
3329
3330        /* Reset the chipset */
3331        RTL_W8(ChipCmd, CmdReset);
3332
3333        /* PCI commit */
3334        RTL_R8(ChipCmd);
3335}
3336
3337static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3338{
3339        void __iomem *ioaddr = tp->mmio_addr;
3340        u32 cfg = rtl8169_rx_config;
3341
3342        cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3343        RTL_W32(RxConfig, cfg);
3344
3345        /* Set DMA burst size and Interframe Gap Time */
3346        RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3347                (InterFrameGap << TxInterFrameGapShift));
3348}
3349
3350static void rtl_hw_start(struct net_device *dev)
3351{
3352        struct rtl8169_private *tp = netdev_priv(dev);
3353        void __iomem *ioaddr = tp->mmio_addr;
3354        unsigned int i;
3355
3356        /* Soft reset the chip. */
3357        RTL_W8(ChipCmd, CmdReset);
3358
3359        /* Check that the chip has finished the reset. */
3360        for (i = 0; i < 100; i++) {
3361                if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3362                        break;
3363                msleep_interruptible(1);
3364        }
3365
3366        tp->hw_start(dev);
3367
3368        netif_start_queue(dev);
3369}
3370
3371
3372static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3373                                         void __iomem *ioaddr)
3374{
3375        /*
3376         * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3377         * register to be written before TxDescAddrLow to work.
3378         * Switching from MMIO to I/O access fixes the issue as well.
3379         */
3380        RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3381        RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3382        RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3383        RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3384}
3385
3386static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3387{
3388        u16 cmd;
3389
3390        cmd = RTL_R16(CPlusCmd);
3391        RTL_W16(CPlusCmd, cmd);
3392        return cmd;
3393}
3394
3395static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3396{
3397        /* Low hurts. Let's disable the filtering. */
3398        RTL_W16(RxMaxSize, rx_buf_sz + 1);
3399}
3400
3401static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3402{
3403        static const struct {
3404                u32 mac_version;
3405                u32 clk;
3406                u32 val;
3407        } cfg2_info [] = {
3408                { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3409                { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3410                { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3411                { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3412        }, *p = cfg2_info;
3413        unsigned int i;
3414        u32 clk;
3415
3416        clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3417        for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3418                if ((p->mac_version == mac_version) && (p->clk == clk)) {
3419                        RTL_W32(0x7c, p->val);
3420                        break;
3421                }
3422        }
3423}
3424
3425static void rtl_hw_start_8169(struct net_device *dev)
3426{
3427        struct rtl8169_private *tp = netdev_priv(dev);
3428        void __iomem *ioaddr = tp->mmio_addr;
3429        struct pci_dev *pdev = tp->pci_dev;
3430
3431        if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3432                RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3433                pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3434        }
3435
3436        RTL_W8(Cfg9346, Cfg9346_Unlock);
3437        if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3438            (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3439            (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3440            (tp->mac_version == RTL_GIGA_MAC_VER_04))
3441                RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3442
3443        RTL_W8(EarlyTxThres, EarlyTxThld);
3444
3445        rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3446
3447        if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3448            (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3449            (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3450            (tp->mac_version == RTL_GIGA_MAC_VER_04))
3451                rtl_set_rx_tx_config_registers(tp);
3452
3453        tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3454
3455        if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3456            (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3457                dprintk("Set MAC Reg C+CR Offset 0xE0. "
3458                        "Bit-3 and bit-14 MUST be 1\n");
3459                tp->cp_cmd |= (1 << 14);
3460        }
3461
3462        RTL_W16(CPlusCmd, tp->cp_cmd);
3463
3464        rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3465
3466        /*
3467         * Undocumented corner. Supposedly:
3468         * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3469         */
3470        RTL_W16(IntrMitigate, 0x0000);
3471
3472        rtl_set_rx_tx_desc_registers(tp, ioaddr);
3473
3474        if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3475            (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3476            (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3477            (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3478                RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3479                rtl_set_rx_tx_config_registers(tp);
3480        }
3481
3482        RTL_W8(Cfg9346, Cfg9346_Lock);
3483
3484        /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3485        RTL_R8(IntrMask);
3486
3487        RTL_W32(RxMissed, 0);
3488
3489        rtl_set_rx_mode(dev);
3490
3491        /* no early-rx interrupts */
3492        RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3493
3494        /* Enable all known interrupts by setting the interrupt mask. */
3495        RTL_W16(IntrMask, tp->intr_event);
3496}
3497
3498static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3499{
3500        struct net_device *dev = pci_get_drvdata(pdev);
3501        struct rtl8169_private *tp = netdev_priv(dev);
3502        int cap = tp->pcie_cap;
3503
3504        if (cap) {
3505                u16 ctl;
3506
3507                pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3508                ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3509                pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3510        }
3511}
3512
3513static void rtl_csi_access_enable(void __iomem *ioaddr)
3514{
3515        u32 csi;
3516
3517        csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3518        rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3519}
3520
3521struct ephy_info {
3522        unsigned int offset;
3523        u16 mask;
3524        u16 bits;
3525};
3526
3527static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3528{
3529        u16 w;
3530
3531        while (len-- > 0) {
3532                w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3533                rtl_ephy_write(ioaddr, e->offset, w);
3534                e++;
3535        }
3536}
3537
3538static void rtl_disable_clock_request(struct pci_dev *pdev)
3539{
3540        struct net_device *dev = pci_get_drvdata(pdev);
3541        struct rtl8169_private *tp = netdev_priv(dev);
3542        int cap = tp->pcie_cap;
3543
3544        if (cap) {
3545                u16 ctl;
3546
3547                pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3548                ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3549                pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3550        }
3551}
3552
3553#define R8168_CPCMD_QUIRK_MASK (\
3554        EnableBist | \
3555        Mac_dbgo_oe | \
3556        Force_half_dup | \
3557        Force_rxflow_en | \
3558        Force_txflow_en | \
3559        Cxpl_dbg_sel | \
3560        ASF | \
3561        PktCntrDisable | \
3562        Mac_dbgo_sel)
3563
3564static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3565{
3566        RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3567
3568        RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3569
3570        rtl_tx_performance_tweak(pdev,
3571                (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3572}
3573
3574static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3575{
3576        rtl_hw_start_8168bb(ioaddr, pdev);
3577
3578        RTL_W8(EarlyTxThres, EarlyTxThld);
3579
3580        RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3581}
3582
3583static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3584{
3585        RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3586
3587        RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3588
3589        rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3590
3591        rtl_disable_clock_request(pdev);
3592
3593        RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3594}
3595
3596static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3597{
3598        static const struct ephy_info e_info_8168cp[] = {
3599                { 0x01, 0,      0x0001 },
3600                { 0x02, 0x0800, 0x1000 },
3601                { 0x03, 0,      0x0042 },
3602                { 0x06, 0x0080, 0x0000 },
3603                { 0x07, 0,      0x2000 }
3604        };
3605
3606        rtl_csi_access_enable(ioaddr);
3607
3608        rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3609
3610        __rtl_hw_start_8168cp(ioaddr, pdev);
3611}
3612
3613static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3614{
3615        rtl_csi_access_enable(ioaddr);
3616
3617        RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3618
3619        rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3620
3621        RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3622}
3623
3624static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3625{
3626        rtl_csi_access_enable(ioaddr);
3627
3628        RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3629
3630        /* Magic. */
3631        RTL_W8(DBG_REG, 0x20);
3632
3633        RTL_W8(EarlyTxThres, EarlyTxThld);
3634
3635        rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3636
3637        RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3638}
3639
3640static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3641{
3642        static const struct ephy_info e_info_8168c_1[] = {
3643                { 0x02, 0x0800, 0x1000 },
3644                { 0x03, 0,      0x0002 },
3645                { 0x06, 0x0080, 0x0000 }
3646        };
3647
3648        rtl_csi_access_enable(ioaddr);
3649
3650        RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3651
3652        rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3653
3654        __rtl_hw_start_8168cp(ioaddr, pdev);
3655}
3656
3657static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3658{
3659        static const struct ephy_info e_info_8168c_2[] = {
3660                { 0x01, 0,      0x0001 },
3661                { 0x03, 0x0400, 0x0220 }
3662        };
3663
3664        rtl_csi_access_enable(ioaddr);
3665
3666        rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3667
3668        __rtl_hw_start_8168cp(ioaddr, pdev);
3669}
3670
3671static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3672{
3673        rtl_hw_start_8168c_2(ioaddr, pdev);
3674}
3675
3676static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3677{
3678        rtl_csi_access_enable(ioaddr);
3679
3680        __rtl_hw_start_8168cp(ioaddr, pdev);
3681}
3682
3683static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3684{
3685        rtl_csi_access_enable(ioaddr);
3686
3687        rtl_disable_clock_request(pdev);
3688
3689        RTL_W8(EarlyTxThres, EarlyTxThld);
3690
3691        rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3692
3693        RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3694}
3695
3696static void rtl_hw_start_8168(struct net_device *dev)
3697{
3698        struct rtl8169_private *tp = netdev_priv(dev);
3699        void __iomem *ioaddr = tp->mmio_addr;
3700        struct pci_dev *pdev = tp->pci_dev;
3701
3702        RTL_W8(Cfg9346, Cfg9346_Unlock);
3703
3704        RTL_W8(EarlyTxThres, EarlyTxThld);
3705
3706        rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3707
3708        tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3709
3710        RTL_W16(CPlusCmd, tp->cp_cmd);
3711
3712        RTL_W16(IntrMitigate, 0x5151);
3713
3714        /* Work around for RxFIFO overflow. */
3715        if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
3716            tp->mac_version == RTL_GIGA_MAC_VER_22) {
3717                tp->intr_event |= RxFIFOOver | PCSTimeout;
3718                tp->intr_event &= ~RxOverflow;
3719        }
3720
3721        rtl_set_rx_tx_desc_registers(tp, ioaddr);
3722
3723        rtl_set_rx_mode(dev);
3724
3725        RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3726                (InterFrameGap << TxInterFrameGapShift));
3727
3728        RTL_R8(IntrMask);
3729
3730        switch (tp->mac_version) {
3731        case RTL_GIGA_MAC_VER_11:
3732                rtl_hw_start_8168bb(ioaddr, pdev);
3733        break;
3734
3735        case RTL_GIGA_MAC_VER_12:
3736        case RTL_GIGA_MAC_VER_17:
3737                rtl_hw_start_8168bef(ioaddr, pdev);
3738        break;
3739
3740        case RTL_GIGA_MAC_VER_18:
3741                rtl_hw_start_8168cp_1(ioaddr, pdev);
3742        break;
3743
3744        case RTL_GIGA_MAC_VER_19:
3745                rtl_hw_start_8168c_1(ioaddr, pdev);
3746        break;
3747
3748        case RTL_GIGA_MAC_VER_20:
3749                rtl_hw_start_8168c_2(ioaddr, pdev);
3750        break;
3751
3752        case RTL_GIGA_MAC_VER_21:
3753                rtl_hw_start_8168c_3(ioaddr, pdev);
3754        break;
3755
3756        case RTL_GIGA_MAC_VER_22:
3757                rtl_hw_start_8168c_4(ioaddr, pdev);
3758        break;
3759
3760        case RTL_GIGA_MAC_VER_23:
3761                rtl_hw_start_8168cp_2(ioaddr, pdev);
3762        break;
3763
3764        case RTL_GIGA_MAC_VER_24:
3765                rtl_hw_start_8168cp_3(ioaddr, pdev);
3766        break;
3767
3768        case RTL_GIGA_MAC_VER_25:
3769        case RTL_GIGA_MAC_VER_26:
3770        case RTL_GIGA_MAC_VER_27:
3771                rtl_hw_start_8168d(ioaddr, pdev);
3772        break;
3773
3774        default:
3775                printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3776                        dev->name, tp->mac_version);
3777        break;
3778        }
3779
3780        RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3781
3782        RTL_W8(Cfg9346, Cfg9346_Lock);
3783
3784        RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3785
3786        RTL_W16(IntrMask, tp->intr_event);
3787}
3788
3789#define R810X_CPCMD_QUIRK_MASK (\
3790        EnableBist | \
3791        Mac_dbgo_oe | \
3792        Force_half_dup | \
3793        Force_rxflow_en | \
3794        Force_txflow_en | \
3795        Cxpl_dbg_sel | \
3796        ASF | \
3797        PktCntrDisable | \
3798        PCIDAC | \
3799        PCIMulRW)
3800
3801static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3802{
3803        static const struct ephy_info e_info_8102e_1[] = {
3804                { 0x01, 0, 0x6e65 },
3805                { 0x02, 0, 0x091f },
3806                { 0x03, 0, 0xc2f9 },
3807                { 0x06, 0, 0xafb5 },
3808                { 0x07, 0, 0x0e00 },
3809                { 0x19, 0, 0xec80 },
3810                { 0x01, 0, 0x2e65 },
3811                { 0x01, 0, 0x6e65 }
3812        };
3813        u8 cfg1;
3814
3815        rtl_csi_access_enable(ioaddr);
3816
3817        RTL_W8(DBG_REG, FIX_NAK_1);
3818
3819        rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3820
3821        RTL_W8(Config1,
3822               LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3823        RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3824
3825        cfg1 = RTL_R8(Config1);
3826        if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3827                RTL_W8(Config1, cfg1 & ~LEDS0);
3828
3829        RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3830
3831        rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3832}
3833
3834static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3835{
3836        rtl_csi_access_enable(ioaddr);
3837
3838        rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3839
3840        RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3841        RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3842
3843        RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3844}
3845
3846static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3847{
3848        rtl_hw_start_8102e_2(ioaddr, pdev);
3849
3850        rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3851}
3852
3853static void rtl_hw_start_8101(struct net_device *dev)
3854{
3855        struct rtl8169_private *tp = netdev_priv(dev);
3856        void __iomem *ioaddr = tp->mmio_addr;
3857        struct pci_dev *pdev = tp->pci_dev;
3858
3859        if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3860            (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3861                int cap = tp->pcie_cap;
3862
3863                if (cap) {
3864                        pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3865                                              PCI_EXP_DEVCTL_NOSNOOP_EN);
3866                }
3867        }
3868
3869        switch (tp->mac_version) {
3870        case RTL_GIGA_MAC_VER_07:
3871                rtl_hw_start_8102e_1(ioaddr, pdev);
3872                break;
3873
3874        case RTL_GIGA_MAC_VER_08:
3875                rtl_hw_start_8102e_3(ioaddr, pdev);
3876                break;
3877
3878        case RTL_GIGA_MAC_VER_09:
3879                rtl_hw_start_8102e_2(ioaddr, pdev);
3880                break;
3881        }
3882
3883        RTL_W8(Cfg9346, Cfg9346_Unlock);
3884
3885        RTL_W8(EarlyTxThres, EarlyTxThld);
3886
3887        rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3888
3889        tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3890
3891        RTL_W16(CPlusCmd, tp->cp_cmd);
3892
3893        RTL_W16(IntrMitigate, 0x0000);
3894
3895        rtl_set_rx_tx_desc_registers(tp, ioaddr);
3896
3897        RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3898        rtl_set_rx_tx_config_registers(tp);
3899
3900        RTL_W8(Cfg9346, Cfg9346_Lock);
3901
3902        RTL_R8(IntrMask);
3903
3904        rtl_set_rx_mode(dev);
3905
3906        RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3907
3908        RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3909
3910        RTL_W16(IntrMask, tp->intr_event);
3911}
3912
3913static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3914{
3915        struct rtl8169_private *tp = netdev_priv(dev);
3916        int ret = 0;
3917
3918        if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3919                return -EINVAL;
3920
3921        dev->mtu = new_mtu;
3922
3923        if (!netif_running(dev))
3924                goto out;
3925
3926        rtl8169_down(dev);
3927
3928        rtl8169_set_rxbufsize(tp, dev->mtu);
3929
3930        ret = rtl8169_init_ring(dev);
3931        if (ret < 0)
3932                goto out;
3933
3934        napi_enable(&tp->napi);
3935
3936        rtl_hw_start(dev);
3937
3938        rtl8169_request_timer(dev);
3939
3940out:
3941        return ret;
3942}
3943
3944static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3945{
3946        desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3947        desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3948}
3949
3950static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
3951                                struct sk_buff **sk_buff, struct RxDesc *desc)
3952{
3953        struct pci_dev *pdev = tp->pci_dev;
3954
3955        pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
3956                         PCI_DMA_FROMDEVICE);
3957        dev_kfree_skb(*sk_buff);
3958        *sk_buff = NULL;
3959        rtl8169_make_unusable_by_asic(desc);
3960}
3961
3962static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3963{
3964        u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3965
3966        desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3967}
3968
3969static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3970                                       u32 rx_buf_sz)
3971{
3972        desc->addr = cpu_to_le64(mapping);
3973        wmb();
3974        rtl8169_mark_to_asic(desc, rx_buf_sz);
3975}
3976
3977static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
3978                                            struct net_device *dev,
3979                                            struct RxDesc *desc, int rx_buf_sz,
3980                                            unsigned int align, gfp_t gfp)
3981{
3982        struct sk_buff *skb;
3983        dma_addr_t mapping;
3984        unsigned int pad;
3985
3986        pad = align ? align : NET_IP_ALIGN;
3987
3988        skb = __netdev_alloc_skb(dev, rx_buf_sz + pad, gfp);
3989        if (!skb)
3990                goto err_out;
3991
3992        skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
3993
3994        mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
3995                                 PCI_DMA_FROMDEVICE);
3996
3997        rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
3998out:
3999        return skb;
4000

4001err_out:
4002        rtl8169_make_unusable_by_asic(desc);
4003        goto out;
4004}
4005
4006static void rtl8169_rx_clear(struct rtl8169_private *tp)
4007{
4008        unsigned int i;
4009
4010        for (i = 0; i < NUM_RX_DESC; i++) {
4011                if (tp->Rx_skbuff[i]) {
4012                        rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
4013                                            tp->RxDescArray + i);
4014                }
4015        }
4016}
4017
4018static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
4019                           u32 start, u32 end, gfp_t gfp)
4020{
4021        u32 cur;
4022
4023        for (cur = start; end - cur != 0; cur++) {
4024                struct sk_buff *skb;
4025                unsigned int i = cur % NUM_RX_DESC;
4026
4027                WARN_ON((s32)(end - cur) < 0);
4028
4029                if (tp->Rx_skbuff[i])
4030                        continue;
4031
4032                skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
4033                                           tp->RxDescArray + i,
4034                                           tp->rx_buf_sz, tp->align, gfp);
4035                if (!skb)
4036                        break;
4037
4038                tp->Rx_skbuff[i] = skb;
4039        }
4040        return cur - start;
4041}
4042
4043static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4044{
4045        desc->opts1 |= cpu_to_le32(RingEnd);
4046}
4047
4048static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4049{
4050        tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4051}
4052
4053static int rtl8169_init_ring(struct net_device *dev)
4054{
4055        struct rtl8169_private *tp = netdev_priv(dev);
4056
4057        rtl8169_init_ring_indexes(tp);
4058
4059        memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4060        memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
4061
4062        if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC, GFP_KERNEL) != NUM_RX_DESC)
4063                goto err_out;
4064
4065        rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4066
4067        return 0;
4068
4069err_out:
4070        rtl8169_rx_clear(tp);
4071        return -ENOMEM;
4072}
4073
4074static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
4075                                 struct TxDesc *desc)
4076{
4077        unsigned int len = tx_skb->len;
4078
4079        pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
4080        desc->opts1 = 0x00;
4081        desc->opts2 = 0x00;
4082        desc->addr = 0x00;
4083        tx_skb->len = 0;
4084}
4085
4086static void rtl8169_tx_clear(struct rtl8169_private *tp)
4087{
4088        unsigned int i;
4089
4090        for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
4091                unsigned int entry = i % NUM_TX_DESC;
4092                struct ring_info *tx_skb = tp->tx_skb + entry;
4093                unsigned int len = tx_skb->len;
4094
4095                if (len) {
4096                        struct sk_buff *skb = tx_skb->skb;
4097
4098                        rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
4099                                             tp->TxDescArray + entry);
4100                        if (skb) {
4101                                dev_kfree_skb(skb);
4102                                tx_skb->skb = NULL;
4103                        }
4104                        tp->dev->stats.tx_dropped++;
4105                }
4106        }
4107        tp->cur_tx = tp->dirty_tx = 0;
4108}
4109
4110static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4111{
4112        struct rtl8169_private *tp = netdev_priv(dev);
4113
4114        PREPARE_DELAYED_WORK(&tp->task, task);
4115        schedule_delayed_work(&tp->task, 4);
4116}
4117
4118static void rtl8169_wait_for_quiescence(struct net_device *dev)
4119{
4120        struct rtl8169_private *tp = netdev_priv(dev);
4121        void __iomem *ioaddr = tp->mmio_addr;
4122
4123        synchronize_irq(dev->irq);
4124
4125        /* Wait for any pending NAPI task to complete */
4126        napi_disable(&tp->napi);
4127
4128        rtl8169_irq_mask_and_ack(ioaddr);
4129
4130        tp->intr_mask = 0xffff;
4131        RTL_W16(IntrMask, tp->intr_event);
4132        napi_enable(&tp->napi);
4133}
4134
4135static void rtl8169_reinit_task(struct work_struct *work)
4136{
4137        struct rtl8169_private *tp =
4138                container_of(work, struct rtl8169_private, task.work);
4139        struct net_device *dev = tp->dev;
4140        int ret;
4141
4142        rtnl_lock();
4143
4144        if (!netif_running(dev))
4145                goto out_unlock;
4146
4147        rtl8169_wait_for_quiescence(dev);
4148        rtl8169_close(dev);
4149
4150        ret = rtl8169_open(dev);
4151        if (unlikely(ret < 0)) {
4152                if (net_ratelimit())
4153                        netif_err(tp, drv, dev,
4154                                  "reinit failure (status = %d). Rescheduling\n",
4155                                  ret);
4156                rtl8169_schedule_work(dev, rtl8169_reinit_task);
4157        }
4158
4159out_unlock:
4160        rtnl_unlock();
4161}
4162
4163static void rtl8169_reset_task(struct work_struct *work)
4164{
4165        struct rtl8169_private *tp =
4166                container_of(work, struct rtl8169_private, task.work);
4167        struct net_device *dev = tp->dev;
4168
4169        rtnl_lock();
4170
4171        if (!netif_running(dev))
4172                goto out_unlock;
4173
4174        rtl8169_wait_for_quiescence(dev);
4175
4176        rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4177        rtl8169_tx_clear(tp);
4178
4179        if (tp->dirty_rx == tp->cur_rx) {
4180                rtl8169_init_ring_indexes(tp);
4181                rtl_hw_start(dev);
4182                netif_wake_queue(dev);
4183                rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4184        } else {
4185                if (net_ratelimit())
4186                        netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4187                rtl8169_schedule_work(dev, rtl8169_reset_task);
4188        }
4189
4190out_unlock:
4191        rtnl_unlock();
4192}
4193
4194static void rtl8169_tx_timeout(struct net_device *dev)
4195{
4196        struct rtl8169_private *tp = netdev_priv(dev);
4197
4198        rtl8169_hw_reset(tp->mmio_addr);
4199
4200        /* Let's wait a bit while any (async) irq lands on */
4201        rtl8169_schedule_work(dev, rtl8169_reset_task);
4202}
4203
4204static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4205                              u32 opts1)
4206{
4207        struct skb_shared_info *info = skb_shinfo(skb);
4208        unsigned int cur_frag, entry;
4209        struct TxDesc * uninitialized_var(txd);
4210
4211        entry = tp->cur_tx;
4212        for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4213                skb_frag_t *frag = info->frags + cur_frag;
4214                dma_addr_t mapping;
4215                u32 status, len;
4216                void *addr;
4217
4218                entry = (entry + 1) % NUM_TX_DESC;
4219
4220                txd = tp->TxDescArray + entry;
4221                len = frag->size;
4222                addr = ((void *) page_address(frag->page)) + frag->page_offset;
4223                mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
4224
4225                /* anti gcc 2.95.3 bugware (sic) */
4226                status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4227
4228                txd->opts1 = cpu_to_le32(status);
4229                txd->addr = cpu_to_le64(mapping);
4230
4231                tp->tx_skb[entry].len = len;
4232        }
4233
4234        if (cur_frag) {
4235                tp->tx_skb[entry].skb = skb;
4236                txd->opts1 |= cpu_to_le32(LastFrag);
4237        }
4238
4239        return cur_frag;
4240}
4241
4242static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4243{
4244        if (dev->features & NETIF_F_TSO) {
4245                u32 mss = skb_shinfo(skb)->gso_size;
4246
4247                if (mss)
4248                        return LargeSend | ((mss & MSSMask) << MSSShift);
4249        }
4250        if (skb->ip_summed == CHECKSUM_PARTIAL) {
4251                const struct iphdr *ip = ip_hdr(skb);
4252
4253                if (ip->protocol == IPPROTO_TCP)
4254                        return IPCS | TCPCS;
4255                else if (ip->protocol == IPPROTO_UDP)
4256                        return IPCS | UDPCS;
4257                WARN_ON(1);     /* we need a WARN() */
4258        }
4259        return 0;
4260}
4261
4262static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4263                                      struct net_device *dev)
4264{
4265        struct rtl8169_private *tp = netdev_priv(dev);
4266        unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
4267        struct TxDesc *txd = tp->TxDescArray + entry;
4268        void __iomem *ioaddr = tp->mmio_addr;
4269        dma_addr_t mapping;
4270        u32 status, len;
4271        u32 opts1;
4272
4273        if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4274                netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4275                goto err_stop;
4276        }
4277
4278        if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4279                goto err_stop;
4280
4281        opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4282
4283        frags = rtl8169_xmit_frags(tp, skb, opts1);
4284        if (frags) {
4285                len = skb_headlen(skb);
4286                opts1 |= FirstFrag;
4287        } else {
4288                len = skb->len;
4289                opts1 |= FirstFrag | LastFrag;
4290                tp->tx_skb[entry].skb = skb;
4291        }
4292
4293        mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
4294
4295        tp->tx_skb[entry].len = len;
4296        txd->addr = cpu_to_le64(mapping);
4297        txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4298
4299        wmb();
4300
4301        /* anti gcc 2.95.3 bugware (sic) */
4302        status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4303        txd->opts1 = cpu_to_le32(status);
4304
4305        tp->cur_tx += frags + 1;
4306
4307        wmb();
4308
4309        RTL_W8(TxPoll, NPQ);    /* set polling bit */
4310
4311        if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4312                netif_stop_queue(dev);
4313                smp_rmb();
4314                if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4315                        netif_wake_queue(dev);
4316        }
4317
4318        return NETDEV_TX_OK;
4319
4320err_stop:
4321        netif_stop_queue(dev);
4322        dev->stats.tx_dropped++;
4323        return NETDEV_TX_BUSY;
4324}
4325
4326static void rtl8169_pcierr_interrupt(struct net_device *dev)
4327{
4328        struct rtl8169_private *tp = netdev_priv(dev);
4329        struct pci_dev *pdev = tp->pci_dev;
4330        void __iomem *ioaddr = tp->mmio_addr;
4331        u16 pci_status, pci_cmd;
4332
4333        pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4334        pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4335
4336        netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4337                  pci_cmd, pci_status);
4338
4339        /*
4340         * The recovery sequence below admits a very elaborated explanation:
4341         * - it seems to work;
4342         * - I did not see what else could be done;
4343         * - it makes iop3xx happy.
4344         *
4345         * Feel free to adjust to your needs.
4346         */
4347        if (pdev->broken_parity_status)
4348                pci_cmd &= ~PCI_COMMAND_PARITY;
4349        else
4350                pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4351
4352        pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4353
4354        pci_write_config_word(pdev, PCI_STATUS,
4355                pci_status & (PCI_STATUS_DETECTED_PARITY |
4356                PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4357                PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4358
4359        /* The infamous DAC f*ckup only happens at boot time */
4360        if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4361                netif_info(tp, intr, dev, "disabling PCI DAC\n");
4362                tp->cp_cmd &= ~PCIDAC;
4363                RTL_W16(CPlusCmd, tp->cp_cmd);
4364                dev->features &= ~NETIF_F_HIGHDMA;
4365        }
4366
4367        rtl8169_hw_reset(ioaddr);
4368
4369        rtl8169_schedule_work(dev, rtl8169_reinit_task);
4370}
4371
4372static void rtl8169_tx_interrupt(struct net_device *dev,
4373                                 struct rtl8169_private *tp,
4374                                 void __iomem *ioaddr)
4375{
4376        unsigned int dirty_tx, tx_left;
4377
4378        dirty_tx = tp->dirty_tx;
4379        smp_rmb();
4380        tx_left = tp->cur_tx - dirty_tx;
4381
4382        while (tx_left > 0) {
4383                unsigned int entry = dirty_tx % NUM_TX_DESC;
4384                struct ring_info *tx_skb = tp->tx_skb + entry;
4385                u32 len = tx_skb->len;
4386                u32 status;
4387
4388                rmb();
4389                status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4390                if (status & DescOwn)
4391                        break;
4392
4393                dev->stats.tx_bytes += len;
4394                dev->stats.tx_packets++;
4395
4396                rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
4397
4398                if (status & LastFrag) {
4399                        dev_kfree_skb(tx_skb->skb);
4400                        tx_skb->skb = NULL;
4401                }
4402                dirty_tx++;
4403                tx_left--;
4404        }
4405
4406        if (tp->dirty_tx != dirty_tx) {
4407                tp->dirty_tx = dirty_tx;
4408                smp_wmb();
4409                if (netif_queue_stopped(dev) &&
4410                    (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4411                        netif_wake_queue(dev);
4412                }
4413                /*
4414                 * 8168 hack: TxPoll requests are lost when the Tx packets are
4415                 * too close. Let's kick an extra TxPoll request when a burst
4416                 * of start_xmit activity is detected (if it is not detected,
4417                 * it is slow enough). -- FR
4418                 */
4419                smp_rmb();
4420                if (tp->cur_tx != dirty_tx)
4421                        RTL_W8(TxPoll, NPQ);
4422        }
4423}
4424
4425static inline int rtl8169_fragmented_frame(u32 status)
4426{
4427        return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4428}
4429
4430static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
4431{
4432        u32 opts1 = le32_to_cpu(desc->opts1);
4433        u32 status = opts1 & RxProtoMask;
4434
4435        if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4436            ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
4437            ((status == RxProtoIP) && !(opts1 & IPFail)))
4438                skb->ip_summed = CHECKSUM_UNNECESSARY;
4439        else
4440                skb->ip_summed = CHECKSUM_NONE;
4441}
4442
4443static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
4444                                       struct rtl8169_private *tp, int pkt_size,
4445                                       dma_addr_t addr)
4446{
4447        struct sk_buff *skb;
4448        bool done = false;
4449
4450        if (pkt_size >= rx_copybreak)
4451                goto out;
4452
4453        skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4454        if (!skb)
4455                goto out;
4456
4457        pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
4458                                    PCI_DMA_FROMDEVICE);
4459        skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
4460        *sk_buff = skb;
4461        done = true;
4462out:
4463        return done;
4464}
4465
4466/*
4467 * Warning : rtl8169_rx_interrupt() might be called :
4468 * 1) from NAPI (softirq) context
4469 *      (polling = 1 : we should call netif_receive_skb())
4470 * 2) from process context (rtl8169_reset_task())
4471 *      (polling = 0 : we must call netif_rx() instead)
4472 */
4473static int rtl8169_rx_interrupt(struct net_device *dev,
4474                                struct rtl8169_private *tp,
4475                                void __iomem *ioaddr, u32 budget)
4476{
4477        unsigned int cur_rx, rx_left;
4478        unsigned int delta, count;
4479        int polling = (budget != ~(u32)0) ? 1 : 0;
4480
4481        cur_rx = tp->cur_rx;
4482        rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4483        rx_left = min(rx_left, budget);
4484
4485        for (; rx_left > 0; rx_left--, cur_rx++) {
4486                unsigned int entry = cur_rx % NUM_RX_DESC;
4487                struct RxDesc *desc = tp->RxDescArray + entry;
4488                u32 status;
4489
4490                rmb();
4491                status = le32_to_cpu(desc->opts1);
4492
4493                if (status & DescOwn)
4494                        break;
4495                if (unlikely(status & RxRES)) {
4496                        netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4497                                   status);
4498                        dev->stats.rx_errors++;
4499                        if (status & (RxRWT | RxRUNT))
4500                                dev->stats.rx_length_errors++;
4501                        if (status & RxCRC)
4502                                dev->stats.rx_crc_errors++;
4503                        if (status & RxFOVF) {
4504                                rtl8169_schedule_work(dev, rtl8169_reset_task);
4505                                dev->stats.rx_fifo_errors++;
4506                        }
4507                        rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4508                } else {
4509                        struct sk_buff *skb = tp->Rx_skbuff[entry];
4510                        dma_addr_t addr = le64_to_cpu(desc->addr);
4511                        int pkt_size = (status & 0x00001FFF) - 4;
4512                        struct pci_dev *pdev = tp->pci_dev;
4513
4514                        /*
4515                         * The driver does not support incoming fragmented
4516                         * frames. They are seen as a symptom of over-mtu
4517                         * sized frames.
4518                         */
4519                        if (unlikely(rtl8169_fragmented_frame(status))) {
4520                                dev->stats.rx_dropped++;
4521                                dev->stats.rx_length_errors++;
4522                                rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4523                                continue;
4524                        }
4525
4526                        rtl8169_rx_csum(skb, desc);
4527
4528                        if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
4529                                pci_dma_sync_single_for_device(pdev, addr,
4530                                        pkt_size, PCI_DMA_FROMDEVICE);
4531                                rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4532                        } else {
4533                                pci_unmap_single(pdev, addr, tp->rx_buf_sz,
4534                                                 PCI_DMA_FROMDEVICE);
4535                                tp->Rx_skbuff[entry] = NULL;
4536                        }
4537
4538                        skb_put(skb, pkt_size);
4539                        skb->protocol = eth_type_trans(skb, dev);
4540
4541                        if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4542                                if (likely(polling))
4543                                        netif_receive_skb(skb);
4544                                else
4545                                        netif_rx(skb);
4546                        }
4547
4548                        dev->stats.rx_bytes += pkt_size;
4549                        dev->stats.rx_packets++;
4550                }
4551
4552                /* Work around for AMD plateform. */
4553                if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4554                    (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4555                        desc->opts2 = 0;
4556                        cur_rx++;
4557                }
4558        }
4559
4560        count = cur_rx - tp->cur_rx;
4561        tp->cur_rx = cur_rx;
4562
4563        delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx, GFP_ATOMIC);
4564        if (!delta && count)
4565                netif_info(tp, intr, dev, "no Rx buffer allocated\n");
4566        tp->dirty_rx += delta;
4567
4568        /*
4569         * FIXME: until there is periodic timer to try and refill the ring,
4570         * a temporary shortage may definitely kill the Rx process.
4571         * - disable the asic to try and avoid an overflow and kick it again
4572         *   after refill ?
4573         * - how do others driver handle this condition (Uh oh...).
4574         */
4575        if (tp->dirty_rx + NUM_RX_DESC == tp->cur_rx)
4576                netif_emerg(tp, intr, dev, "Rx buffers exhausted\n");
4577
4578        return count;
4579}
4580
4581static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4582{
4583        struct net_device *dev = dev_instance;
4584        struct rtl8169_private *tp = netdev_priv(dev);
4585        void __iomem *ioaddr = tp->mmio_addr;
4586        int handled = 0;
4587        int status;
4588
4589        /* loop handling interrupts until we have no new ones or
4590         * we hit a invalid/hotplug case.
4591         */
4592        status = RTL_R16(IntrStatus);
4593        while (status && status != 0xffff) {
4594                handled = 1;
4595
4596                /* Handle all of the error cases first. These will reset
4597                 * the chip, so just exit the loop.
4598                 */
4599                if (unlikely(!netif_running(dev))) {
4600                        rtl8169_asic_down(ioaddr);
4601                        break;
4602                }
4603
4604                /* Work around for rx fifo overflow */
4605                if (unlikely(status & RxFIFOOver) &&
4606                    (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4607                     tp->mac_version == RTL_GIGA_MAC_VER_22)) {
4608                        netif_stop_queue(dev);
4609                        rtl8169_tx_timeout(dev);
4610                        break;
4611                }
4612
4613                if (unlikely(status & SYSErr)) {
4614                        rtl8169_pcierr_interrupt(dev);
4615                        break;
4616                }
4617
4618                if (status & LinkChg)
4619                        rtl8169_check_link_status(dev, tp, ioaddr);
4620
4621                /* We need to see the lastest version of tp->intr_mask to
4622                 * avoid ignoring an MSI interrupt and having to wait for
4623                 * another event which may never come.
4624                 */
4625                smp_rmb();
4626                if (status & tp->intr_mask & tp->napi_event) {
4627                        RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4628                        tp->intr_mask = ~tp->napi_event;
4629
4630                        if (likely(napi_schedule_prep(&tp->napi)))
4631                                __napi_schedule(&tp->napi);
4632                        else
4633                                netif_info(tp, intr, dev,
4634                                           "interrupt %04x in poll\n", status);
4635                }
4636
4637                /* We only get a new MSI interrupt when all active irq
4638                 * sources on the chip have been acknowledged. So, ack
4639                 * everything we've seen and check if new sources have become
4640                 * active to avoid blocking all interrupts from the chip.
4641                 */
4642                RTL_W16(IntrStatus,
4643                        (status & RxFIFOOver) ? (status | RxOverflow) : status);
4644                status = RTL_R16(IntrStatus);
4645        }
4646
4647        return IRQ_RETVAL(handled);
4648}
4649
4650static int rtl8169_poll(struct napi_struct *napi, int budget)
4651{
4652        struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4653        struct net_device *dev = tp->dev;
4654        void __iomem *ioaddr = tp->mmio_addr;
4655        int work_done;
4656
4657        work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4658        rtl8169_tx_interrupt(dev, tp, ioaddr);
4659
4660        if (work_done < budget) {
4661                napi_complete(napi);
4662
4663                /* We need for force the visibility of tp->intr_mask
4664                 * for other CPUs, as we can loose an MSI interrupt
4665                 * and potentially wait for a retransmit timeout if we don't.
4666                 * The posted write to IntrMask is safe, as it will
4667                 * eventually make it to the chip and we won't loose anything
4668                 * until it does.
4669                 */
4670                tp->intr_mask = 0xffff;
4671                wmb();
4672                RTL_W16(IntrMask, tp->intr_event);
4673        }
4674
4675        return work_done;
4676}
4677
4678static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4679{
4680        struct rtl8169_private *tp = netdev_priv(dev);
4681
4682        if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4683                return;
4684
4685        dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4686        RTL_W32(RxMissed, 0);
4687}
4688
4689static void rtl8169_down(struct net_device *dev)
4690{
4691        struct rtl8169_private *tp = netdev_priv(dev);
4692        void __iomem *ioaddr = tp->mmio_addr;
4693        unsigned int intrmask;
4694
4695        rtl8169_delete_timer(dev);
4696
4697        netif_stop_queue(dev);
4698
4699        napi_disable(&tp->napi);
4700
4701core_down:
4702        spin_lock_irq(&tp->lock);
4703
4704        rtl8169_asic_down(ioaddr);
4705
4706        rtl8169_rx_missed(dev, ioaddr);
4707
4708        spin_unlock_irq(&tp->lock);
4709
4710        synchronize_irq(dev->irq);
4711
4712        /* Give a racing hard_start_xmit a few cycles to complete. */
4713        synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
4714
4715        /*
4716         * And now for the 50k$ question: are IRQ disabled or not ?
4717         *
4718         * Two paths lead here:
4719         * 1) dev->close
4720         *    -> netif_running() is available to sync the current code and the
4721         *       IRQ handler. See rtl8169_interrupt for details.
4722         * 2) dev->change_mtu
4723         *    -> rtl8169_poll can not be issued again and re-enable the
4724         *       interruptions. Let's simply issue the IRQ down sequence again.
4725         *
4726         * No loop if hotpluged or major error (0xffff).
4727         */
4728        intrmask = RTL_R16(IntrMask);
4729        if (intrmask && (intrmask != 0xffff))
4730                goto core_down;
4731
4732        rtl8169_tx_clear(tp);
4733
4734        rtl8169_rx_clear(tp);
4735}
4736
4737static int rtl8169_close(struct net_device *dev)
4738{
4739        struct rtl8169_private *tp = netdev_priv(dev);
4740        struct pci_dev *pdev = tp->pci_dev;
4741
4742        /* update counters before going down */
4743        rtl8169_update_counters(dev);
4744
4745        rtl8169_down(dev);
4746
4747        free_irq(dev->irq, dev);
4748
4749        pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
4750                            tp->RxPhyAddr);
4751        pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
4752                            tp->TxPhyAddr);
4753        tp->TxDescArray = NULL;
4754        tp->RxDescArray = NULL;
4755
4756        return 0;
4757}
4758
4759static void rtl_set_rx_mode(struct net_device *dev)
4760{
4761        struct rtl8169_private *tp = netdev_priv(dev);
4762        void __iomem *ioaddr = tp->mmio_addr;
4763        unsigned long flags;
4764        u32 mc_filter[2];       /* Multicast hash filter */
4765        int rx_mode;
4766        u32 tmp = 0;
4767
4768        if (dev->flags & IFF_PROMISC) {
4769                /* Unconditionally log net taps. */
4770                netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4771                rx_mode =
4772                    AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4773                    AcceptAllPhys;
4774                mc_filter[1] = mc_filter[0] = 0xffffffff;
4775        } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4776                   (dev->flags & IFF_ALLMULTI)) {
4777                /* Too many to filter perfectly -- accept all multicasts. */
4778                rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4779                mc_filter[1] = mc_filter[0] = 0xffffffff;
4780        } else {
4781                struct dev_mc_list *mclist;
4782
4783                rx_mode = AcceptBroadcast | AcceptMyPhys;
4784                mc_filter[1] = mc_filter[0] = 0;
4785                netdev_for_each_mc_addr(mclist, dev) {
4786                        int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
4787                        mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4788                        rx_mode |= AcceptMulticast;
4789                }
4790        }
4791
4792        spin_lock_irqsave(&tp->lock, flags);
4793
4794        tmp = rtl8169_rx_config | rx_mode |
4795              (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4796
4797        if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4798                u32 data = mc_filter[0];
4799
4800                mc_filter[0] = swab32(mc_filter[1]);
4801                mc_filter[1] = swab32(data);
4802        }
4803
4804        RTL_W32(MAR0 + 4, mc_filter[1]);
4805        RTL_W32(MAR0 + 0, mc_filter[0]);
4806
4807        RTL_W32(RxConfig, tmp);
4808
4809        spin_unlock_irqrestore(&tp->lock, flags);
4810}
4811
4812/**
4813 *  rtl8169_get_stats - Get rtl8169 read/write statistics
4814 *  @dev: The Ethernet Device to get statistics for
4815 *
4816 *  Get TX/RX statistics for rtl8169
4817 */
4818static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4819{
4820        struct rtl8169_private *tp = netdev_priv(dev);
4821        void __iomem *ioaddr = tp->mmio_addr;
4822        unsigned long flags;
4823
4824        if (netif_running(dev)) {
4825                spin_lock_irqsave(&tp->lock, flags);
4826                rtl8169_rx_missed(dev, ioaddr);
4827                spin_unlock_irqrestore(&tp->lock, flags);
4828        }
4829
4830        return &dev->stats;
4831}
4832
4833static void rtl8169_net_suspend(struct net_device *dev)
4834{
4835        if (!netif_running(dev))
4836                return;
4837
4838        netif_device_detach(dev);
4839        netif_stop_queue(dev);
4840}
4841
4842#ifdef CONFIG_PM
4843
4844static int rtl8169_suspend(struct device *device)
4845{
4846        struct pci_dev *pdev = to_pci_dev(device);
4847        struct net_device *dev = pci_get_drvdata(pdev);
4848
4849        rtl8169_net_suspend(dev);
4850
4851        return 0;
4852}
4853
4854static int rtl8169_resume(struct device *device)
4855{
4856        struct pci_dev *pdev = to_pci_dev(device);
4857        struct net_device *dev = pci_get_drvdata(pdev);
4858
4859        if (!netif_running(dev))
4860                goto out;
4861
4862        netif_device_attach(dev);
4863
4864        rtl8169_schedule_work(dev, rtl8169_reset_task);
4865out:
4866        return 0;
4867}
4868
4869static const struct dev_pm_ops rtl8169_pm_ops = {
4870        .suspend = rtl8169_suspend,
4871        .resume = rtl8169_resume,
4872        .freeze = rtl8169_suspend,
4873        .thaw = rtl8169_resume,
4874        .poweroff = rtl8169_suspend,
4875        .restore = rtl8169_resume,
4876};
4877
4878#define RTL8169_PM_OPS  (&rtl8169_pm_ops)
4879
4880#else /* !CONFIG_PM */
4881
4882#define RTL8169_PM_OPS  NULL
4883
4884#endif /* !CONFIG_PM */
4885
4886static void rtl_shutdown(struct pci_dev *pdev)
4887{
4888        struct net_device *dev = pci_get_drvdata(pdev);
4889        struct rtl8169_private *tp = netdev_priv(dev);
4890        void __iomem *ioaddr = tp->mmio_addr;
4891
4892        rtl8169_net_suspend(dev);
4893
4894        /* restore original MAC address */
4895        rtl_rar_set(tp, dev->perm_addr);
4896
4897        spin_lock_irq(&tp->lock);
4898
4899        rtl8169_asic_down(ioaddr);
4900
4901        spin_unlock_irq(&tp->lock);
4902
4903        if (system_state == SYSTEM_POWER_OFF) {
4904                /* WoL fails with some 8168 when the receiver is disabled. */
4905                if (tp->features & RTL_FEATURE_WOL) {
4906                        pci_clear_master(pdev);
4907
4908                        RTL_W8(ChipCmd, CmdRxEnb);
4909                        /* PCI commit */
4910                        RTL_R8(ChipCmd);
4911                }
4912
4913                pci_wake_from_d3(pdev, true);
4914                pci_set_power_state(pdev, PCI_D3hot);
4915        }
4916}
4917
4918static struct pci_driver rtl8169_pci_driver = {
4919        .name           = MODULENAME,
4920        .id_table       = rtl8169_pci_tbl,
4921        .probe          = rtl8169_init_one,
4922        .remove         = __devexit_p(rtl8169_remove_one),
4923        .shutdown       = rtl_shutdown,
4924        .driver.pm      = RTL8169_PM_OPS,
4925};
4926
4927static int __init rtl8169_init_module(void)
4928{
4929        return pci_register_driver(&rtl8169_pci_driver);
4930}
4931
4932static void __exit rtl8169_cleanup_module(void)
4933{
4934        pci_unregister_driver(&rtl8169_pci_driver);
4935}
4936
4937module_init(rtl8169_init_module);
4938module_exit(rtl8169_cleanup_module);
4939