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30#ifndef __iwl_helpers_h__
31#define __iwl_helpers_h__
32
33#include <linux/ctype.h>
34
35#define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
36
37
38static inline struct ieee80211_conf *ieee80211_get_hw_conf(
39 struct ieee80211_hw *hw)
40{
41 return &hw->conf;
42}
43
44static inline int iwl_check_bits(unsigned long field, unsigned long mask)
45{
46 return ((field & mask) == mask) ? 1 : 0;
47}
48
49static inline unsigned long elapsed_jiffies(unsigned long start,
50 unsigned long end)
51{
52 if (end >= start)
53 return end - start;
54
55 return end + (MAX_JIFFY_OFFSET - start) + 1;
56}
57
58
59
60
61
62
63static inline int iwl_queue_inc_wrap(int index, int n_bd)
64{
65 return ++index & (n_bd - 1);
66}
67
68
69
70
71
72
73static inline int iwl_queue_dec_wrap(int index, int n_bd)
74{
75 return --index & (n_bd - 1);
76}
77
78
79static inline void iwl_free_fw_desc(struct pci_dev *pci_dev,
80 struct fw_desc *desc)
81{
82 if (desc->v_addr)
83 dma_free_coherent(&pci_dev->dev, desc->len,
84 desc->v_addr, desc->p_addr);
85 desc->v_addr = NULL;
86 desc->len = 0;
87}
88
89static inline int iwl_alloc_fw_desc(struct pci_dev *pci_dev,
90 struct fw_desc *desc)
91{
92 desc->v_addr = dma_alloc_coherent(&pci_dev->dev, desc->len,
93 &desc->p_addr, GFP_KERNEL);
94 return (desc->v_addr != NULL) ? 0 : -ENOMEM;
95}
96
97
98
99
100
101
102
103
104
105
106
107
108static inline u8 iwl_virtual_agg_queue_num(u8 ac, u8 hwq)
109{
110 BUG_ON(ac > 3);
111 BUG_ON(hwq > 31);
112
113 return 0x80 | (hwq << 2) | ac;
114}
115
116static inline void iwl_wake_queue(struct iwl_priv *priv, u8 queue)
117{
118 u8 ac = queue;
119 u8 hwq = queue;
120
121 if (queue & 0x80) {
122 ac = queue & 3;
123 hwq = (queue >> 2) & 0x1f;
124 }
125
126 if (test_and_clear_bit(hwq, priv->queue_stopped))
127 if (atomic_dec_return(&priv->queue_stop_count[ac]) <= 0)
128 ieee80211_wake_queue(priv->hw, ac);
129}
130
131static inline void iwl_stop_queue(struct iwl_priv *priv, u8 queue)
132{
133 u8 ac = queue;
134 u8 hwq = queue;
135
136 if (queue & 0x80) {
137 ac = queue & 3;
138 hwq = (queue >> 2) & 0x1f;
139 }
140
141 if (!test_and_set_bit(hwq, priv->queue_stopped))
142 if (atomic_inc_return(&priv->queue_stop_count[ac]) > 0)
143 ieee80211_stop_queue(priv->hw, ac);
144}
145
146#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
147#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
148
149static inline void iwl_disable_interrupts(struct iwl_priv *priv)
150{
151 clear_bit(STATUS_INT_ENABLED, &priv->status);
152
153
154 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
155
156
157
158 iwl_write32(priv, CSR_INT, 0xffffffff);
159 iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
160 IWL_DEBUG_ISR(priv, "Disabled interrupts\n");
161}
162
163static inline void iwl_enable_interrupts(struct iwl_priv *priv)
164{
165 IWL_DEBUG_ISR(priv, "Enabling interrupts\n");
166 set_bit(STATUS_INT_ENABLED, &priv->status);
167 iwl_write32(priv, CSR_INT_MASK, priv->inta_mask);
168}
169
170#endif
171