LXR linux/drivers/staging/rtl8192su/r819xU

   1#ifndef R819XUSB_CMDPKT_H
   2#define R819XUSB_CMDPKT_H
   3/* Different command packet have dedicated message length and definition. */
   4#define         CMPK_RX_TX_FB_SIZE                                      sizeof(cmpk_txfb_t)             //20
   5#define         CMPK_TX_SET_CONFIG_SIZE                         sizeof(cmpk_set_cfg_t)  //16
   6#define         CMPK_BOTH_QUERY_CONFIG_SIZE                     sizeof(cmpk_set_cfg_t)  //16
   7#define         CMPK_RX_TX_STS_SIZE                                     sizeof(cmpk_tx_status_t)//
   8#define         CMPK_RX_DBG_MSG_SIZE                    sizeof(cmpk_rx_dbginfo_t)//
   9#define         CMPK_TX_RAHIS_SIZE                      sizeof(cmpk_tx_rahis_t)
  10
  11/* 2008/05/08 amy For USB constant. */
  12#define ISR_TxBcnOk                                     BIT27                   // Transmit Beacon OK
  13#define ISR_TxBcnErr                            BIT26                   // Transmit Beacon Error
  14#define ISR_BcnTimerIntr                        BIT13                   // Beacon Timer Interrupt
  15
  16/* Define element ID of command packet. */
  17
  18/*------------------------------Define structure----------------------------*/
  19/* Define different command packet structure. */
  20/* 1. RX side: TX feedback packet. */
  21typedef struct tag_cmd_pkt_tx_feedback
  22{
  23        // DWORD 0
  24        u8      element_id;                     /* Command packet type. */
  25        u8      length;                         /* Command packet length. */
  26        /* 2007/07/05 MH Change tx feedback info field. */
  27        /*------TX Feedback Info Field */
  28        u8      TID:4;                          /* */
  29        u8      fail_reason:3;          /* */
  30        u8      tok:1;                          /* Transmit ok. */
  31        u8      reserve1:4;                     /* */
  32        u8      pkt_type:2;             /* */
  33        u8      bandwidth:1;            /* */
  34        u8      qos_pkt:1;                      /* */
  35
  36        // DWORD 1
  37        u8      reserve2;                       /* */
  38        /*------TX Feedback Info Field */
  39        u8      retry_cnt;                      /* */
  40        u16     pkt_id;                         /* */
  41
  42        // DWORD 3
  43        u16     seq_num;                        /* */
  44        u8      s_rate;                         /* Start rate. */
  45        u8      f_rate;                         /* Final rate. */
  46
  47        // DWORD 4
  48        u8      s_rts_rate;                     /* */
  49        u8      f_rts_rate;                     /* */
  50        u16     pkt_length;                     /* */
  51
  52        // DWORD 5
  53        u16     reserve3;                       /* */
  54        u16     duration;                       /* */
  55}cmpk_txfb_t;
  56
  57/* 2. RX side: Interrupt status packet. It includes Beacon State,
  58          Beacon Timer Interrupt and other useful informations in MAC ISR Reg. */
  59typedef struct tag_cmd_pkt_interrupt_status
  60{
  61        u8      element_id;                     /* Command packet type. */
  62        u8      length;                         /* Command packet length. */
  63        u16     reserve;
  64        u32     interrupt_status;                               /* Interrupt Status. */
  65}cmpk_intr_sta_t;
  66
  67
  68/* 3. TX side: Set configuration packet. */
  69typedef struct tag_cmd_pkt_set_configuration
  70{
  71        u8      element_id;                     /* Command packet type. */
  72        u8      length;                         /* Command packet length. */
  73        u16     reserve1;                       /* */
  74        u8      cfg_reserve1:3;
  75        u8      cfg_size:2;                     /* Configuration info. */
  76        u8      cfg_type:2;                     /* Configuration info. */
  77        u8      cfg_action:1;           /* Configuration info. */
  78        u8      cfg_reserve2;           /* Configuration info. */
  79        u8      cfg_page:4;                     /* Configuration info. */
  80        u8      cfg_reserve3:4;         /* Configuration info. */
  81        u8      cfg_offset;                     /* Configuration info. */
  82        u32     value;                          /* */
  83        u32     mask;                           /* */
  84}cmpk_set_cfg_t;
  85
  86/* 4. Both side : TX/RX query configuraton packet. The query structure is the
  87      same as set configuration. */
  88#define         cmpk_query_cfg_t        cmpk_set_cfg_t
  89
  90/* 5. Multi packet feedback status. */
  91typedef struct tag_tx_stats_feedback // PJ quick rxcmd 09042007
  92{
  93        // For endian transfer --> Driver will not the same as firmware structure.
  94        // DW 0
  95        u16     reserve1;
  96        u8      length;                         // Command packet length
  97        u8      element_id;                     // Command packet type
  98
  99        // DW 1
 100        u16     txfail;                         // Tx Fail count
 101        u16     txok;                           // Tx ok count
 102
 103        // DW 2
 104        u16     txmcok;                         // tx multicast
 105        u16     txretry;                        // Tx Retry count
 106
 107        // DW 3
 108        u16  txucok;                            // tx unicast
 109        u16     txbcok;                         // tx broadcast
 110
 111        // DW 4
 112        u16     txbcfail;                       //
 113        u16     txmcfail;                       //
 114
 115        // DW 5
 116        u16     reserve2;                       //
 117        u16     txucfail;                       //
 118
 119        // DW 6-8
 120        u32     txmclength;
 121        u32     txbclength;
 122        u32     txuclength;
 123
 124        // DW 9
 125        u16     reserve3_23;
 126        u8      reserve3_1;
 127        u8      rate;
 128}__attribute__((packed)) cmpk_tx_status_t;
 129
 130/* 6. Debug feedback message. */
 131/* 2007/10/23 MH Define RX debug message  */
 132typedef struct tag_rx_debug_message_feedback
 133{
 134        // For endian transfer --> for driver
 135        // DW 0
 136        u16     reserve1;
 137        u8      length;                         // Command packet length
 138        u8      element_id;                     // Command packet type
 139
 140        // DW 1-??
 141        // Variable debug message.
 142
 143}cmpk_rx_dbginfo_t;
 144
 145/* 2008/03/20 MH Define transmit rate history. For big endian format. */
 146typedef struct tag_tx_rate_history
 147{
 148        // For endian transfer --> for driver
 149        // DW 0
 150        u8      element_id;                     // Command packet type
 151        u8      length;                         // Command packet length
 152        u16     reserved1;
 153
 154        // DW 1-2       CCK rate counter
 155        u16     cck[4];
 156
 157        // DW 3-6
 158        u16     ofdm[8];
 159
 160        // DW 7-14
 161        //UINT16        MCS_BW0_SG0[16];
 162
 163        // DW 15-22
 164        //UINT16        MCS_BW1_SG0[16];
 165
 166        // DW 23-30
 167        //UINT16        MCS_BW0_SG1[16];
 168
 169        // DW 31-38
 170        //UINT16        MCS_BW1_SG1[16];
 171
 172        // DW 7-14      BW=0 SG=0
 173        // DW 15-22     BW=1 SG=0
 174        // DW 23-30     BW=0 SG=1
 175        // DW 31-38     BW=1 SG=1
 176        u16     ht_mcs[4][16];
 177
 178}__attribute__((packed)) cmpk_tx_rahis_t;
 179
 180typedef enum tag_command_packet_directories
 181{
 182    RX_TX_FEEDBACK = 0,
 183    RX_INTERRUPT_STATUS         = 1,
 184    TX_SET_CONFIG                               = 2,
 185    BOTH_QUERY_CONFIG                   = 3,
 186    RX_TX_STATUS                                = 4,
 187    RX_DBGINFO_FEEDBACK         = 5,
 188    RX_TX_PER_PKT_FEEDBACK              = 6,
 189    RX_TX_RATE_HISTORY          = 7,
 190    RX_CMD_ELE_MAX
 191}cmpk_element_e;
 192
 193extern bool cmpk_message_handle_tx(struct net_device *dev, u8* codevirtualaddress, u32 packettype, u32 buffer_len);
 194
 195extern  u32 cmpk_message_handle_rx(struct net_device *dev, struct ieee80211_rx_stats * pstats);
 196extern bool SendTxCommandPacket( struct net_device *dev, void* pData, u32 DataLen);
 197
 198
 199#endif
 200