1/* 2 * Agere Systems Inc. 3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs 4 * 5 * Copyright © 2005 Agere Systems Inc. 6 * All rights reserved. 7 * http://www.agere.com 8 * 9 *------------------------------------------------------------------------------ 10 * 11 * et1310_rx.h - Defines, structs, enums, prototypes, etc. pertaining to data 12 * reception. 13 * 14 *------------------------------------------------------------------------------ 15 * 16 * SOFTWARE LICENSE 17 * 18 * This software is provided subject to the following terms and conditions, 19 * which you should read carefully before using the software. Using this 20 * software indicates your acceptance of these terms and conditions. If you do 21 * not agree with these terms and conditions, do not use the software. 22 * 23 * Copyright © 2005 Agere Systems Inc. 24 * All rights reserved. 25 * 26 * Redistribution and use in source or binary forms, with or without 27 * modifications, are permitted provided that the following conditions are met: 28 * 29 * . Redistributions of source code must retain the above copyright notice, this 30 * list of conditions and the following Disclaimer as comments in the code as 31 * well as in the documentation and/or other materials provided with the 32 * distribution. 33 * 34 * . Redistributions in binary form must reproduce the above copyright notice, 35 * this list of conditions and the following Disclaimer in the documentation 36 * and/or other materials provided with the distribution. 37 * 38 * . Neither the name of Agere Systems Inc. nor the names of the contributors 39 * may be used to endorse or promote products derived from this software 40 * without specific prior written permission. 41 * 42 * Disclaimer 43 * 44 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 45 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY 47 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN 48 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY 49 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 50 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 51 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 52 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 54 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 55 * DAMAGE. 56 * 57 */ 58 59#ifndef __ET1310_RX_H__ 60#define __ET1310_RX_H__ 61 62#include "et1310_address_map.h" 63 64#define USE_FBR0 true 65 66#ifdef USE_FBR0 67/* #define FBR0_BUFFER_SIZE 256 */ 68#endif 69 70/* #define FBR1_BUFFER_SIZE 2048 */ 71 72#define FBR_CHUNKS 32 73 74#define MAX_DESC_PER_RING_RX 1024 75 76/* number of RFDs - default and min */ 77#ifdef USE_FBR0 78#define RFD_LOW_WATER_MARK 40 79#define NIC_MIN_NUM_RFD 64 80#define NIC_DEFAULT_NUM_RFD 1024 81#else 82#define RFD_LOW_WATER_MARK 20 83#define NIC_MIN_NUM_RFD 64 84#define NIC_DEFAULT_NUM_RFD 256 85#endif 86 87#define NUM_PACKETS_HANDLED 256 88 89#define ALCATEL_BAD_STATUS 0xe47f0000 90#define ALCATEL_MULTICAST_PKT 0x01000000 91#define ALCATEL_BROADCAST_PKT 0x02000000 92 93/* typedefs for Free Buffer Descriptors */ 94typedef union _FBR_WORD2_t { 95 u32 value; 96 struct { 97#ifdef _BIT_FIELDS_HTOL 98 u32 reserved:22; /* bits 10-31 */ 99 u32 bi:10; /* bits 0-9(Buffer Index) */ 100#else 101 u32 bi:10; /* bits 0-9(Buffer Index) */ 102 u32 reserved:22; /* bit 10-31 */ 103#endif 104 } bits; 105} FBR_WORD2_t, *PFBR_WORD2_t; 106 107typedef struct _FBR_DESC_t { 108 u32 addr_lo; 109 u32 addr_hi; 110 FBR_WORD2_t word2; 111} FBR_DESC_t, *PFBR_DESC_t; 112 113/* Typedefs for Packet Status Ring Descriptors */ 114typedef union _PKT_STAT_DESC_WORD0_t { 115 u32 value; 116 struct { 117#ifdef _BIT_FIELDS_HTOL 118 /* top 16 bits are from the Alcatel Status Word as enumerated in */ 119 /* PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2) */ 120#if 0 121 u32 asw_trunc:1; /* bit 31(Rx frame truncated) */ 122#endif 123 u32 asw_long_evt:1; /* bit 31(Rx long event) */ 124 u32 asw_VLAN_tag:1; /* bit 30(VLAN tag detected) */ 125 u32 asw_unsupported_op:1; /* bit 29(unsupported OP code) */ 126 u32 asw_pause_frame:1; /* bit 28(is a pause frame) */ 127 u32 asw_control_frame:1; /* bit 27(is a control frame) */ 128 u32 asw_dribble_nibble:1; /* bit 26(spurious bits after EOP) */ 129 u32 asw_broadcast:1; /* bit 25(has a broadcast address) */ 130 u32 asw_multicast:1; /* bit 24(has a multicast address) */ 131 u32 asw_OK:1; /* bit 23(valid CRC + no code error) */ 132 u32 asw_too_long:1; /* bit 22(frame length > 1518 bytes) */ 133 u32 asw_len_chk_err:1; /* bit 21(frame length field incorrect) */ 134 u32 asw_CRC_err:1; /* bit 20(CRC error) */ 135 u32 asw_code_err:1; /* bit 19(one or more nibbles signalled as errors) */ 136 u32 asw_false_carrier_event:1; /* bit 18(bad carrier since last good packet) */ 137 u32 asw_RX_DV_event:1; /* bit 17(short receive event detected) */ 138 u32 asw_prev_pkt_dropped:1;/* bit 16(e.g. IFG too small on previous) */ 139 u32 unused:5; /* bits 11-15 */ 140 u32 vp:1; /* bit 10(VLAN Packet) */ 141 u32 jp:1; /* bit 9(Jumbo Packet) */ 142 u32 ft:1; /* bit 8(Frame Truncated) */ 143 u32 drop:1; /* bit 7(Drop packet) */ 144 u32 rxmac_error:1; /* bit 6(RXMAC Error Indicator) */ 145 u32 wol:1; /* bit 5(WOL Event) */ 146 u32 tcpp:1; /* bit 4(TCP checksum pass) */ 147 u32 tcpa:1; /* bit 3(TCP checksum assist) */ 148 u32 ipp:1; /* bit 2(IP checksum pass) */ 149 u32 ipa:1; /* bit 1(IP checksum assist) */ 150 u32 hp:1; /* bit 0(hash pass) */ 151#else 152 u32 hp:1; /* bit 0(hash pass) */ 153 u32 ipa:1; /* bit 1(IP checksum assist) */ 154 u32 ipp:1; /* bit 2(IP checksum pass) */ 155 u32 tcpa:1; /* bit 3(TCP checksum assist) */ 156 u32 tcpp:1; /* bit 4(TCP checksum pass) */ 157 u32 wol:1; /* bit 5(WOL Event) */ 158 u32 rxmac_error:1; /* bit 6(RXMAC Error Indicator) */ 159 u32 drop:1; /* bit 7(Drop packet) */ 160 u32 ft:1; /* bit 8(Frame Truncated) */ 161 u32 jp:1; /* bit 9(Jumbo Packet) */ 162 u32 vp:1; /* bit 10(VLAN Packet) */ 163 u32 unused:5; /* bits 11-15 */ 164 u32 asw_prev_pkt_dropped:1;/* bit 16(e.g. IFG too small on previous) */ 165 u32 asw_RX_DV_event:1; /* bit 17(short receive event detected) */ 166 u32 asw_false_carrier_event:1; /* bit 18(bad carrier since last good packet) */ 167 u32 asw_code_err:1; /* bit 19(one or more nibbles signalled as errors) */ 168 u32 asw_CRC_err:1; /* bit 20(CRC error) */ 169 u32 asw_len_chk_err:1; /* bit 21(frame length field incorrect) */ 170 u32 asw_too_long:1; /* bit 22(frame length > 1518 bytes) */ 171 u32 asw_OK:1; /* bit 23(valid CRC + no code error) */ 172 u32 asw_multicast:1; /* bit 24(has a multicast address) */ 173 u32 asw_broadcast:1; /* bit 25(has a broadcast address) */ 174 u32 asw_dribble_nibble:1; /* bit 26(spurious bits after EOP) */ 175 u32 asw_control_frame:1; /* bit 27(is a control frame) */ 176 u32 asw_pause_frame:1; /* bit 28(is a pause frame) */ 177 u32 asw_unsupported_op:1; /* bit 29(unsupported OP code) */ 178 u32 asw_VLAN_tag:1; /* bit 30(VLAN tag detected) */ 179 u32 asw_long_evt:1; /* bit 31(Rx long event) */ 180#if 0 181 u32 asw_trunc:1; /* bit 31(Rx frame truncated) */ 182#endif 183#endif 184 } bits; 185} PKT_STAT_DESC_WORD0_t, *PPKT_STAT_WORD0_t; 186 187typedef union _PKT_STAT_DESC_WORD1_t { 188 u32 value; 189 struct { 190#ifdef _BIT_FIELDS_HTOL 191 u32 unused:4; /* bits 28-31 */ 192 u32 ri:2; /* bits 26-27(Ring Index) */ 193 u32 bi:10; /* bits 16-25(Buffer Index) */ 194 u32 length:16; /* bit 0-15(length in bytes) */ 195#else 196 u32 length:16; /* bit 0-15(length in bytes) */ 197 u32 bi:10; /* bits 16-25(Buffer Index) */ 198 u32 ri:2; /* bits 26-27(Ring Index) */ 199 u32 unused:4; /* bits 28-31 */ 200#endif 201 } bits; 202} PKT_STAT_DESC_WORD1_t, *PPKT_STAT_WORD1_t; 203 204typedef struct _PKT_STAT_DESC_t { 205 PKT_STAT_DESC_WORD0_t word0; 206 PKT_STAT_DESC_WORD1_t word1; 207} PKT_STAT_DESC_t, *PPKT_STAT_DESC_t; 208 209/* Typedefs for the RX DMA status word */ 210 211/* 212 * rx status word 0 holds part of the status bits of the Rx DMA engine 213 * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word 214 * which contains the Free Buffer ring 0 and 1 available offset. 215 * 216 * bit 0-9 FBR1 offset 217 * bit 10 Wrap flag for FBR1 218 * bit 16-25 FBR0 offset 219 * bit 26 Wrap flag for FBR0 220 */ 221 222/* 223 * RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine 224 * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word 225 * which contains the Packet Status Ring available offset. 226 */ 227 228#define RXSTAT1_OFFSET 16 229#define RXSTAT1_MASK 0xFFF 230#define RXSTAT1_WRAP 0x10000000 231 232typedef union _rxstat_word1_t { 233 u32 value; 234 struct { 235#ifdef _BIT_FIELDS_HTOL 236 u32 PSRunused:3; /* bits 29-31 */ 237 u32 PSRwrap:1; /* bit 28 */ 238 u32 PSRoffset:12; /* bits 16-27 */ 239 u32 reserved:16; /* bits 0-15 */ 240#else 241 u32 reserved:16; /* bits 0-15 */ 242 u32 PSRoffset:12; /* bits 16-27 */ 243 u32 PSRwrap:1; /* bit 28 */ 244 u32 PSRunused:3; /* bits 29-31 */ 245#endif 246 } bits; 247} RXSTAT_WORD1_t, *PRXSTAT_WORD1_t; 248 249/* 250 * RX_STATUS_BLOCK_t is sructure representing the status of the Rx DMA engine 251 * it sits in free memory, and is pointed to by 0x101c / 0x1020 252 */ 253typedef struct _rx_status_block_t { 254 u32 Word0; 255 RXSTAT_WORD1_t Word1; 256} RX_STATUS_BLOCK_t, *PRX_STATUS_BLOCK_t; 257 258/* 259 * Structure for look-up table holding free buffer ring pointers 260 */ 261typedef struct _FbrLookupTable { 262 void *Va[MAX_DESC_PER_RING_RX]; 263 void *Buffer1[MAX_DESC_PER_RING_RX]; 264 void *Buffer2[MAX_DESC_PER_RING_RX]; 265 u32 PAHigh[MAX_DESC_PER_RING_RX]; 266 u32 PALow[MAX_DESC_PER_RING_RX]; 267} FBRLOOKUPTABLE, *PFBRLOOKUPTABLE; 268 269typedef enum { 270 ONE_PACKET_INTERRUPT, 271 FOUR_PACKET_INTERRUPT 272} eRX_INTERRUPT_STATE_t, *PeRX_INTERRUPT_STATE_t; 273 274/* 275 * RX_RING_t is sructure representing the adaptor's local reference(s) to the 276 * rings 277 */ 278typedef struct _rx_ring_t { 279#ifdef USE_FBR0 280 void *pFbr0RingVa; 281 dma_addr_t pFbr0RingPa; 282 void *Fbr0MemVa[MAX_DESC_PER_RING_RX / FBR_CHUNKS]; 283 dma_addr_t Fbr0MemPa[MAX_DESC_PER_RING_RX / FBR_CHUNKS]; 284 uint64_t Fbr0Realpa; 285 uint64_t Fbr0offset; 286 u32 local_Fbr0_full; 287 u32 Fbr0NumEntries; 288 u32 Fbr0BufferSize; 289#endif 290 void *pFbr1RingVa; 291 dma_addr_t pFbr1RingPa; 292 void *Fbr1MemVa[MAX_DESC_PER_RING_RX / FBR_CHUNKS]; 293 dma_addr_t Fbr1MemPa[MAX_DESC_PER_RING_RX / FBR_CHUNKS]; 294 uint64_t Fbr1Realpa; 295 uint64_t Fbr1offset; 296 FBRLOOKUPTABLE *Fbr[2]; 297 u32 local_Fbr1_full; 298 u32 Fbr1NumEntries; 299 u32 Fbr1BufferSize; 300 301 void *pPSRingVa; 302 dma_addr_t pPSRingPa; 303 u32 local_psr_full; 304 u32 PsrNumEntries; 305 306 void *pRxStatusVa; 307 dma_addr_t pRxStatusPa; 308 309 struct list_head RecvBufferPool; 310 311 /* RECV */ 312 struct list_head RecvList; 313 u32 nReadyRecv; 314 315 u32 NumRfd; 316 317 bool UnfinishedReceives; 318 319 struct list_head RecvPacketPool; 320 321 /* lookaside lists */ 322 struct kmem_cache *RecvLookaside; 323} RX_RING_t, *PRX_RING_t; 324 325/* Forward reference of RFD */ 326struct _MP_RFD; 327 328/* Forward declaration of the private adapter structure */ 329struct et131x_adapter; 330 331/* PROTOTYPES for Initialization */ 332int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter); 333void et131x_rx_dma_memory_free(struct et131x_adapter *adapter); 334int et131x_rfd_resources_alloc(struct et131x_adapter *adapter, 335 struct _MP_RFD *pMpRfd); 336void et131x_rfd_resources_free(struct et131x_adapter *adapter, 337 struct _MP_RFD *pMpRfd); 338int et131x_init_recv(struct et131x_adapter *adapter); 339 340void ConfigRxDmaRegs(struct et131x_adapter *adapter); 341void SetRxDmaTimer(struct et131x_adapter *adapter); 342void et131x_rx_dma_disable(struct et131x_adapter *adapter); 343void et131x_rx_dma_enable(struct et131x_adapter *adapter); 344 345void et131x_reset_recv(struct et131x_adapter *adapter); 346 347void et131x_handle_recv_interrupt(struct et131x_adapter *adapter); 348 349#endif /* __ET1310_RX_H__ */ 350