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61#include <linux/can.h>
62#include <linux/can/core.h>
63#include <linux/can/dev.h>
64#include <linux/can/platform/mcp251x.h>
65#include <linux/completion.h>
66#include <linux/delay.h>
67#include <linux/device.h>
68#include <linux/dma-mapping.h>
69#include <linux/freezer.h>
70#include <linux/interrupt.h>
71#include <linux/io.h>
72#include <linux/kernel.h>
73#include <linux/module.h>
74#include <linux/netdevice.h>
75#include <linux/platform_device.h>
76#include <linux/spi/spi.h>
77#include <linux/uaccess.h>
78
79
80#define INSTRUCTION_WRITE 0x02
81#define INSTRUCTION_READ 0x03
82#define INSTRUCTION_BIT_MODIFY 0x05
83#define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
84#define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
85#define INSTRUCTION_RESET 0xC0
86
87
88#define CANSTAT 0x0e
89#define CANCTRL 0x0f
90# define CANCTRL_REQOP_MASK 0xe0
91# define CANCTRL_REQOP_CONF 0x80
92# define CANCTRL_REQOP_LISTEN_ONLY 0x60
93# define CANCTRL_REQOP_LOOPBACK 0x40
94# define CANCTRL_REQOP_SLEEP 0x20
95# define CANCTRL_REQOP_NORMAL 0x00
96# define CANCTRL_OSM 0x08
97# define CANCTRL_ABAT 0x10
98#define TEC 0x1c
99#define REC 0x1d
100#define CNF1 0x2a
101# define CNF1_SJW_SHIFT 6
102#define CNF2 0x29
103# define CNF2_BTLMODE 0x80
104# define CNF2_SAM 0x40
105# define CNF2_PS1_SHIFT 3
106#define CNF3 0x28
107# define CNF3_SOF 0x08
108# define CNF3_WAKFIL 0x04
109# define CNF3_PHSEG2_MASK 0x07
110#define CANINTE 0x2b
111# define CANINTE_MERRE 0x80
112# define CANINTE_WAKIE 0x40
113# define CANINTE_ERRIE 0x20
114# define CANINTE_TX2IE 0x10
115# define CANINTE_TX1IE 0x08
116# define CANINTE_TX0IE 0x04
117# define CANINTE_RX1IE 0x02
118# define CANINTE_RX0IE 0x01
119#define CANINTF 0x2c
120# define CANINTF_MERRF 0x80
121# define CANINTF_WAKIF 0x40
122# define CANINTF_ERRIF 0x20
123# define CANINTF_TX2IF 0x10
124# define CANINTF_TX1IF 0x08
125# define CANINTF_TX0IF 0x04
126# define CANINTF_RX1IF 0x02
127# define CANINTF_RX0IF 0x01
128#define EFLG 0x2d
129# define EFLG_EWARN 0x01
130# define EFLG_RXWAR 0x02
131# define EFLG_TXWAR 0x04
132# define EFLG_RXEP 0x08
133# define EFLG_TXEP 0x10
134# define EFLG_TXBO 0x20
135# define EFLG_RX0OVR 0x40
136# define EFLG_RX1OVR 0x80
137#define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
138# define TXBCTRL_ABTF 0x40
139# define TXBCTRL_MLOA 0x20
140# define TXBCTRL_TXERR 0x10
141# define TXBCTRL_TXREQ 0x08
142#define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
143# define SIDH_SHIFT 3
144#define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
145# define SIDL_SID_MASK 7
146# define SIDL_SID_SHIFT 5
147# define SIDL_EXIDE_SHIFT 3
148# define SIDL_EID_SHIFT 16
149# define SIDL_EID_MASK 3
150#define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
151#define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
152#define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
153# define DLC_RTR_SHIFT 6
154#define TXBCTRL_OFF 0
155#define TXBSIDH_OFF 1
156#define TXBSIDL_OFF 2
157#define TXBEID8_OFF 3
158#define TXBEID0_OFF 4
159#define TXBDLC_OFF 5
160#define TXBDAT_OFF 6
161#define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
162# define RXBCTRL_BUKT 0x04
163# define RXBCTRL_RXM0 0x20
164# define RXBCTRL_RXM1 0x40
165#define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
166# define RXBSIDH_SHIFT 3
167#define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
168# define RXBSIDL_IDE 0x08
169# define RXBSIDL_EID 3
170# define RXBSIDL_SHIFT 5
171#define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
172#define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
173#define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
174# define RXBDLC_LEN_MASK 0x0f
175# define RXBDLC_RTR 0x40
176#define RXBCTRL_OFF 0
177#define RXBSIDH_OFF 1
178#define RXBSIDL_OFF 2
179#define RXBEID8_OFF 3
180#define RXBEID0_OFF 4
181#define RXBDLC_OFF 5
182#define RXBDAT_OFF 6
183
184#define GET_BYTE(val, byte) \
185 (((val) >> ((byte) * 8)) & 0xff)
186#define SET_BYTE(val, byte) \
187 (((val) & 0xff) << ((byte) * 8))
188
189
190
191
192
193#define CAN_FRAME_MAX_DATA_LEN 8
194#define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
195#define CAN_FRAME_MAX_BITS 128
196
197#define TX_ECHO_SKB_MAX 1
198
199#define DEVICE_NAME "mcp251x"
200
201static int mcp251x_enable_dma;
202module_param(mcp251x_enable_dma, int, S_IRUGO);
203MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)");
204
205static struct can_bittiming_const mcp251x_bittiming_const = {
206 .name = DEVICE_NAME,
207 .tseg1_min = 3,
208 .tseg1_max = 16,
209 .tseg2_min = 2,
210 .tseg2_max = 8,
211 .sjw_max = 4,
212 .brp_min = 1,
213 .brp_max = 64,
214 .brp_inc = 1,
215};
216
217struct mcp251x_priv {
218 struct can_priv can;
219 struct net_device *net;
220 struct spi_device *spi;
221
222 struct mutex spi_lock;
223 u8 *spi_tx_buf;
224 u8 *spi_rx_buf;
225 dma_addr_t spi_tx_dma;
226 dma_addr_t spi_rx_dma;
227
228 struct sk_buff *tx_skb;
229 int tx_len;
230 struct workqueue_struct *wq;
231 struct work_struct tx_work;
232 struct work_struct irq_work;
233 struct completion awake;
234 int wake;
235 int force_quit;
236 int after_suspend;
237#define AFTER_SUSPEND_UP 1
238#define AFTER_SUSPEND_DOWN 2
239#define AFTER_SUSPEND_POWER 4
240#define AFTER_SUSPEND_RESTART 8
241 int restart_tx;
242};
243
244static void mcp251x_clean(struct net_device *net)
245{
246 struct mcp251x_priv *priv = netdev_priv(net);
247
248 net->stats.tx_errors++;
249 if (priv->tx_skb)
250 dev_kfree_skb(priv->tx_skb);
251 if (priv->tx_len)
252 can_free_echo_skb(priv->net, 0);
253 priv->tx_skb = NULL;
254 priv->tx_len = 0;
255}
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270static int mcp251x_spi_trans(struct spi_device *spi, int len)
271{
272 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
273 struct spi_transfer t = {
274 .tx_buf = priv->spi_tx_buf,
275 .rx_buf = priv->spi_rx_buf,
276 .len = len,
277 .cs_change = 0,
278 };
279 struct spi_message m;
280 int ret;
281
282 spi_message_init(&m);
283
284 if (mcp251x_enable_dma) {
285 t.tx_dma = priv->spi_tx_dma;
286 t.rx_dma = priv->spi_rx_dma;
287 m.is_dma_mapped = 1;
288 }
289
290 spi_message_add_tail(&t, &m);
291
292 ret = spi_sync(spi, &m);
293 if (ret)
294 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
295 return ret;
296}
297
298static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg)
299{
300 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
301 u8 val = 0;
302
303 mutex_lock(&priv->spi_lock);
304
305 priv->spi_tx_buf[0] = INSTRUCTION_READ;
306 priv->spi_tx_buf[1] = reg;
307
308 mcp251x_spi_trans(spi, 3);
309 val = priv->spi_rx_buf[2];
310
311 mutex_unlock(&priv->spi_lock);
312
313 return val;
314}
315
316static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val)
317{
318 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
319
320 mutex_lock(&priv->spi_lock);
321
322 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
323 priv->spi_tx_buf[1] = reg;
324 priv->spi_tx_buf[2] = val;
325
326 mcp251x_spi_trans(spi, 3);
327
328 mutex_unlock(&priv->spi_lock);
329}
330
331static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
332 u8 mask, uint8_t val)
333{
334 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
335
336 mutex_lock(&priv->spi_lock);
337
338 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
339 priv->spi_tx_buf[1] = reg;
340 priv->spi_tx_buf[2] = mask;
341 priv->spi_tx_buf[3] = val;
342
343 mcp251x_spi_trans(spi, 4);
344
345 mutex_unlock(&priv->spi_lock);
346}
347
348static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
349 int len, int tx_buf_idx)
350{
351 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
352 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
353
354 if (pdata->model == CAN_MCP251X_MCP2510) {
355 int i;
356
357 for (i = 1; i < TXBDAT_OFF + len; i++)
358 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
359 buf[i]);
360 } else {
361 mutex_lock(&priv->spi_lock);
362 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
363 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
364 mutex_unlock(&priv->spi_lock);
365 }
366}
367
368static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
369 int tx_buf_idx)
370{
371 u32 sid, eid, exide, rtr;
372 u8 buf[SPI_TRANSFER_BUF_LEN];
373
374 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0;
375 if (exide)
376 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
377 else
378 sid = frame->can_id & CAN_SFF_MASK;
379 eid = frame->can_id & CAN_EFF_MASK;
380 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0;
381
382 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
383 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
384 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
385 (exide << SIDL_EXIDE_SHIFT) |
386 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
387 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
388 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
389 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
390 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
391 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
392 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx), TXBCTRL_TXREQ);
393}
394
395static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
396 int buf_idx)
397{
398 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
399 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
400
401 if (pdata->model == CAN_MCP251X_MCP2510) {
402 int i, len;
403
404 for (i = 1; i < RXBDAT_OFF; i++)
405 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
406
407 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
408 for (; i < (RXBDAT_OFF + len); i++)
409 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
410 } else {
411 mutex_lock(&priv->spi_lock);
412
413 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
414 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
415 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
416
417 mutex_unlock(&priv->spi_lock);
418 }
419}
420
421static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
422{
423 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
424 struct sk_buff *skb;
425 struct can_frame *frame;
426 u8 buf[SPI_TRANSFER_BUF_LEN];
427
428 skb = alloc_can_skb(priv->net, &frame);
429 if (!skb) {
430 dev_err(&spi->dev, "cannot allocate RX skb\n");
431 priv->net->stats.rx_dropped++;
432 return;
433 }
434
435 mcp251x_hw_rx_frame(spi, buf, buf_idx);
436 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
437
438 frame->can_id = CAN_EFF_FLAG;
439 frame->can_id |=
440
441 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
442 SET_BYTE(buf[RXBEID8_OFF], 1) |
443 SET_BYTE(buf[RXBEID0_OFF], 0) |
444
445 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
446 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
447
448 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
449 frame->can_id |= CAN_RTR_FLAG;
450 } else {
451
452 frame->can_id =
453 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
454 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
455 }
456
457 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
458 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
459
460 priv->net->stats.rx_packets++;
461 priv->net->stats.rx_bytes += frame->can_dlc;
462 netif_rx(skb);
463}
464
465static void mcp251x_hw_sleep(struct spi_device *spi)
466{
467 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
468}
469
470static void mcp251x_hw_wakeup(struct spi_device *spi)
471{
472 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
473
474 priv->wake = 1;
475
476
477 mcp251x_write_bits(spi, CANINTE, CANINTE_WAKIE, CANINTE_WAKIE);
478 mcp251x_write_bits(spi, CANINTF, CANINTF_WAKIF, CANINTF_WAKIF);
479
480
481 if (!wait_for_completion_timeout(&priv->awake, HZ))
482 dev_err(&spi->dev, "MCP251x didn't wake-up\n");
483}
484
485static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
486 struct net_device *net)
487{
488 struct mcp251x_priv *priv = netdev_priv(net);
489 struct spi_device *spi = priv->spi;
490
491 if (priv->tx_skb || priv->tx_len) {
492 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
493 netif_stop_queue(net);
494 return NETDEV_TX_BUSY;
495 }
496
497 if (skb->len != sizeof(struct can_frame)) {
498 dev_err(&spi->dev, "dropping packet - bad length\n");
499 dev_kfree_skb(skb);
500 net->stats.tx_dropped++;
501 return NETDEV_TX_OK;
502 }
503
504 netif_stop_queue(net);
505 priv->tx_skb = skb;
506 net->trans_start = jiffies;
507 queue_work(priv->wq, &priv->tx_work);
508
509 return NETDEV_TX_OK;
510}
511
512static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
513{
514 struct mcp251x_priv *priv = netdev_priv(net);
515
516 switch (mode) {
517 case CAN_MODE_START:
518
519 priv->can.state = CAN_STATE_ERROR_ACTIVE;
520 priv->restart_tx = 1;
521 if (priv->can.restart_ms == 0)
522 priv->after_suspend = AFTER_SUSPEND_RESTART;
523 queue_work(priv->wq, &priv->irq_work);
524 break;
525 default:
526 return -EOPNOTSUPP;
527 }
528
529 return 0;
530}
531
532static void mcp251x_set_normal_mode(struct spi_device *spi)
533{
534 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
535 unsigned long timeout;
536
537
538 mcp251x_write_reg(spi, CANINTE,
539 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
540 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE |
541 CANINTF_MERRF);
542
543 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
544
545 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
546 } else {
547
548 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
549
550
551 timeout = jiffies + HZ;
552 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
553 schedule();
554 if (time_after(jiffies, timeout)) {
555 dev_err(&spi->dev, "MCP251x didn't"
556 " enter in normal mode\n");
557 return;
558 }
559 }
560 }
561 priv->can.state = CAN_STATE_ERROR_ACTIVE;
562}
563
564static int mcp251x_do_set_bittiming(struct net_device *net)
565{
566 struct mcp251x_priv *priv = netdev_priv(net);
567 struct can_bittiming *bt = &priv->can.bittiming;
568 struct spi_device *spi = priv->spi;
569
570 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
571 (bt->brp - 1));
572 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
573 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
574 CNF2_SAM : 0) |
575 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
576 (bt->prop_seg - 1));
577 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
578 (bt->phase_seg2 - 1));
579 dev_info(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
580 mcp251x_read_reg(spi, CNF1),
581 mcp251x_read_reg(spi, CNF2),
582 mcp251x_read_reg(spi, CNF3));
583
584 return 0;
585}
586
587static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv,
588 struct spi_device *spi)
589{
590 mcp251x_do_set_bittiming(net);
591
592
593 mcp251x_write_bits(spi, RXBCTRL(0),
594 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1,
595 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
596 mcp251x_write_bits(spi, RXBCTRL(1),
597 RXBCTRL_RXM0 | RXBCTRL_RXM1,
598 RXBCTRL_RXM0 | RXBCTRL_RXM1);
599 return 0;
600}
601
602static void mcp251x_hw_reset(struct spi_device *spi)
603{
604 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
605 int ret;
606
607 mutex_lock(&priv->spi_lock);
608
609 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
610
611 ret = spi_write(spi, priv->spi_tx_buf, 1);
612
613 mutex_unlock(&priv->spi_lock);
614
615 if (ret)
616 dev_err(&spi->dev, "reset failed: ret = %d\n", ret);
617
618 mdelay(10);
619}
620
621static int mcp251x_hw_probe(struct spi_device *spi)
622{
623 int st1, st2;
624
625 mcp251x_hw_reset(spi);
626
627
628
629
630
631
632
633 st1 = mcp251x_read_reg(spi, CANSTAT) & 0xEE;
634 st2 = mcp251x_read_reg(spi, CANCTRL) & 0x17;
635
636 dev_dbg(&spi->dev, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1, st2);
637
638
639 return (st1 == 0x80 && st2 == 0x07) ? 1 : 0;
640}
641
642static irqreturn_t mcp251x_can_isr(int irq, void *dev_id)
643{
644 struct net_device *net = (struct net_device *)dev_id;
645 struct mcp251x_priv *priv = netdev_priv(net);
646
647
648 if (!work_pending(&priv->irq_work))
649 queue_work(priv->wq, &priv->irq_work);
650
651 return IRQ_HANDLED;
652}
653
654static int mcp251x_open(struct net_device *net)
655{
656 struct mcp251x_priv *priv = netdev_priv(net);
657 struct spi_device *spi = priv->spi;
658 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
659 int ret;
660
661 ret = open_candev(net);
662 if (ret) {
663 dev_err(&spi->dev, "unable to set initial baudrate!\n");
664 return ret;
665 }
666
667 if (pdata->transceiver_enable)
668 pdata->transceiver_enable(1);
669
670 priv->force_quit = 0;
671 priv->tx_skb = NULL;
672 priv->tx_len = 0;
673
674 ret = request_irq(spi->irq, mcp251x_can_isr,
675 IRQF_TRIGGER_FALLING, DEVICE_NAME, net);
676 if (ret) {
677 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
678 if (pdata->transceiver_enable)
679 pdata->transceiver_enable(0);
680 close_candev(net);
681 return ret;
682 }
683
684 mcp251x_hw_wakeup(spi);
685 mcp251x_hw_reset(spi);
686 ret = mcp251x_setup(net, priv, spi);
687 if (ret) {
688 free_irq(spi->irq, net);
689 mcp251x_hw_sleep(spi);
690 if (pdata->transceiver_enable)
691 pdata->transceiver_enable(0);
692 close_candev(net);
693 return ret;
694 }
695 mcp251x_set_normal_mode(spi);
696 netif_wake_queue(net);
697
698 return 0;
699}
700
701static int mcp251x_stop(struct net_device *net)
702{
703 struct mcp251x_priv *priv = netdev_priv(net);
704 struct spi_device *spi = priv->spi;
705 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
706
707 close_candev(net);
708
709
710 mcp251x_write_reg(spi, CANINTE, 0x00);
711 mcp251x_write_reg(spi, CANINTF, 0x00);
712
713 priv->force_quit = 1;
714 free_irq(spi->irq, net);
715 flush_workqueue(priv->wq);
716
717 mcp251x_write_reg(spi, TXBCTRL(0), 0);
718 if (priv->tx_skb || priv->tx_len)
719 mcp251x_clean(net);
720
721 mcp251x_hw_sleep(spi);
722
723 if (pdata->transceiver_enable)
724 pdata->transceiver_enable(0);
725
726 priv->can.state = CAN_STATE_STOPPED;
727
728 return 0;
729}
730
731static void mcp251x_tx_work_handler(struct work_struct *ws)
732{
733 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
734 tx_work);
735 struct spi_device *spi = priv->spi;
736 struct net_device *net = priv->net;
737 struct can_frame *frame;
738
739 if (priv->tx_skb) {
740 frame = (struct can_frame *)priv->tx_skb->data;
741
742 if (priv->can.state == CAN_STATE_BUS_OFF) {
743 mcp251x_clean(net);
744 netif_wake_queue(net);
745 return;
746 }
747 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
748 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
749 mcp251x_hw_tx(spi, frame, 0);
750 priv->tx_len = 1 + frame->can_dlc;
751 can_put_echo_skb(priv->tx_skb, net, 0);
752 priv->tx_skb = NULL;
753 }
754}
755
756static void mcp251x_irq_work_handler(struct work_struct *ws)
757{
758 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
759 irq_work);
760 struct spi_device *spi = priv->spi;
761 struct net_device *net = priv->net;
762 u8 txbnctrl;
763 u8 intf;
764 enum can_state new_state;
765
766 if (priv->after_suspend) {
767 mdelay(10);
768 mcp251x_hw_reset(spi);
769 mcp251x_setup(net, priv, spi);
770 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
771 mcp251x_set_normal_mode(spi);
772 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
773 netif_device_attach(net);
774
775 if (priv->tx_skb || priv->tx_len) {
776 mcp251x_clean(net);
777 netif_wake_queue(net);
778 }
779 mcp251x_set_normal_mode(spi);
780 } else {
781 mcp251x_hw_sleep(spi);
782 }
783 priv->after_suspend = 0;
784 }
785
786 if (priv->can.restart_ms == 0 && priv->can.state == CAN_STATE_BUS_OFF)
787 return;
788
789 while (!priv->force_quit && !freezing(current)) {
790 u8 eflag = mcp251x_read_reg(spi, EFLG);
791 int can_id = 0, data1 = 0;
792
793 mcp251x_write_reg(spi, EFLG, 0x00);
794
795 if (priv->restart_tx) {
796 priv->restart_tx = 0;
797 mcp251x_write_reg(spi, TXBCTRL(0), 0);
798 if (priv->tx_skb || priv->tx_len)
799 mcp251x_clean(net);
800 netif_wake_queue(net);
801 can_id |= CAN_ERR_RESTARTED;
802 }
803
804 if (priv->wake) {
805
806 mdelay(10);
807 priv->wake = 0;
808 }
809
810 intf = mcp251x_read_reg(spi, CANINTF);
811 mcp251x_write_bits(spi, CANINTF, intf, 0x00);
812
813
814 if (eflag & EFLG_TXBO) {
815 new_state = CAN_STATE_BUS_OFF;
816 can_id |= CAN_ERR_BUSOFF;
817 } else if (eflag & EFLG_TXEP) {
818 new_state = CAN_STATE_ERROR_PASSIVE;
819 can_id |= CAN_ERR_CRTL;
820 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
821 } else if (eflag & EFLG_RXEP) {
822 new_state = CAN_STATE_ERROR_PASSIVE;
823 can_id |= CAN_ERR_CRTL;
824 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
825 } else if (eflag & EFLG_TXWAR) {
826 new_state = CAN_STATE_ERROR_WARNING;
827 can_id |= CAN_ERR_CRTL;
828 data1 |= CAN_ERR_CRTL_TX_WARNING;
829 } else if (eflag & EFLG_RXWAR) {
830 new_state = CAN_STATE_ERROR_WARNING;
831 can_id |= CAN_ERR_CRTL;
832 data1 |= CAN_ERR_CRTL_RX_WARNING;
833 } else {
834 new_state = CAN_STATE_ERROR_ACTIVE;
835 }
836
837
838 switch (priv->can.state) {
839 case CAN_STATE_ERROR_ACTIVE:
840 if (new_state >= CAN_STATE_ERROR_WARNING &&
841 new_state <= CAN_STATE_BUS_OFF)
842 priv->can.can_stats.error_warning++;
843 case CAN_STATE_ERROR_WARNING:
844 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
845 new_state <= CAN_STATE_BUS_OFF)
846 priv->can.can_stats.error_passive++;
847 break;
848 default:
849 break;
850 }
851 priv->can.state = new_state;
852
853 if ((intf & CANINTF_ERRIF) || (can_id & CAN_ERR_RESTARTED)) {
854 struct sk_buff *skb;
855 struct can_frame *frame;
856
857
858 skb = alloc_can_err_skb(net, &frame);
859 if (skb) {
860
861 frame->can_id = can_id;
862 frame->data[1] = data1;
863
864
865 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
866 if (eflag & EFLG_RX0OVR)
867 net->stats.rx_over_errors++;
868 if (eflag & EFLG_RX1OVR)
869 net->stats.rx_over_errors++;
870 frame->can_id |= CAN_ERR_CRTL;
871 frame->data[1] |=
872 CAN_ERR_CRTL_RX_OVERFLOW;
873 }
874
875 netif_rx(skb);
876 } else {
877 dev_info(&spi->dev,
878 "cannot allocate error skb\n");
879 }
880 }
881
882 if (priv->can.state == CAN_STATE_BUS_OFF) {
883 if (priv->can.restart_ms == 0) {
884 can_bus_off(net);
885 mcp251x_hw_sleep(spi);
886 return;
887 }
888 }
889
890 if (intf == 0)
891 break;
892
893 if (intf & CANINTF_WAKIF)
894 complete(&priv->awake);
895
896 if (intf & CANINTF_MERRF) {
897
898 txbnctrl = mcp251x_read_reg(spi, TXBCTRL(0));
899 if (!(txbnctrl & TXBCTRL_TXREQ)) {
900 if (priv->tx_skb || priv->tx_len)
901 mcp251x_clean(net);
902 netif_wake_queue(net);
903 }
904 }
905
906 if (intf & (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)) {
907 net->stats.tx_packets++;
908 net->stats.tx_bytes += priv->tx_len - 1;
909 if (priv->tx_len) {
910 can_get_echo_skb(net, 0);
911 priv->tx_len = 0;
912 }
913 netif_wake_queue(net);
914 }
915
916 if (intf & CANINTF_RX0IF)
917 mcp251x_hw_rx(spi, 0);
918
919 if (intf & CANINTF_RX1IF)
920 mcp251x_hw_rx(spi, 1);
921 }
922}
923
924static const struct net_device_ops mcp251x_netdev_ops = {
925 .ndo_open = mcp251x_open,
926 .ndo_stop = mcp251x_stop,
927 .ndo_start_xmit = mcp251x_hard_start_xmit,
928};
929
930static int __devinit mcp251x_can_probe(struct spi_device *spi)
931{
932 struct net_device *net;
933 struct mcp251x_priv *priv;
934 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
935 int ret = -ENODEV;
936
937 if (!pdata)
938
939 goto error_out;
940
941
942 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
943 if (!net) {
944 ret = -ENOMEM;
945 goto error_alloc;
946 }
947
948 net->netdev_ops = &mcp251x_netdev_ops;
949 net->flags |= IFF_ECHO;
950
951 priv = netdev_priv(net);
952 priv->can.bittiming_const = &mcp251x_bittiming_const;
953 priv->can.do_set_mode = mcp251x_do_set_mode;
954 priv->can.clock.freq = pdata->oscillator_frequency / 2;
955 priv->net = net;
956 dev_set_drvdata(&spi->dev, priv);
957
958 priv->spi = spi;
959 mutex_init(&priv->spi_lock);
960
961
962 if (mcp251x_enable_dma) {
963 spi->dev.coherent_dma_mask = ~0;
964
965
966
967
968
969 priv->spi_tx_buf = dma_alloc_coherent(&spi->dev,
970 PAGE_SIZE,
971 &priv->spi_tx_dma,
972 GFP_DMA);
973
974 if (priv->spi_tx_buf) {
975 priv->spi_rx_buf = (u8 *)(priv->spi_tx_buf +
976 (PAGE_SIZE / 2));
977 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
978 (PAGE_SIZE / 2));
979 } else {
980
981 mcp251x_enable_dma = 0;
982 }
983 }
984
985
986 if (!mcp251x_enable_dma) {
987 priv->spi_tx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
988 if (!priv->spi_tx_buf) {
989 ret = -ENOMEM;
990 goto error_tx_buf;
991 }
992 priv->spi_rx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
993 if (!priv->spi_rx_buf) {
994 ret = -ENOMEM;
995 goto error_rx_buf;
996 }
997 }
998
999 if (pdata->power_enable)
1000 pdata->power_enable(1);
1001
1002
1003 if (pdata->board_specific_setup)
1004 pdata->board_specific_setup(spi);
1005
1006 SET_NETDEV_DEV(net, &spi->dev);
1007
1008 priv->wq = create_freezeable_workqueue("mcp251x_wq");
1009
1010 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
1011 INIT_WORK(&priv->irq_work, mcp251x_irq_work_handler);
1012
1013 init_completion(&priv->awake);
1014
1015
1016 spi->mode = SPI_MODE_0;
1017 spi->bits_per_word = 8;
1018 spi_setup(spi);
1019
1020 if (!mcp251x_hw_probe(spi)) {
1021 dev_info(&spi->dev, "Probe failed\n");
1022 goto error_probe;
1023 }
1024 mcp251x_hw_sleep(spi);
1025
1026 if (pdata->transceiver_enable)
1027 pdata->transceiver_enable(0);
1028
1029 ret = register_candev(net);
1030 if (!ret) {
1031 dev_info(&spi->dev, "probed\n");
1032 return ret;
1033 }
1034error_probe:
1035 if (!mcp251x_enable_dma)
1036 kfree(priv->spi_rx_buf);
1037error_rx_buf:
1038 if (!mcp251x_enable_dma)
1039 kfree(priv->spi_tx_buf);
1040error_tx_buf:
1041 free_candev(net);
1042 if (mcp251x_enable_dma)
1043 dma_free_coherent(&spi->dev, PAGE_SIZE,
1044 priv->spi_tx_buf, priv->spi_tx_dma);
1045error_alloc:
1046 if (pdata->power_enable)
1047 pdata->power_enable(0);
1048 dev_err(&spi->dev, "probe failed\n");
1049error_out:
1050 return ret;
1051}
1052
1053static int __devexit mcp251x_can_remove(struct spi_device *spi)
1054{
1055 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1056 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1057 struct net_device *net = priv->net;
1058
1059 unregister_candev(net);
1060 free_candev(net);
1061
1062 priv->force_quit = 1;
1063 flush_workqueue(priv->wq);
1064 destroy_workqueue(priv->wq);
1065
1066 if (mcp251x_enable_dma) {
1067 dma_free_coherent(&spi->dev, PAGE_SIZE,
1068 priv->spi_tx_buf, priv->spi_tx_dma);
1069 } else {
1070 kfree(priv->spi_tx_buf);
1071 kfree(priv->spi_rx_buf);
1072 }
1073
1074 if (pdata->power_enable)
1075 pdata->power_enable(0);
1076
1077 return 0;
1078}
1079
1080#ifdef CONFIG_PM
1081static int mcp251x_can_suspend(struct spi_device *spi, pm_message_t state)
1082{
1083 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1084 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1085 struct net_device *net = priv->net;
1086
1087 if (netif_running(net)) {
1088 netif_device_detach(net);
1089
1090 mcp251x_hw_sleep(spi);
1091 if (pdata->transceiver_enable)
1092 pdata->transceiver_enable(0);
1093 priv->after_suspend = AFTER_SUSPEND_UP;
1094 } else {
1095 priv->after_suspend = AFTER_SUSPEND_DOWN;
1096 }
1097
1098 if (pdata->power_enable) {
1099 pdata->power_enable(0);
1100 priv->after_suspend |= AFTER_SUSPEND_POWER;
1101 }
1102
1103 return 0;
1104}
1105
1106static int mcp251x_can_resume(struct spi_device *spi)
1107{
1108 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1109 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1110
1111 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
1112 pdata->power_enable(1);
1113 queue_work(priv->wq, &priv->irq_work);
1114 } else {
1115 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1116 if (pdata->transceiver_enable)
1117 pdata->transceiver_enable(1);
1118 queue_work(priv->wq, &priv->irq_work);
1119 } else {
1120 priv->after_suspend = 0;
1121 }
1122 }
1123 return 0;
1124}
1125#else
1126#define mcp251x_can_suspend NULL
1127#define mcp251x_can_resume NULL
1128#endif
1129
1130static struct spi_driver mcp251x_can_driver = {
1131 .driver = {
1132 .name = DEVICE_NAME,
1133 .bus = &spi_bus_type,
1134 .owner = THIS_MODULE,
1135 },
1136
1137 .probe = mcp251x_can_probe,
1138 .remove = __devexit_p(mcp251x_can_remove),
1139 .suspend = mcp251x_can_suspend,
1140 .resume = mcp251x_can_resume,
1141};
1142
1143static int __init mcp251x_can_init(void)
1144{
1145 return spi_register_driver(&mcp251x_can_driver);
1146}
1147
1148static void __exit mcp251x_can_exit(void)
1149{
1150 spi_unregister_driver(&mcp251x_can_driver);
1151}
1152
1153module_init(mcp251x_can_init);
1154module_exit(mcp251x_can_exit);
1155
1156MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1157 "Christian Pellegrin <chripell@evolware.org>");
1158MODULE_DESCRIPTION("Microchip 251x CAN driver");
1159MODULE_LICENSE("GPL v2");
1160
