LXR linux/drivers/ata/pata

   1/*
   2 * Libata driver for the highpoint 372N and 302N UDMA66 ATA controllers.
   3 *
   4 * This driver is heavily based upon:
   5 *
   6 * linux/drivers/ide/pci/hpt366.c               Version 0.36    April 25, 2003
   7 *
   8 * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   9 * Portions Copyright (C) 2001          Sun Microsystems, Inc.
  10 * Portions Copyright (C) 2003          Red Hat Inc
  11 * Portions Copyright (C) 2005-2009     MontaVista Software, Inc.
  12 *
  13 *
  14 * TODO
  15 *      Work out best PLL policy
  16 */
  17
  18#include <linux/kernel.h>
  19#include <linux/module.h>
  20#include <linux/pci.h>
  21#include <linux/init.h>
  22#include <linux/blkdev.h>
  23#include <linux/delay.h>
  24#include <scsi/scsi_host.h>
  25#include <linux/libata.h>
  26
  27#define DRV_NAME        "pata_hpt3x2n"
  28#define DRV_VERSION     "0.3.8"
  29
  30enum {
  31        HPT_PCI_FAST    =       (1 << 31),
  32        PCI66           =       (1 << 1),
  33        USE_DPLL        =       (1 << 0)
  34};
  35
  36struct hpt_clock {
  37        u8      xfer_speed;
  38        u32     timing;
  39};
  40
  41struct hpt_chip {
  42        const char *name;
  43        struct hpt_clock *clocks[3];
  44};
  45
  46/* key for bus clock timings
  47 * bit
  48 * 0:3    data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
  49 *        DMA. cycles = value + 1
  50 * 4:8    data_low_time. active time of DIOW_/DIOR_ for PIO and MW
  51 *        DMA. cycles = value + 1
  52 * 9:12   cmd_high_time. inactive time of DIOW_/DIOR_ during task file
  53 *        register access.
  54 * 13:17  cmd_low_time. active time of DIOW_/DIOR_ during task file
  55 *        register access.
  56 * 18:21  udma_cycle_time. clock freq and clock cycles for UDMA xfer.
  57 *        during task file register access.
  58 * 22:24  pre_high_time. time to initialize 1st cycle for PIO and MW DMA
  59 *        xfer.
  60 * 25:27  cmd_pre_high_time. time to initialize 1st PIO cycle for task
  61 *        register access.
  62 * 28     UDMA enable
  63 * 29     DMA enable
  64 * 30     PIO_MST enable. if set, the chip is in bus master mode during
  65 *        PIO.
  66 * 31     FIFO enable.
  67 */
  68
  69/* 66MHz DPLL clocks */
  70
  71static struct hpt_clock hpt3x2n_clocks[] = {
  72        {       XFER_UDMA_7,    0x1c869c62      },
  73        {       XFER_UDMA_6,    0x1c869c62      },
  74        {       XFER_UDMA_5,    0x1c8a9c62      },
  75        {       XFER_UDMA_4,    0x1c8a9c62      },
  76        {       XFER_UDMA_3,    0x1c8e9c62      },
  77        {       XFER_UDMA_2,    0x1c929c62      },
  78        {       XFER_UDMA_1,    0x1c9a9c62      },
  79        {       XFER_UDMA_0,    0x1c829c62      },
  80
  81        {       XFER_MW_DMA_2,  0x2c829c62      },
  82        {       XFER_MW_DMA_1,  0x2c829c66      },
  83        {       XFER_MW_DMA_0,  0x2c829d2e      },
  84
  85        {       XFER_PIO_4,     0x0c829c62      },
  86        {       XFER_PIO_3,     0x0c829c84      },
  87        {       XFER_PIO_2,     0x0c829ca6      },
  88        {       XFER_PIO_1,     0x0d029d26      },
  89        {       XFER_PIO_0,     0x0d029d5e      },
  90};
  91
  92/**
  93 *      hpt3x2n_find_mode       -       reset the hpt3x2n bus
  94 *      @ap: ATA port
  95 *      @speed: transfer mode
  96 *
  97 *      Return the 32bit register programming information for this channel
  98 *      that matches the speed provided. For the moment the clocks table
  99 *      is hard coded but easy to change. This will be needed if we use
 100 *      different DPLLs
 101 */
 102
 103static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
 104{
 105        struct hpt_clock *clocks = hpt3x2n_clocks;
 106
 107        while(clocks->xfer_speed) {
 108                if (clocks->xfer_speed == speed)
 109                        return clocks->timing;
 110                clocks++;
 111        }
 112        BUG();
 113        return 0xffffffffU;     /* silence compiler warning */
 114}
 115
 116/**
 117 *      hpt3x2n_cable_detect    -       Detect the cable type
 118 *      @ap: ATA port to detect on
 119 *
 120 *      Return the cable type attached to this port
 121 */
 122
 123static int hpt3x2n_cable_detect(struct ata_port *ap)
 124{
 125        u8 scr2, ata66;
 126        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 127
 128        pci_read_config_byte(pdev, 0x5B, &scr2);
 129        pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
 130
 131        udelay(10); /* debounce */
 132
 133        /* Cable register now active */
 134        pci_read_config_byte(pdev, 0x5A, &ata66);
 135        /* Restore state */
 136        pci_write_config_byte(pdev, 0x5B, scr2);
 137
 138        if (ata66 & (2 >> ap->port_no))
 139                return ATA_CBL_PATA40;
 140        else
 141                return ATA_CBL_PATA80;
 142}
 143
 144/**
 145 *      hpt3x2n_pre_reset       -       reset the hpt3x2n bus
 146 *      @link: ATA link to reset
 147 *      @deadline: deadline jiffies for the operation
 148 *
 149 *      Perform the initial reset handling for the 3x2n series controllers.
 150 *      Reset the hardware and state machine,
 151 */
 152
 153static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline)
 154{
 155        struct ata_port *ap = link->ap;
 156        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 157        /* Reset the state machine */
 158        pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
 159        udelay(100);
 160
 161        return ata_sff_prereset(link, deadline);
 162}
 163
 164/**
 165 *      hpt3x2n_set_piomode             -       PIO setup
 166 *      @ap: ATA interface
 167 *      @adev: device on the interface
 168 *
 169 *      Perform PIO mode setup.
 170 */
 171
 172static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
 173{
 174        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 175        u32 addr1, addr2;
 176        u32 reg;
 177        u32 mode;
 178        u8 fast;
 179
 180        addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
 181        addr2 = 0x51 + 4 * ap->port_no;
 182
 183        /* Fast interrupt prediction disable, hold off interrupt disable */
 184        pci_read_config_byte(pdev, addr2, &fast);
 185        fast &= ~0x07;
 186        pci_write_config_byte(pdev, addr2, fast);
 187
 188        pci_read_config_dword(pdev, addr1, &reg);
 189        mode = hpt3x2n_find_mode(ap, adev->pio_mode);
 190        mode &= 0xCFC3FFFF;     /* Leave DMA bits alone */
 191        reg &= ~0xCFC3FFFF;     /* Strip timing bits */
 192        pci_write_config_dword(pdev, addr1, reg | mode);
 193}
 194
 195/**
 196 *      hpt3x2n_set_dmamode             -       DMA timing setup
 197 *      @ap: ATA interface
 198 *      @adev: Device being configured
 199 *
 200 *      Set up the channel for MWDMA or UDMA modes. Much the same as with
 201 *      PIO, load the mode number and then set MWDMA or UDMA flag.
 202 */
 203
 204static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 205{
 206        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 207        u32 addr1, addr2;
 208        u32 reg, mode, mask;
 209        u8 fast;
 210
 211        addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
 212        addr2 = 0x51 + 4 * ap->port_no;
 213
 214        /* Fast interrupt prediction disable, hold off interrupt disable */
 215        pci_read_config_byte(pdev, addr2, &fast);
 216        fast &= ~0x07;
 217        pci_write_config_byte(pdev, addr2, fast);
 218
 219        mask = adev->dma_mode < XFER_UDMA_0 ? 0x31C001FF : 0x303C0000;
 220
 221        pci_read_config_dword(pdev, addr1, &reg);
 222        mode = hpt3x2n_find_mode(ap, adev->dma_mode);
 223        mode &= mask;
 224        reg &= ~mask;
 225        pci_write_config_dword(pdev, addr1, reg | mode);
 226}
 227
 228/**
 229 *      hpt3x2n_bmdma_end               -       DMA engine stop
 230 *      @qc: ATA command
 231 *
 232 *      Clean up after the HPT3x2n and later DMA engine
 233 */
 234
 235static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
 236{
 237        struct ata_port *ap = qc->ap;
 238        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 239        int mscreg = 0x50 + 2 * ap->port_no;
 240        u8 bwsr_stat, msc_stat;
 241
 242        pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
 243        pci_read_config_byte(pdev, mscreg, &msc_stat);
 244        if (bwsr_stat & (1 << ap->port_no))
 245                pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
 246        ata_bmdma_stop(qc);
 247}
 248
 249/**
 250 *      hpt3x2n_set_clock       -       clock control
 251 *      @ap: ATA port
 252 *      @source: 0x21 or 0x23 for PLL or PCI sourced clock
 253 *
 254 *      Switch the ATA bus clock between the PLL and PCI clock sources
 255 *      while correctly isolating the bus and resetting internal logic
 256 *
 257 *      We must use the DPLL for
 258 *      -       writing
 259 *      -       second channel UDMA7 (SATA ports) or higher
 260 *      -       66MHz PCI
 261 *
 262 *      or we will underclock the device and get reduced performance.
 263 */
 264
 265static void hpt3x2n_set_clock(struct ata_port *ap, int source)
 266{
 267        void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8;
 268
 269        /* Tristate the bus */
 270        iowrite8(0x80, bmdma+0x73);
 271        iowrite8(0x80, bmdma+0x77);
 272
 273        /* Switch clock and reset channels */
 274        iowrite8(source, bmdma+0x7B);
 275        iowrite8(0xC0, bmdma+0x79);
 276
 277        /* Reset state machines, avoid enabling the disabled channels */
 278        iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70);
 279        iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74);
 280
 281        /* Complete reset */
 282        iowrite8(0x00, bmdma+0x79);
 283
 284        /* Reconnect channels to bus */
 285        iowrite8(0x00, bmdma+0x73);
 286        iowrite8(0x00, bmdma+0x77);
 287}
 288
 289static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
 290{
 291        long flags = (long)ap->host->private_data;
 292
 293        /* See if we should use the DPLL */
 294        if (writing)
 295                return USE_DPLL;        /* Needed for write */
 296        if (flags & PCI66)
 297                return USE_DPLL;        /* Needed at 66Mhz */
 298        return 0;
 299}
 300
 301static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc)
 302{
 303        struct ata_port *ap = qc->ap;
 304        struct ata_port *alt = ap->host->ports[ap->port_no ^ 1];
 305        int rc, flags = (long)ap->host->private_data;
 306        int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
 307
 308        /* First apply the usual rules */
 309        rc = ata_std_qc_defer(qc);
 310        if (rc != 0)
 311                return rc;
 312
 313        if ((flags & USE_DPLL) != dpll && alt->qc_active)
 314                return ATA_DEFER_PORT;
 315        return 0;
 316}
 317
 318static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc)
 319{
 320        struct ata_port *ap = qc->ap;
 321        int flags = (long)ap->host->private_data;
 322        int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
 323
 324        if ((flags & USE_DPLL) != dpll) {
 325                flags &= ~USE_DPLL;
 326                flags |= dpll;
 327                ap->host->private_data = (void *)(long)flags;
 328
 329                hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23);
 330        }
 331        return ata_sff_qc_issue(qc);
 332}
 333
 334static struct scsi_host_template hpt3x2n_sht = {
 335        ATA_BMDMA_SHT(DRV_NAME),
 336};
 337
 338/*
 339 *      Configuration for HPT3x2n.
 340 */
 341
 342static struct ata_port_operations hpt3x2n_port_ops = {
 343        .inherits       = &ata_bmdma_port_ops,
 344
 345        .bmdma_stop     = hpt3x2n_bmdma_stop,
 346
 347        .qc_defer       = hpt3x2n_qc_defer,
 348        .qc_issue       = hpt3x2n_qc_issue,
 349
 350        .cable_detect   = hpt3x2n_cable_detect,
 351        .set_piomode    = hpt3x2n_set_piomode,
 352        .set_dmamode    = hpt3x2n_set_dmamode,
 353        .prereset       = hpt3x2n_pre_reset,
 354};
 355
 356/**
 357 *      hpt3xn_calibrate_dpll           -       Calibrate the DPLL loop
 358 *      @dev: PCI device
 359 *
 360 *      Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
 361 *      succeeds
 362 */
 363
 364static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
 365{
 366        u8 reg5b;
 367        u32 reg5c;
 368        int tries;
 369
 370        for(tries = 0; tries < 0x5000; tries++) {
 371                udelay(50);
 372                pci_read_config_byte(dev, 0x5b, &reg5b);
 373                if (reg5b & 0x80) {
 374                        /* See if it stays set */
 375                        for(tries = 0; tries < 0x1000; tries ++) {
 376                                pci_read_config_byte(dev, 0x5b, &reg5b);
 377                                /* Failed ? */
 378                                if ((reg5b & 0x80) == 0)
 379                                        return 0;
 380                        }
 381                        /* Turn off tuning, we have the DPLL set */
 382                        pci_read_config_dword(dev, 0x5c, &reg5c);
 383                        pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
 384                        return 1;
 385                }
 386        }
 387        /* Never went stable */
 388        return 0;
 389}
 390
 391static int hpt3x2n_pci_clock(struct pci_dev *pdev)
 392{
 393        unsigned long freq;
 394        u32 fcnt;
 395        unsigned long iobase = pci_resource_start(pdev, 4);
 396
 397        fcnt = inl(iobase + 0x90);      /* Not PCI readable for some chips */
 398        if ((fcnt >> 12) != 0xABCDE) {
 399                printk(KERN_WARNING "hpt3xn: BIOS clock data not set.\n");
 400                return 33;      /* Not BIOS set */
 401        }
 402        fcnt &= 0x1FF;
 403
 404        freq = (fcnt * 77) / 192;
 405
 406        /* Clamp to bands */
 407        if (freq < 40)
 408                return 33;
 409        if (freq < 45)
 410                return 40;
 411        if (freq < 55)
 412                return 50;
 413        return 66;
 414}
 415
 416/**
 417 *      hpt3x2n_init_one                -       Initialise an HPT37X/302
 418 *      @dev: PCI device
 419 *      @id: Entry in match table
 420 *
 421 *      Initialise an HPT3x2n device. There are some interesting complications
 422 *      here. Firstly the chip may report 366 and be one of several variants.
 423 *      Secondly all the timings depend on the clock for the chip which we must
 424 *      detect and look up
 425 *
 426 *      This is the known chip mappings. It may be missing a couple of later
 427 *      releases.
 428 *
 429 *      Chip version            PCI             Rev     Notes
 430 *      HPT372                  4 (HPT366)      5       Other driver
 431 *      HPT372N                 4 (HPT366)      6       UDMA133
 432 *      HPT372                  5 (HPT372)      1       Other driver
 433 *      HPT372N                 5 (HPT372)      2       UDMA133
 434 *      HPT302                  6 (HPT302)      *       Other driver
 435 *      HPT302N                 6 (HPT302)      > 1     UDMA133
 436 *      HPT371                  7 (HPT371)      *       Other driver
 437 *      HPT371N                 7 (HPT371)      > 1     UDMA133
 438 *      HPT374                  8 (HPT374)      *       Other driver
 439 *      HPT372N                 9 (HPT372N)     *       UDMA133
 440 *
 441 *      (1) UDMA133 support depends on the bus clock
 442 *
 443 *      To pin down             HPT371N
 444 */
 445
 446static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 447{
 448        /* HPT372N and friends - UDMA133 */
 449        static const struct ata_port_info info = {
 450                .flags = ATA_FLAG_SLAVE_POSS,
 451                .pio_mask = ATA_PIO4,
 452                .mwdma_mask = ATA_MWDMA2,
 453                .udma_mask = ATA_UDMA6,
 454                .port_ops = &hpt3x2n_port_ops
 455        };
 456        const struct ata_port_info *ppi[] = { &info, NULL };
 457        u8 rev = dev->revision;
 458        u8 irqmask;
 459        unsigned int pci_mhz;
 460        unsigned int f_low, f_high;
 461        int adjust;
 462        unsigned long iobase = pci_resource_start(dev, 4);
 463        void *hpriv = (void *)USE_DPLL;
 464        int rc;
 465
 466        rc = pcim_enable_device(dev);
 467        if (rc)
 468                return rc;
 469
 470        switch(dev->device) {
 471                case PCI_DEVICE_ID_TTI_HPT366:
 472                        if (rev < 6)
 473                                return -ENODEV;
 474                        break;
 475                case PCI_DEVICE_ID_TTI_HPT371:
 476                        if (rev < 2)
 477                                return -ENODEV;
 478                        /* 371N if rev > 1 */
 479                        break;
 480                case PCI_DEVICE_ID_TTI_HPT372:
 481                        /* 372N if rev >= 2*/
 482                        if (rev < 2)
 483                                return -ENODEV;
 484                        break;
 485                case PCI_DEVICE_ID_TTI_HPT302:
 486                        if (rev < 2)
 487                                return -ENODEV;
 488                        break;
 489                case PCI_DEVICE_ID_TTI_HPT372N:
 490                        break;
 491                default:
 492                        printk(KERN_ERR "pata_hpt3x2n: PCI table is bogus please report (%d).\n", dev->device);
 493                        return -ENODEV;
 494        }
 495
 496        /* Ok so this is a chip we support */
 497
 498        pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
 499        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
 500        pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
 501        pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
 502
 503        pci_read_config_byte(dev, 0x5A, &irqmask);
 504        irqmask &= ~0x10;
 505        pci_write_config_byte(dev, 0x5a, irqmask);
 506
 507        /*
 508         * HPT371 chips physically have only one channel, the secondary one,
 509         * but the primary channel registers do exist!  Go figure...
 510         * So,  we manually disable the non-existing channel here
 511         * (if the BIOS hasn't done this already).
 512         */
 513        if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
 514                u8 mcr1;
 515                pci_read_config_byte(dev, 0x50, &mcr1);
 516                mcr1 &= ~0x04;
 517                pci_write_config_byte(dev, 0x50, mcr1);
 518        }
 519
 520        /* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
 521           50 for UDMA100. Right now we always use 66 */
 522
 523        pci_mhz = hpt3x2n_pci_clock(dev);
 524
 525        f_low = (pci_mhz * 48) / 66;    /* PCI Mhz for 66Mhz DPLL */
 526        f_high = f_low + 2;             /* Tolerance */
 527
 528        pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
 529        /* PLL clock */
 530        pci_write_config_byte(dev, 0x5B, 0x21);
 531
 532        /* Unlike the 37x we don't try jiggling the frequency */
 533        for(adjust = 0; adjust < 8; adjust++) {
 534                if (hpt3xn_calibrate_dpll(dev))
 535                        break;
 536                pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
 537        }
 538        if (adjust == 8) {
 539                printk(KERN_ERR "pata_hpt3x2n: DPLL did not stabilize!\n");
 540                return -ENODEV;
 541        }
 542
 543        printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using 66MHz DPLL.\n",
 544               pci_mhz);
 545        /* Set our private data up. We only need a few flags so we use
 546           it directly */
 547        if (pci_mhz > 60) {
 548                hpriv = (void *)(PCI66 | USE_DPLL);
 549                /*
 550                 * On  HPT371N, if ATA clock is 66 MHz we must set bit 2 in
 551                 * the MISC. register to stretch the UltraDMA Tss timing.
 552                 * NOTE: This register is only writeable via I/O space.
 553                 */
 554                if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
 555                        outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
 556        }
 557
 558        /* Now kick off ATA set up */
 559        return ata_pci_sff_init_one(dev, ppi, &hpt3x2n_sht, hpriv);
 560}
 561
 562static const struct pci_device_id hpt3x2n[] = {
 563        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
 564        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
 565        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
 566        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
 567        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), },
 568
 569        { },
 570};
 571
 572static struct pci_driver hpt3x2n_pci_driver = {
 573        .name           = DRV_NAME,
 574        .id_table       = hpt3x2n,
 575        .probe          = hpt3x2n_init_one,
 576        .remove         = ata_pci_remove_one
 577};
 578
 579static int __init hpt3x2n_init(void)
 580{
 581        return pci_register_driver(&hpt3x2n_pci_driver);
 582}
 583
 584static void __exit hpt3x2n_exit(void)
 585{
 586        pci_unregister_driver(&hpt3x2n_pci_driver);
 587}
 588
 589MODULE_AUTHOR("Alan Cox");
 590MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3x2n/30x");
 591MODULE_LICENSE("GPL");
 592MODULE_DEVICE_TABLE(pci, hpt3x2n);
 593MODULE_VERSION(DRV_VERSION);
 594
 595module_init(hpt3x2n_init);
 596module_exit(hpt3x2n_exit);
 597